Vertex-splitting connectivity prediction for improved progressive mesh compression

Abstract

The encoder includes a processor and a memory. The encoder may perform a method of progressive compression. In one example implementation, the method may include identifying a pair of split vertices to be connected to a split vertex associated with a collapse of an edge, creating the split vertex by collapsing the edge, encoding split vertex information associated with the pair of split vertices, the encoding of the split vertex information being based on an order of vertices of an umbrella of the split vertex, and the order of the vertices of the umbrella being determined based on a geometry and connectivity of the umbrella, and generating vertex splitting information including the split vertex information. In another example implementation, the method may include entropy encoding the vertex splitting information before sending.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application of U.S. Patent Application No. 15 / 951,963, filed on April 12, 2018, entitled “INCREASED DENSITY OF BATCHES FOR IMPROVED PROGRESSIVE MESH COMPRESSION”, a non-provisional application of U.S. Patent Application No. 15 / 951,944, filed on April 12, 2018, entitled “ENCODINGCOST AWARE EDGE SELECTION FOR IMPROVED PROGRESSIVE MESH COMPRESSION”, and a non-provisional application of U.S. Patent Application No. 15 / 951,944, filed on April 12, 2018, entitled “VERTEX SPLIT CONNECTIVITY PREDICTION FOR IMPROVED PROGRESSIVE MESH COMPRESSION”.

[0013] This application is a continuation of and claims priority to U.S. non-provisional patent application No. 15 / 951,969, entitled "VERTEX-SPLIT CONNECTIVITY PREDICTION FOR IMPROVED PROGRESSIVE MESH COMPRESSION," the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates generally to mesh compression, and more particularly to progressive mesh compression. Background Art

[0004] Progressive mesh compression (or progressive compression) is a hierarchical encoding of mesh geometry, where each level generates information about mesh connectivity, position, and other properties. Each subsequent level results in a coarser level of detail (LOD) of the model, and the encoding of the next LOD utilizes information already contained in the previous LOD. This is relevant for transmitting high-resolution models over the Internet, because the user on the receiving end (e.g., client, client device, or application) does not have to wait until the entire model is received from the server. The client can quickly display a lower resolution LOD of the model before receiving information associated with the high-resolution LOD at the client device. Summary of the invention

[0005] In one aspect, a method includes a computer-implemented method of progressive mesh compression. In one example implementation, the method may include identifying a pair of split vertices to be connected to a split vertex associated with a collapse of an edge, creating the split vertex by collapsing the edge, encoding split vertex information associated with the pair of split vertices, the encoding of the split vertex information being based on an order of vertices of an umbrella of the split vertex, and the order of the vertices of the umbrella being determined based on a geometry and connectivity of the umbrella, and generating vertex splitting information including the split vertex information. In another example implementation, the method may include entropy encoding the vertex splitting information before transmitting. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Example implementations will become more fully understood through the following detailed description given herein and the accompanying drawings, wherein like elements are denoted by like reference numerals, which are given by way of illustration only and thus do not limit example implementations and wherein:

[0007] Figure 1A Illustrated is a portion of a geometric model (or an image of a geometric model) compressed using an edge collapse operation according to at least one example implementation.

[0008] Figure 1B Illustrated is a portion of a geometric model (or an image of a geometric model) compressed using another edge collapse operation according to at least one example implementation.

[0009] Figure 2A A full edge collapse operation is illustrated according to at least one example implementation.

[0010] Figure 2B A half-edge collapse operation is illustrated according to at least one example implementation.

[0011] Figure 3A Illustrated is progressive compression according to at least one example implementation.

[0012] Figure 3B Illustrated is progressive compression according to at least another example implementation.

[0013] Figure 4 Illustrated is vertex split connectivity prediction according to at least one example implementation.

[0014] Figure 5 A flow chart illustrating a method of vertex splitting connectivity prediction according to at least one example implementation.

[0015] Figure 6 Examples of a computer device and a mobile computer device are illustrated according to at least one example implementation.

[0016] It should be noted that these figures are intended to illustrate the general characteristics of methods, structures, or materials utilized in certain example implementations, and are intended to supplement the written description provided below. However, these drawings are not to scale and may not accurately reflect the precise structure or performance characteristics of any given implementation, and should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the example implementations. The use of similar or identical reference numerals in various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0017] In one implementation, the encoder may determine a priority value for each edge in the plurality of edges, determine the priority value for the edge in the plurality of edges based on an estimated coding cost and an error metric value associated with the edge. The encoder may further determine a set of edges to collapse from the plurality of edges based on the priority value, collapse the set of edges and generate vertex splitting information, and send the generated vertex splitting information in response to a message received from the decoder. In some implementations, the encoder entropy encodes the vertex splitting information before being sent.

[0018] Figure 1A 1 illustrates a portion of a geometric model 100 compressed using an edge collapse operation according to at least one example implementation. Figure 1A In the example, region 102 of geometric model 100 represents a region that can be compressed using improved progressive mesh compression. Figure 2A The full edge collapse operation (or use of the full edge collapse operator) described in detail compresses the region 102. During progressive mesh compression, the encoder may generate multiple LODs and associated vertex split records. The LODs and associated vertex split records may be generated by collapsing the input mesh with successive batches (one or more batches) of edge collapse operators until a very coarse mesh is generated or there are no more edges to collapse (e.g., the edge collapse error metric value may be too high for the LOD).

[0019] Figure 1B 1 illustrates a portion of a geometric model 150 compressed using another edge collapse operation according to at least one example implementation. Figure 1B In the example, region 152 of geometric model 150 represents an area that can be compressed using improved progressive mesh compression. Figure 2B The region 152 is compressed using a half-edge collapse operation (or using a half-edge collapse operator) as described in detail.

[0020] Figure 2A A full edge collapse operation 200 is illustrated according to at least one example implementation.

[0021] exist Figure 2A , the edge 206 connecting the vertices 202, 210 can be collapsed via a full edge collapse operation (e.g., using a full edge collapse operator). In such a full edge collapse operation, the two vertices 202, 210 are merged into one vertex (e.g., a merged vertex, a split vertex, etc.), and a new vertex 218 is generated. The position of the new vertex 218 can be determined based on, for example, minimizing an error associated with the collapse of the edge 206 (e.g., minimizing an associated local error).

[0022] Full edge collapse requires a higher number of bits (e.g., when compared with Figure 2B 2 (when compared to the half-edge collapse operation described above) to encode the two residuals between the merged vertex 218 and its two ancestors 202, 210 so that the decoder can appropriately reverse the full edge collapse operation during decoding. During the full edge collapse operation, as edge 206 is collapsed, edges 204 and 208 collapse into a new edge (e.g., edge 216), and edges 222 and 224 collapse into another new edge (e.g., edge 226). Vertices 212 and 214 illustrate the merging of vertices 202 and 204 during the transition of the full edge operation. The collapsing of edges (e.g., using a full edge collapse operation) and the merging of vertices as described above can generate an LOD (e.g., a lower LOD) and an associated vertex split record. The decoder uses the vertex split record to decode (e.g., reconstruct) vertices and / or edges that were encoded (e.g., collapsed, merged, etc.) during the full edge collapse operation.

[0023] Figure 2B A half-edge collapse operation 250 is illustrated according to at least one example implementation.

[0024] exist Figure 2B , the edge 206 connecting the vertices 202, 210 may be collapsed via a half-edge collapse operation (e.g., using a half-edge collapse operator). In such a half-edge collapse operation, one of the two vertices (e.g., vertex 210) may be merged into the other vertex (e.g., vertex 202), and data may be generated such that a decoder may regenerate the vertex / edge during decoding.

[0025] The half-edge collapse operation requires a smaller number of bits (e.g., when compared to the above reference Figure 2AThe half-edge collapse operation may be performed in a manner similar to that described above (when compared to the full edge collapse operation described above) because only one residual associated with the vertex being merged (e.g., vertex 210) has to be encoded to reverse the half-edge collapse operation during decoding. During the half-edge collapse operation, as vertex 210 is merged into vertex 202, edge 208 collapses into edge 204, and edge 224 collapses into edge 222. Vertex 234 illustrates vertex 210 merging into vertex 202 during the transition of the half-edge collapse operation. As described above, collapsing / merging edges and / or merging vertices using the half-edge collapse operation may generate an LOD (e.g., a lower LOD) and associated vertex split records. The decoder uses the vertex split records to decode (e.g., reconstruct) the vertices and / or edges that were encoded (e.g., collapsed, merged, etc.) during the half-edge collapse operation. Although the half-edge collapse operation may require fewer bits (e.g., when compared to the full edge collapse operation) to represent the information required for decoding, the distortion rate may be higher (e.g., a more distorted lower LOD).

[0026] Figure 3A A progressive compression mechanism 300 is illustrated according to at least one example implementation. Figure 3B A progressive compression mechanism 350 is illustrated according to at least another example implementation.

[0027] A series of levels of detail (LODs) may be created (or generated) during progressive compression by decimating the input mesh with successive batches of edges collapsed (e.g., using an edge collapse operator) until a very coarse mesh is generated (or no more edges are available for collapse because the edge collapse error metric value may be too high for the LOD). The edge-collapsed batch may include collapsing a subset of the edges of the current mesh.

[0028] During progressive mesh compression, edges must form independent edge sets such that they can collapse without being disturbed by (or blocked by) other edges in their immediate neighborhood (e.g., nearby edges that may affect their predictions). Edge sets can be defined as independent edge sets if they are sufficiently separated from each other so that each edge in the edge set can collapse without being disturbed. For example, in Figure 3AIn the example, an edge 302 that can be part of an independent edge set can collapse without interference from other nearby edges (e.g., edge 304). However, an edge 304 near edge 302 may be blocked from collapsing by edge 302. An edge 304 that is blocked (e.g., blocked from collapsing) by another edge (e.g., edge 302) is generally referred to as a blocked edge and cannot be collapsed in the current round (e.g., when generating the current LOD). That is, edge 304 cannot be collapsed in the same round as edge 302. However, one or more edges 304 can become part of another independent edge set during edge collapse in the next round to generate another LOD.

[0029] Similarly, in Figure 3B , in addition to edge 302, edge 352 can be part of an independent edge set and can collapse without interference from other edges (e.g., 354 or 304) near edge 352. However, 354 near edge 352 can be blocked from collapsing by edge 352. Edge 354 blocked (e.g., blocked from collapsing) by another edge (e.g., edge 352) is called a blocked edge and cannot collapse in the current round (e.g., when generating the current LOD). That is, edge 354 cannot collapse in the same round as edge 352. However, one or more edges 354 can become part of another independent edge set during edge collapse in the next round to generate another LOD.

[0030] In some implementations, for example, a full edge collapse operation (eg, as described above with reference to Figure 2A Detailed description) or half-edge collapse operation (e.g., referenced above Figure 2B ) to collapse edges 302 and 352. In some other implementations, one type of edge collapse operation (e.g., half-edge or full-edge collapse operation) can be used to generate one LOD and / or another type of edge collapse operation (e.g., full-edge or half-edge collapse operation) can be used to generate the next LOD to achieve a balance between quality (e.g., distortion) and cost (e.g., bit rate or bits per vertex).

[0031] In progressive mesh compression, when edges collapse, each edge collapse may be associated with an error (e.g., an error metric value). The error metric value reflects (e.g., represents) the impact of edge collapse on mesh quality. In other words, the error metric value associated with edge collapse indicates how the quality of the mesh may be affected (e.g., negatively affected) by edge collapse. Therefore, in order to avoid collapsing edges that are too costly (e.g., a major impact on mesh quality, etc.), edges may be sorted (e.g., prioritized) based on their associated error metric values ​​before selecting them for collapse (or before adding them to an independent edge set). In some implementations, for example, the error metric value may be an initial error metric value (e.g., a quadratic error metric) and / or may depend on the application using the mesh. For example, edges may be sorted based on their error metric values, and edges with the lowest associated error metric values ​​may be ranked first. In an example implementation, when selecting edges of an input mesh, unblocked edges are added to form (or create) an independent edge set (e.g., a first independent edge set) and edges near edges that may be blocked are not considered for collapse in the current round. Edges may continue to be added to the independent edge set until all edges are blocked or the error metric is above a corresponding threshold.

[0032] As batches of edges are collapsed, lower LODs (e.g., lower resolution or coarser LODs) are generated along with additional information (e.g., vertex splitting information) that allows the decoder to recover a previous LOD (e.g., higher resolution LOD). In some implementations, the information generated during LOD generation can include, for example, a header with initial information for the decoder (e.g., indicating whether to perform full-edge or half-edge operations); information about how to split the encoded vertices into edges at the decoder; information about how to connect a vertex (e.g., a split vertex) to its surrounding vertices (neighbors of the split vertex); information necessary to recover the split vertex position; and / or texture coordinates or any other optional attributes.

[0033] In some implementations, for example, the independent edge set for collapse can be determined by adding the next best edge that is not blocked based on an error metric value associated with the edge (e.g., a quadratic error metric value, a Hausdorff distance value, etc.). However, this may not be the most efficient method because the error metric value does not take into account the residual (or residual value) or coding cost associated with edge collapse. Therefore, the proposed coding cost-aware edge selection for improved progressive mesh compression describes a method in which an independent edge set (e.g., for LOD) can be determined based on a priority value assigned to each of a plurality of edges of a mesh. In some implementations, the priority value of an edge can be determined based on, for example, an estimated coding cost associated with the edge and an error metric value. For example, when two nearby edges have relatively similar (e.g., close) error metric values, the proposed coding cost-aware edge selection mechanism also considers their associated coding costs to select the edge. That is, a combination of error metric values ​​and residual values ​​can be compared to select a better edge because, for example, the edge selected during entropy coding of the residual value can provide a better compression rate.

[0034] The present disclosure discloses a mechanism for predicting the direction of a new edge, for example, when a new edge is recreated from a split vertex during decoding. The split vertex may have been created during encoding by collapsing the edge between two vertices. In one implementation, the encoder can predict the split vertex by calculating the diameter of the umbrella by determining the pair of vertices that are farthest apart. This helps predict the direction of the new edge. Then, the two opposite vertices are determined as the most likely split vertices.

[0035] In some implementations, the present disclosure includes a method for vertex split connectivity prediction. The method may include: identifying a pair of split vertices to be connected to a split vertex associated with a collapse of an edge, creating the split vertex by collapsing the edge, encoding split vertex information associated with the pair of split vertices, encoding the split vertex information based on an order of vertices of an umbrella of the split vertex and an order of vertices of the umbrella determined based on the geometry and connectivity of the umbrella, and generating vertex split information including the split vertex information.

[0036] Figure 4 A vertex splitting connectivity prediction mechanism 400 for progressive mesh compression is illustrated according to at least one example implementation.

[0037] The encoder identifies vertices 402 and 404 (as shown in 400) as split vertices, just as before the collapse began. In some implementations, a diameter 424 (as shown in 420) can be determined based on the maximum possible distance between the vertices, and a perpendicular bisector 452 (as shown in 450) is determined. Once the perpendicular bisector 452 is determined, a pair of vertices closest to the perpendicular bisector 452 is determined and sorted as shown in 460, as described below with reference to Figure 5 Described in detail.

[0038] Figure 5 Flowchart 500 illustrates a method of progressive mesh compression. In one implementation, for example, the method may be performed by an encoder and may include vertex splitting connectivity prediction to improve progressive mesh compression.

[0039] At block 510, the encoder may identify a pair of split vertices to be connected to the split vertex associated with the collapse of the edge. For example, in one implementation, the encoder may identify a pair of split vertices (e.g., vertices 402, 404) to be connected to the split vertex associated with the collapse of the edge. The encoder may identify a pair of split vertices when the identification is performed before collapsing the edge.

[0040] At block 520, the encoder may create a split vertex by collapsing the edge. For example, in one implementation, the encoder may create a split vertex (e.g., split vertex 422) by collapsing edge 406. In one implementation, edge 406 may be collapsed using a half-edge or full-edge collapse operation. In another implementation, edge 404 may be collapsed using a midpoint collapse operation.

[0041] At box 530, the encoder may encode split vertex information associated with a pair of split vertices, the encoding of the split vertex information being based on the order of vertices of the umbrella of the split vertex, and the order of the vertices of the umbrella is determined based on the geometry and connectivity of the umbrella. In some implementations, for example, the umbrella of a vertex may be the first neighbor of the vertex, for example, the adjacent triangles including its edges and vertices. For example, in one implementation, the encoder may encode split vertex information associated with a pair of split vertices (e.g., vertices 402, 404). The split vertex information helps the decoder identify the split vertices during decoding. The encoding of the split vertex information may be based on the order of vertices of the umbrella of the split vertex (e.g., split vertex 422) (e.g., the order of vertices, e.g., 426, 428, 432, 434, 436, 438, 440, and 442). As described above with reference to Figure 4 As described, the order of the vertices of the umbrella is determined based on the geometry and connectivity of the umbrella. For example, the order of the vertices of the umbrella can also be defined as the order of the vertices connected to or associated with the split vertex.

[0042] In some implementations, the order of the vertices of the umbrella can be determined based on determining the diameter of the umbrella, the diameter being determined based on the maximum possible distance between a pair of vertices of the umbrella, determining the distance between each vertex of the umbrella and a perpendicular bisector of the diameter, and ordering the vertices of the umbrella in increasing order of the determined distances. For example, the diameter 424 can be determined based on the maximum possible distance between a pair of vertices of the umbrella (e.g., the distance between vertices 426 and 428). In other words, the diameter 424 can be determined based on determining the distance between each possible pair of vertices (e.g., vertices 426 and 442, 426 and 440, 440 and 438, 426 and 428, etc.), and considering the maximum distance between the two vertices determined as the diameter. Once the diameter 424 is determined, the perpendicular bisector 452 can be determined, and the distance between each vertex of the umbrella and the perpendicular bisector 452 of the diameter 424 can be determined. The perpendicular bisector 452 is perpendicular to the diameter 424 and splits the diameter 424 into two equal parts. In other words, the distance from each vertex of the umbrella and the perpendicular bisector 452 is determined.

[0043] The encoder may sort the vertices of the umbrella in increasing order based on the determined distances. For example, the vertices of the umbrella may be sorted as shown in diagram 460. In one example implementation, the encoder may determine that vertices 432 and 438 may have the shortest distance to perpendicular bisector 452, as represented by 1 and 2 (e.g., Figure 4 460). In other words, the vertices are sorted based on their distance from the perpendicular bisector 452 of the diameter 424 (e.g., the vertex with the shortest distance is sorted first). In one implementation, the two vertices with the shortest distance from the perpendicular bisector 452 can be considered as split vertices. In some implementations, for example, depending on the geometry of the input, a pair of vertices closest to the perpendicular bisector 452 and on opposite sides of the diameter 424 can be considered as split vertices (e.g., to avoid determining vertices on the side of the same diameter as the split vertices, but this may depend on the geometry of the mesh).

[0044] At block 540, the encoder may generate vertex splitting information including split vertex information. For example, in one implementation, the encoder may generate vertex splitting information, which may include split vertex information. In some implementations, the encoder for each sorted vertex may add a 0 to the stream if the vertex is splitting the vertex, and a 1 otherwise. Once the encoder encounters two split vertices, the encoder will stop encoding more vertices because the encoder has already encoded the two split vertices that the decoder needs for decoding.

[0045] Figure 6Examples of computer device 600 and mobile computer device 650 that can be used with the techniques described herein are shown. Computing device 600 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Computing device 650 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, and other similar computing devices. The components shown here, their connections and relationships, and their functions are intended to be exemplary only and are not intended to limit the implementation of the inventions described and / or claimed in this document.

[0046] The computing device 600 includes a processor 602, a memory 604, a storage device 606, a high-speed interface 608 connected to the memory 604 and a high-speed expansion port 610, and a low-speed interface 612 connected to a low-speed bus 614 and the storage device 606. Each of the components 602, 604, 606, 608, 610, and 612 is interconnected using various buses and can be mounted on a common motherboard or otherwise installed as appropriate. The processor 602 can process instructions for execution within the computing device 600, including instructions stored in the memory 604 or on the storage device 606 to display graphical information for a GUI on an external input / output device such as a display 616 coupled to the high-speed interface 608. In other implementations, multiple processors and / or multiple buses can be used together with multiple memories and multiple types of memories as appropriate. In addition, multiple computing devices 600 can be connected, each of which provides a portion of the necessary operations (for example, as a server group, a group of blade servers, or a multi-processor system).

[0047] The memory 604 stores information within the computing device 600. In one implementation, the memory 604 is one or more volatile memory units. In another implementation, the memory 604 is one or more non-volatile memory units. The memory 604 may also be another form of computer-readable medium, such as a magnetic disk or optical disk.

[0048] Storage device 606 can provide mass storage for computing device 600. In one implementation, storage device 606 can be or include a computer-readable medium, such as a floppy disk device, a hard disk device, an optical disk device or a tape device, a flash memory or other similar solid-state storage device or array of devices, including devices in a storage area network or other configurations. A computer program product can be tangibly embodied in an information carrier. A computer program product can also include instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer-readable medium or a machine-readable medium, such as a memory 604, a storage device 606, or a memory on a processor 602.

[0049] The high-speed controller 608 manages bandwidth-intensive operations of the computing device 600, while the low-speed controller 612 manages less bandwidth-intensive operations. This allocation of functions is exemplary only. In one implementation, the high-speed controller 608 is coupled to the memory 604, the display 616 (e.g., through a graphics processor or accelerator), and is coupled to the high-speed expansion port 610, which can accept various expansion cards (not shown). In this implementation, the low-speed controller 612 is coupled to the storage device 606 and the low-speed expansion port 614. The low-speed expansion port, which can include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), can be coupled to one or more input / output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or a router, for example, through a network adapter.

[0050] As shown in the figure, computing device 600 can be implemented in many different forms. For example, it can be implemented as a standard server 620, or multiple times in a group of such servers. It can also be implemented as part of a rack server system 624. In addition, it can be implemented in a personal computer such as a laptop computer 622. Alternatively, components from computing device 600 can be combined with other components in a mobile device (not shown) such as device 650. Each of such devices can contain one or more of computing devices 600, 650, and the entire system can be composed of multiple computing devices 600, 650 that communicate with each other.

[0051] Computing device 650 includes processor 652, memory 664, input / output devices such as display 654, communication interface 666, and transceiver 668, among other components. Device 650 may also be provided with a storage device, such as a microdrive or other device, to provide additional storage. Each of components 650, 652, 654, 654, 666, and 668 are interconnected using various buses, and several components may be mounted on a common motherboard or otherwise as appropriate.

[0052] The processor 652 can execute instructions within the computing device 650, including instructions stored in the memory 664. The processor can be implemented as a chipset of chips that include separate and multiple analog and digital processors. The processor can, for example, provide coordination for other components of the device 650, such as control of a user interface, applications executed by the device 650, and wireless communications performed by the device 650.

[0053] The processor 652 can communicate with the user through a control interface 658 and a display interface 656 coupled to the display 654. The display 654 can be, for example, a TFT LCD (thin film transistor liquid crystal display) or an OLED (organic light emitting diode) display or other appropriate display technology. The display interface 656 may include appropriate circuits for driving the display 654 to present graphics and other information to the user. The control interface 658 may receive commands from the user and convert them for submission to the processor 652. In addition, an external interface 662 in communication with the processor 652 may be provided to enable near-area communication of the device 650 with other devices. The external interface 662 may be provided, for example, for wired communication in some implementations, or for wireless communication in other implementations, and multiple interfaces may also be used.

[0054] The memory 664 stores information within the computing device 650. The memory 664 may be implemented as one or more of one or more computer-readable media, one or more volatile memory units, or one or more non-volatile memory units. An expansion memory 674 may also be provided and connected to the device 650 via an expansion interface 672, which may include, for example, a SIMM (single in-line memory module) card interface. Such an expansion memory 674 may provide additional storage space for the device 650, or may also store applications or other information for the device 650. Specifically, the expansion memory 674 may include instructions for executing or supplementing the above-mentioned processes, and may also include security information. Therefore, for example, the expansion memory 674 may be provided as a security module for the device 650, and may be programmed with instructions that allow the secure use of the device 650. In addition, security applications and additional information may be provided via a SIMM card, such as placing identification information on a SIMM card in an unbreakable manner.

[0055] The memory may include, for example, flash memory and / or NVRAM memory, as discussed below. In one implementation, a computer program product is tangibly embodied in an information carrier. The computer program product includes instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer or machine readable medium, such as memory 664, expansion memory 674, or memory on processor 652, which may be received, for example, via transceiver 668 or external interface 662.

[0056] Device 650 can communicate wirelessly via communication interface 666, which may include digital signal processing circuitry as necessary. Communication interface 666 may provide for communication under various modes or protocols, such as GSM voice calls, SMS, EMS or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000 or GPRS. Such communication may occur, for example, via radio frequency transceiver 668. In addition, short-range communication may occur, such as using Bluetooth, WiFi or other such transceivers (not shown). In addition, GPS (global positioning system) receiver module 670 may provide additional navigation and location-related wireless data to device 650, which may be used by applications running on device 650 as appropriate.

[0057] Device 650 may also communicate audibly using audio codec 660, which may receive spoken information from a user and convert it into usable digital information. Audio codec 660 may likewise generate audible sounds for the user, such as through, for example, a speaker in a headset of device 650. Such sounds may include sounds from voice phone calls, may include recorded sounds (e.g., voice messages, music files, etc.), and may also include sounds generated by applications operating on device 650.

[0058] As shown in the figure, computing device 650 can be implemented in many different forms. For example, it can be implemented as a cellular phone 680. It can also be implemented as part of a smart phone 682, a personal digital assistant, or other similar mobile device.

[0059] Various implementations of the systems and techniques described herein may be implemented using digital electronic circuits, integrated circuits, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs executable and / or interpretable on a programmable system, the programmable system including at least one programmable processor, which may be dedicated or general purpose, coupled to receive data and instructions from a storage system, at least one input device, and at least one output device, and to send data and instructions to a storage system, at least one input device, and at least one output device. Various implementations of the systems and techniques described herein may be implemented as circuits, modules, blocks, or systems that can be combined in software and hardware and / or are generally referred to herein as circuits, modules, blocks, or systems that can be combined in software and hardware. For example, a module may include functions / actions / computer program instructions executed on a processor (e.g., a processor formed on a silicon substrate, a GaAs substrate, etc.) or some other programmable data processing device.

[0060] Some of the above example embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the operations as sequential processes, many operations may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be rearranged. These processes may be terminated when their operations are completed, but may also have additional steps not included in the figure. These processes may correspond to methods, functions, programs, subroutines, subprograms, etc.

[0061] The methods discussed above (some of which are illustrated by flow charts) may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments for performing the necessary tasks may be stored in a machine or computer readable medium such as a storage medium. A processor may perform the necessary tasks.

[0062] The specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments are embodied in many alternate forms, however, and should not be construed as limited to only the embodiments set forth herein.

[0063] It should be understood that, although the terms first, second, etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element can be called the second element, and similarly, the second element can be called the first element without departing from the scope of the exemplary embodiment. As used herein, the terms and / or include any and all combinations of one or more of the related enumerated items.

[0064] It should be understood that when an element is referred to as being connected or coupled to another element, it may be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements. Other words used to describe the relationship between elements (e.g., between versus directly between, adjacent versus directly adjacent, etc.) should be interpreted in a similar manner.

[0065] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms a, an and the are also intended to include plural forms. It should be further understood that the terms contain, include, include and / or include when used in this article, specifying the features, integers, steps, operations, elements and / or components of the statement, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0066] It should also be noted that, in some alternative implementations, the functions / actions indicated may not occur in the order indicated in the figures. For example, depending on the functionality / actions involved, two figures shown in succession may actually be executed concurrently or may sometimes be executed in reverse order.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should be further understood that, unless explicitly defined as such herein, terms (e.g., those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0068] The various parts of the above-mentioned example implementations and corresponding detailed descriptions are presented in terms of software or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and representations are descriptions and representations used by those of ordinary skill in the art to effectively convey the essence of their work to other persons of ordinary skill in the art. An algorithm (when the term is used here, and when it is used generally) is considered to be a self-consistent sequence of steps leading to a desired result. These steps are those steps that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of optical, electrical or magnetic signals that can be stored, transferred, combined, compared and otherwise manipulated. Sometimes, mainly due to common reasons, it has proven to be convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0069] In the above illustrative implementations, references to actions and symbolic representations of operations that can be implemented as program modules or functional processes (e.g., in the form of flowcharts) include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types and can be described and / or implemented using existing hardware at existing structural elements. Such existing hardware may include one or more central processing units (CPUs), digital signal processors (DSPs), application specific integrated circuits, field programmable gate arrays (FPGAs), computers, etc.

[0070] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated, or as is apparent from the discussion, terms such as process or compute or calculate or determine display refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage, transmission or display devices.

[0071] Note also that the software-implemented aspects of the example implementations are typically encoded on some form of non-transitory program storage medium or implemented on some type of transmission medium. The program storage medium may be magnetic (e.g., a floppy disk or hard drive) or optical (e.g., a compact disk read-only memory or CD ROM), and may be read-only or random access. Similarly, the transmission medium may be a twisted pair, a coaxial cable, an optical fiber, or some other suitable transmission medium known in the art. The example implementations are not limited by these aspects of any given implementation.

[0072] Finally, it should also be noted that although the appended claims set out particular combinations of features described herein, the scope of the present disclosure is not limited to the particular combinations claimed thereafter, but instead extends to include any combination of features or implementations disclosed herein, regardless of whether the particular combination has been specifically enumerated in the appended claims at this time.

[0073] Although the example implementations may include various modifications and alternative forms, their implementations are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the example implementations are not intended to be limited to the specific forms disclosed, but on the contrary, the example implementations will cover all modifications, equivalents, and alternative forms falling within the scope of the claims. Throughout the description of the drawings, the same reference numerals refer to the same elements.

Claims

1. A computer-implemented progressive grid compression method comprising: identifying, by the encoder, a pair of split vertices to be connected to a split vertex associated with a collapse of an edge; creating, by the encoder, the split vertex by collapsing the edge; Encoding, by the encoder, split vertex information associated with the pair of split vertices, the encoding of the split vertex information being based on an order of vertices of an umbrella of the split vertex, and the order of the vertices of the umbrella being determined based on distances between the vertices of the umbrella and a perpendicular bisector of a diameter of the umbrella; and Vertex splitting information including the segmented vertex information is generated by the encoder.

2. The method according to claim 1, further comprising: The vertex splitting information is entropy encoded.

3. The method according to claim 1, further comprising: The vertex splitting information is sent from the encoder to the decoder in response to a message received from the decoder.

4. The method according to claim 1, wherein: The order of the vertices of the umbrella further includes: determining the diameter of the umbrella, the diameter being determined based on a maximum possible distance between a pair of vertices of the umbrella; determining the distance between each vertex of the umbrella and the perpendicular bisector of the diameter; and The vertices of the umbrella are sorted in increasing order of the determined distances.

5. The method according to claim 4, wherein: The perpendicular bisector is perpendicular to the diameter and splits the diameter into two equal halves, and wherein the pair of split vertices are on opposite sides of the diameter of the umbrella.

6. The method according to claim 1, wherein: The encoding further comprises: encoding each of the pair of split vertices with a first value; and Each non-segmented vertex of the vertices of the umbrella is encoded with a second value, and wherein the first value is different from the second value.

7. The method according to claim 1, further comprising: encoding each of the pair of split vertices with a first value; encoding each non-segmented vertex of the vertices of the umbrella with a second value, and wherein the first value is different from the second value; and The encoding is terminated in response to encoding two split vertices.

8. The method according to any one of claims 1 to 7, wherein: The split vertices are created by collapsing the edges based on a full-edge or half-edge collapse operation.

9. An encoder comprising: processor; as well as A memory comprising instructions configured to cause the processor to execute: identifying a pair of split vertices to be connected to the split vertex associated with the collapse of the edge; creating the split vertex by collapsing the edge; encoding split vertex information associated with the pair of split vertices, the encoding of the split vertex information being based on an order of vertices of an umbrella of the split vertex, and the order of the vertices of the umbrella being determined based on distances between the vertices of the umbrella and a perpendicular bisector of a diameter of the umbrella; and Vertex splitting information including the segmented vertex information is generated.

10. The encoder of claim 9, further comprising instructions for causing the processor to: The vertex splitting information is entropy encoded.

11. The encoder of claim 9, further comprising instructions for causing the processor to: The vertex splitting information is sent to the decoder in response to a message received from the decoder.

12. The encoder according to any one of claims 9 to 11, further comprising instructions for causing the processor to: determining the diameter of the umbrella, the diameter being determined based on a maximum possible distance between a pair of vertices of the umbrella; determining the distance between each vertex of the umbrella and the perpendicular bisector of the diameter; and The vertices of the umbrella are sorted in increasing order of the determined distances.

13. A non-transitory computer readable storage medium having computer executable program code stored thereon, which, when executed on a computer system, causes the computer system to perform a method of progressive mesh compression, the method comprising: identifying, by the encoder, a pair of split vertices to be connected to a split vertex associated with a collapse of an edge; creating, by the encoder, the split vertex by collapsing the edge; Encoding, by the encoder, split vertex information associated with the pair of split vertices, the encoding of the split vertex information being based on an order of vertices of an umbrella of the split vertex, and the order of the vertices of the umbrella being determined based on distances between the vertices of the umbrella and a perpendicular bisector of a diameter of the umbrella; and Vertex splitting information including the segmented vertex information is generated by the encoder.

14. The computer-readable storage medium of claim 13, further comprising code for: The vertex splitting information is entropy encoded.

15. The computer-readable storage medium of claim 13, further comprising code for: The vertex splitting information is sent from the encoder to the decoder in response to a message received from the decoder.

16. The computer-readable storage medium of claim 13, wherein: The order of the vertices of the umbrella further includes codes for: determining the diameter of the umbrella, the diameter being determined based on a maximum possible distance between a pair of vertices of the umbrella; determining the distance between each vertex of the umbrella and the perpendicular bisector of the diameter; as well as The vertices of the umbrella are sorted in increasing order of the determined distances.

17. The computer-readable storage medium of claim 16, wherein: The perpendicular bisector is perpendicular to the diameter and splits the diameter into two equal halves, and wherein the pair of split vertices are on opposite sides of the diameter of the umbrella.

18. The computer-readable storage medium of claim 13, wherein: The encoding further includes codes for: encoding each of the pair of split vertices with a first value; and Each non-segmented vertex of the vertices of the umbrella is encoded with a second value, and wherein the first value is different from the second value.

19. The computer-readable storage medium of claim 13, further comprising code for: encoding each of the pair of split vertices with a first value; encoding each non-segmented vertex of the vertices of the umbrella with a second value, and wherein the first value is different from the second value; and The encoding is terminated in response to encoding two split vertices.

20. The computer-readable storage medium according to any one of claims 13 to 19, wherein: The split vertices are created by collapsing the edges based on a full-edge or half-edge collapse operation.

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