A transmission electron microscope high-resolution in-situ fluid freezing chip and its preparation method

Abstract

The present invention discloses a transmission electron microscope high-resolution in-situ fluid freezing chip and a preparation method thereof. The lower plate of the chip is provided with a support layer, a freezing layer, an insulating layer, holes and a central window; the freezing layer is provided with three contact electrodes, six pairs of semiconductor films and a conductive metal film; the periphery of the central window has a circle of conductive metal film, the center of which is the central window; three contact electrodes are placed at the edge of the chip; one end of the six pairs of semiconductor films is placed on the conductive metal film, and the other end is placed on the electrode; with the central window as the center and in the outer edge area larger than the conductive metal film, silicon is etched away to leave holes, and the support layer covers the top of the holes; the conductive metal film is placed on the support layer on the holes, and the freezing layer is covered with an insulating layer except for the contact electrode area; there are multiple small holes on the central window. The chip has the advantages of rapid micro-area freezing, high resolution and low sample drift rate.

Description

Technical Field

[0001] The invention relates to the field of chips, and in particular to a transmission electron microscope high-resolution in-situ fluid freezing chip and a preparation method thereof. Background Art

[0002] At present, in-situ transmission electron microscopy technology provides a fully dynamic gas-fluid environment. On the one hand, this helps technicians capture more dynamic structural change information. On the other hand, due to the high-speed movement of molecules, it is difficult for technicians to capture certain important instantaneous information with high resolution in the dynamic process, such as the change information of element valence and molecular structure during chemical reactions, the distribution information of ions in the double layer of the electrochemical solid-liquid interface, and the change of three-dimensional structure when biological molecules (such as antigens / antibodies) interact with each other, etc. The instantaneous chemical state and spatial distribution information in these process information are very necessary for technicians to interpret the reaction principles from the molecular and atomic scales. These information characterizations require an unchanging state for a long time, which cannot be achieved by the existing low-temperature cryo-electron microscopes and in-situ fluid transmission electron microscopes. In order to obtain this information, technicians must achieve micro-area rapid freezing during the in-situ test process, and then combine it with high-resolution STEM / EDS / EELES characterization. Summary of the invention

[0003] The purpose of the present invention is to provide a transmission electron microscope high-resolution in-situ fluid freezing chip that can perform micro-area rapid freezing during in-situ testing. The chip also has the advantages of micro-area rapid freezing, high resolution and low sample drift rate.

[0004] To achieve the above-mentioned purpose, the present invention provides a transmission electron microscope high-resolution in-situ fluid freezing chip, which has a structure of an upper sheet and a lower sheet combined by a metal bonding layer, wherein the upper sheet and the lower sheet are both divided into a front side and a back side, and the front side of the upper sheet is directly bonded to the front side of the lower sheet by a metal bonding layer, and a self-sealed ultra-thin chamber is formed; the material of the upper sheet and the lower sheet are both silicon substrates with silicon nitride or silicon oxide on both sides, the upper sheet is provided with two injection ports and a central window 1, and is characterized in that the lower sheet is provided with a supporting layer, a freezing layer, an insulating layer, holes and a central window 2; the The freezing layer is provided with three contact electrodes, six pairs of semiconductor films and a conductive metal film; there is a circle of conductive metal film around the central window 2, and the center is the central window 2; three contact electrodes are placed at the edge of the chip; one end of the six pairs of semiconductor films is placed on the conductive metal film, and the other end is placed on the electrode; with the central window 2 as the center and in the outer edge area larger than the conductive metal film, a hole is left after silicon is etched away, and the support layer covers the top of the hole; the conductive metal film is placed on the support layer on the hole, and the freezing layer is covered with an insulating layer except for the contact electrode area;

[0005] The area of ​​the upper piece is slightly smaller than that of the lower piece. The central window 1 of the upper piece is aligned with the central window 2 of the lower piece. Both the central window 1 and the central window 2 are provided with a plurality of small holes.

[0006] Further, the outer dimensions of the lower piece are 2mm*2mm-10mm*10mm; preferably, the outer dimensions of the lower piece are 4mm*8mm;

[0007] Optionally, the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;

[0008] Optionally, the thickness of the silicon nitride or silicon oxide is 5-200 nm;

[0009] Optionally, the thickness of the silicon substrate is 50-500 μm;

[0010] The central viewing window 1 of the upper plate is located at the center of the upper plate, and the two sample injection ports are symmetrically arranged about the central viewing window 1 .

[0011] Furthermore, the support layer is silicon nitride or silicon oxide, and has a thickness of 0.5-5 μm.

[0012] Furthermore, in the freezing layer, two of the three contact electrodes are used as positive input currents; and one electrode is used as negative output current;

[0013] Optionally, the contact electrode is made of gold, silver or copper, with a thickness of 50nm-300nm, the length of the positive electrode is 1-1.5mm, and the width is 0.5-1.2mm; the length of the negative electrode is 1-1.5mm, and the width is 0.4-0.8mm;

[0014] Optionally, the six pairs of semiconductor films are six n-type semiconductor films and six p-type semiconductor films; the six n-type semiconductor films are in the shape of L-shaped strips and are placed in parallel and symmetrically on the outside of the chip; the six p-type semiconductor films are in the shape of regular rectangles and are placed in parallel and side by side on the inside of the chip; preferably, the n-type semiconductor in the n-type semiconductor film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; the p-type semiconductor in the p-type semiconductor film is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0015] Optionally, the semiconductor film has a length of 4-6 mm, a width of 0.4-0.8 mm, and a thickness of 50 nm-500 nm.

[0016] Furthermore, the conductive metal film is a U-shaped conductive metal film formed of a conductive metal, and the center of the conductive metal film is the central window 2; preferably, the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;

[0017] The outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm;

[0018] Furthermore, the insulating layer is a layer of silicon nitride or silicon oxide with a thickness of 30-150 nm.

[0019] Furthermore, the holes are circular or square; preferably, the diameter of the circular holes is 200 μm-600 μm; the size of the square holes is 200 μm*200 μm-800 μm*800 μm;

[0020] Optionally, the central window 1 and the central window 2 are both square central windows; preferably, the size of the square central window is 5 μm*5 μm-100 μm*100 μm; more preferably, the size of the square central window is 20 μm*50 μm;

[0021] Optionally, the size of the pores is 0.5 μm-5 μm.

[0022] Furthermore, the preparation method of the upper sheet is:

[0023] S1. Using a photolithography process, the central window pattern is transferred from a photolithography mask to a Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1;

[0024] Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; and the development time is 50 s;

[0025] More preferably, the exposure time is 15 s;

[0026] S2. Using a reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0027] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3;

[0028] Preferably, the development time is 50s;

[0029] S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0030] Preferably, the size of the pores is 0.5 μm-5 μm;

[0031] S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0032] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours;

[0033] More preferably, the etching time is 2h;

[0034] S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0035] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0036] More preferably, the exposure time is 15 s;

[0037] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0038] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000nm;

[0039] More preferably, the metal is In, Sn or Al;

[0040] S8. Laser scribe the wafer A-7 into independent chips.

[0041] Further, the preparation method of the lower sheet is:

[0042] S1. Prepare a Si(100) wafer B with a silicon nitride or silicon oxide layer on both sides, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

[0043] S2. Using a photolithography process, the conductive metal carrier film pattern of the outer circle of the central window is transferred from the photolithography mask to the back of the above-mentioned wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1;

[0044] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0045] More preferably, the exposure time is 20 s;

[0046] S3. Using a reactive ion etching process, the silicon nitride or silicon oxide of the conductive metal is etched out on the silicon nitride layer on the back of the wafer B-1, and then the wafer is immersed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2;

[0047] Optionally, the outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm;

[0048] S4. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-2 to obtain a wafer B-3;

[0049] Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

[0050] S5. Using a photolithography process, the metal film pattern and the contact electrode pattern are transferred from the photolithography mask to the front side of the wafer B-3, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-4;

[0051] S6. Using DC magnetron sputtering, a metal film is sputtered on the front side of the wafer B-4, and then the wafer B-4 is immersed in acetone with the front side facing up to be peeled off, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, and obtaining the wafer B-5;

[0052] Optionally, the metal film is made of gold, silver or copper, with a thickness of 50nm-300nm;

[0053] S7. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-6;

[0054] S8. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor film on the front side of wafer B-6, then put the front side of wafer B-6 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor film, and obtain wafer B-7;

[0055] Preferably, the n-type semiconductor in the n-type semiconductor film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0056] S9. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-7, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-8;

[0057] Preferably, the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0058] S10. Using radio frequency magnetron sputtering, a layer of p-type semiconductor film is sputtered on the front side of wafer B-8, and then the front side of wafer 11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor film, to obtain wafer B-9;

[0059] Preferably, the p-type semiconductor in the p-type semiconductor film is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride.

[0060] S11. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor film of wafer B-9 as an insulating layer to obtain wafer B-10;

[0061] Preferably, the thickness of the insulating layer is 30-150 nm;

[0062] S12. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the central window is transferred from the photolithography mask to the front side of the wafer B-10, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-11;

[0063] Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W / us;

[0064] S13. Using a reactive ion etching process, silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-11, and then the front side of the wafer B-11 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-12;

[0065] Preferably, the size of the pores is 0.5 μm-5 μm;

[0066] S14. Laser scribe the wafer B-12 into independent chips.

[0067] The present invention also protects a method for preparing the transmission electron microscope high-resolution in-situ fluid freezing chip, which is characterized by:

[0068] The preparation method of the upper sheet is:

[0069] S1. Using a photolithography process, the central window pattern is transferred from a photolithography mask to a Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1;

[0070] Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; and the development time is 50 s;

[0071] More preferably, the exposure time is 15 s;

[0072] S2. Using a reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0073] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3;

[0074] Preferably, the development time is 50s;

[0075] S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0076] Preferably, the size of the pores is 0.5 μm-5 μm;

[0077] S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0078] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours;

[0079] More preferably, the etching time is 2h;

[0080] S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0081] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0082] More preferably, the exposure time is 15 s;

[0083] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0084] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000nm;

[0085] More preferably, the metal is In, Sn or Al;

[0086] S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading;

[0087] The preparation method of the lower sheet is:

[0088] S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

[0089] Preferably, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

[0090] S2. Using a photolithography process, the conductive metal carrier film pattern of the outer circle of the central window is transferred from the photolithography mask to the back of the above-mentioned wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1;

[0091] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0092] More preferably, the exposure time is 20 s;

[0093] S3. Using a reactive ion etching process, the silicon nitride or silicon oxide of the conductive metal is etched out on the silicon nitride layer on the back of the wafer B-1, and then the wafer is immersed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2;

[0094] The outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm;

[0095] S4. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-2 to obtain a wafer B-3;

[0096] Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

[0097] S5. Using a photolithography process, the metal film pattern and the contact electrode pattern are transferred from the photolithography mask to the front side of the wafer B-3, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-4;

[0098] S6. Using DC magnetron sputtering, a metal film is sputtered on the front side of the wafer B-4, and then the wafer B-4 is immersed in acetone with the front side facing up to be peeled off, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, and obtaining the wafer B-5;

[0099] Optionally, the metal film is made of gold, silver or copper, with a thickness of 50nm-300nm;

[0100] S7. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-6;

[0101] S8. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor film on the front side of wafer B-6, then put the front side of wafer B-6 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor film, and obtain wafer B-7;

[0102] Preferably, the n-type semiconductor in the n-type semiconductor film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0103] S9. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-7, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-8;

[0104] Preferably, the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0105] S10. Using radio frequency magnetron sputtering, a layer of p-type semiconductor film is sputtered on the front side of wafer B-8, and then the front side of wafer 11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor film, to obtain wafer B-9;

[0106] Preferably, the p-type semiconductor in the p-type semiconductor film is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0107] S11. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor film of wafer B-9 as an insulating layer to obtain wafer B-10;

[0108] Preferably, the thickness of the insulating layer is 30-150 nm;

[0109] S12. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the central window is transferred from the photolithography mask to the front side of the wafer B-10, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-11;

[0110] Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W / us;

[0111] S13. Using a reactive ion etching process, silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-11, and then the front side of the wafer B-11 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-12;

[0112] Preferably, the size of the pores is 0.5 μm-5 μm;

[0113] S14. Laser scribing the wafer B-12 into independent chips is performed as the bottom wafer;

[0114] Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

[0115] The chip temperature control area of ​​the present invention is small (100 μm*100 μm-500 μm*500 μm area), and is designed with heat insulation treatment, so the heat transfer is small, so that micro-area rapid temperature control can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] Figure 1 It is a schematic diagram of the freezing layer structure of the lower chip of the present invention;

[0117] Figure 2 It is a schematic diagram of the structure after the holes are etched during the chip bottom preparation process of the present invention;

[0118] Figure 3 It is a schematic diagram of the structure after the holes are etched, the conductive metal film and the contact electrodes are plated during the chip bottom preparation process of the present invention;

[0119] Figure 4 is Figure 3 Schematic diagram of the structure after coating the n-type semiconductor film on the basis;

[0120] Figure 5 is Figure 4 Schematic diagram of the structure after coating a p-type semiconductor film on the base;

[0121] Figure 6 It is a schematic diagram of the lower chip structure of the chip of the present invention;

[0122] Figure 7 It is a schematic diagram of the structure of the chip of the present invention before the upper and lower chips are assembled;

[0123] Figure 8 It is a schematic diagram of the structure of the upper and lower chips of the chip of the present invention after being combined;

[0124] Fig. 9 It is an enlarged view of the center window 1 of 51 and the center window 2 of 52;

[0125] Fig.10 It is an enlarged view of 52 center window 1 and 52 center window 2;

[0126] Fig.11 is an electron microscope image of a sample observed using the chip of the present invention;

[0127] Fig.12 It is a temperature standard curve diagram obtained by using the chip of the present invention. DETAILED DESCRIPTION

[0128] Embodiments of the present invention are described in detail below, and the examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by reference to the accompanying drawings are exemplary, are intended to be used to explain the present invention, and are not to be construed as limitations of the present invention. Those who do not indicate specific techniques or conditions in the embodiments are carried out according to the techniques or conditions described in the documents in this area or according to the product specification. Those who do not indicate the manufacturer of reagents or instruments used are all conventional products that can be obtained commercially.

[0129] according to Figure 1-Figure 10The following chip is fabricated based on the structure of FIG. 1 : a transmission electron microscope high-resolution in-situ fluid freezing chip; 2 : an upper chip; 3 : a lower chip; 4 : a metal bonding layer; 5 : a central window; 51 : a central window of the upper chip; 52 : a central window of the lower chip; 6 : a small hole; 7 : a sample injection port; 8 : a support layer; 9 : a freezing layer; 10 : an insulating layer; 11 : three contact electrodes; 12 : a silicon substrate; 13 and 14 : both silicon nitride or silicon oxide layers; 15 : a hole; 161 : an n-type semiconductor film; 162 : a p-type semiconductor film; and 17 : a conductive metal film.

[0130] Example 1: Preparation of high-resolution in-situ fluid freezing chip for transmission electron microscopy

[0131] The preparation method of the upper sheet is as follows:

[0132] S1. Using a photolithography process, the central window pattern is transferred from a photolithography mask to a Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1;

[0133] Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; and the development time is 50 s;

[0134] More preferably, the exposure time is 15 s;

[0135] S2. Using a reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0136] S3. Using an ultraviolet laser direct writing process, the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3;

[0137] Preferably, the development time is 50s;

[0138] S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0139] Preferably, the size of the pores is 0.5 μm-5 μm;

[0140] S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

[0141] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours;

[0142] More preferably, the etching time is 2h;

[0143] S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0144] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0145] More preferably, the exposure time is 15 s;

[0146] S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0147] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000nm;

[0148] More preferably, the metal is In, Sn or Al;

[0149] S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading;

[0150] The preparation method of the lower sheet is:

[0151] S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

[0152] Preferably, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

[0153] S2. Using a photolithography process, the conductive metal carrier film pattern of the outer circle of the central window is transferred from the photolithography mask to the back of the above-mentioned wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1;

[0154] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0155] More preferably, the exposure time is 20 s;

[0156] S3. Using a reactive ion etching process, the silicon nitride or silicon oxide of the conductive metal is etched out on the silicon nitride layer on the back of the wafer B-1, and then the wafer is immersed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2;

[0157] Optionally, the outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm;

[0158] S4. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-2 to obtain a wafer B-3;

[0159] Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

[0160] S5. Using a photolithography process, the metal film pattern and the contact electrode pattern are transferred from the photolithography mask to the front side of the wafer B-3, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-4;

[0161] S6. Using DC magnetron sputtering, a metal film is sputtered on the front side of the wafer B-4, and then the wafer B-4 is immersed in acetone with the front side facing up to be peeled off, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, and obtaining the wafer B-5;

[0162] Optionally, the metal film is made of gold, silver or copper, with a thickness of 50nm-300nm;

[0163] S7. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-6;

[0164] S8. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor film on the front side of wafer B-6, then put the front side of wafer B-6 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor film, and obtain wafer B-7;

[0165] Preferably, the n-type semiconductor in the n-type semiconductor film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

[0166] S9. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-7, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-8;

[0167] Preferably, the p-type semiconductor is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0168] S10. Using radio frequency magnetron sputtering, a layer of p-type semiconductor film is sputtered on the front side of wafer B-8, and then the front side of wafer 11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor film, to obtain wafer B-9;

[0169] Preferably, the p-type semiconductor in the p-type semiconductor film is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

[0170] S11. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor film of wafer B-9 as an insulating layer to obtain wafer B-10;

[0171] Preferably, the thickness of the insulating layer is 30-150 nm;

[0172] S12. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the central window is transferred from the photolithography mask to the front side of the wafer B-10, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-11;

[0173] Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W / us;

[0174] S13. Using a reactive ion etching process, silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-11, and then the front side of the wafer B-11 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-12;

[0175] Preferably, the size of the pores is 0.5 μm-5 μm;

[0176] S14. Laser scribing the wafer B-12 into independent chips is performed as the bottom wafer;

[0177] Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

[0178] Example 2: Use of high-resolution in-situ fluid freezing chip for transmission electron microscopy

[0179] A supersaturated calcium hydroxide aqueous solution (containing trace calcium hydroxide particles) was injected into the sample injection port of the transmission electron microscope high-resolution in-situ fluid freezing chip prepared in Example 1, and the chip temperature was set to -30°C by an external temperature control device combined with temperature control software to obtain Fig.11Electron micrographs from Fig.11 A and B observed that during the temperature reduction process, the nanoparticles became smaller due to the increase in solute solubility. During this process, the particle morphology and contour were clear, indicating that the imaging resolution of the chip in the electron microscope was high; at the same time, the position of the sample did not shift during the entire shooting process, indicating that the chip had good stability during the experiment and the sample drift rate was low.

[0180] Example 3: Temperature Standard Curve

[0181] Before using the transmission electron microscope high-resolution in-situ fluid freezing chip, the temperature reached by the chip under different output powers is measured by a temperature meter to obtain a temperature standard curve, and then the temperature is precisely controlled by precisely adjusting the output power of the power supply device. Fig.12 .from Fig.12 The line graph shows that the temperature difference reaches 70 degrees within 5-6 seconds, and the cooling rate is fast. And it can be stable at -50 degrees Celsius for a long time, which shows that the temperature control accuracy is high, and it also shows that the temperature control range of the chip of the present invention is large, from low temperature to high temperature.

[0182] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention.

Claims

1. A transmission electron microscope high-resolution in-situ liquid phase freezing chip, which has a structure of an upper plate and a lower plate combined by a metal bonding layer, wherein the upper plate and the lower plate are both divided into a front side and a back side, the front side of the upper plate is directly bonded to the front side of the lower plate by a metal bonding layer, and a self-sealed ultra-thin chamber is formed; the material of the upper plate and the lower plate are both silicon substrates with silicon nitride or silicon oxide on both sides, the upper plate is provided with two injection ports and a central window 1, It is characterized in that The lower chip is provided with a support layer, a freezing layer, an insulating layer, a hole and a central window 2; the freezing layer is provided with three contact electrodes, six pairs of semiconductor films and a conductive metal film; the outer periphery of the central window 2 is a circle of conductive metal film, the center of which is the central window 2; the three contact electrodes are placed at the edge of the chip; one end of the six pairs of semiconductor films is placed on the conductive metal film, and the other end is placed on the electrode; with the central window 2 as the center and in the outer edge area larger than the conductive metal film, a hole is left after silicon is etched away, and the support layer covers the top of the hole; the conductive metal film is placed on the support layer on the hole, and the freezing layer is covered with an insulating layer except for the contact electrode area; The area of ​​the upper sheet is slightly smaller than that of the lower sheet, the central window 1 of the upper sheet is aligned with the central window 2 of the lower sheet, and there are multiple small holes on the central window 1 and the central window 2; The preparation method of the upper sheet is: S1. Using a photolithography process, the central window pattern is transferred from a photolithography mask to a Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1; S2. Using a reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2; S3. Using an ultraviolet laser direct writing process, the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3; S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4; S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5; S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6; S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7; S8. Laser scribe the wafer A-7 into independent chips.

2. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The outer dimensions of the lower piece are 2mm*2mm-10mm*10mm.

3. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 2, It is characterized in that The outer dimensions of the lower piece are 4mm*8mm.

4. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal.

5. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The material of the metal bonding layer is In, Sn or Al.

6. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The thickness of the silicon nitride or silicon oxide is 5-200 nm.

7. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The thickness of the silicon substrate is 50-500 μm.

8. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The central viewing window 1 of the upper plate is located at the center of the upper plate, and the two sample injection ports are symmetrically arranged about the central viewing window 1 .

9. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The support layer is silicon nitride or silicon oxide, and has a thickness of 0.5-5 μm.

10. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that In the freezing layer, two of the three contact electrodes serve as positive input currents; and one electrode serves as negative output currents.

11. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, Features Optionally, the contact electrode is made of gold, silver or copper, with a thickness of 50nm-300nm, the length of the positive electrode is 1-1.5mm, and the width is 0.5-1.2mm; the length of the negative electrode is 1-1.5mm, and the width is 0.4-0.8mm.

12. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The six pairs of semiconductor films are six n-type semiconductor films and six P-type semiconductor films; the six n-type semiconductor films are in the shape of L-shaped strips and are placed in parallel and symmetrically on the outside of the chip; the six P-type semiconductor films are in the shape of regular rectangles and are placed in parallel on the inside of the chip.

13. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 12, It is characterized in that The n-type semiconductor in the n-type semiconductor film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; the p-type semiconductor in the p-type semiconductor film is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride.

14. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The semiconductor film has a length of 4-6 mm, a width of 0.4-0.8 mm, and a thickness of 50 nm-500 nm.

15. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 1, It is characterized in that The conductive metal thin film is a meandering conductive metal thin film formed by a conductive metal, and the center of the conductive metal thin film is the central window 2.

16. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 15, wherein, the conductive metal used is gold, silver or copper, and the thickness is 50 nm - 300 nm.

17. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 1, wherein, the outer square size of the conductive metal thin film is 100 μm * 100 μm - 500 μm * 500 μm, and the inner square size is 5 μm * 5 μm - 100 μm * 100 μm.

18. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 1, wherein, the insulating layer is a layer of silicon nitride or silicon oxide, and the thickness is 30 - 150 nm.

19. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 1, wherein, the holes are circular holes or square holes.

20. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 19, wherein, the diameter of the circular hole is 200 μm - 600 μm; the size of the square hole is 200 μm * 200 μm - 800 μm * 800 μm.

21. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 1, wherein, both the central window 1 and the central window 2 are square central windows.

22. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 21, wherein, the size of the square central window is 5 μm * 5 μm - 100 μm * 100 μm.

23. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 22, wherein, the size of the square central window is 20 μm * 50 μm; 24. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 1, wherein, the size of the small holes is 0.5 μm - 5 μm.

25. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 1, wherein, in step S1 of the preparation method of the upper chip, the photolithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the thickness of the silicon nitride or silicon oxide layer is 5 - 200 nm; the development time is 50 s; and / or in step S3, the development time is 50 s; and / or in step S4, the size of the small holes is 0.5 μm - 5 μm; and / or in step S5, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80 °C, and the time is 1.5 - 4 h; and / or in step S6, the photolithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the development time is 50 s; and / or in step S7, the metal is a low-melting-point metal; the thickness of the metal bonding layer is 50 - 2000 nm.

26. The high-resolution in-situ liquid-phase cryogenic chip for a transmission electron microscope according to claim 25, wherein, In the preparation method of the upper wafer, in step S1, the exposure time is 15 s; and / or in step S5, the etching time is 2 h; and / or in step S6, the exposure time is 15 s; and / or in step S7, the metal is In, Sn or Al.

27. The transmission electron microscope high-resolution in-situ liquid-phase freezing chip according to claim 1, characterized in that the preparation method of the lower wafer is S1. Prepare a Si(100) wafer B with silicon nitride or silicon oxide layers on both sides; S2. Using the photolithography process, transfer the conductive metal carrier film pattern outside the central viewing window from the photomask to the back of the above-mentioned wafer, then develop it in the positive photoresist developer, and then wash the surface with deionized water to obtain wafer B-1; S3. Using the reactive ion etching process, etch away the silicon nitride or silicon oxide of the conductive metal on the back silicon nitride layer of wafer B-1, then soak the wafer face up in acetone successively, and finally rinse with acetone to remove the photoresist to obtain wafer B-2; S4. Using the PECVD process, grow silicon oxide or silicon nitride on the front of the silicon wafer after etching wafer B-2 to obtain wafer B-3; S5. Using the photolithography process, transfer the metal thin film pattern and the contact electrode pattern from the photomask to the front of wafer B-3, then develop it in the positive photoresist developer, and then rinse the surface with deionized water to obtain wafer B-4; S6. Using DC magnetron sputtering, sputter a metal thin film on the front of wafer B-4, then soak and strip the wafer face up in acetone successively, and finally rinse with deionized water to remove the photoresist and leave the metal thin film to obtain wafer B-5; S7. Using the photolithography process, transfer the n-type semiconductor pattern from the photomask to the front of wafer B-5, then develop it in the positive photoresist developer, and then rinse the surface with deionized water to obtain wafer B-6; S8. Using RF magnetron sputtering, sputter an n-type semiconductor thin film on the front of wafer B-6, then soak and strip the wafer face up in acetone successively, and finally rinse with deionized water to remove the photoresist and leave the n-type semiconductor thin film to obtain wafer B-7; S9. Using the photolithography process, transfer the p-type semiconductor pattern from the photomask to the front of wafer B-7, then develop it in the positive photoresist developer, and then rinse the surface with deionized water to obtain wafer B-8; S10. Using RF magnetron sputtering, sputter a p-type semiconductor thin film on the front of wafer B-8, then soak and strip the wafer face up in acetone successively, and finally rinse with deionized water to remove the photoresist and leave the p-type semiconductor thin film to obtain wafer B-9; S11. Using the PECVD process, grow a layer of silicon nitride or silicon oxide or aluminum oxide as an insulating layer on the semiconductor thin film of wafer B-9 to obtain wafer B-10; S12. Using the ultraviolet laser direct writing photolithography process, transfer the small hole pattern of the central viewing window from the photomask to the front of wafer B-10, then develop it in the positive photoresist developer, and then rinse the surface with deionized water to obtain wafer B-11; S13. Using a reactive ion etching process, silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-11, and then the front side of the wafer B-11 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-12; S14. Laser scribe the wafer B-12 into independent chips.

28. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 27, It is characterized in that In the method for preparing the lower wafer, the thickness of the silicon nitride or silicon oxide layer in step S1 is 5-200 nm; and / or The photolithography process in step S2 is exposure in the hard contact mode of the UV lithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s; and / or In step S3, the outer square size of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the inner square size is 5 μm*5 μm-100 μm*100 μm; and / or In step S4, the thickness of silicon oxide or silicon nitride is 0.5-5 μm; and / or The metal film in step S6 is made of gold, silver or copper, with a thickness of 50nm-300nm; and / or The n-type semiconductor in the n-type semiconductor film in step S8 is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; and / or The p-type semiconductor in step S9 is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride; and / or The p-type semiconductor in the p-type semiconductor film in step S10 is polycrystalline silicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride; and / or The thickness of the insulating layer in step S11 is 30-150 nm; and / or The photoresist used in the UV laser direct writing process in step S12 is AZ5214E; the output power is 260W / us; and / or In step S13, the size of the small hole is 0.5 μm-5 μm.

29. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 28, It is characterized in that In the preparation method of the lower film, the exposure time is 20 seconds.

30. A method for preparing the transmission electron microscope high-resolution in-situ liquid phase freezing chip according to any one of claims 1 to 29, It is characterized in that The preparation method of the upper sheet is: S1. Using a photolithography process, the central window pattern is transferred from a photolithography mask to a Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then developed in a positive photoresist developer to obtain a wafer A-1; S2. Using a reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2; S3. Using an ultraviolet laser direct writing process, the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3; S4. Using a reactive ion etching process, the silicon nitride thickness at the small hole on the back of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4; S5. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5; S6. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6; S7. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7; S8. Laser scribing the wafer A-7 into independent chips is performed as wafer loading; The preparation method of the lower sheet is: S1. Prepare a Si(100) wafer B with a silicon nitride or silicon oxide layer on both sides, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm; S2. Using a photolithography process, the conductive metal carrier film pattern of the outer circle of the central window is transferred from the photolithography mask to the back of the above-mentioned wafer, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-1; S3. Using a reactive ion etching process, the silicon nitride or silicon oxide of the conductive metal is etched out on the silicon nitride layer on the back of the wafer B-1, and then the wafer is immersed in acetone with the back side facing up, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2; S4. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the silicon wafer after etching of the wafer B-2 to obtain a wafer B-3; S5. Using a photolithography process, the metal film pattern and the contact electrode pattern are transferred from the photolithography mask to the front side of the wafer B-3, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-4; S6. Using DC magnetron sputtering, a metal film is sputtered on the front side of the wafer B-4, and then the wafer B-4 is immersed in acetone with the front side facing up to be peeled off, and finally rinsed with deionized water to remove the photoresist, leaving the metal film, and obtaining the wafer B-5; S7. Using a photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-6; S8. Use radio frequency magnetron sputtering to sputter a layer of n-type semiconductor film on the front side of wafer B-6, then put the front side of wafer B-6 into acetone for immersion and peeling, and finally rinse with deionized water to remove the photoresist, leaving the n-type semiconductor film, and obtain wafer B-7; S9. Using a photolithography process, the p-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-7, and then developed in a positive photoresist developer, and then the surface is rinsed and cleaned with deionized water to obtain a wafer B-8; S10. Using radio frequency magnetron sputtering, a layer of p-type semiconductor film is sputtered on the front side of wafer B-8, and then the front side of wafer 11 is placed in acetone for immersion and peeling, and finally rinsed with deionized water to remove the photoresist, leaving the p-type semiconductor film, to obtain wafer B-9; S11. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor film of wafer B-9 as an insulating layer to obtain wafer B-10; S12. Using an ultraviolet laser direct writing lithography process, the small hole pattern of the central window is transferred from the photolithography mask to the front side of the wafer B-10, and then developed in a positive photoresist developer, and then rinsed and cleaned the surface with deionized water to obtain a wafer B-11; S13. Using a reactive ion etching process, silicon nitride or silicon oxide is etched at the small hole on the back of the wafer B-11, and then the front side of the wafer B-11 is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-12; S14. Laser scribing the wafer B-12 into independent chips is performed as the bottom wafer; Assembly: Assemble the obtained upper and lower sheets under a microscope so that the central windows of the upper and lower sheets are aligned.

31. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 30, It is characterized in that In the preparation method of the upper sheet, In step S1, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s; and / or In step S3, the developing time is 50s; and / or In step S4, the size of the small hole is 0.5 μm-5 μm; and / or In step S5, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5-4 hours; and / or In step S6, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s; and / or In step S7, the metal is a low melting point metal; and the thickness of the metal bonding layer is 50-2000 nm.

32. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 31, It is characterized in that In the method for preparing the upper film, in step S1, the exposure time is 15 seconds; and / or In the step S5, the etching time is 2 hours; and / or In the step S6, the exposure time is 15 s; and / or In the step S7, the metal is In, Sn or Al.

33. The transmission electron microscope high-resolution in-situ liquid phase freezing chip as claimed in claim 31, It is characterized in that In the method for preparing the lower wafer, the thickness of the silicon nitride or silicon oxide layer in step S1 is 5-200 nm; and / or The photolithography process in step S2 is exposure in the hard contact mode of the UV lithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s; and / or In step S3, the outer square size of the conductive metal thin film is 100μm * 100μm - 500μm * 500μm, and the inner square size is 5μm * 5μm - 100μm * 100μm; and / or In step S4, the thickness of the silicon oxide or silicon nitride is 0.5 - 5μm; and / or In step S6, the metal thin film used is gold, silver or copper, and the thickness is 50nm - 300nm; and / or In step S8, the n-type semiconductor in the n-type semiconductor thin film is n-type bismuth telluride, n-type silicon germanide, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; and / or In step S9, the p-type semiconductor used is polysilicon, p-type bismuth telluride, p-type silicon germanide or p-type antimony telluride; and / or In step S10, the p-type semiconductor in the p-type semiconductor thin film is polysilicon, p-type bismuth telluride, p-type silicon germanide or p-type antimony telluride; and / or In step S11, the thickness of the insulating layer is 30 - 150nm; and / or In step S12, the photoresist used in the ultraviolet laser direct writing process is AZ5214E; the output power is 260W / us; and / or In step S13, the size of the small hole is 0.5μm - 5μm.

34. The transmission electron microscope high-resolution in-situ liquid-phase freezing chip according to claim 33, characterized in that in the preparation method of the lower wafer, the exposure time is 20s.

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