Cache management method and microcontroller
Manage SRAM and DRAM objects through an object-oriented cache controller, and optimize object loading and storage using group policy and exclusive policies, solving the problem of high DRAM power consumption in ultra-low power consumption applications, achieving more efficient power saving and System efficiency is improved.
Patent Information
- Application Number
- CN202010080814.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-05-03
- Filing Date
- 2020-02-05
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2040-02-05
AI Technical Summary
In ultra-low power consumption, DRAM consumes too high power, and due to the small cache line, DRAM cannot sleep effectively to save power, and frequent power on/off increases overhead.
Use an object-oriented cache controller to manage SRAM and DRAM objects, optimize the loading and storage of objects through group policy and exclusive policies, reduce the power on/off frequency of DRAM, and use hardware cache to optimize task scheduling to save power.
It effectively reduces DRAM power consumption, reduces frequent power switching and on/off operations, and improves the efficiency of the system in ultra-low power consumption applications.
Smart Images
Figure CN111880722B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory technology, and more particularly to a cache management method and a microcontroller. Background Art
[0002] For embedded microcontroller (MCU) systems, since cache memory (e.g., static random access memory (SRAM)) is expensive, large / slow / high-power memory such as dynamic random access memory (DRAM) is usually used together with cache memory to provide a larger storage space; however, this arrangement consumes a lot of power. In some ultra-low-power applications (such as sensor hubs or pedometers), DRAM power consumption is too high for these ultra-low-power applications, so DRAM must be powered off during certain periods to save power. However, because the current cache lines are too small, it is easy to randomly access DRAM, resulting in DRAM not being able to sleep long enough to save power, and the overhead of DRAM is increased due to frequent on / off power. Summary of the invention
[0003] The invention provides a cache management method and a microcontroller, which can be used in ultra-low power consumption applications.
[0004] A microcontroller provided by the present invention comprises: a processor; a first memory coupled to the processor, wherein the first memory comprises at least a working space; a cache controller coupled to the first memory, for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.
[0005] A cache management method provided by the present invention comprises: providing a first memory having a working space; and using a cache controller to dynamically load at least one object from a second memory to the working space of the first memory in an object-oriented manner.
[0006] The technical solution provided by the present invention can be used in ultra-low power consumption applications through an object-oriented approach. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0008] Figure 1 is a diagram showing a microcontroller (MCU) 100 according to one embodiment of the present invention.
[0009] Figure 2 The management of the workspace 122 and the object pool 154 when the group policy is applied according to the first embodiment of the present invention is shown.
[0010] Figure 3 The management of the workspace 122 and the object pool 154 when the group policy is applied according to the second embodiment of the present invention is shown.
[0011] Figure 4 The management of the workspace 122 and the object pool 154 when the exclusive policy is applied according to the first embodiment of the present invention is shown.
[0012] Figure 5 The management of the workspace 122 and the object pool 154 when the exclusive policy is applied according to the second embodiment of the present invention is shown.
[0013] Figure 6 is a flow chart of a cache management method according to an embodiment of the present invention.
[0014] Figure 7 is a diagram showing a microcontroller 700 according to another embodiment of the present invention. DETAILED DESCRIPTION
[0015] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of components as the criteria for distinction. "Including" and "including" mentioned throughout the specification and claims are open-ended terms, so they should be interpreted as "including but not limited to". "Substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect. In addition, the term "coupled" includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following is a preferred way to implement the present invention, the purpose of which is to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the definition of the attached claims.
[0016] The following description is the best embodiment of the present invention. These descriptions are used to illustrate the general principles of the present invention and should not be used to limit the present invention. The scope of protection of the present invention should be determined based on the claims of the present invention.
[0017] Figure 1 1 is a diagram showing a microcontroller (MCU) 100 according to an embodiment of the present invention. Figure 1 As shown, the microcontroller 100 includes a central processing unit (CPU) 110, a memory 120 such as a static random access memory (SRAM), a cache controller 130 and a hardware cache 140. Among them, the SRAM 120 includes at least a workspace 122. The cache controller 130 includes an object-oriented policy manager 132, an object allocator 134 and a dynamic loader 136. In this embodiment, the cache controller 130 is used to manage the workspace 122. As an example and not intended to limit the present invention, the cache controller 130 is implemented by pure software (that is, the operation of the cache controller 130 is performed by executing program code).
[0018] The microcontroller 100 is coupled to a DRAM 150 having a power unit 152 and an object pool 154, and the microcontroller 100 loads an object from the object pool 154 to execute a corresponding function, wherein the term "object" is a collection of code or data for a specific function and can be linked and loaded into the SRAM 120 to be executed. In detail, the dynamic loader 136 of the cache controller 130 loads the object from the object pool 154 to the work space 122 of the SRAM 120, and the CPU 110 reads and executes the loaded object in the work space 122.
[0019] In this embodiment, the hardware cache 140 serves as an optimization tool for the operation of the cache controller 130. In detail, when the microcontroller 100 has a low power consumption feature, the hardware cache 140 may be used to group tasks to increase the location of the cache and schedule tasks that do not have ultra-low power consumption requirements for the DRAM 150 to save the use of the cache controller 130. When the microcontroller 100 has an ultra-low power consumption feature, the hardware cache 140 may not be able to implement the work of storing objects corresponding to the ultra-low power requirements to prevent more frequent access to the DRAM 150. In order to save power of a system including the microcontroller 100 and the DRAM 150, the cache controller 130 may manage objects in the SRAM 120 and the DRAM 150 in an object-oriented manner so that the DRAM 150 is not powered on / off more frequently. In detail, the object-oriented policy manager 132 is arranged to provide at least one cache policy indicating the relationship of a plurality of objects. The object allocator 134 is arranged to determine at least one object with reference to the cache policy provided by the object-oriented policy manager 132, and the dynamic loader 136 loads at least one object determined by the object allocator 134 from the DRAM 150 to the SRAM 120. By loading objects in an object-oriented manner using the cache controller 130, the object allocator 134 can more efficiently control the power supply unit 152 of the DRAM 150 to save power to make the system suitable for ultra-low power consumption applications, such as a sensor hub or a pedometer.
[0020] Specifically, the cache policy can be programmed by the user or by the user scenario analyzed by the processor, for example, the cache policy can be a group policy and / or an exclusive policy. The group policy can indicate a plurality of specific objects that are always used together, and if one of the specific objects is to be loaded from the object pool 154 to the workspace 122, the other specific objects are simultaneously loaded to the workspace 122. The exclusive policy can indicate a plurality of specific objects that are never used together, and if one of the specific objects is to be loaded from the object pool 154 to the workspace 122, the dynamic loader 136 moves the other specific objects (if any) from the workspace 122 to the object pool 154.
[0021] Figure 2 FIG. 2 shows the management of the workspace 122 and the object pool 154 when applying the group policy according to the first embodiment of the present invention. Figure 2As shown, it is assumed that objects OB1, OB4, and OB5 are grouped by the object-oriented policy manager 132, and initially the workspace 122 stores objects OB1, OB2, and OB3, and the object pool 154 stores objects OB4 and OB5. According to the group policy of the object-oriented policy manager 132, objects OB2 and OB3 following object OB1 in the workspace 122 are moved to the object pool 154 of the DRAM 150 to free up space, and then objects OB4 and OB5 are pre-fetched from the object pool 154 to the workspace 122, where objects OB4 and OB5 are located after object OB1 (i.e., there is no fragmentation in the group (OB1, OB4, and OB5)). In addition, if object OB2 needs to be loaded into the workspace 122, object OB1 can be moved to the object pool 154 without moving objects OB4 and OB5 in the workspace, and then object OB2 is moved to the workspace. In Figure 2 In the illustrated embodiment, because objects OB4 and OB5 are pre-fetched and objects of the same group are stored together in the workspace, the operating efficiency of the system can be improved and frequent switching (ie, switching objects between SRAM 120 and DRAM 150) can be prevented.
[0022] Figure 3 FIG. 2 shows the management of the workspace 122 and the object pool 154 when applying the group policy according to the second embodiment of the present invention. Figure 3 In the illustrated case, it is assumed that objects OB1-OB6 are sequentially used by CPU 110, that is, objects OB1-OB6 are sequentially loaded from object pool 154 into workspace 122. In the prior art, initially, objects OB1-OB3 are sequentially stored in workspace 122, and then object OB1 is moved out of workspace 122 to free up space for storing object OB4, object OB2 is moved out of workspace 122 to free up space for storing object OB5, and object OB3 is moved out of workspace 122 to free up space for storing object OB6. Figure 3 As shown, the method of the prior art will cause some fragmented space between objects OB4-OB6, and these fragmented spaces are usually too small to be used. In contrast, in the group policy of this embodiment, objects OB1-OB3 can be set as the first group, and objects OB4-OB6 can be set as the second group, and objects OB1-OB3 can be moved together so that objects OB4-OB6 can be loaded into workspace 122 at the same time. By using the group policy of this embodiment, since there is no fragmented space between objects OB4-OB6, workspace 122 can have enough space to load another object.
[0023] Figure 4FIG. 2 shows the management of the workspace 122 and the object pool 154 when the exclusive strategy is applied according to the first embodiment of the present invention. Figure 4 As shown, it is assumed that objects OB1 and OB3 are grouped by the object-oriented policy manager 132, and at the beginning, the workspace 122 stores objects OB1, OB2, and OB3, and the object pool 154 stores objects OB4 and OB5. According to the exclusive policy of the object-oriented policy manager 132, the object OB3 is moved to the object pool 154 of the DRAM 150 to free up space. Then, if the object OB3 needs to be loaded into the workspace 122, the object OB1 can be moved to the object pool 154 first, and then the object OB3 can be moved to the workspace 122. Figure 4 As shown, since the objects in the group are not loaded at the same time, frequent switching can be prevented and the average loading overhead can be reduced.
[0024] Figure 5 FIG. 1 shows the management of the workspace 122 and the object pool 154 when the exclusive strategy is applied according to the second embodiment of the present invention. Figure 5 In the illustrated case, it is assumed that objects OB3, OB1, and OB2 are sequentially and repeatedly used by the CPU 110, that is, objects OB3, OB1, and OB2 are sequentially and repeatedly loaded from the object pool 154 to the workspace 122. In the prior art, objects OB1 and OB3 are first stored in the workspace 122, and then an attempt is made to load object OB2 into the workspace 122. Since the workspace 122 does not have enough space to store object OB2, object OB3 is removed from the workspace 122 by using a least recently used (Least Recently Used, LRU) mechanism, and object OB2 is stored in the workspace 122. Then, an attempt is made to load object OB3 into the workspace 122. Since object OB3 has a large size, both objects OB1 and OB2 need to be moved to the DRAM 150 to free up space for storing object OB3, resulting in a large switching overhead. In contrast, in the exclusive policy of the present embodiment, objects OB1 and OB2 can be set to be exclusive, that is, when an attempt is made to load object OB2 into workspace 122, object OB1 is moved out of workspace 122 to free up space for storing object OB2, and even if object OB3 is the least recently used object, object OB3 does not need to be moved. Therefore, object OB3 does not need to be loaded in the next cycle, and switching overhead can be greatly improved.
[0025] Figure 6 is a flow chart of a cache management method according to an embodiment of the present invention. Figure 1-Figure 5 And related description, the flow chart is described as follows.
[0026] Step 602: The cache controller 130 attempts to load the object A from the DRAM 150 (step 602-1), or the cache controller 130 attempts to load the group G including a plurality of objects from the DRAM 150 (step 602-2).
[0027] Step 604 : The cache controller 130 determines whether the exclusive policy is applied and object A has an exclusive pair. If yes, the process proceeds to step 608 ; otherwise, the process proceeds to step 606 .
[0028] Step 606 : The cache controller 130 allocates a block for storing object A or group G in the workspace 122 .
[0029] Step 608 : The cache controller 130 determines whether one of the mutex pair has been loaded into the workspace 122 . If yes, the flow goes to step 610 ; if no, the flow goes to step 606 .
[0030] Step 610: The cache controller 130 removes one of the mutex pairs to free the block.
[0031] Step 612: The cache controller 130 allocates the block to object A.
[0032] Step 614: The cache controller 130 determines whether the block allocation is successful. If yes, the process proceeds to step 618; if no, the process proceeds to step 616.
[0033] Step 616 : The cache controller 130 releases / frees up the blocks of the workspace 122 using the LRU mechanism, and the flow returns to step 606 .
[0034] Step 618 : The cache controller 130 loads the object A or the group G from the DRAM 150 to the workspace 122 .
[0035] Figure 7 2 is a diagram showing a microcontroller 700 according to another embodiment of the present invention. Figure 7As shown, the microcontroller 700 includes a CPU 710, a memory such as an SRAM 720, an object-based memory management unit (MMU) 715, a cache controller 730, and a hardware cache 740. The SRAM 720 includes at least a workspace 722. The cache controller 730 includes an object-oriented policy manager 732, an object allocator 734, and a dynamic loader 736. In this embodiment, the cache controller 730 is used to manage the workspace 722, and the cache controller 730 is implemented by pure software. In addition, the microcontroller 700 is coupled to a DRAM 750 having a power supply unit 752 and an object pool 754. The microcontroller 700 is similar to Figure 1 The only difference is that the microcontroller 700 also includes an object-based MMU 715. The object-based MMU 715 can provide virtual address and physical address mapping for the CPU 710, the memories 720 and 740, and the cache controller 730 can send control signals to modify the object-based MMU 715 to change objects between the hardware cache 740 and the software cache (i.e., SRAM 720). As those skilled in the art can read Figure 1-Figure 6 The operation of the microcontroller 700 should be understood after the embodiments, and further description is omitted here.
[0036] Briefly, in the cache management method and microcontroller of the present invention, a cache controller with an object-oriented strategy is used to manage objects of SRAM and DRAM. The cache management method of the embodiment of the present invention can effectively access DRAM and reduce the overhead of SRAM, so that the microcontroller can be used in ultra-low power consumption applications.
[0037] Various aspects of the devices and techniques described herein may be used alone, in combination, or in various arrangements not specifically discussed in the embodiments described in the foregoing description, and are therefore not limited in their application to the details of the foregoing components and arrangements or to the details shown in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.
[0038] In some embodiments, the terms "approximately", "substantially" and "substantially" may be used to indicate a range of less than ±10% of a target value and may include the target value, for example: less than ±5% of a target value, less than ±1% of a target value.
[0039] The use of ordinal terms such as "first", "second", "third" etc. in the claims to modify claim elements does not imply any priority or order, but serves merely as labels to distinguish one claim element with a particular name from another claim element with the same name.
[0040] Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.
Claims
1. A microcontroller, characterized in that: include: processor; a first memory coupled to the processor, wherein the first memory includes at least a workspace; a cache controller, coupled to the first memory, for managing a working space of the first memory and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner; Wherein, the cache controller comprises: an object-oriented policy manager for providing at least one cache policy indicating a relationship between a plurality of objects; an object allocator, coupled to the object-oriented policy manager, for referencing the at least one cache policy to determine at least one object; and a dynamic loader, coupled to the object allocator, for loading at least one object determined by the object allocator from the second memory into the workspace of the first memory; The at least one cache policy includes an exclusive policy indicating a plurality of specific objects that are never used simultaneously by the processor.
2. The microcontroller according to claim 1, characterized in that The second memory is a dynamic random access memory, and the cache controller is further arranged to control a power supply of the second memory.
3. The microcontroller according to claim 1, characterized in that The cache controller is implemented by software, and the microcontroller further comprises a hardware cache coupled between the processor and the second memory, and the hardware cache is arranged to store data read from the second memory.
4. The microcontroller according to claim 3, characterized in that: The microcontroller also includes: A memory management unit is coupled between the processor, the first memory and the hardware cache, and is used to provide virtual address and physical address mapping operations.
5. The microcontroller according to claim 4, characterized in that: The memory management unit also refers to a control signal of the cache controller to manage objects of the first memory and the hardware cache.
6. The microcontroller according to claim 1, characterized in that: The at least one cache policy is programmable.
7. The microcontroller according to claim 1, characterized in that: The at least one cache policy also includes a group policy indicating a plurality of specific objects that are always used together.
8. The microcontroller according to claim 7, characterized in that: When one of the specific objects in the group policy is to be loaded, the dynamic loader simultaneously loads all the specific objects in the group policy from the second memory to the workspace of the first memory.
9. The microcontroller according to claim 1, characterized in that: When one of the multiple specific objects in the exclusive policy is to be loaded from the second memory to the workspace of the first memory, if there are other specific objects in the exclusive policy in the workspace of the first memory, the dynamic loader will move the other specific objects from the workspace of the first memory to the second memory.
10. A cache management method, characterized in that: include: providing a first memory having a workspace; and dynamically loading at least one object from a second memory to the workspace of the first memory in an object-oriented manner using a cache controller; The step of dynamically loading the at least one object from the second memory to the working space of the first memory using the cache controller in an object-oriented manner comprises: providing at least one cache policy indicating a relationship between a plurality of objects; determining at least one object with reference to the at least one cache policy; and loading the at least one object from the second memory into the workspace of the first memory; Wherein, the at least one cache policy includes an exclusive policy indicating a plurality of specific objects that are never used simultaneously by the processor.
11. The cache management method according to claim 10, characterized in that: The second memory is a dynamic random access memory, and the cache management method further comprises: The cache controller is used to control power to the second memory.
12. The cache management method according to claim 10, characterized in that: The cache controller is implemented by software, and the cache management method further includes: A hardware cache coupled between the processor and the second memory is provided to store data read from the second memory.
13. The cache management method according to claim 12, characterized in that: Also includes: A memory management unit is provided coupled between the processor, the first memory and the hardware cache to provide virtual address and physical address mapping operations.
14. The cache management method according to claim 13, characterized in that: The memory management unit also refers to a control signal of the cache controller to manage objects of the first memory and the hardware cache.
15. The cache management method according to claim 10, characterized in that: The at least one cache policy is programmable.
16. The cache management method according to claim 10, characterized in that: The at least one cache policy further includes a group policy indicating a plurality of specific objects, and when one of the specific objects in the group policy is loaded, all the specific objects in the group policy are simultaneously loaded from the second memory to the workspace of the first memory.
17. The cache management method according to claim 10, characterized in that: When one of the multiple specific objects in the exclusive policy is loaded from the second memory into the workspace of the first memory, if there are other specific objects in the exclusive policy in the workspace of the first memory, the other specific objects are moved from the workspace of the first memory to the second memory.