Semiconductor device

Abstract

The present disclosure provides a semiconductor device. A semiconductor device includes: a substrate; a first electrode including a first hole; a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole; a second electrode on the first dielectric layer; a second dielectric layer on the second electrode; a third electrode on the second dielectric layer and including a second hole; and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. Sidewalls of the first contact plug are disengaged from direct contact with sidewalls of the first hole and sidewalls of the second hole, and have a stepped portion positioned adjacent to an upper surface of the second electrode.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to semiconductor devices, and more particularly, to metal-insulator-metal (MIM) capacitors. Background Art

[0002] As the integration density of semiconductor devices (e.g., dynamic random access memory (DRAM) devices) increases, the area of a unit cell in a semiconductor device decreases, and thus the area of one or more capacitors in the semiconductor device also decreases. However, for integrating semiconductor devices, it is desirable to increase the capacitance of capacitors.

[0003] When the thickness of a capacitor dielectric layer of a capacitor is decreased to increase the capacitance of the capacitor, the leakage current of the capacitor increases. Thus, a high dielectric layer can be used as the capacitor dielectric layer of the capacitor. However, when the high dielectric layer is used as the capacitor dielectric layer in a capacitor, in the case where the upper electrode of the capacitor is formed of polysilicon, a low dielectric layer is formed between the high dielectric layer and the upper electrode. As a result, the desired capacitance of the capacitor cannot be obtained. Thus, a metal-insulator-metal (MIM) capacitor can be used in a semiconductor device instead of a metal-insulator-semiconductor (MIS) capacitor. Summary of the Invention

[0004] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate; a first electrode including a first hole; a first dielectric layer on an upper surface of the first electrode and filling at least a portion of the first hole; a second electrode on the first dielectric layer; a second dielectric layer on the second electrode; a third electrode on the second dielectric layer, the third electrode including a second hole; and a first contact plug extending through the first hole, the second electrode, the second dielectric layer, and the second hole. Sidewalls of the first contact plug may be disengaged from direct contact with the first electrode and the third electrode. The sidewalls of the first contact plug may have a stepped portion. The stepped portion of the sidewalls of the first contact plug may be adjacent to an upper surface of the second electrode.

[0005] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate; a first electrode on the substrate; a first dielectric layer on the first electrode; a second electrode on the first dielectric layer; a second dielectric layer on the second electrode; a third electrode on the second dielectric layer; and a first contact plug extending through the first electrode and the third electrode and contacting the first electrode and the third electrode. The first contact plug may include a first portion, a second portion, and a third portion, the first portion being at least partially between a lower surface of the first electrode and the substrate, the second portion being at least partially away from an upper surface of the substrate with respect to an upper surface of the third electrode, and the third portion being at least partially between an upper surface of the first electrode and a lower surface of the third electrode. A sidewall of the first portion may be offset from a sidewall of the third portion. A sidewall of the third portion may be offset from a sidewall of the second portion.

[0006] According to some example embodiments of the inventive concept, a semiconductor device may include: a substrate; a first electrode on the substrate; a first dielectric layer on the first electrode; a second electrode on the first dielectric layer, the second electrode including a first hole; a second dielectric layer on the second electrode, the second dielectric layer at least partially filling the first hole; a third electrode on the second dielectric layer; and a first contact plug extending through the first electrode, the first dielectric layer, the first hole, and the third electrode. The first contact plug may cover at least one of a part of an upper surface of the first electrode and a part of an upper surface of the third electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view showing a semiconductor device according to some example embodiments of the inventive concept.

[0008] Figure 2 is along Figure 1 line I-I' of, showing a semiconductor device according to some example embodiments of the inventive concept.

[0009] Figure 3A is Figure 2 an enlarged view of part A of.

[0010] Figure 3B is Figure 2 an enlarged view of part B of.

[0011] Figure 4 is along Figure 1 line I-I' of, showing a semiconductor device according to some example embodiments of the inventive concept.

[0012] Figure 5 is along Figure 1A cross-sectional view taken along line I-I' shows a semiconductor device according to some example embodiments of the inventive concept.

[0013] Figure 6 is a cross-sectional view taken along Figure 1 line I-I' and shows a semiconductor device according to some example embodiments of the inventive concept.

[0014] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F and Figure 7G show a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept and are cross-sectional views taken along Figure 1 line I-I'. DETAILED DESCRIPTION

[0015] Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Throughout this application, like reference numerals may refer to like elements.

[0016] Figure 1 is a plan view showing a semiconductor device according to some example embodiments of the inventive concept. Figure 2 is taken along Figure 1 line I-I' and shows a semiconductor device according to some example embodiments of the inventive concept. Figure 3A is Figure 2 an enlarged view of part A of Figure 3B is Figure 2 an enlarged view of part B of

[0017] Referring to Figure 1 and Figure 2 , a first interlayer insulating layer 101 may be disposed on an upper surface 100U of a substrate 100. The substrate 100 may be, for example, a silicon single crystal wafer or a silicon-on-insulator (SOI) substrate. The first interlayer insulating layer 101 may include an insulating material such as silicon oxide or silicon nitride. A first lower wiring layer 103 may be disposed in the first interlayer insulating layer 101. An upper surface of the first lower wiring layer 103 may be coplanar with an upper surface of the first interlayer insulating layer 101. The first lower wiring layer 103 may include a metal such as copper, aluminum, or tungsten. A first buffer insulating layer 105 may be disposed on the upper surface of the first interlayer insulating layer 101. The first buffer insulating layer 105 may cover a part of the upper surface of the first lower wiring layer 103 and the entire upper surface of the first interlayer insulating layer 101. The first buffer insulating layer 105 may include, for example, silicon carbonitride (SiCN).

[0018] The second interlayer insulating layer 107 may be disposed on the first buffer insulating layer 105. The second interlayer insulating layer 107 may cover the upper surface of the first buffer insulating layer 105. The second interlayer insulating layer 107 may include an insulating material such as silicon oxide or silicon nitride. The second buffer insulating layer 109 may be disposed on the second interlayer insulating layer 107. The second buffer insulating layer 109 may cover the upper surface of the second interlayer insulating layer 107. The second buffer insulating layer 109 may include, for example, silicon carbonitride (SiCN). The third interlayer insulating layer 111 may be disposed on the second buffer insulating layer 109. The third interlayer insulating layer 111 may cover the upper surface of the second buffer insulating layer 109. The third interlayer insulating layer 111 may include an insulating material such as silicon oxide or silicon nitride.

[0019] It will be understood that, as described herein, an element “on” another element may be above or below the said another element. Additionally, an element “on” another element may be directly on the said another element such that the element is in direct contact with at least a portion of the said another element, or may be indirectly on the said another element such that the element is isolated from direct contact with the said another element by one or more intervening structures and / or spaces.

[0020] The second lower wiring layer 113 may be disposed in the second buffer insulating layer 109 and the third interlayer insulating layer 111. The second lower wiring layer 113 may penetrate the third interlayer insulating layer 111 and the second buffer insulating layer 109. The upper surface of the second lower wiring layer 113 may be coplanar with the upper surface of the third interlayer insulating layer 111. The second lower wiring layer 113 may include a metal, such as copper, aluminum, or tungsten. The third lower wiring layer 115 may be disposed in the third interlayer insulating layer 111 and the second buffer insulating layer 109. The third lower wiring layer 115 may penetrate the third interlayer insulating layer 111 and the second buffer insulating layer 109. The third lower wiring layer 115 may be spaced apart from the second lower wiring layer 113. The upper surface of the third lower wiring layer 115 may be coplanar with the upper surface of the third interlayer insulating layer 111. The third lower wiring layer 115 may include a metal, such as copper, aluminum, or tungsten. The fourth lower wiring layer 117 may be disposed in the second buffer insulating layer 109 and the third interlayer insulating layer 111. The fourth lower wiring layer 117 may penetrate the third interlayer insulating layer 111 and the second buffer insulating layer 109. The fourth lower wiring layer 117 may be spaced apart from the second lower wiring layer 113 and the third lower wiring layer 115. The upper surface of the fourth lower wiring layer 117 may be coplanar with the upper surface of the third interlayer insulating layer 111. The fourth lower wiring layer 117 may be electrically connected to a resistor. The fourth lower wiring layer 117 may include a metal, such as copper, aluminum, or tungsten. The conductive through-via 119 may be disposed between the first lower wiring layer 103 and the third lower wiring layer 115. The conductive through-via 119 may penetrate the first buffer insulating layer 105 and the second interlayer insulating layer 107. The conductive through-via 119 may contact the first lower wiring layer 103 and the third lower wiring layer 115 and may be electrically connected between the first lower wiring layer 103 and the third lower wiring layer 115. The conductive through-via 119 may include a metal, such as copper, aluminum, or tungsten.

[0021] The third buffer insulating layer 121 may be disposed on the third interlayer insulating layer 111. The third buffer insulating layer 121 may cover the upper surfaces of the second to fourth lower wiring layers 113, 115, and 117 and the upper surface of the third interlayer insulating layer 111. The third buffer insulating layer 121 may include, for example, silicon carbonitride (SiCN). The fourth interlayer insulating layer 123 may be disposed on the third buffer insulating layer 121. The thickness of the fourth interlayer insulating layer 123 may be greater than the thickness of each of the first to third interlayer insulating layers 101, 107, and 111. The fourth interlayer insulating layer 123 may include an insulating material, such as silicon oxide or silicon nitride.

[0022] The first electrode 201 may be disposed on the upper surface 123U of the fourth interlayer insulating layer 123 and may be in contact with the upper surface 123U of the fourth interlayer insulating layer 123, such that the first through fourth interlayer insulating layers 101, 107, 111, and 123 are between the upper surface 100U of the substrate 100 and the first electrode 201. The first electrode 201 may overlap perpendicularly with the second lower wiring layer 113 and the third lower wiring layer 115. The first electrode 201 may not be disposed on the fourth lower wiring layer 117 or may not overlap perpendicularly with the fourth lower wiring layer 117. The first electrode 201 may include a first hole H1 therein. The first hole H1 may overlap perpendicularly with the second lower wiring layer 113 (e.g., overlap in a vertical direction perpendicular to the upper surface 100U of the substrate 100). The first hole H1 may expose a part of the upper surface of the fourth interlayer insulating layer 123. The first electrode 201 may include, for example, TaN, Ta, Al, Ti, TiN, TaSiN, WN, and / or WSiN.

[0023] The first dielectric layer 203 may be disposed on the first electrode 201. As Figure 2 and Figure 3A shown, the first dielectric layer 203 may be on the upper surface 201U and sidewalls 201S of the first electrode 201 and may cover the upper surface 201U and sidewalls 201S of the first electrode 201. The first dielectric layer 203 may be disposed on the bottom surface H1B and sidewalls H1S of the first hole H1. That is, the first dielectric layer 203 may be on the part of the upper surface 123U of the fourth interlayer insulating layer 123 exposed by the first hole H1, may be in contact with the part, and may thus cover the part. The first dielectric layer 203 may include, for example, Si3N4, Ta2O5, Al2O3, and / or ZrO2. As at least Figure 3A shown, the first dielectric layer 203 may include a part that fills at least a part of the first hole H1 (e.g., fills a limited part of the first hole H1 such that the remaining part of the first hole H1 is not filled by the first dielectric layer 203).

[0024] The second electrode 205 may be disposed on the first dielectric layer 203. The second electrode 205 may cover a part of the upper surface of the first dielectric layer 203. The second electrode 205 may overlap perpendicularly with the second lower wiring layer 113 and the third lower wiring layer 115. The second electrode 205 may not be disposed on the fourth lower wiring layer 117 or may not overlap perpendicularly with the fourth lower wiring layer 117. The second electrode 205 may fill the first hole H1 of the first electrode 201 in which the first dielectric layer 203 is disposed. For example, as Figure 3AAs shown, the second electrode 205 may include a portion that fills the remainder of the first hole H1 not filled by at least the portion of the first dielectric layer 203. The second electrode 205 may include a second hole H2 therein. The second hole H2 may vertically overlap with the third lower wiring layer 115. The second hole H2 may expose a portion of the upper surface of the first dielectric layer 203. The second electrode 205 may include, for example, TaN, Ta, Al, Ti, TiN, TaSiN, WN, and / or WSiN.

[0025] The second dielectric layer 207 may be disposed on the second electrode 205. The second dielectric layer 207 may cover the upper surface and sidewalls of the second electrode 205. The second dielectric layer 207 may be disposed on the bottom surface H2B and sidewalls H2S of the second hole H2. As at least Figure 3B shown, the second dielectric layer 207 may include a portion that fills at least a part of the second hole H2 (e.g., fills a limited part of the second hole H2 such that the remainder of the second hole H2 is not filled by the second dielectric layer 207). The second dielectric layer 207 may cover the portion of the upper surface 203U of the first dielectric layer 203 exposed by the second hole H2. The second dielectric layer 207 may contact the portion of the upper surface 203U of the first dielectric layer 203 exposed by the second hole H2. The second dielectric layer 207 may contact the portion of the upper surface 203U of the first dielectric layer 203 above the fourth lower wiring layer 117. The second dielectric layer 207 may include, for example, Si3N4, Ta2O5, Al2O3, and / or ZrO2.

[0026] The third electrode 209 may be disposed on the second dielectric layer 207. The third electrode 209 may cover the upper surface and sidewalls of the second dielectric layer 207. For example, as Figure 3B shown, the third electrode 209 may include a portion that fills the remainder of the second hole H2 not filled by the portion of the second dielectric layer 207. The third electrode 209 may vertically overlap with the second lower wiring layer 113 and the third lower wiring layer 115. The third electrode 209 may not be disposed on the fourth lower wiring layer 117 or vertically overlap with the fourth lower wiring layer 117. The third electrode 209 may include a third hole H3 therein. As Figure 3AAs shown, the third hole H3 may overlap with the first hole H1 of the first electrode 201 partially or completely perpendicularly (e.g., partially or completely overlap in a direction perpendicular to the upper surface 100U of the substrate 100). The third hole H3 may expose a part of the upper surface of the second dielectric layer 207. The third electrode 209 may fill the second hole H2 of the second electrode 205 in which the second dielectric layer 207 is provided. The third electrode 209 may include, for example, TaN, Ta, Al, Ti, TiN, TaSiN, WN, and / or WSiN. The fifth interlayer insulating layer 211 may be provided on the third electrode 209. The fifth interlayer insulating layer 211 may cover the third electrode 209 and the second dielectric layer 207. The fifth interlayer insulating layer 211 may fill the third hole H3. The fifth interlayer insulating layer 211 may include an insulating material, such as silicon oxide or silicon nitride.

[0027] Referring to Figure 2 and Figure 3A , the first contact plug CP1 may extend through (e.g., penetrate) the first hole H1 of the first electrode 201 and the third hole H3 of the third electrode 209. The first contact plug CP1 may extend through the fifth interlayer insulating layer 211, the second electrode 205, the first dielectric layer 203, the second dielectric layer 207, the fourth interlayer insulating layer 123, and the third buffer insulating layer 121. As Figure 3A shown, the first contact plug CP1 may extend through a part of the first dielectric layer 203 that fills a part of the first hole H1 and a part of the second electrode 205 that fills the remaining part of the first hole H1 not filled by the first dielectric layer 203. The first contact plug CP1 may contact the second electrode 205 and the second lower wiring layer 113. The first contact plug CP1 may be electrically connected to the second electrode 205 and the second lower wiring layer 113. As Figure 3A shown, the upper surface S1 of the second electrode 205 may have a stepped profile. For example, as Figure 3A shown, a part S1a of the upper surface S1 of the second electrode 205 covered by the first contact plug CP1 may be a part recessed from a part S1b of the upper surface S1 of the second electrode 205 covered by the second dielectric layer 207 (e.g., overlapping in a vertical direction perpendicular to the upper surface 100U of the substrate 100). The first contact plug CP1 may contact the part S1a of the upper surface S1 of the second electrode 205 and, as Figure 3A shown, may cover the part S1a of the upper surface S1 of the second electrode 205. The first contact plug CP1 may be physically spaced apart (e.g., disengaged from direct contact) from both the first electrode 201 and the third electrode 209 and electrically insulated from both the first electrode 201 and the third electrode 209.

[0028] The first contact plug CP1 may include a first portion P1 and a second portion P2. The first portion P1 may be disposed at least partially on a portion S1a of the upper surface S1 of the second electrode 205 (e.g., at least partially away from the upper surface 100U of the substrate 100 relative to the upper surface S1). The second portion P2 may be disposed at least partially below the lower surface L1 of the second electrode 205 that contacts the uppermost surface of the first dielectric layer 203 (e.g., at least partially between the lower surface L1 and the upper surface 100U of the substrate 100). The second portion P2 may be disposed at least partially below the upper surface S1 of the second electrode 205 (e.g., at least partially between the upper surface S1 and the upper surface 100U of the substrate 100). The first portion P1 may extend through the third hole H3 of the third electrode 209, and the second portion P2 may extend through the first hole H1 of the first electrode 201. The width Wa1 of the first portion P1 extending through the third hole H3 may be less than the width W1 of the third hole H3. The first portion P1 may be spaced apart from the sidewall of the third hole H3. The width Wa2 of the second portion P2 extending through the first hole H1 may be less than the width W2 of the first hole H1. The second portion P2 may be spaced apart from the sidewall of the first hole H1. For example, a portion of the first dielectric layer 203 may be interposed between the second portion P2 and the sidewall of the first hole H1.

[0029] The first contact plug CP1 may have a sidewall SW1. As Figure 3A shown, the sidewall SW1 of the first contact plug CP1 may be physically spaced apart (e.g., out of direct contact) from both the first electrode 201 and the third electrode 209 and electrically insulated from both the first electrode 201 and the third electrode 209, for example, at least partially based on being directly covered by portions of the first dielectric layer 203, portions of the second electrode 205, and portions of the second dielectric layer 207 and being physically out of direct contact with the sidewall H3S of the third hole H3. The sidewall SW1 of the first contact plug CP1 may have a stepped portion SP. As Figure 3A shown, the stepped portion SP of the sidewall SW1 of the first contact plug CP1 may be positioned adjacent to the upper surface S1 of the second electrode 205 (e.g., between the portion S1b of the upper surface S1 of the second electrode 205 covered by the second dielectric layer 207 and the lower surface L1 of the second electrode 205). The portion S1a of the upper surface S1 and the inner sidewall 205IS of the second electrode 205 may contact (e.g., directly contact) the stepped portion SP of the sidewall SW1 of the first contact plug CP1. As Figure 3AAs shown, the sidewall SW1 of the first part P1 of the first contact plug CP1 can be offset to the sidewall SW1 of the second part P2 of the first contact plug CP1, such that there is a step change (e.g., a discontinuous change in width) in the sidewall SW1 between the first part P1 and the second part P2 (e.g., at the step portion SP). The width Wa1 of the first part P1 of the first contact plug CP1 can be greater than the width Wa2 of the second part P2 of the first contact plug CP1. The width Wa1 of the first part P1 of the first contact plug CP1 can gradually (e.g., continuously) decrease proportionally with increasing proximity to the second part P2 and / or proportionally with increasing proximity to the second electrode 205. The width of the second part P2 of the first contact plug CP1 can gradually (e.g., continuously) decrease proportionally with increasing proximity to the upper surface 100U of the substrate 100. The first contact plug CP1 can have a T shape. The first contact plug CP1 can include, for example, copper, aluminum, or tungsten.

[0030] Referring to Figure 2 and Figure 3B , the second contact plug CP2 can extend through (e.g., penetrate) the second hole H2 of the second electrode 205. The second contact plug CP2 can extend through (e.g., penetrate) the fifth interlayer insulating layer 211, the third electrode 209, the second dielectric layer 207, the first dielectric layer 203, the first electrode 201, the fourth interlayer insulating layer 123, and the third buffer insulating layer 121. The second contact plug CP2 can physically and electrically contact (e.g., directly contact) the third electrode 209, the first electrode 201, and the third lower wiring layer 115. The second contact plug CP2 can be physically spaced apart (e.g., out of direct contact) from the second electrode 205 and electrically insulated from the second electrode 205. The upper surface S2 of the first electrode 201 can have a stepped shape. For example, the portion S2a of the upper surface S2 of the first electrode 201 covered by the second contact plug CP2 can be a recessed portion from the portion S2b of the upper surface S2 of the first electrode 201 covered by the first dielectric layer 203. The upper surface S3 of the third electrode 209 can have a stepped profile. For example, the portion S3a of the upper surface S3 of the third electrode 209 covered by the second contact plug CP2 can be a recessed portion from the portion S3b of the upper surface S3 of the third electrode 209 covered by the fifth interlayer insulating layer 211.

[0031] The second contact plug CP2 can contact a portion S2a of the upper surface S2 of the first electrode 201 and a portion S3a of the upper surface S3 of the third electrode 209. The second contact plug CP2 can be spaced apart from the sidewall H2S of the second via H2. For example, a portion of the second dielectric layer 207 can be interposed between the sidewall H2S of the second via H2 and the second contact plug CP2. A portion of the third electrode 209 that fills a portion of the second via H2 can be interposed between the second contact plug CP2 and the portion of the second dielectric layer 207 within the second via H2.

[0032] The second contact plug CP2 can include a first portion P1a, a second portion P2a, and a third portion P3a. As Figure 3B shown, the third portion P3a can be between the first portion P1a and the second portion P2a. As Figure 3B shown, the first portion P1a can be at least partially disposed below the lower surface L2 of the first electrode 201 (e.g., at least partially between the lower surface L2 and the upper surface 100U of the substrate 100). As Figure 3B shown, the first portion P1a can be disposed below the upper surface S2 of the first electrode 201 (e.g., between the upper surface S2 and the upper surface 100U of the substrate 100). As Figure 3B shown, the second portion P2a can be at least partially disposed on the recessed portion S3a of the upper surface S3 of the third electrode 209 (e.g., at least partially away from the upper surface 100U of the substrate 100 relative to the upper surface S3 of the third electrode 209). The third portion P3a can be at least partially disposed between the lower surface L3 of the third electrode 209 and the recessed portion S2a of the upper surface S2 of the first electrode 201. The third portion P3a can extend through the second via H2 and can penetrate (e.g., extend through) both the first dielectric layer 203 and the second dielectric layer 207. As Figure 3B shown, for example, the third portion P3a can extend through the portion of the second dielectric layer 207 that fills a portion of the second via H2 and the portion of the third electrode 209 that fills the remaining portion of the second via H2 not filled by the second dielectric layer 207. As Figure 3B shown, a portion of the third electrode 209 can be between the second dielectric layer 207 and the second contact plug CP2 and can also be at least partially within the second via H2 such that this portion of the third electrode 209 at least partially fills the second via H2. The width Wa3 of the third portion P3a extending through the second via H2 can be less than the width W3 of the second via H2. As Figure 3BAs shown, the width Waa2 of the second portion P2a may be greater than the width Waa1 of the first portion P1a and the width Wa3 of the third portion P3a. The width Wa3 of the third portion P3a may be greater than the width Waa1 of the first portion P1a. That is, the width Waa1 of the first portion P1a may be less than the width Waa2 of the second portion P2a and the width Wa3 of the third portion P3a. The width Waa2 of the second portion P2a may gradually (e.g., continuously) decrease in proportion to approaching the third portion P3a. The width Waa1 of the first portion P1a may gradually (e.g., continuously) decrease in proportion to approaching the upper surface 100U of the substrate 100.

[0033] The second contact plug CP2 may have a sidewall SW2. The sidewall SW2 of the second contact plug CP2 may have a plurality of stepped portions (e.g., SP1 and SP2). The first stepped portion SP1 may be positioned adjacent to the upper surface S2 of the first electrode 201. The portion S2a of the upper surface S2 of the first electrode 201 and the inner sidewall 201IS of the first electrode 201 may contact the first stepped portion SP1 of the sidewall SW2 of the second contact plug CP2, so that the third portion P3a may cover the portion S2a of the upper surface S2 of the first electrode 201. The first stepped portion SP1 may be located between the lower surface L2 of the first electrode 201 and the upper surface S2 of the first electrode 201. Specifically, the first stepped portion SP1 may be located between the lower surface L2 of the first electrode 201 and the portion (e.g., the portion S2b of the upper surface S2) of the upper surface S2 of the first electrode 201 covered by the first dielectric layer 203 (e.g., overlapping in a vertical direction perpendicular to the upper surface 100U of the substrate 100). The second stepped portion SP2 may be positioned adjacent to the upper surface S3 of the third electrode 209. The portion S3a of the upper surface S3 and the inner sidewall 209IS of the third electrode 209 may contact the second stepped portion SP2 of the sidewall SW2 of the second contact plug CP2, so that the second portion P2a may cover the portion S3a of the upper surface S3 of the third electrode 209. The second stepped portion SP2 may be located between the lower surface L3 of the third electrode 209 and the upper surface S3 of the third electrode 209. Specifically, the second stepped portion SP2 may be located between the lower surface L3 of the third electrode 209 and the portion (e.g., the portion S3b of the upper surface S3) of the upper surface S3 of the third electrode 209 covered by the fifth interlayer insulating layer 211 (e.g., overlapping in a vertical direction perpendicular to the upper surface 100U of the substrate 100). As Figure 3B shown, the sidewall SW2 of the first portion P1a of the second contact plug CP2 may be offset to the sidewall SW2 of the third portion P3a of the second contact plug CP2, so that there is a stepped change (e.g., a discontinuous change in width) in the sidewall SW2 between the first portion P1a and the third portion P3a (e.g., at the first stepped portion SP1). AsFigure 3B As shown, the sidewall SW2 of the third part P3a of the second contact plug CP2 may be offset to the sidewall SW2 of the second part P2a of the second contact plug CP2, such that there is a step change (e.g., a discontinuous change in width) in the sidewall SW2 between the second part P2a and the third part P3a (e.g., at the second step part SP2). The second contact plug CP2 may include a metal, such as copper, aluminum, or tungsten.

[0034] According to some example embodiments of the inventive concept, the first contact plug CP1 may cover a portion S1a of the upper surface S1 of the second electrode 205 and may contact the second electrode 205. The second contact plug CP2 may cover a portion S2a of the upper surface S2 of the first electrode 201 and a portion S3a of the upper surface S3 of the third electrode 209 and may contact the first electrode 201 and the third electrode 209. Thus, the second contact plug CP2 may cover at least one of a portion (e.g., portion S2a) of the upper surface S2 of the first electrode 201 and a portion (e.g., portion S3a) of the upper surface S3 of the third electrode 209. The contact area between the first contact plug CP1 and the second electrode 205 may be increased, and the contact area between each of the first electrode 201 and the third electrode 209 and the second contact plug CP2 may be increased. Accordingly, the resistance of each of the first contact plug CP1 and the second contact plug CP2 may be reduced.

[0035] Referring again to Figure 2 , the third contact plug CP3 may contact the fourth lower wiring layer 117. The third contact plug CP3 may extend through the third buffer insulating layer 121, the fourth interlayer insulating layer 123, the first dielectric layer 203, the second dielectric layer 207, and the fifth interlayer insulating layer 211 and may contact the upper surface of the fourth lower wiring layer 117 to be electrically connected to the fourth lower wiring layer 117. The third contact plug CP3 may include a metal, such as copper, aluminum, or tungsten.

[0036] The first upper wiring layer 221, the second upper wiring layer 223, and the third upper wiring layer 225 may be disposed on the fifth interlayer insulating layer 211. The first upper wiring layer 221 may be disposed on the upper surface of the first contact plug CP1 and may be electrically connected to the first contact plug CP1. The second upper wiring layer 223 may be disposed on the upper surface of the second contact plug CP2 and may be electrically connected to the second contact plug CP2. The third upper wiring layer 225 may be disposed on the upper surface of the third contact plug CP3 and may be electrically connected to the third contact plug CP3.

[0037] Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 showing a semiconductor device according to some example embodiments of the inventive concept.

[0038] Referring to Figure 4 , a third portion P3a of the second contact plug CP2 extending through the second hole H2 of the second electrode 205 may contact a portion of the second dielectric layer 207 covering the sidewall of the second hole H2. For example, the third electrode 209 may not be disposed between the third portion P3a of the second contact plug CP2 and the portion of the second dielectric layer 207 covering the sidewall of the second hole H2. That is, different from Figure 2 shown, the third electrode 209 may not fill the second hole H2.

[0039] Figure 5 is a cross-sectional view taken along line I-I' of Figure 1 , showing a semiconductor device according to some example embodiments of the inventive concept.

[0040] Referring to Figure 5 , the first contact plug CP1 may include a first portion P1 on the upper surface S1 of the second electrode 205 and a second portion P2 below the upper surface S1 of the second electrode 205. The first contact plug CP1 may extend through the second electrode 205 and contact the second electrode 205, but may not cover the upper surface S1 of the second electrode 205. For example, the sidewall SW1 of the first contact plug CP1 may be flat. That is, the sidewall SW1 of the first portion P1 of the first contact plug CP1 may be aligned with the sidewall SW1 of the second portion P2 of the first contact plug CP1. As Figure 5 shown, the sidewall SW1 of the first portion P1 and the sidewall SW1 of the second portion P2 may be inclined with respect to the upper surface 100U of the substrate 100. The sidewall SW1 of the first portion P1 and the sidewall SW1 of the second portion P2 may be inclined and aligned with each other. In some embodiments, the sidewall SW1 of the first portion P1 and the sidewall SW1 of the second portion P2 may be perpendicular to the upper surface 100U of the substrate 100. That is, the sidewall SW1 of the first portion P1 and the sidewall SW1 of the second portion P2 may be perpendicularly aligned with each other (e.g., aligned in a vertical direction perpendicular to the upper surface 100U of the substrate 100). The first contact plug CP1 may have a tapered cross-section or a rectangular cross-section.

[0041] Figure 6 is a cross-sectional view taken along line I-I' of Figure 1 , showing a semiconductor device according to some example embodiments of the inventive concept.

[0042] Referring to Figure 6, the second contact plug CP2 may include a first portion P1a, a second portion P2a, and a third portion P3a. The first portion P1a may be disposed below the upper surface S2 of the first electrode 201. The second portion P2a may be disposed on the upper surface S3 of the third electrode 209. The third portion P3a may be disposed between the first portion P1a and the second portion P2a. The second contact plug CP2 may extend through the first electrode 201 and the third electrode 209 and may contact the first electrode 201 and the third electrode 209, but may not cover the upper surface S2 of the first electrode 201 and the upper surface S3 of the third electrode 209. For example, the sidewall SW2 of the second contact plug CP2 may be flat. That is, in the second contact plug CP2, the sidewall SW2 of the first portion P1a, the sidewall SW2 of the second portion P2a, and the sidewall SW2 of the third portion P3a may be aligned with each other, such as Figure 6 shown, such that the sidewall SW2 of the first portion P1a, the sidewall SW2 of the second portion P2a, and the sidewall SW2 of the third portion P3a define respective portions of a surface of a single continuous three-dimensional geometry (e.g., respective portions of a single conical shape or a conical surface, as Figure 6 shown).

[0043] As Figure 6 shown, in the second contact plug CP2, the sidewall SW2 of the first portion P1a, the sidewall SW2 of the second portion P2a, and the sidewall SW2 of the third portion P3a may be inclined with respect to the upper surface 100U of the substrate 100 and may be aligned with each other in an inclined manner. In some embodiments, in the second contact plug CP2, the sidewall SW2 of the first portion P1a, the sidewall SW2 of the second portion P2a, and the sidewall SW2 of the third portion P3a may be perpendicular to the upper surface 100U of the substrate 100 and may be aligned with each other vertically (e.g., aligned in a vertical direction perpendicular to the upper surface 100U of the substrate 100). The second contact plug CP2 may have a tapered cross-section or a rectangular cross-section.

[0044] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F and Figure 7G show methods of manufacturing a semiconductor device according to some example embodiments of the inventive concept and are cross-sectional views taken along the line Figure 1 I-I'

[0045] Referring to Figure 7A, the first interlayer insulating layer 101 may be formed on the substrate 100. The first lower wiring layer 103 may be formed in the first interlayer insulating layer 101. The upper surface of the first lower wiring layer 103 may be coplanar with the upper surface of the first interlayer insulating layer 101. The first buffer insulating layer 105 may be formed on the upper surface of the first interlayer insulating layer 101. The first buffer insulating layer 105 may cover a part of the upper surface of the first lower wiring layer 103. The second interlayer insulating layer 107 may be formed to cover the upper surface of the first buffer insulating layer 105. The conductive through-via 119 may be formed to extend through the first buffer insulating layer 105 and the second interlayer insulating layer 107. The conductive through-via 119 may contact the upper surface of the first lower wiring layer 103. The second buffer insulating layer 109 and the third interlayer insulating layer 111 may be sequentially formed on the upper surface of the second interlayer insulating layer 107. The second lower wiring layer 113, the third lower wiring layer 115, and the fourth lower wiring layer 117 may be disposed in the second buffer insulating layer 109 and the third interlayer insulating layer 111. The third lower wiring layer 115 may contact the upper surface of the conductive through-via 119. The upper surfaces of the second to fourth lower wiring layers 113, 115, and 117 may be coplanar with the upper surface of the third interlayer insulating layer 111.

[0046] The third buffer insulating layer 121 may be formed on the upper surface of the third interlayer insulating layer 111. The third buffer insulating layer 121 may cover the upper surface of the third interlayer insulating layer 111 and the upper surfaces of the second to fourth lower wiring layers 113, 115, and 117. The fourth interlayer insulating layer 123 may be formed to cover the upper surface of the third buffer insulating layer 121. The first electrode layer EL1 may be formed on the upper surface of the fourth interlayer insulating layer 123. The first electrode layer EL1 may include, for example, TaN, Ta, Al, Ti, TiN, TaSiN, WN, and / or WSiN.

[0047] Referring to Figure 7B , the first mask pattern MP1 may be formed on the first electrode layer EL1. The first electrode layer EL1 may be patterned using the first mask pattern MP1 as an etching mask to form the first electrode 201. The first mask pattern MP1 may be, for example, a photoresist pattern. A part of the upper surface of the fourth interlayer insulating layer 123 may be exposed by the patterning process of the first electrode layer EL1. The first electrode 201 may include a first hole H1 and a fifth hole H5. The first hole H1 may be formed to vertically overlap with the second lower wiring layer 113 (e.g., overlap in the vertical direction perpendicular to the upper surface 100U of the substrate 100). The fifth hole H5 may be formed to vertically overlap with the third lower wiring layer 115. The patterning process of the first electrode layer EL1 may be performed, for example, by a dry etching process. After performing the patterning process of the first electrode layer EL1, the first mask pattern MP1 may be removed by, for example, an ashing process or a lift-off process.

[0048] Referring to Figure 7C , the first dielectric layer 203 may be formed on the first electrode 201 and the fourth interlayer insulating layer 123. The first dielectric layer 203 may conformally cover the upper surface and sidewalls of the first electrode 201 and the upper surface of the fourth interlayer insulating layer 123. The first dielectric layer 203 may be formed to cover the bottom surface and sidewalls of the first hole H1 and the bottom surface and sidewalls of the third hole H5. For example, the first dielectric layer 203 may conformally cover the sidewalls of the first hole H1 and the portion of the upper surface of the fourth interlayer insulating layer 123 exposed by the first hole H1. For example, the first dielectric layer 203 may conformally cover the sidewalls of the fifth hole H5 and the portion of the upper surface of the fourth interlayer insulating layer 123 exposed by the fifth hole H5. The first dielectric layer 203 may include, for example, Si3N4, Ta2O5, Al2O3, and / or ZrO2.

[0049] The second electrode layer EL2 may be formed on the first dielectric layer 203. The second electrode layer EL2 may cover the upper surface of the first dielectric layer 203. The second electrode layer EL2 may fill the first hole H1 in which the first dielectric layer 203 is formed and the fifth hole H5 in which the first dielectric layer 203 is formed. The second electrode layer EL2 may include, for example, TaN, Ta, Al, Ti, TiN, TaSiN, WN, and / or WSiN.

[0050] Referring to Figure 7D , the second mask pattern MP2 may be formed on the second electrode layer EL2. The second electrode layer EL2 may be patterned using the second mask pattern MP2 as an etching mask to form the second electrode 205. The second mask pattern MP2 may be, for example, a photoresist pattern. The second electrode 205 may expose a portion of the upper surface of the first dielectric layer 203. The second electrode 205 may include a second hole H2 and a sixth hole H6. The second hole H2 may be formed to vertically overlap with the fifth hole H5 of the first electrode 201. The sixth hole H6 may be formed to vertically overlap with the first hole H1 of the first electrode 201. As an example, the width of the second hole H2 of the second electrode 205 may be greater than the width of the fifth hole H5 of the first electrode 201, and the width of the sixth hole H6 of the second electrode 205 may be less than the width of the first hole H1 of the first electrode 201.

[0051] The portion of the second electrode layer EL2 filling the fifth hole H5 of the first electrode 201 can be removed by a patterning process. Accordingly, a part of the first dielectric layer 203 can be exposed by the second hole H2. The portion of the second electrode layer EL2 filling the first hole H1 can be partially removed by a patterning process. A part of the upper surface of the first dielectric layer 203 can be exposed by the sixth hole H6 of the second electrode 205. After performing the patterning process of the second electrode layer EL2, a part of the second electrode 205 can remain on the portion of the sidewall of the first dielectric layer 203 covering the first hole H1. The patterning process of the second electrode layer EL2 can be performed, for example, by a dry etching process. After performing the patterning process of the second electrode layer EL2, the second mask pattern MP2 can be removed. The second mask pattern MP2 can be removed by, for example, an ashing process or a lift-off process.

[0052] Referring Figure 7E , a second dielectric layer 207 can be formed on the second electrode 205. The second dielectric layer 207 can conformally cover the upper surface and the sidewalls of the second electrode 205, the portion of the upper surface of the first dielectric layer 203 exposed by the second electrode 205, and the inner surface of the second hole H2 of the second electrode 205. The second dielectric layer 207 can fill the sixth hole H6 of the second electrode 205. The second dielectric layer 207 can include, for example, Si3N4, Ta2O5, Al2O3, and / or ZrO2. A third electrode layer EL3 can be formed on the second dielectric layer 207. The third electrode layer EL3 can conformally cover the upper surface of the second dielectric layer 207 and can fill the second hole H2 in which the second dielectric layer 207 is formed. The third electrode layer EL3 can include, for example, TaN, Ta, Al, Ti, TiN, TaSiN, WN, and / or WSiN.

[0053] Referring Figure 7F , a third mask pattern MP3 can be formed on the third electrode layer EL3. The third electrode layer EL3 can be patterned using the third mask pattern MP3 as an etching mask to form a third electrode 209. The third mask pattern MP3 can be, for example, a photoresist pattern. The third electrode 209 can expose a part of the upper surface of the second dielectric layer 207. The third electrode 209 can include a third hole H3 and a seventh hole H7. The third hole H3 can be formed to vertically overlap with the sixth hole H6 of the second electrode 205 and the first hole H1 of the first electrode 201. The seventh hole H7 can be formed to vertically overlap with the second hole H2 of the second electrode 205 and the fifth hole H5 of the first electrode 201. As an example, the width of the third hole H3 of the third electrode 209 can be greater than the width of the sixth hole H6 of the second electrode 205, and the width of the seventh hole H7 of the third electrode 209 can be smaller than the width of the second hole H2 of the second electrode 205.

[0054] The portion of the third electrode layer EL3 that fills the second hole H2 of the second electrode 205 can be partially removed by a patterning process. Accordingly, a part of the upper surface of the second dielectric layer 207 can be exposed by the seventh hole H7 of the third electrode 209. After performing the patterning process of the third electrode layer EL3, a part of the third electrode 209 can remain on the part of the sidewall of the second dielectric layer 207 that covers the second hole H2. A part of the upper surface of the second dielectric layer 207 can be exposed by the third hole H3 of the third electrode 209. The patterning process of the third electrode layer EL3 can be performed, for example, by a dry etching process. After performing the patterning process of the third electrode layer EL3, the third mask pattern MP3 can be removed. The third mask pattern MP3 can be removed by, for example, an ashing process or a lift-off process.

[0055] Referring to Figure 7G , a fifth interlayer insulating layer 211 can be formed on the third electrode 209 and the second dielectric layer 207. The fifth interlayer insulating layer 211 can be formed to fill the third hole H3 and the seventh hole H7 of the third electrode 209. The fifth interlayer insulating layer 211 can cover the upper surface and the sidewall of the third electrode 209 and the upper surface of the second dielectric layer 207.

[0056] A first through hole TH1, a second through hole TH2, and a third through hole TH3 can be formed. The first through hole TH1 can be formed to penetrate the fifth interlayer insulating layer 211, the second electrode 205, the second dielectric layer 207, the first dielectric layer 203, the fourth interlayer insulating layer 123, and the third buffer insulating layer 121. The first through hole TH1 can be formed in the first hole H1 of the first electrode 201, the sixth hole H6 of the second electrode 205, and the third hole H3 of the third electrode 209. A part of the upper surface and the inner sidewall of the second electrode 205 can be exposed by the first through hole TH1. The width of the first through hole TH1 formed on the upper surface of the second electrode 205 can be smaller than the width of the third hole H3 of the third electrode 209 and can be larger than the width of the sixth hole H6 of the second electrode 205. The width of the first through hole TH1 formed under the upper surface of the second electrode 205 can be smaller than the width of the first hole H1 of the first electrode 201. The first through hole TH1 can not expose the first electrode 201 and the third electrode 209. The first through hole TH1 can expose a part of the upper surface of the second lower wiring layer 113.

[0057] The second through-hole TH2 may be formed to pass through the fifth interlayer insulating layer 211, the third electrode 209, the second dielectric layer 207, the first dielectric layer 203, the first electrode 201, the fourth interlayer insulating layer 123, and the third buffer insulating layer 121. The second through-hole TH2 may be formed in the fifth hole H5 of the first electrode 201, the second hole H2 of the second electrode 205, and the seventh hole H7 of the third electrode 209. The second through-hole TH2 may expose a part of the upper surface and the inner sidewall of the third electrode 209 and a part of the upper surface and the inner sidewall of the first electrode 201. The width of the second through-hole TH2 formed on the upper surface of the third electrode 209 may be greater than the width of the seventh hole H7 of the third electrode 209. The width of the second through-hole TH2 formed on the upper surface of the first electrode 201 may be greater than the width of the fifth hole H5 of the first electrode 201. The second through-hole TH2 may not expose the second electrode 205. The second through-hole TH2 may expose a part of the upper surface of the third lower wiring layer 115.

[0058] The third through-hole TH3 may pass through the fifth interlayer insulating layer 211, the first dielectric layer 203, the second dielectric layer 207, the fourth interlayer insulating layer 123, and the third buffer insulating layer 121. The third through-hole TH3 may expose a part of the upper surface of the fourth lower wiring layer 117. The first through-hole TH1, the second through-hole TH2, and the third through-hole TH3 may be formed by an etching process. The etching process may be performed using an etching recipe for etching the fifth interlayer insulating layer 211, the first dielectric layer 203, the second dielectric layer 207, the fourth interlayer insulating layer 123, and the third buffer insulating layer 121. The etching recipe may have an etching selectivity with respect to the first to third electrodes 201, 205, and 209 and the second to fourth lower wiring layers 113, 115, and 117. The etching process may be performed by, for example, a dry etching process.

[0059] Refer again to Figure 2, the first contact plug CP1, the second contact plug CP2, and the third contact plug CP3 can be formed. The first contact plug CP1 can be formed in the first through hole TH1. The second contact plug CP2 can be formed in the second through hole TH2. The third contact plug CP3 can be formed in the third through hole TH3. The first contact plug CP1 can be formed to cover the portion of the upper surface and the inner sidewall of the second electrode 205 exposed by the first through hole TH1. The second contact plug CP2 can be formed to cover the portion of the upper surface and the inner sidewall of the third electrode 209 exposed by the second through hole TH2 and the portion of the upper surface and the inner sidewall of the first electrode 201 exposed by the second through hole TH2. The first to third upper wiring layers 221, 223, and 225 can be formed on the first to third contact plugs CP1, CP2, and CP3, respectively. For example, the first upper wiring layer 221 can be formed on the upper surface of the first contact plug CP1. The second upper wiring layer 223 can be formed on the upper surface of the second contact plug CP2. The third upper wiring layer 225 can be formed on the upper surface of the third contact plug CP3.

[0060] Although the inventive concept has been shown and described with reference to some exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

[0061] This application claims priority to Korean Patent Application No. 10-2019-0052419, filed with the Korean Intellectual Property Office on May 3, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a substrate; a first electrode including a first hole; a first dielectric layer on an upper surface of the first electrode and filling at least a part of the first hole; a second electrode on the first dielectric layer; a second dielectric layer on the second electrode; a third electrode on the second dielectric layer, the third electrode including a second hole; and a first contact plug extending through the first hole, the second electrode, the second dielectric layer, and the second hole, wherein sidewalls of the first contact plug are disengaged from direct contact with the first electrode and the third electrode, the sidewalls of the first contact plug have a stepped portion, and the stepped portion of the sidewalls of the first contact plug is adjacent to an upper surface of the second electrode, wherein a part of the second electrode is between the first dielectric layer and the first contact plug and at least partially fills the first hole.

2. The semiconductor device according to claim 1, wherein the stepped portion of the sidewalls of the first contact plug is between a portion of the upper surface of the second electrode covered by the second dielectric layer and a lower surface of the second electrode.

3. The semiconductor device according to claim 1, wherein the stepped portion of the sidewalls of the first contact plug contacts a part of the upper surface of the second electrode.

4. The semiconductor device according to claim 1, further comprising: a second contact plug extending through the first electrode, the first dielectric layer, the second dielectric layer, and the third electrode, the second contact plug contacting the first electrode and the third electrode, and the second contact plug being disengaged from direct contact with the second electrode, wherein sidewalls of the second contact plug have a plurality of stepped portions.

5. The semiconductor device according to claim 1, further comprising: a second contact plug extending through the first electrode, the first dielectric layer, the second dielectric layer, and the third electrode, the second contact plug contacting the first electrode and the third electrode, and the second contact plug being disengaged from direct contact with the second electrode, wherein the second contact plug covers a part of the upper surface of the first electrode and a part of the upper surface of the third electrode.

6. The semiconductor device according to claim 1, further comprising: a second contact plug extending through the first electrode, the first dielectric layer, the second dielectric layer, and the third electrode, the second contact plug contacting the first electrode and the third electrode, and the second contact plug being disengaged from direct contact with the second electrode, wherein the second contact plug includes a first portion between the upper surface of the first electrode and the upper surface of the substrate, a second portion at least partially away from the upper surface of the substrate relative to the upper surface of the third electrode, and a third portion between the first portion and the second portion, and The sidewalls of the first part, the sidewalls of the second part, and the sidewalls of the third part are aligned with each other to define respective portions of a surface of a single continuous three-dimensional geometry.

7. The semiconductor device according to claim 1, wherein the first contact plug includes a first portion that is at least partially away from the upper surface of the substrate relative to the upper surface of the second electrode; and a second portion that is at least partially between the lower surface of the second electrode and the upper surface of the substrate, the width of the first portion continuously decreases in proportion as it gets closer to the second electrode, and the width of the second portion continuously decreases in proportion as it gets closer to the upper surface of the substrate.

8. The semiconductor device according to claim 1, further comprising: an interlayer insulating layer between the upper surface of the substrate and the first electrode; a lower wiring layer between the interlayer insulating layer and the upper surface of the substrate; and a second contact plug extending through the interlayer insulating layer, the first dielectric layer, and the second dielectric layer, the second contact plug contacting the lower wiring layer, wherein the first electrode is on the upper surface of the interlayer insulating layer and in contact with the upper surface of the interlayer insulating layer, and a portion of the first dielectric layer is on a portion of the upper surface of the interlayer insulating layer and in contact with the portion of the upper surface of the interlayer insulating layer.

9. A semiconductor device, comprising: a substrate; a first electrode on the substrate; a first dielectric layer on the first electrode; a second electrode on the first dielectric layer; a second dielectric layer on the second electrode; a third electrode on the second dielectric layer; and a first contact plug extending through the first electrode and the third electrode and contacting the first electrode and the third electrode, wherein the first contact plug includes a first portion that is at least partially between the lower surface of the first electrode and the upper surface of the substrate, a second portion that is at least partially away from the upper surface of the substrate relative to the upper surface of the third electrode, and a third portion that is at least partially between the upper surface of the first electrode and the lower surface of the third electrode, wherein the sidewall of the first portion is offset to the sidewall of the third portion, wherein the sidewall of the third portion is offset to the sidewall of the second portion, wherein the second electrode includes a hole, the second dielectric layer includes a first portion that fills a portion of the hole, the third electrode includes a second portion that fills the remaining portion of the hole not filled by the first portion of the second dielectric layer, and the third portion of the first contact plug extends through both the second portion of the third electrode and the first portion of the second dielectric layer.

10. The semiconductor device according to claim 9, wherein the first contact plug is disengaged from direct contact with the second electrode, and the third portion of the first contact plug extends through both the first dielectric layer and the second dielectric layer.

11. The semiconductor device according to claim 9, wherein the second portion of the first contact plug covers a part of the upper surface of the third electrode, and the third portion of the first contact plug covers a part of the upper surface of the first electrode.

12. The semiconductor device according to claim 9, wherein the width of the second portion of the first contact plug is greater than the width of the third portion of the first contact plug, and the width of the third portion of the first contact plug is greater than the width of the first portion of the first contact plug.

13. The semiconductor device according to claim 9, further comprising: a second contact plug extending through the second electrode and contacting the second electrode.

14. The semiconductor device according to claim 13, wherein the second contact plug includes a first portion at least partially away from the upper surface of the substrate relative to the upper surface of the second electrode, and a second portion at least partially between the lower surface of the second electrode and the upper surface of the substrate, and the sidewall of the first portion of the second contact plug is offset to the sidewall of the second portion of the second contact plug.

15. The semiconductor device according to claim 13, wherein the second contact plug is disengaged from direct contact with the first electrode and the third electrode, and the second contact plug extends through both the first dielectric layer and the second dielectric layer.

16. The semiconductor device according to claim 13, wherein the first electrode includes a first hole, the third electrode includes a second hole vertically overlapping the first hole, and the second contact plug extends through both the first hole and the second hole.

17. The semiconductor device according to claim 16, wherein the first dielectric layer includes a first portion filling a part of the first hole, the second electrode includes a second portion filling the remaining part of the first hole not filled by the first portion of the first dielectric layer, and the second contact plug extends through the first portion of the first dielectric layer and the second portion of the second electrode.

18. The semiconductor device according to claim 13, wherein the second contact plug includes a first portion at least partially away from the upper surface of the substrate relative to the upper surface of the second electrode, and a second portion at least partially between the upper surface of the second electrode and the upper surface of the substrate, and the sidewall of the first portion of the second contact plug is aligned with the sidewall of the second portion of the second contact plug.

19. The semiconductor device according to claim 9, further comprising: an interlayer insulating layer between the upper surface of the substrate and the first electrode; and a first lower wiring layer between the upper surface of the substrate and the interlayer insulating layer, wherein the first contact plug extends through the interlayer insulating layer and contacts the first lower wiring layer.

20. A semiconductor device, comprising: a substrate; The first electrode, on the substrate; The first dielectric layer, on the first electrode; The second electrode, on the first dielectric layer, the second electrode including a first hole; The second dielectric layer, on the second electrode, the second dielectric layer at least partially filling the first hole; The third electrode, on the second dielectric layer; And The first contact plug, extending through the first electrode, the first dielectric layer, the first hole, and the third electrode, wherein the first contact plug covers at least one of a part of the upper surface of the first electrode and a part of the upper surface of the third electrode, wherein a part of the third electrode is between the second dielectric layer and the first contact plug and at least partially fills the first hole.

21. The semiconductor device according to claim 20, wherein the second dielectric layer contacts the upper surface of the first dielectric layer.

22. The semiconductor device according to claim 20, further comprising: The second contact plug, wherein the first electrode includes a second hole, wherein the third electrode includes a third hole vertically overlapping the second hole, wherein the second contact plug extends through the second hole, the first dielectric layer, the second electrode, the second dielectric layer, and the third hole, and wherein the second contact plug contacts the second electrode.

23. The semiconductor device according to claim 22, wherein the first dielectric layer fills at least a part of the second hole.

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