Display device

Abstract

A display device is provided. The display device includes a first signal line and a second signal line, a first signal pad and a second signal pad, and a pad insulating layer overlapping the first signal line and the second signal line. The first signal pad includes an intermediate conductive pattern and an upper conductive pattern, the intermediate conductive pattern overlaps the end portion of the first signal line and is connected to the end portion of the first signal line, the upper conductive pattern is located on the intermediate conductive pattern, and the upper conductive pattern is exposed through the pad insulating layer. The intermediate conductive pattern includes a first portion and a second portion, the first portion overlaps the end portion of the first signal line, and the second portion is located between the end portion of the first signal line and the end portion of the second signal line and extends from the first portion. The upper conductive pattern is connected to the second portion of the intermediate conductive pattern.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0051270, filed on May 2, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0002] An aspect of one or more exemplary embodiments of the present disclosure relates to a display device.One or more exemplary embodiments of the present disclosure relates to a pad area of ​​a display device. Background Art

[0003] Various display devices for multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game devices are being developed. The display device includes a keyboard or a mouse as an input device. In addition, the display device includes an input sensor such as a touch panel as an input device.

[0004] The display device includes a display panel and a circuit board. The display panel is connected to a main board via the circuit board.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] One or more exemplary embodiments of the present disclosure are directed to a display device including a signal pad having reduced defects.

[0007] According to one or more exemplary embodiments, a display device includes: a base layer; a plurality of electronic components located on the base layer; a plurality of signal lines electrically connected to the electronic components; a plurality of signal pads, each signal pad connected to a corresponding signal line among the plurality of signal lines; and a pad insulating layer. Each signal pad includes: a first conductive pattern, overlapping with and contacting the end portion of the corresponding signal line; a second conductive pattern, located on the first conductive pattern, the second conductive pattern overlapping with and contacting the first conductive pattern; and a third conductive pattern, located on the second conductive pattern, the third conductive pattern overlapping with and contacting the second conductive pattern. One of the first conductive pattern and the second conductive pattern includes: a first portion overlapping with the end portion of the corresponding signal line; and a second portion, located between the end portion of the corresponding signal line and the end portion of another signal line adjacent to the corresponding signal line among the signal lines, the second portion extending from the first portion. The pad insulating layer overlaps with the electronic components, the signal lines and the first conductive pattern, and has a pad contact hole exposing at least a portion of the second conductive pattern. The third conductive pattern is connected to the second conductive pattern through the pad contact hole.

[0008] In exemplary embodiments, the third conductive pattern may be positioned within the pad contact hole in plan view.

[0009] In an exemplary embodiment, the display device may further include: a first insulating layer located on an end portion of the corresponding signal line; and a second insulating layer located on the first conductive pattern. The first insulating layer may have a first contact hole exposing the end portion of the corresponding signal line; the first conductive pattern may be connected to the end portion of the corresponding signal line through the first contact hole; the second insulating layer may have a second contact hole exposing the first conductive pattern; and the second conductive pattern may be connected to the first conductive pattern through the second contact hole.

[0010] In exemplary embodiments, the first conductive pattern may include a first portion and a second portion, and the second contact hole may overlap the second portion of the first conductive pattern in a plan view.

[0011] In exemplary embodiments, the second conductive pattern may include a first portion and a second portion; the second contact hole may overlap the first portion of the second conductive pattern and the first conductive pattern in a plan view; and the pad contact hole may overlap the second portion of the second conductive pattern.

[0012] In an exemplary embodiment, the display device may further include: a first insulating layer; a second insulating layer; a third insulating layer; and a fourth insulating layer. Each of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be positioned under the pad insulating layer, the plurality of electronic components may include an upper electrode, a transistor, and a light emitting element connected to the transistor, the transistor may include an active region, a gate located on the active region, a source extending from one side of the active region, and a drain extending from the other side of the active region, the first insulating layer may cover the active region, the source, and the drain, the second insulating layer may be located on the first insulating layer and may cover the gate, the third insulating layer may be located on the second insulating layer and may cover the upper electrode, and the fourth insulating layer may cover the third insulating layer.

[0013] In exemplary embodiments, the end portion may be located in the same layer as that of the gate or the upper electrode.

[0014] In an exemplary embodiment, the first conductive pattern is located on the third insulating layer, and the second conductive pattern is located on the fourth insulating layer.

[0015] In an exemplary embodiment, the pad insulating layer may include an organic layer, the organic layer including a first portion located between an end portion of a corresponding signal line and an end portion of the other signal line and a second portion overlapping the transistor, and a thickness of the first portion of the organic layer may be in a range from about 45% to about 55% of a thickness of the second portion of the organic layer.

[0016] In exemplary embodiments, each of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may include an inorganic layer, and the pad insulating layer may include an organic layer.

[0017] In an exemplary embodiment, the display device may further include a thin film encapsulation layer and an input sensor. The electronic element may include a light emitting element; the thin film encapsulation layer may be located on the pad insulating layer and may cover the light emitting element; and the input sensor may be located on the thin film encapsulation layer, the input sensor including a sensing electrode.

[0018] In an exemplary embodiment, the signal line may include a first signal line connected to the light emitting element and a second signal line connected to the sensing electrode.

[0019] In an exemplary embodiment, the signal line may include a plurality of portions located on different layers.

[0020] In an exemplary embodiment, the signal pads may include first signal pads and second signal pads; the first signal pads may form a first pad row; the second signal pads may form a second pad row different from the first pad row; and the second signal pads may be staggered relative to the first signal pads.

[0021] In exemplary embodiments, the second signal pads may be closer to an edge of the base layer than the first signal pads, and a signal line connected to one of the second signal pads may overlap a second portion of a corresponding first signal pad among the first signal pads.

[0022] In exemplary embodiments, an end portion of the signal line connected to one of the second signal pads among the signal lines may be located on a layer different from a layer on which an end portion of the signal line connected to one of the first signal pads is located.

[0023] In an exemplary embodiment, the display device may further include: a circuit board electrically connected to the signal pad; and an anisotropic conductive film configured to couple the signal pad to the circuit board.

[0024] According to one or more exemplary embodiments, a display device includes: a first signal line; a second signal line; a first signal pad connected to the first signal line; a second signal pad connected to the second signal line; and a pad insulating layer overlapping the first signal line and the second signal line. The first signal pad includes: an intermediate conductive pattern overlapping the end portion of the first signal line, the intermediate conductive pattern connected to the end portion of the first signal line; and an upper conductive pattern located on the intermediate conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The intermediate conductive pattern includes a first portion and a second portion, the first portion overlapping the end portion of the first signal line, the second portion being located between the end portion of the first signal line and the end portion of the second signal line, the second portion extending from the first portion, and the upper conductive pattern connected to the second portion of the intermediate conductive pattern.

[0025] In exemplary embodiments, the upper conductive pattern may not overlap each of the end portion of the first signal line and the end portion of the second signal line.

[0026] According to one or more exemplary embodiments, a display device includes: a base layer including a display area and a non-display area; a first switch transistor located on the display area; a second switch transistor located on the display area; a first signal line connected to the first switch transistor; a second signal line connected to the second switch transistor; a first signal pad connected to the first signal line; a second signal pad connected to the second signal line; and a pad insulating layer overlapping the first switch transistor, the second switch transistor, the first signal line, and the second signal line. Each of the first signal pad and the second signal pad includes: an intermediate conductive pattern overlapping the end portion of the corresponding signal line among the first signal line and the second signal line, the intermediate conductive pattern being electrically connected to the end portion of the corresponding signal line; and an upper conductive pattern located on the intermediate conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The pad insulating layer has a pad contact hole exposing a portion of the intermediate conductive pattern, the pad contact hole overlapping the end portion of the corresponding signal line, the upper conductive pattern being connected to the intermediate conductive pattern through the pad contact hole, and in a plan view, the upper conductive pattern is positioned within the pad contact hole.

[0027] In an exemplary embodiment, the pad insulating layer may include an organic layer, the organic layer including a first portion located between the first signal pad and the second signal pad and a second portion overlapping the first switching transistor, and the thickness of the first portion of the organic layer may be in a range from about 60% to about 80% of the thickness of the second portion of the organic layer.

[0028] In an exemplary embodiment, the pad insulating layer may include a first organic layer, at least one inorganic layer located on the first organic layer, and a second organic layer located on the at least one inorganic layer. The first organic layer may include a first portion located between the first signal pad and the second signal pad and a second portion overlapping the first switch transistor. The thickness of the first portion of the first organic layer may be in a range from about 45% to about 55% of the thickness of the second portion of the first organic layer.

[0029] In exemplary embodiments, the pad insulating layer may include at least one inorganic layer and an organic layer on the at least one inorganic layer, and an upper surface of a portion of the organic layer between the first signal pad and the second signal pad may be higher than an uppermost end of the upper conductive pattern.

[0030] According to the above, because the upper conductive pattern is disposed between the end portion of the corresponding signal line and the end portion of the adjacent signal line, the uppermost pattern of the signal pad may not overlap with the end portion of the corresponding signal line. When viewed in a cross-sectional view, the upper conductive pattern is disposed lower than the upper surface of the pad insulating layer. The portion of the pad insulating layer overlapping the end portion of the corresponding signal line has the function of a barrier to prevent or substantially prevent the upper conductive patterns from short-circuiting with each other.

[0031] By adjusting the thickness of a portion of the pad insulating layer disposed between the end portions of the signal line, the upper conductive patterns can be prevented from being short-circuited with each other or substantially prevented. The portion of the pad insulating layer has a function as a barrier. By controlling the stacking structure of the pad insulating layer or adjusting the thickness of the organic layer, a barrier that prevents or substantially prevents the upper conductive patterns from being short-circuited with each other is formed by the pad insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting example embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 2 is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 3 is a cross-sectional view showing a display panel according to an exemplary embodiment of the present disclosure;

[0036] Figure 4A and Figure 4B is a plan view showing a display panel according to one or more exemplary embodiments of the present disclosure;

[0037] Figure 5Ais an enlarged cross-sectional view showing a display panel according to an exemplary embodiment of the present disclosure;

[0038] Figure 5B is an enlarged cross-sectional view showing an upper insulating layer according to an exemplary embodiment of the present disclosure;

[0039] Fig. 6A is a cross-sectional view showing an input sensing layer according to an exemplary embodiment of the present disclosure;

[0040] Figure 6B is a plan view showing an input sensing layer according to an exemplary embodiment of the present disclosure;

[0041] FIG. 6C to FIG. 6D is a partial cross-sectional view showing an input sensing layer according to an exemplary embodiment of the present disclosure;

[0042] Fig. 7A is a partial plan view showing a pad area according to an exemplary embodiment of the present disclosure;

[0043] FIG. 7B to FIG. 7D is along Fig. 7A A cross-sectional view taken along line II';

[0044] Fig. 8A is a partial plan view showing a pad area according to an exemplary embodiment of the present disclosure;

[0045] Figure 8B is along Fig. 8A A cross-sectional view taken along line II-II';

[0046] Figure 8C is along Fig. 8A A cross-sectional view taken along line III-III';

[0047] Fig. 9 is a cross-sectional view showing a pad region according to an exemplary embodiment of the present disclosure;

[0048] Fig. 10A is a partial plan view showing a pad area according to an exemplary embodiment of the present disclosure; and

[0049] FIG. 10B to FIG. 10E is along Fig. 10A A cross-sectional view taken along line IV-IV'. DETAILED DESCRIPTION

[0050] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings. However, the inventive concept may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the inventive concept to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the inventive concept may not be described. Unless otherwise stated, the same reference numerals always represent the same elements in the drawings and written descriptions, and therefore their descriptions may not be repeated.

[0051] In the accompanying drawings, for the sake of clarity, the thickness, ratio, size and relative size of elements, layers and regions can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "under ... ", "under ... ", "under ... ", "above ... ", "on ", etc. can be used to describe the relationship between an element or feature and another (other) element or feature as shown in the figure. It will be understood that the spatial relative terms are intended to cover the different orientations of the device in use or in operation except the orientation depicted in the figure. For example, if the device in the figure is turned over, the element described as "under" or "under" or "under" other elements or features will then be positioned as "above" the other elements or features. Therefore, the example terms "under ... " and "under ... " can cover both the upper and lower orientations. The device can be positioned additionally (for example, rotated 90 degrees or at other orientations), and the spatial relative descriptors used here should be interpreted accordingly.

[0052] It will be understood that, although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the inventive concept, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0053] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0054] The term used herein is for the purpose of describing specific embodiments, and is not intended to be a limitation of the inventive concept. As used herein, the singular "one" and "one (kind / person)" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the term "comprising" and its variant forms and "including" and its variant forms are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. When the expression such as "at least one (kind / person) in ... " is after a column of elements, the entire column of elements is modified, and the single element in the column is not modified.

[0055] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the inventive concept, the use of "may" means "one or more embodiments of the inventive concept." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively. In addition, the term "exemplary" is intended to mean an example or illustration.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the inventive concept belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0057] Figure 1 is a perspective view showing a display device DD according to an exemplary embodiment of the present disclosure. Figure 2 is a cross-sectional view showing a display device DD according to an exemplary embodiment of the present disclosure.

[0058] like Figure 1 As shown in , the display device DD displays an image IM at (e.g., through) a display surface DD-IS. The display surface DD-IS may be parallel or substantially parallel to a plane defined by the first direction axis DR1 and the second direction axis DR2. The third direction axis DR3 indicates a normal direction of the display surface DD-IS (e.g., a thickness direction of the display device DD).

[0059] The front (or upper) surface and the rear (or lower) surface of each member or each unit described below are distinguished from each other by the third directional axis DR3. However, the directions indicated by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3 are merely exemplary. Hereinafter, the first direction, the second direction, and the third direction correspond to the directions indicated by the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3, respectively, and are assigned the same reference numerals as the first directional axis DR1, the second directional axis DR2, and the third directional axis DR3.

[0060] In an exemplary embodiment of the present disclosure, the display device DD includes a flat display surface. However, the present disclosure is not limited thereto. For example, in another exemplary embodiment, the display device DD may include a curved display surface. In another example, the display device DD may include a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas indicating directions different from each other, for example, a polygonal cylindrical display surface.

[0061] In an exemplary embodiment, the display device DD may be a rigid display device, but the present disclosure is not limited thereto. For example, in another exemplary embodiment, the display device DD may be a flexible display device DD. The flexible display device DD may include a foldable display device or a bendable display device that can be partially bent.

[0062] For convenience, the display device DD is Figure 1 The portion shown as a mobile phone terminal is used as a representative example. Although not shown in the figure, one or more of the electronic module, camera module and / or power module that can be mounted on the mainboard can be arranged on a bracket or a housing together with the display device DD to form a mobile phone terminal. However, the present disclosure is not limited thereto, and the display device DD according to various embodiments of the present disclosure can be applied to large electronic items (such as televisions, monitors, etc.) and / or small and medium-sized electronic items (such as tablet computers, vehicle navigation units (e.g., vehicle navigation devices), game units (e.g., game consoles), smart watches, etc.).

[0063] like Figure 1 As shown in , the display surface DD-IS includes an image area DD-DA and a border area DD-NDA, where the image IM is displayed (e.g., through the image area DD-DA), and the border area DD-NDA is defined as being adjacent to the image area DD-DA (e.g., around the periphery of the image area DD-DA). The image IM is not displayed at or through the border area DD-NDA. Figure 1 An icon image is shown as a representative example of the image IM.

[0064] like Figure 1As shown in , the image area DD-DA may have a quadrilateral shape or a substantially quadrilateral shape. The expression “substantially quadrilateral shape” as used in this specification may mean not only a quadrilateral shape as mathematically defined, but also a quadrilateral shape defining a curved boundary instead of a vertex at or in a vertex area (or corner area).

[0065] The frame area DD-NDA may surround the image area DD-DA (e.g., may be around the periphery of the image area DD-DA), but the present disclosure is not limited thereto. The image area DD-DA and the frame area DD-NDA may have various suitable shapes. The frame area DD-NDA may be limited only to one side of the image area DD-DA. Depending on the combination between the display device DD and other components of the electronic device, the frame area DD-NDA may not be exposed to the outside.

[0066] Figure 2 A cross section defined by the second direction DR2 and the third direction DR3 is shown. Components of the display device DD are schematically shown to illustrate their stacked relationship.

[0067] The display device DD according to an exemplary embodiment of the present disclosure may include a display panel DP, an input sensor ISL, an anti-reflector RPP and a window WP. At least some of the display panel DP, the input sensor ISL, the anti-reflector RPP and the window WP may be formed by a continuous process, or may be attached to each other by an adhesive member (e.g., an adhesive or an adhesive layer). The adhesive member ADS may be a transparent adhesive member (e.g., a transparent adhesive layer) such as a pressure-sensitive adhesive (PSA) film, an optically clear adhesive (OCA) film, an optically clear resin (OCR), etc. The adhesive member described hereinafter may include an adhesive or a pressure-sensitive adhesive. In an exemplary embodiment of the present disclosure, the anti-reflector RPP and / or the window WP may be omitted or may be replaced by other components.

[0068] like Figure 2 As shown in, among the input sensor ISL, the anti-reflector RPP and the window WP, the input sensor ISL can be formed together with the display panel DP through a continuous process and can be directly disposed on the display panel DP. As used in the present disclosure, the expression "component B is directly disposed on component A" means that there is no intermediate element (such as a separate adhesive layer or adhesive member as an example) between component "B" and component "A". For example, component "B" can be formed on the substrate surface provided by component "A" through a continuous process after component "A" is formed.

[0069] In an exemplary embodiment, the anti-reflector RPP and the window WP may be a "panel" type component, and the input sensor ISL may be a "layer" type component. As used in the present disclosure, a "panel" type component includes a substrate layer (e.g., a synthetic resin film, a composite film, a glass substrate, etc.) providing a substrate surface, while for a "layer" type component, the substrate layer may be omitted. In other words, a component referred to as a "layer" type component may be disposed on a substrate surface provided by another component. In another exemplary embodiment, the anti-reflector RPP and the window WP may be a "layer" type component.

[0070] The display panel DP generates an image, and the input sensor ISL obtains coordinate information of an external input (e.g., a touch event). Although not shown separately, the display device DD according to an exemplary embodiment of the present disclosure may further include a protective member disposed on the lower surface of the display panel DP. The protective member and the display panel DP may be bonded to each other by an adhesive member.

[0071] The display panel DP according to the exemplary embodiment of the present disclosure may be a light-emitting display panel, but the present disclosure is not limited thereto. For example, the display panel DP may include or may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The panels are different from each other according to the material of the light-emitting element. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods. Hereinafter, the organic light-emitting display panel will be described as a representative example of the display panel DP.

[0072] The anti-reflector RPP reduces the reflectivity of external light incident thereon from above the window WP. The anti-reflector RPP according to an exemplary embodiment of the present disclosure may include a retarder and a polarizer. The retarder may be a film-type retarder or a liquid crystal coating retarder, and may include a half-wave retarder (e.g., a λ / 2 retarder) and / or a quarter-wave retarder (e.g., a λ / 4 retarder). The polarizer may be a film-type polarizer or a liquid crystal coating polarizer. The film-type retarder and / or the polarizer may include a stretched synthetic resin film, and the liquid crystal coating retarder and / or the polarizer may include liquid crystals oriented in a certain arrangement (e.g., a predetermined arrangement). The polarizer and / or the retarder may also include a protective film. The retarder and / or the polarizer or the protective film may be defined as a base layer of the anti-reflector RPP.

[0073] The anti-reflector RPP according to an exemplary embodiment of the present disclosure may include a color filter. The color filter may have a certain arrangement (e.g., a predetermined arrangement). The arrangement of the color filter may be determined by considering the emission color of the pixels included in the display panel DP. The anti-reflector RPP may also include a black matrix disposed adjacent to the color filter.

[0074] The anti-reflector RPP according to an exemplary embodiment of the present disclosure may include a destructive interference structure. For example, the destructive interference structure may include a first reflection layer and a second reflection layer that may be disposed at different layers from each other (e.g., disposed on different layers from each other or disposed in different layers from each other). The first reflected light and the second reflected light reflected by the first reflection layer and the second reflection layer, respectively, may destructively interfere, and thus, the reflectivity of the external light may be reduced.

[0075] The window WP according to an exemplary embodiment of the present disclosure includes a base layer WP-BS and a light shielding pattern WP-BZ. The base layer WP-BS may include a glass substrate and / or a synthetic resin film. The base layer WP-BS may include a single-layer structure or a multi-layer structure. For example, the base layer WP-BS may include two or more films bonded to each other by an adhesive member.

[0076] The light shielding pattern WP-BZ partially overlaps with the base layer WP-BS. The light shielding pattern WP-BZ is disposed on the rear surface of the base layer WP-BS, and the light shielding pattern WP-BZ defines or substantially defines a frame area DD-NDA of the display device DD. An area where the light shielding pattern WP-BZ is not disposed (e.g., an area where the light shielding pattern WP-BZ is not disposed or an area on which the light shielding pattern WP-BZ is not disposed) may define an image area DD-DA of the display device DD. In the case of the window WP, an area where the light shielding pattern WP-BZ is disposed may be defined as a light shielding area, and an area where the light shielding pattern WP-BZ is not disposed may be defined as a transmission area.

[0077] The shading pattern WP-BZ may have a multilayer structure. The multilayer structure may include a color layer and a non-color (e.g., black) shading layer. The color layer and the non-color shading layer may be formed by a deposition process, a printing process, and / or a coating process. Although not shown in the figure, the window WP may further include a functional coating disposed on the front surface of the base layer WP-BS. The functional coating may include one or more of an anti-fingerprint layer, an anti-reflection layer, and / or a hard coating layer.

[0078] Figure 3 is a cross-sectional view showing a display panel DP according to an exemplary embodiment of the present disclosure. Figure 4A and Figure 4B is a plan view illustrating a display panel DP according to one or more exemplary embodiments of the present disclosure.

[0079] Reference Figure 3 The display panel DP includes a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED and an upper insulating layer TFL. Figure 1The display area DP-DA and the non-display area DP-NDA corresponding to the image area DD-DA and the frame area DD-NDA shown in the figure may be defined at the display panel DP (e.g., defined in the display panel DP or defined on the display panel DP). As used in the present disclosure, the expression "one area / portion corresponds to another area / portion" means areas / portions overlapping each other, and is not limited to areas / portions having the same size and / or the same shape as each other.

[0080] The base layer BL may include at least one synthetic resin film. The base layer BL may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0081] The circuit element layer DP-CL includes at least one insulating layer and a circuit element. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element includes a signal line and a pixel driving circuit.

[0082] The display element layer DP-OLED includes at least one organic light emitting diode as a light emitting element. The display element layer DP-OLED may further include an organic layer, such as a pixel defining layer, for example.

[0083] The upper insulating layer TFL includes a plurality of thin layers. Some of the thin layers of the upper insulating layer TFL (e.g., at least one of the thin layers) may improve optical efficiency, and some of the thin layers of the upper insulating layer TFL (e.g., at least one of the thin layers) may protect the organic light emitting diode. The upper insulating layer TFL will be described in more detail below.

[0084] like Figure 4A and Figure 4B As shown in the figure, the display panel DP includes a driving circuit GDC, a plurality of signal lines (hereinafter referred to as "signal lines") SGL, a plurality of signal pads (or referred to as "pads") (hereinafter referred to as "signal pads") DP-PD and ISL-PD, and a plurality of pixels (hereinafter referred to as "pixels") PX.

[0085] The drive circuit GDC includes a scan drive circuit. The scan drive circuit generates a plurality of scan signals (hereinafter, referred to as "scan signals") and outputs (e.g., sequentially outputs) the scan signals to a plurality of scan lines (hereinafter, referred to as "scan lines") GL. The scan drive circuit may also output other control signals to the drive circuit of the pixel PX.

[0086] The scan driving circuit may include a plurality of transistors, and the transistors may be formed by a process identical or substantially identical to that of the driving circuit of the pixel PX (eg, a low temperature polysilicon (LTPS) process, a low temperature polycrystalline oxide (LTPO) process, etc.).

[0087] The signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the scan lines GL is connected to a corresponding pixel among the pixels PX, and each of the data lines DL is connected to a corresponding pixel among the pixels PX. The power lines PL are connected to the pixels PX. The control signal lines CSL provide control signals to the scan drive circuit.

[0088] In an exemplary embodiment, the signal line SGL may further include an auxiliary line SSL. The auxiliary line SSL may be connected to the input sensor ISL (eg, Figure 2 However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the auxiliary line SSL may be omitted.

[0089] The signal line SGL may include a plurality of portions disposed at different layers from each other (eg, disposed on different layers from each other or disposed in different layers from each other). Figure 4A 1 shows a data line DL including four portions P1, P2, P3, and P4 and an auxiliary line SSL including two portions P10 and P20. The four portions P1, P2, P3, and P4 of the data line DL may be connected to each other via a contact hole CNT, and the two portions P10 and P20 of the auxiliary line SSL may be connected to each other via the contact hole CNT. The first portion P10 of the auxiliary line SSL may be connected to the input sensor ISL (e.g., see FIG. 1 ) via the contact hole CNT. Figure 6B ) signal line.

[0090] The signal pads DP-PD and ISL-PD may include a first signal pad (e.g., a first type signal pad) DP-PD connected to the data line DL, the power line PL, and the control signal line CSL, and a second signal pad (e.g., a second type signal pad) ISL-PD connected to the auxiliary line SSL. The first signal pad DP-PD and the second signal pad ISL-PD may be disposed adjacent to each other at a pad area NDA-PA defined at a portion of the non-display area DP-NDA (e.g., defined in a portion of the non-display area DP-NDA or defined on a portion of the non-display area DP-NDA) (e.g., in the pad area NDA-PA or on the pad area NDA-PA). The stacking structure and / or material of the first signal pad DP-PD may be the same or substantially the same as the stacking structure and / or material of the second signal pad ISL-PD (e.g., may not be distinguished from the stacking structure and / or material of the second signal pad ISL-PD), and the first signal pad DP-PD and the second signal pad ISL-PD may be formed by the same or substantially the same process.

[0091] The display area DP-DA may be defined as an area where the pixels PX are arranged (e.g., arranged therein or arranged on thereof). A plurality of electronic devices may be arranged at the display area DP-DA (e.g., arranged in the display area DP-DA or arranged on the display area DP-DA). The electronic devices may include an organic light emitting diode that may be arranged at each pixel PX (e.g., arranged in each pixel PX or arranged on each pixel PX) and a pixel driving circuit connected to the organic light emitting diode. The driving circuit GDC, the signal line SGL, the signal pads DP-PD and ISL-PD, and the pixel driving circuit may be included in the circuit element layer DP-CL (e.g., such as Figure 3 as shown in ) at (eg, included in or on the circuit element layer DP-CL).

[0092] The pixel PX may include, for example, a first transistor T1, a second transistor T2, a capacitor CP, and an organic light emitting diode OLED. However, the present disclosure is not limited thereto, and for example, the pixel PX may include various suitable pixel circuit structures including at least a switching transistor and a driving transistor. The first transistor T1 is connected to the scan line GL and the data line DL. The organic light emitting diode OLED receives a power voltage provided by the power line PL.

[0093] Figure 4A A circuit board PCB connected to the display panel DP is also shown. The circuit board PCB may be a rigid circuit board or a flexible circuit board.

[0094] The timing control circuit TC may be provided on the circuit board PCB to control the operation of the display panel DP. The input sensing circuit ISL-C may be provided on the circuit board PCB to control the input sensor ISL. Each of the timing control circuit TC and the input sensing circuit ISL-C may be mounted on the circuit board PCB in the form of an integrated chip. In an exemplary embodiment of the present disclosure, the timing control circuit TC and the input sensing circuit ISL-C may be mounted on the circuit board PCB in the form of an integrated chip. The circuit board PCB may include a circuit board pad PCB-P electrically connected to the signal pads DP-PD and ISL-PD. Although not shown in the figure, the circuit board PCB may further include a signal line that connects the circuit board pad PCB-P to the timing control circuit TC and / or the input sensing circuit ISL-C. In some embodiments, the circuit board pad PCB-P may be an output pad, and the circuit board PCB may further include an input pad.

[0095] The signal pads DP-PD and ISL-PD of the display panel DP may be electrically connected to the circuit board pads PCB-P of the circuit board PCB through a conductive member such as an anisotropic conductive film ACF. However, the present disclosure is not limited thereto, and in another exemplary embodiment, the anisotropic conductive film ACF may be replaced by a conductive ball.

[0096] like Figure 4B As shown in , the display panel DP according to the exemplary embodiment of the present disclosure may further include a chip mounting area NDA-TC defined at the non-display area DP-NDA (e.g., defined in the non-display area DP-NDA or defined on the non-display area DP-NDA). The timing control circuit TC (e.g., referring to Figure 4A ) can be mounted on the chip mounting area NDA-TC in chip form.

[0097] The first chip pad TC-PD1 and the second chip pad TC-PD2 can be arranged at the chip mounting area NDA-TC (for example, arranged in the chip mounting area NDA-TC or arranged on the chip mounting area NDA-TC). The first chip pad TC-PD1 can be connected to the data line DL, and the second chip pad TC-PD2 can be connected to the first signal pad DP-PD via the input signal line SIL. The terminals of the timing control circuit TC can be connected to the first chip pad TC-PD1 and the second chip pad TC-PD2. The data line DL can be electrically connected to the signal pad DP-PD via the timing control circuit TC. In an exemplary embodiment of the present disclosure, at least one of the control signal line CSL and the power line PL can be connected to the timing control circuit TC.

[0098] Figure 4A and Figure 4B The display panel DP shown in FIG. 1 may be partially bent. In this case, a portion of the non-display area DP-NDA may be bent relative to a bending axis that is parallel or substantially parallel to the second direction DR2. The bending axis may be defined to overlap with the third portion P3 of the data line DL and the first portion P10 of the auxiliary line SSL.

[0099] Figure 5A is an enlarged cross-sectional view showing a display panel DP according to an exemplary embodiment of the present disclosure. Figure 5B is an enlarged cross-sectional view showing an upper insulating layer TFL according to an exemplary embodiment of the present disclosure.

[0100] Reference Figure 5A, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers, semiconductor layers, and conductive layers may be formed by a coating process and a deposition process. The insulating layers, semiconductor layers, and conductive layers may be patterned (e.g., selectively patterned) by a photolithography process. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by the method described above.

[0101] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The base layer BL may have a multilayer structure. For example, the base layer BL may have a three-layer structure including a synthetic resin layer, an adhesive layer and a synthetic resin layer (e.g., another synthetic resin layer). In more detail, the synthetic resin layer may include or may be a polyimide resin layer, but the present disclosure is not limited thereto. The synthetic resin layer may include, for example, at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyamide resin and / or a perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate and / or an organic / inorganic composite substrate.

[0102] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be provided as a multilayer. The inorganic layer may form a barrier layer and / or a buffer layer. In an exemplary embodiment, as shown in FIG. Figure 5A As shown in , the display panel DP includes a buffer layer BFL.

[0103] The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked on each other (eg, alternately stacked on each other).

[0104] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, but the present disclosure is not limited thereto. The semiconductor pattern may include amorphous silicon or metal oxide.

[0105] Figure 5AA portion of a semiconductor pattern is shown, and when viewed in a plan view (e.g., on a plane parallel or substantially parallel to the top surface of the display panel DP), the semiconductor pattern may also be disposed in another region of the pixel PX. The semiconductor pattern may be arranged throughout the pixel PX in a specific pattern (or regularity). For example, a semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. For example, if the first transistor T1 and the second transistor T2 (e.g., see Figure 4A ) includes a P-type transistor, the P-type transistor includes a doped region of the semiconductor pattern doped with a P-type dopant.

[0106] The doped region of the semiconductor pattern may have a conductivity greater than that of the non-doped region. The doped region of the semiconductor pattern may serve as or substantially serve as an electrode or a signal line. The non-doped region of the semiconductor pattern may correspond to or substantially correspond to the active region (or channel) of the transistor. In other words, a portion of the semiconductor pattern may include or may be the active region of the transistor, another portion of the semiconductor pattern may include or may be the source or drain of the transistor, and another portion of the semiconductor pattern may be a connecting electrode or a connecting signal line.

[0107] like Figure 5A As shown in , the source S1, active area A1 and drain D1 of the first transistor T1 can be formed using a semiconductor pattern, and the source S2, active area A2 and drain D2 of the second transistor T2 can be formed using a semiconductor pattern. The sources S1 and S2 and the drains D1 and D2 extend in opposite directions from the active areas A1 and A2 in a cross-sectional view. Figure 5A A portion of a connection signal line SCL formed using a semiconductor pattern is shown. Although not separately shown, the connection signal line SCL may be connected to the drain electrode D2 of the second transistor T2 when viewed in a plan view.

[0108] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is connected to the pixel PX (eg, Figure 4A and Figure 4B ) is stacked (e.g., commonly stacked) and covers the semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an exemplary embodiment, as Figure 5AAs shown in , the first insulating layer 10 may include or may be a single silicon oxide layer. The insulating layer of the circuit element layer DP-CL (described in more detail below) may include an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the materials described above.

[0109] The gates G1 and G2 are disposed on the first insulating layer 10. The gate G1 may be part of a metal pattern. The gates G1 and G2 overlap the active areas A1 and A2, respectively. The gates G1 and G2 may serve as masks during a doping process of the semiconductor pattern.

[0110] The second insulating layer 20 is disposed on the first insulating layer 10 to cover the gates G1 and G2. The second insulating layer 20 is disposed on the first insulating layer 10 to cover the gates G1 and G2. Figure 4A and Figure 4B ) are stacked (eg, commonly stacked). The second insulating layer 20 may include an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In an exemplary embodiment, as Figure 5A As shown in FIG. , the second insulating layer 20 may be a single silicon oxide layer.

[0111] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate G2 of the second transistor T2. The upper electrode UE may be part of the metal pattern. The portion of the gate G2 and the upper electrode UE overlapping the portion of the gate G2 may define a capacitor CP (eg, referring to Figure 4A ). However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the upper electrode UE may be omitted.

[0112] The third insulating layer 30 is disposed on the second insulating layer 20 to cover the upper electrode UE. Figure 5A As shown in , the third insulating layer 30 may be a single silicon oxide layer, but the present disclosure is not limited thereto, and the third insulating layer 30 may have another suitable single-layer structure or multi-layer structure. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 extending through (e.g., penetrating) the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0113] The fourth insulating layer 40 is disposed on the third insulating layer 30. The fourth insulating layer 40 may include or may be a single silicon oxide layer. The fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may include or may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 extending through (e.g., penetrating) the fourth insulating layer 40 and the fifth insulating layer 50.

[0114] The sixth insulating layer 60 is disposed on the fifth insulating layer 50 to cover the second connection electrode CNE2. The sixth insulating layer 60 may include or may be an organic layer. The first electrode AE ​​is disposed on the sixth insulating layer 60. The first electrode AE ​​is connected to the second connection electrode CNE2 through a contact hole CNT-3 extending through (e.g., penetrating) the sixth insulating layer 60. An opening OP is defined by the pixel defining layer PDL. At least a portion of the first electrode AE ​​is exposed through the opening OP of the pixel defining layer PDL.

[0115] like Figure 5A As shown in , the display area DP-DA may include a light emitting area PXA and a non-light emitting area NPXA disposed adjacent to the light emitting area PXA. For example, the non-light emitting area NPXA may surround the light emitting area PXA (e.g., may be around the periphery of the light emitting area PXA). In an exemplary embodiment, the light emitting area PXA is defined to correspond to a portion of the first electrode AE ​​exposed by the opening OP.

[0116] The hole control layer HCL may be disposed (e.g., commonly disposed) at the light emitting region PXA and the non-light emitting region NPXA (e.g., disposed (e.g., commonly disposed) on the light emitting region PXA and the non-light emitting region NPXA or disposed (e.g., commonly disposed) in the light emitting region PXA and the non-light emitting region NPXA). The hole control layer HCL may include a hole transport layer and / or a hole injection layer. The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed at a region corresponding to the opening OP (e.g., disposed in a region corresponding to the opening OP or disposed on a region corresponding to the opening OP). For example, the light emitting layer EML may be formed at each of the pixels PX (e.g., formed in each of the pixels PX or formed on each of the pixels PX) after being divided into a plurality of portions.

[0117] The electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and / or an electron injection layer. The hole control layer HCL and the electron control layer ECL may be formed (e.g., formed in common) at a plurality of pixels PX (e.g., in a plurality of pixels PX or on a plurality of pixels PX) using an open mask. The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have a single integral form and may be disposed (e.g., disposed in common) at a plurality of pixels PX (e.g., with reference to Figure 4A ) at (eg, disposed (eg, commonly disposed) in a plurality of pixels PX or disposed (eg, commonly disposed) on a plurality of pixels PX).

[0118] like Figure 5A and Figure 5B As shown in FIG. 1 , the upper insulating layer TFL is disposed on the second electrode CE. The upper insulating layer TFL may include a plurality of thin films. Figure 5B As shown in , in an exemplary embodiment, the upper insulating layer TFL may include a cap layer CPL and a thin film encapsulation layer TFE. The thin film encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2.

[0119] The cap layer CPL is disposed on the second electrode CE and may be in contact with the second electrode CE. The cap layer CPL includes an organic material. The first inorganic layer IOL1 is disposed on the cap layer CPL and may be in contact with the cap layer CPL. The organic layer OL is disposed on the first inorganic layer IOL1 and may be in contact with the first inorganic layer IOL1. The second inorganic layer IOL2 is disposed on the organic layer OL and may be in contact with the organic layer OL.

[0120] The capping layer CPL may protect the second electrode CE from subsequent processes (eg, a sputtering process) and may improve light emitting efficiency of the organic light emitting diode OLED. The capping layer CPL has a refractive index greater than that of the first inorganic layer IOL1.

[0121] The first inorganic layer IOL1 and the second inorganic layer IOL2 can protect the display element layer DP-OLED from moisture and / or oxygen, and the organic layer OL can protect the display element layer DP-OLED from foreign matter (e.g., such as dust particles). Each of the first inorganic layer IOL1 and the second inorganic layer IOL2 may include one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. In an exemplary embodiment of the present disclosure, the first inorganic layer IOL1 and the second inorganic layer IOL2 may include a titanium oxide layer or an aluminum oxide layer. The organic layer OL may include an acrylic organic layer, but the present disclosure is not limited thereto.

[0122] In an exemplary embodiment of the present disclosure, an inorganic layer (eg, LiF layer) may be further disposed between the cap layer CPL and the first inorganic layer IOL1. In this case, the inorganic layer (eg, LiF layer) may improve the light emitting efficiency of the organic light emitting diode OLED.

[0123] Fig. 6A is a cross-sectional view illustrating an input sensor ISL according to an exemplary embodiment of the present disclosure. Figure 6B is a plan view illustrating an input sensor ISL according to an exemplary embodiment of the present disclosure. Figure 6C and Fig.6D is a partial cross-sectional view showing an input sensor ISL according to an exemplary embodiment of the present disclosure.

[0124] like Fig. 6A As shown in , the input sensor ISL may include a first insulating layer (hereinafter, referred to as a "first input insulating layer") ISL-IL1, a first conductive layer ISL-CL1, a second insulating layer (hereinafter, referred to as a "second input insulating layer") ISL-IL2, a second conductive layer ISL-CL2, and a third insulating layer (hereinafter, referred to as a "third input insulating layer") ISL-IL3. The first input insulating layer ISL-IL1 may be disposed (e.g., directly disposed) on the upper insulating layer TFL. However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the first input insulating layer ISL-IL1 may be omitted.

[0125] Each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 may have a single-layer structure or a multilayer structure in which a plurality of layers are stacked on each other in the third direction DR3. The conductive layer having a multilayer structure may include at least two layers among a transparent conductive layer and a metal layer. The conductive layer having a multilayer structure may include a metal layer having metals different from each other. The transparent conductive layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires and / or graphene. The metal layer may include, for example, molybdenum, silver, titanium, copper, aluminum and / or their alloys. For example, each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 may have a three-layer structure of titanium / aluminum / titanium. A metal having relatively high durability and low reflectivity may be an outer layer (e.g., or multiple outer layers), and a metal having relatively high electrical conductivity may be an inner layer (e.g., an insertion layer, an intermediate layer or multiple intermediate layers).

[0126] Each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 includes a plurality of patterns. Hereinafter, the first conductive layer ISL-CL1 will be described as including a first pattern, and the second conductive layer ISL-CL2 will be described as including a second pattern. Each of the first pattern and the second pattern may include a sensing electrode and a signal line connected to the sensing electrode.

[0127] Each of the first input insulating layer ISL-IL1, the second input insulating layer ISL-IL2, and the third input insulating layer ISL-IL3 may include an inorganic layer or an organic layer. For example, in an exemplary embodiment, the first input insulating layer ISL-IL1 and the second input insulating layer ISL-IL2 may include or may be an inorganic layer. The inorganic layer may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The third input insulating layer ISL-IL3 may include or may be an organic layer. The organic layer may include, for example, at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0128] like Figure 6B As shown in , the input sensor ISL includes a first electrode group EG1, a second electrode group EG2, and a signal line group connected to the first electrode group EG1 and the second electrode group EG2. In an exemplary embodiment, as shown in Figure 6B As shown in , an input sensor ISL including two signal line groups SG1 and SG2 is shown as a representative example. The input sensor ISL may include a sensing area ISL-DA and a line area ISL-NDA corresponding to the display area DP-DA and the non-display area DP-NDA of the display panel DP, respectively. The sensing area ISL-DA may be defined as an area where (e.g., disposed in or disposed on) the first electrode group EG1 and the second electrode group EG2 are disposed. The first signal line group SG1 and the second signal line group SG2 are disposed in the line area ISL-NDA.

[0129] In an exemplary embodiment, the input sensor ISL may include a capacitive touch sensor, but the present disclosure is not limited thereto. One of the first electrode group EG1 and the second electrode group EG2 receives a driving signal, and the other of the first electrode group EG1 and the second electrode group EG2 outputs a sensing signal corresponding to a change in capacitance between the first electrode group EG1 and the second electrode group EG2.

[0130] In an exemplary embodiment, the driving time period may be divided into a first driving time period and a second driving time period. In this case, the input sensor ISL may be driven in the manner described above during the first driving time period, and the input sensor ISL may be driven in the manner opposite to the manner described above during the second driving time period. For example, during the first driving time period, one of the first electrode group EG1 and the second electrode group EG2 may receive a driving signal, and the other of the first electrode group EG1 and the second electrode group EG2 may output a sensing signal. During the second driving time period, the other of the first electrode group EG1 and the second electrode group EG2 may receive a driving signal, and the one of the first electrode group EG1 and the second electrode group EG2 may output a sensing signal.

[0131] The first electrode group EG1 includes a plurality of first sensing electrodes IE1-1 to IE1-10. The first electrode group EG1 including ten first sensing electrodes IE1-1 to IE1-10 is shown as a representative example, but the present disclosure is not limited to Figure 6B The number of first sensing electrodes shown in FIG. The first sensing electrodes IE1-1 to IE1-10 have a shape extending in the second direction DR2. The second electrode group EG2 includes a plurality of second sensing electrodes IE2-1 to IE2-8. The second electrode group EG2 including eight second sensing electrodes IE2-1 to IE2-8 is shown as a representative example, but the present disclosure is not limited thereto. Figure 6B The number of second sensing electrodes shown in . The second sensing electrodes IE2-1 to IE2-8 have a shape extending in the first direction DR1. The second sensing electrodes IE2-1 to IE2-8 have a length greater than that of the first sensing electrodes IE1-1 to IE1-10.

[0132] The first signal line group SG1 may include the same or substantially the same number of signal lines as the first sensing electrodes IE1-1 to IE1-10. The signal lines of the first signal line group SG1 may be connected to at least one of the two ends of each of the first sensing electrodes IE1-1 to IE1-10. The second signal line group SG2 may include the same or substantially the same number of signal lines as the second sensing electrodes IE2-1 to IE2-8. The signal lines of the second signal line group SG2 may be connected to at least one of the two ends of each of the second sensing electrodes IE2-1 to IE2-8.

[0133] The signal lines of the first signal line group SG1 may be connected to the auxiliary lines SSL (eg, referring to Figure 4A ) are provided at one side of the pad area NDA-PA. The signal lines of the second signal line group SG2 may be connected to the auxiliary lines SSL via contact holes CNT (eg, refer to Figure 4A ) are provided at the other side of the pad area NDA-PA.

[0134] The contact hole CNT extends through (e.g., penetrates) the insulating layer provided between the signal line of the first signal line group SG1 and the auxiliary line SSL. For example, the contact hole CNT may extend through (e.g., penetrate) the first input insulating layer ISL-IL1 and the second input insulating layer ISL-IL2 of the input sensor ISL and some of the first to sixth insulating layers 10 to 60.

[0135] Each of the first sensing electrodes IE1-1 to IE1-10 may include a plurality of sensor portions SP1 and a plurality of bridge portions CP1. The plurality of sensor portions SP1 may be connected by a plurality of bridge portions CP1. Each of the second sensing electrodes IE2-1 to IE2-8 may include a plurality of first portions SP2 and a plurality of second portions CP2. At least two of the plurality of first portions SP2 may be arranged so that each of the plurality of second portions CP2 is located between the first portions SP2.

[0136] Figure 6C Shown along Figure 6B A cross-sectional view taken along line XX'. Figure 6C An example is shown in which the bridge portion CP1 crosses the second portion CP2. In an exemplary embodiment, the bridge portion CP1 may correspond to a bridge pattern. However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the second portion CP2 may correspond to a bridge pattern.

[0137] Reference FIG. 6A to FIG. 6C , a bridge portion CP1 is formed using a first conductive layer ISL-CL1, and a sensor portion SP1, a first portion SP2, and a second portion CP2 are formed using a second conductive layer ISL-CL2. The sensor portion SP1 may be connected to the bridge portion CP1 through a contact hole CNT-IL2 extending through (e.g., penetrating) the second input insulating layer ISL-IL2.

[0138] In an exemplary embodiment, if Figure 6C As shown in , the bridging portion CP1 may intersect the second portion CP2, but the present disclosure is not limited thereto. For example, each of the bridging portions CP1 may be modified to have a curved form in the shape of "∧" corresponding to a V-shape rotated approximately 180 degrees and / or a curved form in the shape of a V-shape "∨" so as not to overlap with the second portion CP2. When viewed in a plan view, the bridging portion CP1 in the curved form in the shape of "∧" and / or the curved form in the shape of "∨" may overlap with the first portion SP2.

[0139] According to an exemplary embodiment, the signal lines of the first signal line group SG1 and the second signal line group SG2 include at least one of a portion disposed in the same or substantially the same layer as the first sensing electrodes IE1-1 to IE1-10 and a portion disposed in the same or substantially the same layer as the second sensing electrodes IE2-1 to IE2-8.

[0140] Fig.6D Shown along Figure 6B 1-10 is shown as a representative example. The first signal line group SG1 includes at least a portion disposed in the same or substantially the same layer as the second sensing electrodes IE2-1 to IE2-8. The signal lines of the first signal line group SG1 and the second signal line group SG2 may also include a first conductive layer ISL-CL1 (e.g., referring to Fig. 6A ) formed part.

[0141] Fig. 7A is a partial plan view showing a pad area NDA-PA of the display panel DP according to an exemplary embodiment of the present disclosure. FIG. 7B to FIG. 7D is along Fig. 7A In the following, the cross-sectional view taken along the line II' may not be repeated with reference to Figures 1 to 6D The components and / or configurations described are identical or substantially identical to the components and / or configurations described redundantly.

[0142] FIG. 7A to FIG. 7D The first signal pad DP-PD is illustrated as a representative example, but the second signal pad ISL-PD may have the same or substantially the same structure and / or arrangement as those of the first signal pad DP-PD.

[0143] The first signal pads DP-PD may be arranged at certain intervals (eg, regular intervals) along the second direction DR2. Fig. 7A The portion of the data line DL shown in FIG. Figure 4A The end portion DL-E of the data line DL may have a relatively large width when compared to the width of the line portion DL-S. The width may be defined as the length in the second direction DR2 (e.g., the shortest length). However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the end portion DL-E may have the same or substantially the same width as the width of the line portion DL-S without being distinguished from the line portion DL-S. Fig. 7A , the contact hole CNT is shown as a representative example of the plurality of contact holes.

[0144] Reference Figure 7B, the end portion DL-E of the data line DL is disposed on the second insulating layer 20. The end portion DL-E of the data line DL is disposed on the second insulating layer 20. Figure 5A The upper electrode UE shown in FIG. 1 is in the same or substantially the same layer as the upper electrode UE shown in FIG. Figure 4A The fourth portion P4 of the data line DL shown in FIG. 5 is disposed in the same or substantially the same layer as that of the upper electrode UE. Figure 4A The first portion P1 and the third portion P3 of the data line DL shown in FIG. Figure 5A The second connection electrode CNE2 shown in FIG. 1 is in the same or substantially the same layer as that of the second connection electrode CNE2 , and the second portion P2 of the data line DL may be disposed in the same or substantially the same layer as that of the upper electrode UE.

[0145] The first conductive pattern CL1 is disposed on the third insulating layer 30 and overlaps the end portion DL-E. The first conductive pattern CL1 contacts (or electrically connects) the end portion DL-E through a first contact hole CNT1 extending (eg, penetrating) through the third insulating layer 30.

[0146] The first conductive pattern CL1 includes a first portion CL-P1 overlapping the end portion DL-E and a second portion CL-P2 extending from the first portion CL-P1. The second portion CL-P2 is disposed between the end portion DL-E of the corresponding data line DL and an end portion DL-E of another data line DL adjacent to (e.g., closest to) the corresponding data line DL.

[0147] exist Fig. 7A and Figure 7B , the second portion CL-P2 is defined by a portion extending to the left side of the first portion CL-P1. In an exemplary embodiment, the first conductive pattern CL1 may further include a portion extending to the right side of the first portion CL-P1 and not overlapping the end portion DL-E. The portion extending to the right side of the first portion CL-P1 may be defined as a third portion. However, a portion (e.g., the third portion) where the contact hole cannot ensure a sufficient contact area may be omitted.

[0148] The second portion CL-P2 may be defined by a portion that does not overlap the end portion DL-E of the corresponding data line DL. Figure 7B The second part CL-P2 of the signal pad DP-PD shown on the right side is set at Figure 7B Between the two end portions DL-E of the two data lines DL shown in FIG.

[0149] The second conductive pattern CL2 is disposed on the fourth insulating layer 40. The second conductive pattern CL2 contacts the second portion CL-P2 through a second contact hole CNT2 extending through (e.g., penetrating) the fourth insulating layer 40. The second contact hole CNT2 does not overlap the end portion DL-E when viewed in a plan view (e.g., on a plane parallel or substantially parallel to the top surface of the display panel DP).

[0150] The sixth insulating layer 60 is disposed on the fourth insulating layer 40. The third contact holes CNT3 and CNT30 are defined through the sixth insulating layer 60 to expose the second conductive pattern CL2. Figure 7B Two types of third contact holes CNT3 and CNT30 are shown as representative examples. They may be formed by different processes from each other. Figure 7B The third contact hole CNT3 shown on the left side and Figure 7B The third contact hole CNT30 shown on the right side of FIG. For example, the first input insulating layer ISL-IL1 can be obtained by forming the third contact hole CNT3 after forming the first input insulating layer ISL-IL1. Figure 7B The contact structure shown on the left side of FIG. can be obtained by forming the third contact hole CNT30 passing through the first input insulating layer ISL-IL1 and the sixth insulating layer 60 after forming the sixth insulating layer 60 and the first input insulating layer ISL-IL1. Figure 7B The contact structure is shown on the right side of FIG.

[0151] In more detail, it can be obtained by Figure 7B The contact structure shown on the left side of FIG: the first input insulating layer ISL-IL1 is deposited after the third contact hole CNT3 is formed; and the fourth contact hole CNT4 is formed through the first input insulating layer ISL-IL1 to expose the second conductive pattern CL2.

[0152] For a pad area NDA-PA shows Figure 7B The third contact hole CNT3 and the fourth contact hole CNT4 shown on the left side of Figure 7B The third contact hole CNT30 is shown on the right side of the pad area NDA-PA, but the present disclosure is not limited thereto. For example, in various exemplary embodiments, the contact structure in the pad area NDA-PA may be formed to have a Figure 7B The contact structure shown on the left side or Figure 7B The structure of the contact structure shown on the right side of is the same or substantially the same as the structure.

[0153] Reference Figure 7B A cross-sectional view of the pad area NDA-PA shown in FIG. Figure 5A In the cross-sectional view of the display area DP-DA shown in FIG, the stacking structures of the insulating layers are different from each other. For example, the fifth insulating layer 50 may not be provided in the pad area NDA-PA. Therefore, even if Figure 5A The second connection electrode CNE2 and Figure 7B The second conductive pattern CL2 shown in FIG. 1 may be formed by the same or substantially the same process, Figure 5A The second connection electrode CNE2 and Figure 7B The second conductive patterns CL2 shown in FIG. 1 may also be disposed on different layers from each other.

[0154] In addition, refer to Figures 3 to 5A , the upper insulating layer TFL may not be formed in the pad area NDA-PA. Fig. 6A Among the described first input insulating layer ISL-IL1, the second input insulating layer ISL-IL2, and the third input insulating layer ISL-IL3, the second input insulating layer ISL-IL2 and the third input insulating layer ISL-IL3 may not be formed in the pad area NDA-PA. In the pad area NDA-PA, the sixth insulating layer 60 may be directly disposed on the fourth insulating layer 40, and the first input insulating layer ISL-IL1 may be directly disposed on the sixth insulating layer 60.

[0155] In an exemplary embodiment, the insulating layer disposed on the second conductive pattern CL2 and exposing the second conductive pattern CL2 may be defined as a pad insulating layer. The pad insulating layer may overlap the display area DP-DA and the pad area NDA-PA. Figure 7B As shown in FIG. 1 , in an exemplary embodiment, the pad insulating layer may include a sixth insulating layer 60 and a first input insulating layer ISL-IL1.

[0156] Figure 7B The contact holes CNT3 and CNT4 as well as Figure 7B Each of the contact holes CNT30 shown on the right side of the can be defined as a pad contact hole. The third conductive pattern CL3 contacts the second conductive pattern CL2 through the pad contact holes CNT3, CNT4, and CNT30. Fig. 6A The second conductive layer ISL-CL2 shown in FIG. 4 forms a third conductive pattern CL3. The third conductive pattern CL3 may have a multi-layer structure, for example, a three-layer structure of titanium / aluminum / titanium.

[0157] When viewed in a plan view, the third conductive pattern CL3 is disposed at the pad contact holes CNT3, CNT4, and CNT30 (e.g., disposed inside, disposed inside, or disposed on the pad contact holes CNT3, CNT4, and CNT30). The third conductive pattern CL3 is disposed at the pad contact holes CNT3, CNT4, and CNT30 in a third direction DR3 (e.g., disposed inside, disposed inside, disposed inside, or disposed on the pad contact holes CNT3, CNT4, and CNT30). Figure 7B The pad contact holes CNT3 and CNT4 shown on the left side of the figure, the third conductive pattern CL3 is disposed at at least one of the two pad contact holes CNT3 and CNT4 (for example, disposed inside at least one pad contact hole CNT3, disposed in at least one pad contact hole CNT3, or disposed on at least one pad contact hole CNT3). The third conductive pattern CL3 is connected to the anisotropic conductive film ACF (for example, referring to Figure 4A ) in contact with (eg, in direct contact with) a pattern, and in Figure 7B In the exemplary embodiment shown in FIG. 1 , the third conductive pattern CL3 may be defined as an upper conductive pattern. The sixth insulating layer 60 (eg, referring to FIG. 1 ) in the pad area NDA-PA Figure 7B ) may have a thickness TH61 that is equal to the thickness of the sixth insulating layer 60 (eg, referring to Figure 5A The thickness TH60 of the sixth insulating layer 60, which may be an organic layer, may be controlled according to regions using a half-tone mask.

[0158] The thickness TH61 of the sixth insulating layer 60 in the pad area NDA-PA may be smaller than the thickness TH60 of the sixth insulating layer 60 in the display area DP-DA. The thickness TH61 of the sixth insulating layer 60 in the pad area NDA-PA may be, for example, in a range from about 45% to about 55% of the thickness TH60 of the sixth insulating layer 60 in the display area DP-DA. The thickness TH61 is obtained by measuring the thickness of an area (hereinafter, referred to as a "blocking area") 60-BP between two end portions DL-E of the sixth insulating layer 60 disposed at the pad area NDA-PA (e.g., disposed in the pad area NDA-PA or disposed on the pad area NDA-PA), and the thickness TH60 is obtained by measuring the thickness of the sixth insulating layer 60 at an area overlapping with the transistor T2 in the display area DP-DA.

[0159] When the thickness TH61 of the sixth insulating layer 60 in the pad area NDA-PA is small, the third conductive pattern CL3 and the anisotropic conductive film ACF (eg, refer to Figure 4A ). The third conductive pattern CL3 is positioned lower than the upper surface of the sixth insulating layer 60 and the upper surface of the first input insulating layer ISL-IL1. The portion of the pad insulating layer overlapping the end portion DL-E of the data line DL acts as a barrier to prevent or substantially prevent the third conductive patterns CL3 from being short-circuited with each other.

[0160] For example, the first conductive layer ISL-CL1 may be formed on a surface (eg, the entire surface) of the first input insulating layer ISL-IL1, and the first conductive layer ISL-CL1 may be patterned by an etching process to form a bridge portion CP1 (eg, refer to Figure 6C During the etching process of the first conductive layer ISL-CL1 at (e.g., in or on) the pad area NDA-PA, residues may remain on the first input insulating layer ISL-IL1. The blocking area 60-BP may function as a barrier to prevent or substantially prevent the etching residues from short-circuiting the third conductive pattern CL3 of the signal pad DP-PD adjacent to the etching residues.

[0161] like Figure 7C As shown in FIG. 1 , in an exemplary embodiment of the present invention, the end portion DL-E of the data line DL may be disposed at a position corresponding to Figure 5A The first contact hole CNT1 extends through (eg, penetrates) the second insulating layer 20 and the third insulating layer 30. The gate G2 and the end portion DL-E of the data line DL may be formed by the same or substantially the same process.

[0162] like Fig.7D As shown in, in an exemplary embodiment of the present invention, the second conductive pattern CL2 may include a first portion CL-P1 overlapping the end portion DL-E and a second portion CL-P2 extending from the first portion CL-P1. When viewed in a plan view, the second contact hole CNT2 may overlap the first contact hole CNT1. The first portion CL-P1 of the second conductive pattern CL2 contacts the first conductive pattern CL1 through the second contact hole CNT2.

[0163] The second portion CL-P2 of the second conductive pattern CL2 is exposed through the third contact holes CNT3 and CNT30, and the third conductive pattern CL3 contacts the second portion CL-P2 of the second conductive pattern CL2.

[0164] In this case, the first conductive pattern CL1 may have a length in the second direction DR2 that is smaller than that of the second conductive pattern CL2. When viewed in a plan view (e.g., on a plane parallel or substantially parallel to the top surface of the display panel DP), the first conductive pattern CL1 may not overlap the third contact holes CNT3 and CNT30. The first conductive pattern CL1 may further include a portion corresponding to (e.g., overlapping) the second portion CL-P2 of the second conductive pattern CL2.

[0165] Fig. 8A is a partial plan view showing a pad area NDA-PA according to an exemplary embodiment of the present disclosure. Figure 8B is along Fig. 8A A cross-sectional view taken along line II-II'. Figure 8C is along Fig. 8A The cross-sectional view taken along the line III-III' of FIG. Figures 1 to 7D The components and / or configurations described are identical or substantially identical to the components and / or configurations described redundantly.

[0166] The signal pads DP-PD may be arranged in a plurality of rows different from each other, for example, a first pad row PDL1 and a second pad row PDL2. The second pad row PDL2 is disposed adjacent to an edge DP-E of the display panel DP in the first direction DR1, so that the second pad row PDL2 is closer to the edge DP-E than the first pad row PDL1 in the first direction DR1. The signal pads of the first pad row PDL1 may be referred to as first signal pads DP-PD1, and the signal pads of the second pad row PDL2 may be referred to as second signal pads DP-PD2.

[0167] The second signal pads DP-PD2 are arranged in a staggered arrangement relative to the first signal pads DP-PD1. The third conductive patterns CL3 of the first pad row PDL1 are aligned with the end portions DL-E of the data lines DL connected to the second pad row PDL2 in the first direction DR1. The third conductive patterns CL3 of the first pad row PDL1 are arranged diagonally (e.g., on a diagonal line) relative to the third conductive patterns CL3 of the second pad row PDL2.

[0168] Figure 8B A cross-sectional view showing the structure of the first signal pad DP-PD1 is shown. Figure 8B The structure of the first signal pad DP-PD1 shown in FIG. Figure 7B The structures of the signal pads DP-PD shown as representative examples are the same or substantially the same. Figure 8B ,exist Figure 8B The contact holes CNT3 and Figure 8B The contact holes CNT3 shown on the right side of are identical or substantially identical to each other.

[0169] The line portion DL-S of the data line DL connected to the second signal pad DP-PD2 overlaps the third conductive pattern CL3 of the first pad line PDL1. The data line DL connected to the second signal pad DP-PD2 is disposed at the same Figure 5A The gate G2 shown in FIG. 1 is in the same layer or substantially the same layer as that in FIG.

[0170] Figure 8C The structure of the second signal pad DP-PD2 can be similar to Figure 7C The structure of the signal pad DP-PD as a representative example shown on the left side of FIG. 1 is the same or substantially the same. However, the present disclosure is not limited thereto. For example, in various exemplary embodiments of the present disclosure, Figure 8B and Figure 8C The cross-sectional structure of the first signal pad DP-PD1 and the second signal pad DP-PD2 shown in FIG. 1 may be modified to have the same Fig.7D The structure of the signal pad DP-PD shown on the left side is the same or substantially the same as that of the signal pad DP-PD, or may be modified to be the same as that of Fig.7D In other words, in another exemplary embodiment, the second conductive pattern CL2 may include a first portion CL-P1 and a second portion CL-P2.

[0171] Fig. 9 is a partial cross-sectional view showing a pad area NDA-PA according to an exemplary embodiment of the present disclosure. Figures 1 to 8C The components and / or configurations described are identical or substantially identical to the components and / or configurations described redundantly.

[0172] Reference Fig. 9 , when Figure 7B Compared with the signal pads DP-PD shown in FIG. 1 , the second conductive pattern CL2 is omitted. The stacked structure of the insulating layers 10 to 40 is shown to have the same Figure 7B The stacking structure of the insulating layers 10 to 40 shown in FIG. 1 is the same or substantially the same. However, the present disclosure is not limited thereto, and one or more of the insulating layers 10 to 40 may be omitted, for example, the fourth insulating layer 40 may be omitted in another exemplary embodiment of the present disclosure.

[0173] In more detail, the signal pads DP-PD respectively connected to the first and second data lines DL may have the same or substantially the same stacked structure. In this case, the signal pad DP-PD includes an intermediate conductive pattern CL1 and an upper conductive pattern CL3. The intermediate conductive pattern CL1 includes a first portion CL-P1 overlapping the end portion DL-E of the data line DL and a second portion CL-P2 extending from the first portion CL-P1. When viewed in a plan view, the second portion CL-P2 of the intermediate conductive pattern CL1 may be disposed between the end portions DL-E of the two data lines DL. According to an exemplary embodiment, as Fig. 9 As shown in FIG. 1 , the intermediate conductive pattern CL1 includes a conductive pattern having a single-layer structure formed using one conductive layer. However, the present disclosure is not limited thereto. For example, according to reference Figure 7B In the described embodiment, the intermediate conductive pattern CL1 may include a conductive pattern having a multi-layer structure which may be formed using two or more conductive layers.

[0174] The first portion CL-P1 of the middle conductive pattern CL1 may be connected (e.g., directly connected) to the end portion DL-E of the data line DL, or may be connected to the end portion DL-E through one or more other conductive patterns. The upper conductive pattern CL3 does not overlap the end portions DL-E of the first and second data lines DL. The middle conductive pattern CL1 may be referred to as a first conductive pattern CL1. The upper conductive pattern CL3 may be referred to as a third conductive pattern CL3.

[0175] Fig. 10A is a partial plan view showing a pad area NDA-PA according to an exemplary embodiment of the present disclosure. FIG. 10B to FIG. 10E is along Fig. 10A The cross-sectional view taken along the line IV-IV' of FIG. Figures 1 to 9 The components and / or configurations described are identical or substantially identical to the components and / or configurations described redundantly.

[0176] Fig. 10A The pad area NDA-PA including the first pad line PDL1 and the second pad line PDL2 is shown. According to an exemplary embodiment, the signal pad DP-PD may not include a conductive pattern extending in the second direction DR2 , which may be different from the signal pad DP-PD described with reference to one or more of the above exemplary embodiments.

[0177] Fig. 10B and Fig. 10C According to other exemplary embodiments, Figure 7B and Figure 7CCorresponding cross-sectional view. The signal pad DP-PD includes a first conductive pattern CL1, a second conductive pattern CL2, and a third conductive pattern CL3. The second contact hole CNT2 overlaps the first contact hole CNT1. The second contact hole CNT2 and the first contact hole CNT1 overlap the end portion DL-E, the first conductive pattern CL1, the second conductive pattern CL2, and the third conductive pattern CL3. In an exemplary embodiment, the intermediate conductive pattern may have a two-layer structure, but the present disclosure is not limited thereto. In an exemplary embodiment of the present disclosure, the intermediate conductive pattern may include the first conductive pattern CL1 or the second conductive pattern CL2.

[0178] The thickness TH62 of the barrier region 60-BP in the pad region NDA-PA may be greater than Figure 5A The thickness TH60 of the sixth insulating layer 60 in the display area DP-DA shown in FIG. is small. The thickness TH62 of the blocking area 60-BP may be in a range from about 60% to about 80% of the thickness TH60 of the sixth insulating layer 60 in the display area DP-DA. The thickness TH62 of the blocking area 60-BP may be adjusted by controlling the amount of light irradiated onto the blocking area 60-BP during the exposure process.

[0179] In an exemplary embodiment, the thickness TH62 of the barrier region 60-BP is relatively greater than Figure 7B In the exemplary embodiment, because the end portion DL-E, the first conductive pattern CL1, the second conductive pattern CL2, and the third conductive pattern CL3 are stacked to overlap each other, the uppermost position of the third conductive pattern CL3 is relatively higher than Figure 7B Therefore, in an exemplary embodiment, when the thickness of the barrier region 60-BP is greater than Figure 7B When the thickness of the barrier region 60-BP shown in FIG. 1 is large, Fig. 10B The barrier region 60-BP shown in FIG. 5 may have the above-described function of a barrier (eg, the barrier region 60-BP may function as a barrier to prevent or substantially prevent etching residues from short-circuiting the third conductive patterns CL3 to each other).

[0180] Fig. 10D According to another exemplary embodiment, Figure 7B In an exemplary embodiment, the thickness TH61 of the barrier region 60-BP may be within the display region DP-DA (eg, see Figure 5A) is within a range from about 45% to about 55% of the thickness TH60 of the sixth insulating layer 60 in the pad insulating layer 60. According to an exemplary embodiment, the pad insulating layer may further include a third input insulating layer ISL-IL3. The third input insulating layer ISL-IL3 includes an opening IL3-OP defined therethrough to expose the third conductive pattern CL3. In an exemplary embodiment of the present disclosure, the pad insulating layer may further include a first input insulating layer ISL-IL1. In this case, the contact hole is defined through the first input insulating layer ISL-IL1 to expose the second conductive pattern CL2.

[0181] The third input insulating layer ISL-IL3 may be an organic layer. A region of the third input insulating layer ISL-IL3 disposed between the two end portions DL-E may be used as a barrier. An upper surface IL3-US of a portion of the third input insulating layer ISL-IL3 disposed between the two signal pads DP-PD is disposed higher than an uppermost end portion CL3-UP of the third conductive pattern CL3.

[0182] Fig.10E A cross-sectional view of a pad area NDA-PA according to an exemplary embodiment is shown. Fig.10E The exemplary embodiments shown in Fig. 10D The exemplary embodiments shown are different. According to the exemplary embodiments, Fig.10E As shown in , the pad insulating layer may not include the sixth insulating layer 60. In this case, the pad insulating layer may include a first input insulating layer ISL-IL1, a second input insulating layer ISL-IL2, and a third input insulating layer ISL-IL3. The first input insulating layer ISL-IL1 and the second input insulating layer ISL-IL2 may include an inorganic layer, and the third input insulating layer ISL-IL3 may include an organic layer.

[0183] The region of the third input insulating layer ISL-IL3 disposed between the two end portions DL-E may serve as a barrier. An upper surface IL3-US of a portion of the third input insulating layer ISL-IL3 disposed between the two signal pads DP-PD is disposed higher than an uppermost end portion CL3-UP of the third conductive pattern CL3.

[0184] Reference FIG. 10A to FIG. 10E , the third conductive patterns CL3 may be prevented or substantially prevented from being short-circuited with each other by modifying (e.g., adjusting) the thickness of the pad insulating layer disposed between the end portions DL-E of the data lines DL. Portions of the pad insulating layer may function as (or play the role of) a barrier. In addition, the barrier may be formed by controlling the stacking structure of the pad insulating layer and / or adjusting the thickness of an organic layer formed together with (e.g., concurrently or simultaneously with) the input sensor ISL.

[0185] Although one or more exemplary embodiments of the present disclosure are described with reference to the accompanying drawings, it should be understood that the embodiments described herein should be considered only in a descriptive sense and not for limiting purposes. Therefore, it will be understood by those skilled in the art that the various aspects and features of the present invention may be modified without departing from the spirit and scope of the present invention as defined by the claims and their equivalents.

Claims

1. A display device, comprising: Base layer; A plurality of electronic components are located on the substrate layer; a plurality of signal lines electrically connected to the plurality of electronic components; a plurality of signal pads, each of the plurality of signal pads being connected to a corresponding signal line among the plurality of signal lines; as well as Insulation pad, Each of the plurality of signal pads comprises: a first conductive pattern, overlapping with and contacting the end portion of the corresponding signal line; a second conductive pattern, located on the first conductive pattern, overlapping with and contacting the first conductive pattern; and a third conductive pattern, located on the second conductive pattern, overlapping with and contacting the second conductive pattern. wherein one of the first conductive pattern and the second conductive pattern comprises: a first portion overlapping the end portion of the corresponding signal line; and a second portion located between the end portion of the corresponding signal line and an end portion of another signal line adjacent to the corresponding signal line among the plurality of signal lines, the second portion extending from the first portion, and in: The pad insulating layer overlaps the plurality of electronic components, the plurality of signal lines, and the first conductive pattern; The pad insulating layer has a pad contact hole exposing at least a portion of the second conductive pattern; and The third conductive pattern is connected to the second conductive pattern through the pad contact hole.

2. The display device according to claim 1, wherein: The third conductive pattern is positioned within the pad contact hole in a plan view.

3. The display device according to claim 1, further comprising: a first insulating layer located on the end portion of the corresponding signal line; as well as a second insulating layer, located on the first conductive pattern, in: The first insulating layer has a first contact hole exposing the end portion of the corresponding signal line; The first conductive pattern is connected to the end portion of the corresponding signal line through the first contact hole; The second insulating layer has a second contact hole exposing the first conductive pattern; and The second conductive pattern is connected to the first conductive pattern through the second contact hole.

4. The display device according to claim 3, wherein: The first conductive pattern includes the first portion and the second portion, and The second contact hole overlaps the second portion of the first conductive pattern in a plan view.

5. The display device according to claim 3, wherein: The second conductive pattern includes the first portion and the second portion; The second contact hole overlaps the first portion of the second conductive pattern and the first conductive pattern in a plan view; and The pad contact hole overlaps the second portion of the second conductive pattern.

6. The display device according to claim 1, further comprising: a first insulating layer; a second insulating layer; A third insulating layer; as well as The fourth insulating layer, in: Each of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer is positioned under the pad insulating layer, The plurality of electronic components include an upper electrode, a transistor, and a light emitting element connected to the transistor, The transistor includes an active region, a gate located on the active region, a source extending from one side of the active region, and a drain extending from another side of the active region, The first insulating layer covers the active area, the source electrode and the drain electrode, The second insulating layer is located on the first insulating layer and covers the gate. The third insulating layer is located on the second insulating layer and covers the upper electrode, and The fourth insulating layer covers the third insulating layer.

7. The display device according to claim 6, wherein: The end portion is located in the same layer as that of the gate electrode or the upper electrode.

8. The display device according to claim 6, wherein: The first conductive pattern is located on the third insulating layer, and the second conductive pattern is located on the fourth insulating layer.

9. The display device according to claim 6, wherein: The pad insulating layer includes an organic layer, the organic layer including: a first portion located between the end portion of the corresponding signal line and the end portion of the other signal line; and a second portion overlapping the transistor, and Wherein, a thickness of the first portion of the organic layer is in a range from 45% to 55% of a thickness of the second portion of the organic layer.

10. The display device according to claim 6, wherein: Each of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer includes an inorganic layer, and Wherein, the pad insulating layer includes an organic layer.

11. The display device according to claim 1, further comprising a thin film encapsulation layer and an input sensor, in: The plurality of electronic components include light emitting components; The thin film encapsulation layer is located on the pad insulating layer and covers the light emitting element; and The input sensor is located on the thin film encapsulation layer, and the input sensor includes a sensing electrode.

12. The display device according to claim 11, wherein: The plurality of signal lines include a first signal line connected to the light emitting element and a second signal line connected to the sensing electrode.

13. The display device according to claim 1, wherein: The plurality of signal lines include a plurality of portions located on different layers.

14. The display device according to claim 1, wherein: The plurality of signal pads include a first signal pad and a second signal pad; The first signal pads form a first pad row; The second signal pads form a second pad row different from the first pad row; and The second signal pads are arranged in a staggered manner relative to the first signal pads.

15. The display device according to claim 14, wherein: The second signal pad is closer to the edge of the base layer than the first signal pad, and A signal line among the plurality of signal lines connected to one of the second signal pads overlaps the second portion of a corresponding first signal pad among the first signal pads.

16. The display device according to claim 14, wherein: An end portion of a signal line among the plurality of signal lines connected to a second signal pad among the second signal pads is located on a layer different from a layer where an end portion of a signal line among the plurality of signal lines connected to a first signal pad among the first signal pads is located.

17. The display device according to claim 1, further comprising: a circuit board electrically connected to the plurality of signal pads; as well as An anisotropic conductive film is configured to bond the plurality of signal pads to the circuit board.

18. A display device, comprising: The first signal line; The second signal line; A first signal pad connected to the first signal line; a second signal pad connected to the second signal line; as well as a pad insulating layer overlapping the first signal line and the second signal line, Wherein, the first signal pad comprises: an intermediate conductive pattern overlapping an end portion of the first signal line, the intermediate conductive pattern being connected to the end portion of the first signal line; and an upper conductive pattern located on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer, wherein the intermediate conductive pattern includes a first portion and a second portion, the first portion overlaps the end portion of the first signal line, the second portion is located between the end portion of the first signal line and the end portion of the second signal line, and the second portion extends from the first portion, and Wherein, the upper conductive pattern is connected to the second portion of the middle conductive pattern.

19. The display device according to claim 18, wherein: The upper conductive pattern does not overlap each of the end portion of the first signal line and the end portion of the second signal line.

20. A display device, comprising: A substrate layer including a display area and a non-display area; A first switch transistor, located on the display area; A second switch transistor, located on the display area; A first signal line connected to the first switch transistor; a second signal line connected to the second switch transistor; A first signal pad connected to the first signal line; a second signal pad connected to the second signal line; as well as a pad insulating layer overlapping the first switch transistor, the second switch transistor, the first signal line and the second signal line, Wherein, each of the first signal pad and the second signal pad comprises: an intermediate conductive pattern overlapping an end portion of a corresponding signal line among the first signal line and the second signal line, the intermediate conductive pattern being electrically connected to the end portion of the corresponding signal line; and an upper conductive pattern located on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer, wherein the pad insulating layer has a pad contact hole exposing a portion of the intermediate conductive pattern, the pad contact hole overlaps the end portion of the corresponding signal line, and The upper conductive pattern is connected to the middle conductive pattern through the pad contact hole, and in a plan view, the upper conductive pattern is positioned within the pad contact hole.

21. The display device according to claim 20, wherein: The pad insulating layer includes an organic layer, the organic layer includes: a first portion located between the first signal pad and the second signal pad; and a second portion overlapping the first switch transistor, and Wherein, a thickness of the first portion of the organic layer is in a range from 60% to 80% of a thickness of the second portion of the organic layer.

22. The display device according to claim 20, wherein: The pad insulating layer includes a first organic layer, at least one inorganic layer on the first organic layer, and a second organic layer on the at least one inorganic layer. The first organic layer includes: a first portion located between the first signal pad and the second signal pad; and a second portion overlapping the first switch transistor, and The thickness of the first portion of the first organic layer is in a range from 45% to 55% of the thickness of the second portion of the first organic layer.

23. The display device according to claim 20, wherein: The pad insulating layer includes at least one inorganic layer and an organic layer located on the at least one inorganic layer, and Wherein, an upper surface of a portion of the organic layer located between the first signal pad and the second signal pad is higher than an uppermost end portion of the upper conductive pattern.

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