A thyristor chip, a thyristor and a manufacturing method thereof

Abstract

The present invention discloses a thyristor chip and a manufacturing method thereof, wherein the chip comprises an N-type base region and a P-type base region located on an anode P-type layer; a cathode N-type region located on the upper surface of the P-type base region; a cathode metal located on the cathode emitter N-type region; an amplifying gate metal and a center gate metal located on the surface of the P-type base region; a first dielectric film layer of a specified thickness located on the amplifying gate metal; and an anode metal under the anode P-type layer. The present invention does not require a traditional structure to realize the suspension of the amplifying gate level, and can achieve the purpose of isolating the amplifying gate level from the cathode during packaging, and can improve the ability to withstand di / dt, which is beneficial to improving the performance of the thyristor, extending the service life, reducing the process complexity, and reducing the process cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a thyristor chip, a thyristor and a manufacturing method thereof. Background Art

[0002] High-power thyristor discrete devices with current levels greater than 300A and voltage levels greater than 1200V generally use flat-panel packaging structures such as Figure 1 As shown, from top to bottom are the tube cover 1, the upper molybdenum sheet 2, the thyristor chip 3, the lower molybdenum sheet 4, and the tube base 15. During the packaging process, a force of several tens of kilonewtons is applied to press the above components.

[0003] The thyristor chip 3 is a three-terminal four-layer semiconductor device, such as Figure 2 As shown, the three ends of the conventional thyristor are respectively an anode metal 31, a cathode metal 32, and a gate metal 33 (including an amplifying gate metal 34), and the four layers are respectively: an anode P-type layer 35 of a deep diffusion layer, a low-resistance N-type base region 36, a P-type base region 37 of a deep diffusion layer, and a high-concentration cathode N-type region 38 diffused to form an ohmic contact metal electrode on the anode P-type layer 35 and the cathode N-type region 38 as the anode and cathode terminals respectively, and an ohmic contact metal electrode is led out from the P-type base region 37 as the gate.

[0004] There are three electrodes in the thyristor chip: anode, cathode and gate. Adding a positive trigger signal between the gate and cathode can control the conduction of the thyristor. The gate and cathode are on the same surface, and both surfaces need to be covered with a metal film. The metal film leads to the electrode and realizes ohmic contact. The gate metal layer and the cathode metal layer must be isolated. Figure 3 As shown in the figure, the schematic diagram of the gate cathode surface structure, usually high-power thyristors are divided into a central gate level and an amplified gate level. The central gate is connected to the external trigger circuit through a gate component. The amplified gate can reduce the turn-on time, reduce the turn-on current, and increase the turn-on di / dt. Figure 1 As shown, the center gate is isolated from the cathode through the opening of the upper molybdenum sheet, and the amplification gate requires a special structure to be isolated from the cathode.

[0005] There are mainly three structures and manufacturing methods for isolating the gate and cathode of the amplifier in the prior art:

[0006] 1) The thickness of cathode metal 32 is 30um, the thickness of gate metal 34 is 10um, and the height difference between gate metal 34 and cathode metal 32 is 20um. During packaging, the upper molybdenum sheet 2 is a flat molybdenum sheet with a thickness of 3mm. The height difference between gate metal and cathode metal makes gate suspended, so as to isolate gate from cathode. Figure 4As shown. The manufacturing method for realizing this structure is: silicon wafer is diffused to realize doping of anode P-type layer 35, P-type base region 37, cathode N-type region 38 → evaporation / sputtering deposits a 20μm metal layer on the cathode surface of silicon wafer → photolithography process leaves out the metal layer of center gate and cathode → evaporation / sputtering deposits a 10μm metal layer on the cathode surface of silicon wafer → photolithography process leaves out the metal layer of center gate, cathode and amplification gate, and realizes the structure shown in 4.

[0007] The disadvantage is that the process is complicated and the gate cathode is prone to short circuit.

[0008] 2) There is a height difference of 20um between the gate and cathode of the silicon wafer layer, and the height of the metal layer is consistent. When encapsulating, the upper molybdenum sheet is a flat molybdenum sheet with a thickness of 3mm, and the gate is suspended. The silicon wafer is diffused with aluminum to form the anode P-type layer 35 and the P-type base region 37 → the gate region is chemically wet-grooved to dig a 20μm deep groove → evaporation / sputtering to deposit a 20μm metal layer on the cathode surface of the silicon wafer → photolithography process flows out the center gate, gate and cathode metal layers such as Figure 5 As shown, this is achieved by performing one photolithography and one chemical etching on the silicon in the amplification gate region, one metal layer deposition and one photolithography.

[0009] The disadvantage is that the process is complicated and the gate cathode is prone to short circuit.

[0010] 3) The height of the silicon wafer layer and the metal layer of the amplifying gate and cathode are consistent with each other, and are all 30μm. During packaging, the upper molybdenum sheet has a through hole groove or a blind hole groove that is consistent with the amplifying gate pattern of the tube core. The thickness of the molybdenum sheet is 3mm, and the blind hole groove is 1mm. The amplifying gate is suspended. The silicon wafer is diffused to achieve the doping of the anode P-type layer 35, the P-type base region 37, and the cathode N-type region 38 → a 30μm metal layer is deposited on the cathode surface of the silicon wafer by evaporation / sputtering → the photolithography process leaves the metal layer of the center gate, the amplifying gate, and the cathode → the molybdenum sheet is opened with a 1mm deep groove that is consistent with the amplifying gate pattern toward the core surface of the thyristor. Figure 6 This is achieved by opening a blind hole or through hole groove in the molybdenum sheet that is consistent with the pattern of the amplified gate.

[0011] The disadvantages are high cost, the pattern of the molybdenum sheet needs to be aligned with the pattern on the tube core, assembly is troublesome, and the gate cathode is prone to short circuit.

[0012] Achieving effective isolation between the gate and cathode without significantly increasing the cost has always been a technical problem that technical personnel in the field want to solve. Therefore, a new structure and manufacturing method are needed to achieve effective isolation between the gate and cathode without significantly increasing the cost. Summary of the invention

[0013] The present invention solves the technical problem of effectively isolating the amplifying gate and the cathode while reducing the cost, thereby improving the electrical performance of the thyristor and extending the service life.

[0014] The present invention provides a thyristor chip, comprising:

[0015] An N-type base region located above the anode P-type layer, and a P-type base region located above the N-type base region;

[0016] A cathode N-type region located in a partial area of ​​the P-type base region and having an upper surface flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region;

[0017] A cathode metal located above the cathode emission N-type region and exposing a portion of the upper surface of the cathode emission N-type region;

[0018] an amplified gate metal located on the surface of the P-type base region and in contact with both the P-type base region and the gate N-type region, and a central gate metal located on the upper surface of the P-type base region and not in contact with the gate N-type region;

[0019] A first dielectric film layer of a specified thickness located above the amplifying gate metal;

[0020] and an anode metal below the anode P-type layer.

[0021] In an embodiment of the present invention,

[0022] The amplifying gate metal has the same thickness as the cathode metal, and the first dielectric film layer has a thickness much smaller than that of the amplifying gate metal and the cathode metal.

[0023] In an embodiment of the present invention,

[0024] The first dielectric film includes at least one of a DLC film, a silicon nitride film or a silicon oxide film.

[0025] In an embodiment of the present invention,

[0026] A second dielectric film layer of a specified thickness is also provided on the upper surface of the P-type base region not covered by the cathode metal, the amplifying gate metal and the center gate metal. The thickness of the second dielectric film layer is much smaller than the thickness of the amplifying gate metal and the cathode metal. The second dielectric film includes a DLC film.

[0027] In an embodiment of the present invention,

[0028] The specified thickness of the first dielectric DLC film layer is set to 20 to 300 nm;

[0029] The specified thickness of the second dielectric thin film layer is set to 20 to 500 nm;

[0030] The total thickness of the chip is set to 1.2 mm;

[0031] The thickness of the amplifying gate metal and the cathode metal is set to 30 μm;

[0032] The carrier concentration of the N-type base region is set to 10 13 cm -3 ;

[0033] The anode P-type layer and the P-type base region are doped with aluminum, and the carrier concentration is set to 10 14 cm -3 ~10 16 cm -3 ;

[0034] The cathode N-type region is doped with phosphorus, and the carrier concentration is set to 10 19 cm -3 ;

[0035] The anode metal, cathode metal and gate metal are made of aluminum.

[0036] The present invention also provides a thyristor,

[0037] A thyristor chip comprising any of the above.

[0038] The present invention also provides a method for manufacturing a thyristor chip, comprising the following steps:

[0039] Simultaneously forming an anode P-type layer and a P-type base region on the lower surface and upper surface of the N-type substrate respectively;

[0040] Forming a cathode N-type region in a partial region of the P-type base region, the upper surface of which is flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region;

[0041] Synchronously forming ohmic contact electrode metals on the cathode emitter N-type region, the P-type base region, the gate N-type region and under the anode P-type layer, wherein a cathode metal exposing a portion of the upper surface of the cathode emitter N-type region is formed on the cathode emitter N-type region, an amplified gate metal contacting both the P-type base region and the gate N-type region is formed on the surface of the P-type base region, a central gate metal not contacting the gate N-type region is formed on the upper surface of the P-type base region, and an anode metal is formed under the anode P-type layer;

[0042] A first dielectric film layer of a specified thickness is formed on the amplification gate metal by a deposition process.

[0043] In an embodiment of the present invention,

[0044] The deposition process includes chemical vapor deposition process, physical vapor deposition process, ion beam deposition process, filtered vacuum cathode arc process, pulsed laser deposition process, magnetron sputtering process, wherein the chemical vapor deposition process includes PECVD process;

[0045] A second dielectric film layer of a specified thickness is also arranged on the upper surface of the P-type base region not covered by the cathode metal, the amplification gate metal and the center gate metal.

[0046] In an embodiment of the present invention,

[0047] The amplifying gate metal has the same thickness as the cathode metal;

[0048] The thickness of the first dielectric film layer and the thickness of the second dielectric film layer are both much smaller than the thickness of the amplifying gate metal and the cathode metal;

[0049] The first dielectric film includes at least one of a DLC film, a silicon nitride film or a silicon oxide film;

[0050] The second dielectric film includes a DLC film.

[0051] In an embodiment of the present invention,

[0052] The specified thickness of the first dielectric DLC film layer is set to 20 to 300 nm;

[0053] The specified thickness of the second dielectric thin film layer is set to 20 to 500 nm;

[0054] The PECVD process parameters for depositing the DLC film include the following settings:

[0055] The vacuum pressure of the deposition chamber was set to 10 -6 Pa;

[0056] The alkane gas flow rate range is set to 0-500 sccm;

[0057] The pressure range in the deposition chamber is set to 0-66.5 Pa;

[0058] The RF source was set to 13.56 MHz;

[0059] The deposition process time range is set to 3 to 10 minutes;

[0060] The chip temperature is kept constant during the deposition process, and the chip temperature is ≤300° C. during the deposition process.

[0061] The present invention provides a method for manufacturing a thyristor, including the method for manufacturing a thyristor chip according to any one of the above.

[0062] Compared with the prior art, one or more embodiments of the present invention may have the following advantages:

[0063] 1. The present invention applies DLC (diamond-like carbon) thin film material to the thyristor structure, and does not require a metal layer height difference, a silicon layer height difference, or a molybdenum sheet groove structure to achieve the purpose of isolating the amplifying gate level from the cathode during packaging.

[0064] 2. After adopting the structure of the present invention, the center gate level, the amplifying gate level, and the cathode metal layer are in the same height, and the molybdenum sheet is a complete and flat molybdenum sheet, which reduces the risk of gate cathode short circuit and further thyristor failure caused by contamination, gas breakdown, and misalignment of the molybdenum sheet pattern and the tube core pattern between the amplifying gate level and the cathode metal layer, and improves the isolation effect between the amplifying gate level and the cathode, which is beneficial to improving the performance of the thyristor and extending its service life.

[0065] 3. After adopting the structure of the present invention, the process steps of electrode deposition or metal layer etching, or the silicon wafer etching process, or the molybdenum sheet grooving process are reduced, thereby reducing the process complexity and the process cost.

[0066] 4. The present invention can improve the heat dissipation capacity of the thyristor by applying DLC ​​(diamond-like carbon) thin film material to the thyristor structure, and can improve the di / dt tolerance ability of thyristors of various types, sizes and structures, which is beneficial to improving the performance of the thyristor and extending the service life.

[0067] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0069] Figure 1 A schematic diagram of an explosion of a flat-plate thyristor package component is shown;

[0070] Figure 2 This is a schematic diagram of the structure of a traditional thyristor chip;

[0071] Figure 3 This is a schematic diagram of the gate cathode structure in a traditional thyristor chip;

[0072] Figure 4 It is a schematic diagram of the structure of the amplification gate and cathode isolation method 1 in the traditional thyristor chip;

[0073] Figure 5 It is a schematic diagram of the structure of the amplification gate and cathode isolation method 2 in the traditional thyristor chip;

[0074] Figure 6 It is a schematic diagram of the structure of the amplification gate and cathode isolation method 3 in the traditional thyristor chip;

[0075] Figure 7 is a schematic diagram of the structure of a thyristor chip according to an embodiment of the present invention;

[0076] Figure 8 is a schematic diagram of the structure of a thyristor chip according to another embodiment of the present invention;

[0077] Fig. 9 is a schematic flow chart of a method for manufacturing a thyristor chip according to an embodiment of the present invention;

[0078] Figure 10-12 is a schematic diagram of the structure of a thyristor chip for performing step 3 according to an embodiment of the present invention;

[0079] Figure 13-14 is a schematic diagram of the structure of a thyristor chip for performing step 4 according to an embodiment of the present invention;

[0080] Fig.15 Schematic diagram of a PEVCD process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.

[0082] First embodiment

[0083] Figure 7 is a schematic diagram of the structure of a thyristor chip according to an embodiment of the present invention. Figure 7 As shown, this embodiment provides a thyristor chip, including: an anode metal 31, a cathode metal 32, a center gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emitter N-type region 381 and a gate N-type region 382), and a first DLC film layer 391.

[0084] Diamond like carbon (DLC) film is a metastable type of amorphous carbon film containing a certain amount of diamond bonds (sp3). The main component of the film is carbon, in which the carbon atoms are bonded by covalent bonds. It has excellent properties such as high infrared transmittance, high hardness, low friction coefficient, high corrosion resistance, high resistivity, high thermal conductivity, and high chemical stability. It has many applications in the field of power semiconductor chip manufacturing.

[0085] This embodiment provides a thyristor chip, including:

[0086] An N-type base region 36 located on the anode P-type layer 35, and a P-type base region 37 located on the N-type base region 36;

[0087] A cathode N-type region 38 located in a partial region of the P-type base region 37 and having an upper surface flush with the upper surface of the P-type base region 37 , wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 ;

[0088] A cathode metal 32 located on the cathode emission N-type region 381 and partially exposing the upper surface of the cathode emission N-type region 381;

[0089] an enlarged gate metal 34 located on the upper surface of the P-type base region 37 and in contact with both the P-type base region 37 and the gate N-type region 382 , and a central gate metal 33 located on the surface of the P-type base region 37 and not in contact with the gate N-type region 382 ;

[0090] A first dielectric film layer 391 with a specified thickness located on the amplification gate metal 34;

[0091] and the anode metal 31 below the anode P-type layer 35 .

[0092] Specifically, the four layers of the thyristor chip of this embodiment are all made of semiconductor material silicon, and the total thickness of the thyristor chip is set to 1.2 mm. An N-type base region 36 is set on the anode P-type layer 35, and a P-type base region 37 is set on the N-type base region 36; a cathode N-type region 38 that does not completely cover the P-type base region 37 is set on the upper surface of the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 that is closer to the center of the chip in a direction parallel to the surface of the P-type base region 37;

[0093] The anode P-type layer 35 and the P-type base region 37 are doped with aluminum, and the carrier concentration is set to 10 14 cm -3 ~10 16 cm -3 ; The carrier concentration of the N-type base region 36 is set to 10 13 cm -3; The cathode N-type region 38 is doped with phosphorus, and the carrier concentration is set to 10 19 cm -3 ;

[0094] A cathode metal 32 that does not completely cover the cathode emitter N-type region 381 is disposed on the cathode emitter N-type region 381, an amplified gate metal 34 that contacts both the P-type base region 37 and the gate N-type region 382 is disposed on the upper surface of the P-type base region 37, and a central gate metal 33 that does not contact the gate N-type region 382 is disposed on the surface of the P-type base region 37, the amplified gate metal 34 and the cathode metal 32 have the same thickness, and the amplified gate metal 34 and the cathode metal 32 are set to have a thickness of 30 μm, and an anode metal 31 is disposed under the anode P-type layer 35, and the anode metal, cathode metal and gate metal are all made of aluminum. The values ​​of the doping elements, concentrations, preset thicknesses, etc. of each region can be selected according to actual needs.

[0095] A first dielectric film layer 391 of a specified thickness is arranged on the amplifying gate metal 34, and the first dielectric film 391 includes at least one of a DLC film, a silicon nitride film or a silicon oxide film. The specified thickness range of the DLC film layer is set to 20 to 300 nm, and the preferred range is set to 100 to 200 nm. The thickness of the first dielectric film layer 391 is much smaller than the thickness of the amplifying gate metal 34 and the cathode metal 32. In this embodiment, a layer of DLC (diamond-like carbon) film is deposited on the amplifying gate metal 34. The DLC film is a very good insulating dielectric material, and the set thickness is nanometers, which is much smaller than the thickness of the metal layer and the molybdenum sheet, and much smaller than the tolerance of the metal layer and the molybdenum sheet. The thyristor chip does not need to use the height difference of the metal layer, the height difference of the silicon sheet layer, or the structure of the molybdenum sheet slotting to perform the amplifying gate suspension treatment, and the purpose of isolating the amplifying gate and the cathode can be achieved, and the purpose of contacting the cathode metal layer with the molybdenum sheet can also be achieved. The use of the present invention can reduce the complexity and cost of the process and reduce the risk of gate cathode short circuit. A DLC film layer 391 is set. After adopting the structure of this embodiment, the center gate-level metal 33, the amplifier gate-level metal 34, and the cathode metal 32 have the same height, which is 30μm. The molybdenum sheet is a complete and flat molybdenum sheet, which reduces the risk of gate cathode short circuit and further thyristor failure caused by contamination, gas breakdown, misalignment of the molybdenum sheet pattern and the tube core pattern between the amplifier gate level and the cathode metal layer, and improves the isolation effect between the amplifier gate level and the cathode, which is beneficial to improving the performance of the thyristor and extending the service life.

[0096] In summary, one or more embodiments of the present invention have the following advantages:

[0097] 1. The present invention applies DLC (diamond-like carbon) thin film material to the thyristor structure, and does not require a metal layer height difference, a silicon layer height difference, or a molybdenum sheet groove structure to achieve the purpose of isolating the amplifying gate level from the cathode during packaging.

[0098] 2. After adopting the structure of the present invention, the center gate level, the amplifying gate level, and the cathode metal layer are in the same height, and the molybdenum sheet is a complete and flat molybdenum sheet, which reduces the risk of gate cathode short circuit and further thyristor failure caused by contamination, gas breakdown, and misalignment of the molybdenum sheet pattern and the tube core pattern between the amplifying gate level and the cathode metal layer, and improves the isolation effect between the amplifying gate level and the cathode, which is beneficial to improving the performance of the thyristor and extending its service life.

[0099] 3. After adopting the structure of the present invention, the process steps of electrode deposition or metal layer etching, or the silicon wafer etching process, or the molybdenum sheet grooving process are reduced, thereby reducing the process complexity and the process cost.

[0100] Second embodiment

[0101] Figure 8 is a schematic diagram of the structure of a thyristor chip according to another embodiment of the present invention. Figure 8 As shown, this embodiment provides a thyristor chip, including: an anode metal 31, a cathode metal 32, a center gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emitter N-type region 381 and a gate N-type region 382), a first dielectric film layer 391, and a second dielectric film layer 392.

[0102] This embodiment provides another thyristor chip, which is improved on the basis of the first embodiment, and a second dielectric film layer 392 of a specified thickness is further provided on the upper surface of the P-type base region 37 not covered by the cathode metal 32, the amplifying gate metal 34 and the central gate metal 33, and the specified thickness of the second dielectric film layer 392 is set to 20-500nm. The second dielectric film includes a DLC film.

[0103] The present invention applies DLC (diamond-like carbon) film material to the thyristor chip structure. Since the DLC film has high thermal conductivity, the heat dissipation capacity of the thyristor can be improved, and the di / dt tolerance of thyristors of various types, sizes and structures can be improved, which is beneficial to improving the performance of the thyristor and extending the service life.

[0104] Third embodiment

[0105] This embodiment provides a thyristor, comprising a thyristor chip of any one of the structures in the first or second embodiment above, and having the advantages of the first or second embodiment.

[0106] Fourth embodiment

[0107] Figure 7is a schematic diagram of the structure of a thyristor chip according to an embodiment of the present invention;

[0108] Fig. 9 is a schematic flow chart of a method for manufacturing a thyristor chip according to an embodiment of the present invention;

[0109] Figure 10-12 is a schematic diagram of the structure of a thyristor chip for performing step 3 according to an embodiment of the present invention;

[0110] Figure 13-14 is a schematic diagram of the structure of a thyristor chip for performing step 4 according to an embodiment of the present invention;

[0111] Fig.15 Schematic diagram of a PEVCD process according to an embodiment of the present invention.

[0112] like Figure 7 As shown, a thyristor chip manufactured by a thyristor chip manufacturing method provided by this embodiment includes: an anode metal 31, a cathode metal 32, a center gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emitter N-type region 381 and a gate N-type region 382), and a first dielectric film layer 391.

[0113] This embodiment provides a method for manufacturing a thyristor chip, comprising the following steps:

[0114] Step 1, synchronously forming an anode P-type layer 35 and a P-type base region 37 on the lower surface and upper surface of the N-type substrate respectively,

[0115] Step 2, forming a cathode N-type region 38 whose upper surface is flush with the upper surface of the P-type base region 37 in a partial area on the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.

[0116] Specifically, after the upper surface of the P-type base region 37 is photolithographically processed, ions are injected at the corresponding position to form a cathode N-type region 38 that does not completely cover the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 that is closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.

[0117] Step 3, simultaneously forming ohmic contact electrode metals on the cathode emitter N-type region 381, the P-type base region 37, the gate N-type region 382 and under the anode P-type layer 35, wherein a cathode metal 32 is formed on the cathode emitter N-type region 381 to expose a portion of the upper surface of the cathode emitter N-type region 381, and an amplified gate metal 34 is formed on the upper surface of the P-type base region 37 to contact both the P-type base region 37 and the gate N-type region 382, ​​and a central gate metal 33 is formed on the upper surface of the P-type base region 37 that is not in contact with the gate N-type region 382, ​​and an anode metal is formed under the anode P-type layer.

[0118] Specifically, a metal layer is deposited on the upper surface of the P-type base region 37 of the thyristor silicon-based chip by evaporation / sputtering process, such as Fig.10 Then, a photoresist layer consistent with the target pattern is obtained on this metal layer through a photolithography process, such as Fig.11 As shown; the metal layer at the non-target position is removed by etching to obtain the metal layer of the target pattern, and the photoresist is removed, thereby obtaining the cathode metal 32 on the cathode emitter N-type region 381 that does not completely cover the cathode emitter N-type region 381, the amplified gate metal 34 on the upper surface of the P-type base region 37 and in contact with the P-type base region 37 and the gate N-type region 382, ​​and the central gate metal 33 on the upper surface of the P-type base region 37 that does not contact the gate N-type region 382, ​​as shown Fig.12 As shown. The thickness of the gate metal 34 and the cathode metal 32 are the same, both set to 30um, and the other specified thicknesses and doping concentration ranges are all set using the parameters in the first embodiment. While the metal layer is being made on the upper surface of the P-type base region 37, the anode metal 31 is also deposited under the anode P-type layer 35 to form the anode metal 31.

[0119] Step 4: Form a first dielectric film layer 391 of a specified thickness on the amplification gate metal 34 by a deposition process.

[0120] Specifically, firstly, photoresist is coated on the surface of the amplified gate metal 34, the central gate metal 33, the cathode metal 32 and the P-type base region 37 not covered by the metal. Fig.13 As shown, a first dielectric film layer 391 of a specified thickness is deposited on the photoresist by a PECVD process, as shown in FIG. Fig.14 As shown. The thickness of the first dielectric film layer 391 is much smaller than the thickness of the gate metal 34 and the cathode metal 32, and the first dielectric film includes at least one of a DLC film, a silicon nitride film or a silicon oxide film. Fig.15 As shown in the figure, the PECVD process places the thyristor chip on which the DLC film is to be deposited on a heating plate and evacuates the vacuum pressure in the deposition chamber to 10 -6Pa; the alkane gas flow rate is set to 0-500sccm and sprayed into the cavity; the pressure in the cavity is automatically adjusted to 0-500mTorr, i.e., 0-66.5Pa, by the vacuum regulating valve; the alkane gas sprayed into the cavity is decomposed into C n H m+ ; The RF power supply is applied to both ends of the parallel plate capacitor, the heating plate is used as the cathode and grounded, the deposition chamber wall is used as the anode, and the areas of the positive and negative plates are different; the movement speeds of ions and electrons in the plasma are different under the excitation of the RF source, and the different areas of the plates cause a negative bias voltage of 200 to 1000 V between the plates, C n H m+ Under the action of negative bias, the substrate material is bombarded at high speed, and a DLC film with a thickness of about 20 to 300 nm is obtained in a deposition process time of 3 to 10 minutes. The temperature of the heating plate is set to remain constant during the deposition process, and the chip temperature is set to no more than 300°C during the deposition process. If the temperature is too high, the deposited diamond structure (sp 3 ) to graphite structure (sp 2 )change.

[0121] The deposition process also includes a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtered vacuum cathode arc process, a pulsed laser deposition process, and a magnetron sputtering process, wherein the chemical vapor deposition process includes a PECVD process.

[0122] In summary, this embodiment has the following advantages:

[0123] 1. The thyristor structure manufactured by the thyristor chip manufacturing method using DLC ​​(diamond-like carbon) thin film material in this embodiment does not require a metal layer height difference, a silicon layer height difference, or a molybdenum sheet groove structure to achieve the amplification gate level suspension, thereby achieving the purpose of isolating the amplification gate level from the cathode during packaging.

[0124] 2. After the thyristor structure is manufactured using the thyristor chip manufacturing method of DLC (diamond-like carbon) thin film material, the center gate level, the amplifying gate level, and the cathode metal layer are highly consistent, and the molybdenum sheet is a complete and flat molybdenum sheet, which reduces the risk of gate cathode short circuit and further thyristor failure caused by contamination, gas breakdown, and misalignment of the molybdenum sheet pattern and the tube core pattern between the amplifying gate level and the cathode metal layer, and improves the isolation effect between the amplifying gate level and the cathode, which is beneficial to improving the performance of the thyristor and extending its service life.

[0125] 3. After adopting the thyristor chip manufacturing method using DLC ​​(diamond-like carbon) thin film material, the process steps of electrode deposition or metal layer etching, or the silicon wafer etching process, or the molybdenum sheet grooving process is reduced, thereby reducing the process complexity and the process cost.

[0126] Fifth embodiment

[0127] like Figure 8 As shown, this embodiment provides a thyristor chip manufactured by a thyristor chip manufacturing method, including: an anode metal 31, a cathode metal 32, a center gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emitter N-type region 381 and a gate N-type region 382), a first dielectric film layer 391, and a second dielectric film layer 392.

[0128] This embodiment provides another method for manufacturing a thyristor chip, which is improved on the basis of the fourth embodiment, wherein a second dielectric film layer 392 of a specified thickness is further deposited on the upper surface of the P-type base region 37 not covered by the cathode metal 32, the amplifying gate metal 34 and the center gate metal 33 by a PEVCD process, and the specified thickness of the second dielectric film layer 392 is set to 20-500 nm. The second dielectric film includes a DLC film.

[0129] This embodiment applies DLC (diamond-like carbon) film material to the thyristor chip structure. Since the DLC film has high thermal conductivity, it can improve the heat dissipation capacity of the thyristor and the ability of thyristors of various types, sizes and structures to withstand di / dt, which is beneficial to improving the performance of the thyristor and extending its service life.

[0130] Sixth embodiment

[0131] This embodiment provides a method for manufacturing a thyristor, including the method for manufacturing a thyristor chip of any one of the fourth or fifth embodiments, and the advantages are as described in the fourth and fifth embodiments.

[0132] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention, and are not intended to limit the present invention. Any technician in the technical field of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. The protection scope of the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A thyristor chip, characterized in that: include: An N-type base region located above the anode P-type layer, and a P-type base region located above the N-type base region; A cathode N-type region located in a partial area of ​​the P-type base region and having an upper surface flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region; A cathode metal located above the cathode emission N-type region and exposing a portion of the upper surface of the cathode emission N-type region; an amplified gate metal located on the surface of the P-type base region and in contact with both the P-type base region and the gate N-type region, and a central gate metal located on the upper surface of the P-type base region and not in contact with the gate N-type region; A first insulating dielectric film layer of a specified thickness located above the amplifying gate metal; and an anode metal below the anode P-type layer; A molybdenum sheet located on the amplifying gate metal and on the cathode metal; The thickness of the amplifier gate metal is the same as that of the cathode metal, and the thickness of the first insulating dielectric film layer is much smaller than the thickness of the amplifier gate metal, the cathode metal and the molybdenum sheet, and is much smaller than the tolerance of the amplifier gate metal, the cathode metal and the molybdenum sheet, so as to achieve the purpose of isolating the amplifier gate metal and the cathode metal, and also achieve the purpose of contacting the cathode metal with the molybdenum sheet.

2. The thyristor chip according to claim 1, characterized in that: The first insulating dielectric film layer includes at least one of a DLC film, a silicon nitride film or a silicon oxide film.

3. The thyristor chip according to claim 2, characterized in that: A second dielectric film layer of a specified thickness is also provided on the upper surface of the P-type base region not covered by the cathode metal, the amplifying gate metal and the center gate metal. The thickness of the second dielectric film layer is much smaller than the thickness of the amplifying gate metal and the cathode metal. The second dielectric film layer includes a DLC film. The specified thickness of the second dielectric film layer is set to 20 to 500 nm. The thickness of the amplifying gate metal and the cathode metal is set to 30 μm.

4. The thyristor chip according to claim 3, characterized in that: The specified thickness of the first insulating dielectric film layer is set to 20 to 300 nm; The total thickness of the chip is set to 1.2 mm; The carrier concentration of the N-type base region is set to 10 13 cm -3 ; The anode P-type layer and the P-type base region are doped with aluminum, and the carrier concentration is set to 10 14 cm -3 ~10 16 cm -3 ; The cathode N-type region includes phosphorus doping, and the carrier concentration is set to 10 19 cm -3 ; The anode metal, cathode metal and gate metal are made of aluminum.

5. A thyristor, characterized in that: A thyristor chip comprising any one of claims 1 to 4.

6. A method for manufacturing a thyristor chip, characterized in that: The following steps are involved: Simultaneously forming an anode P-type layer and a P-type base region on the lower surface and upper surface of the N-type substrate respectively; Forming a cathode N-type region in a partial region of the P-type base region, the upper surface of which is flush with the upper surface of the P-type base region, wherein the cathode N-type region includes a cathode emitter N-type region and a gate N-type region; Synchronously forming ohmic contact electrode metals on the cathode emitter N-type region, the P-type base region, the gate N-type region and under the anode P-type layer, wherein a cathode metal exposing a portion of the upper surface of the cathode emitter N-type region is formed on the cathode emitter N-type region, an amplified gate metal contacting both the P-type base region and the gate N-type region is formed on the surface of the P-type base region, a central gate metal not contacting the gate N-type region is formed on the upper surface of the P-type base region, and an anode metal is formed under the anode P-type layer; Forming a first insulating dielectric film layer of a specified thickness on the amplifying gate metal by a deposition process; forming a molybdenum sheet on the amplifying gate metal and on the cathode metal; The thickness of the amplifier gate metal is the same as that of the cathode metal, and the thickness of the first insulating dielectric film layer is much smaller than the thickness of the amplifier gate metal, the cathode metal and the molybdenum sheet, and is much smaller than the tolerance of the amplifier gate metal, the cathode metal and the molybdenum sheet, so as to achieve the purpose of isolating the amplifier gate metal and the cathode metal, and also achieve the purpose of contacting the cathode metal with the molybdenum sheet.

7. The method according to claim 6, characterized in that The deposition process includes chemical vapor deposition process, physical vapor deposition process, ion beam deposition process, filtered vacuum cathode arc process, pulsed laser deposition process, magnetron sputtering process, wherein the chemical vapor deposition process includes PECVD process; A second dielectric film layer of a specified thickness is also arranged on the upper surface of the P-type base region not covered by the cathode metal, the amplifying gate metal and the central gate metal.

8. The method according to claim 7, characterized in that The thickness of the second dielectric film layer is much smaller than the thickness of the amplifying gate metal and the cathode metal; the specified thickness of the second dielectric film layer is set to 20-500nm; the thickness of the amplifying gate metal and the cathode metal is set to 30μm; The first insulating dielectric film layer includes at least one of a DLC film, a silicon nitride film or a silicon oxide film; The second dielectric film layer includes a DLC film.

9. The method according to claim 8, characterized in that The specified thickness of the first insulating dielectric film layer is set to 20 to 300 nm; The PECVD process parameters for depositing the DLC film include the following settings: The vacuum pressure of the deposition chamber was set to 10 -6 Pa; The alkane gas flow rate range is set to 0-500 sccm; The pressure range in the deposition chamber is set to 0-66.5 Pa; The RF source was set to 13.56 MHz; The deposition process time range is set to 3 to 10 minutes; The chip temperature is kept constant during the deposition process, and the chip temperature is ≤300° C. during the deposition process.

10. A method for manufacturing a thyristor, characterized in that: A method for manufacturing a thyristor chip comprising any one of claims 6 to 9.

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