Memory system, memory controller, and memory control method

Abstract

A memory system, a memory controller, and a memory control method, including a computer-readable medium for partially erasing a block in the memory system to enhance reliability. In one aspect, the memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: perform a first erase operation on a specific block in the memory, the specific block including a plurality of sub-blocks each having individual memory cells, one or more memory cells in the specific block being in one or more programming states before the first erase operation; and then perform a second erase operation on the first sub-block of the specific block, so that the first individual memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller may be configured not to perform the second erase operation on one or more other sub-blocks of the specific block.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and relates to a memory system, a memory controller and a memory control method, and in particular to a memory system, a memory controller and a memory control method capable of enhancing the reliability of the memory. Background Art

[0002] Some memory systems suffer from read disturb effects caused by repeated read operations, which can affect data integrity. Specifically, as the size of memory blocks increases, such as in three-dimensional (3D) memories, the read disturb effects become larger, and some memory pages in a memory block may not be in a precisely erased state before programming, which can deteriorate memory reliability. In some cases, even if a memory block experiences less read disturb effects after erasure, some pages may be irrecoverably damaged if the pages remain blank (or unprogrammed) for a very long time. Summary of the invention

[0003] The present invention describes systems and techniques, e.g., non-volatile memory systems, such as 3D NAND or NOR flash memory, for partially erasing memory blocks in the memory system to enhance the reliability of the memory system, e.g., by performing a coarse erase on the entire block and then performing a fine erase on one or more sub-blocks in the block.

[0004] A feature of one embodiment of the present invention is a memory system, which includes: a memory, including multiple blocks; and a memory controller, coupled to the memory and configured to: perform a first erase operation on a specific block in the memory, the specific block including multiple sub-blocks each having individual storage cells, wherein, before the first erase operation, one or more storage cells in the specific block are in one or more programming states; and then perform a second erase operation on a first sub-block of the specific block, so that the first individual storage cells of the first sub-block are in an erased state after the second erase operation.

[0005] After the first erase operation, memory cells of one or more other sub-blocks of the particular block may still be in the same state as memory cells of one or more other sub-blocks. The memory controller may be configured not to perform the second erase operation on one or more other sub-blocks of the particular block. The memory controller may be configured to perform the second erase operation only on the first sub-block of the particular block.

[0006] In some embodiments, after the first erase operation and before the second erase operation, the states of the memory cells in the particular block are distributed between the erased state and one of the programmed states. After the first erase operation, at least one of the memory cells in the particular block may be in one of the programmed states.

[0007] The first erase operation may be performed without a verify operation for verifying whether memory cells of a specific block are in an erased state.

[0008] In some embodiments, the memory controller is configured to perform a second erase operation by applying an erase voltage to the first individual memory cells and then verifying the state of the first individual memory cells. The memory controller may be configured to determine that at least one of the first individual memory cells is in one of the programmed states, and in response, reapply the erase voltage to the first individual memory cells. The memory controller may be configured to verify the state of the first individual memory cells after reapplying the erase voltage.

[0009] The memory controller may be configured to determine to program data in the specific block, and may perform a first erase operation on the specific block in response to the determination to program data in the specific block.

[0010] The memory controller may be configured to determine to program the data in the first sub-block, and may perform a second erase operation on the first sub-block in response to the determination to program the data in the first sub-block.

[0011] In some embodiments, the memory controller is configured to: program data in first individual memory cells of the first sub-block after the second erase operation. The first sub-block may include a plurality of memory pages, and the memory controller may be configured to sequentially program data in the plurality of memory pages of the first sub-block. The memory controller may be configured to: program a first portion of data in a first memory page of the plurality of memory pages; and program a second portion of data in a second memory page of the plurality of memory pages. The memory controller may be configured to: suspend programming of data in the plurality of memory pages after programming the first portion of data in the first memory page of the plurality of memory pages; and resume programming of the second portion of data in the second memory page of the plurality of memory pages after one or more other operations are completed.

[0012] In some cases, the memory controller is configured to suspend operations on the specific block after a first erase operation on the specific block; and resume operations on the specific block including performing a second erase operation on a first sub-block of the specific block.

[0013] In some cases, the memory controller is configured to: perform a third erase operation on a second sub-block of a specific block, so that each second memory cell of the second sub-block is in an erased state after the third erase operation, wherein one or more second other sub-blocks of the specific block still do not perform the third erase operation, and the one or more second other sub-blocks include the first sub-block. The third erase operation may be performed on the second sub-block after the first sub-block is filled with programming data.

[0014] In some embodiments, the memory controller is configured to perform a programming operation on a particular block such that at least one self-erased state in the memory cells is programmed to be in one of the programmed states, wherein the programming operation is performed after a first erase operation and before a second erase operation. The memory controller may be configured to perform the programming operation by applying one or more programming pulses to the memory cells of the particular block, and the programming operation may be performed without a verification operation for verifying the states of the memory cells of the particular block. After the programming operation, the states of the memory cells of the particular block may be distributed between the erased state and one of the programmed states.

[0015] The memory controller can be configured to: perform a first erase operation by issuing a first erase command, the first erase command including a first program code and an address of a specific block; and perform a second erase operation by issuing a second erase command, the second erase command including a second program code and an address of a first sub-block of the specific block, the second program code being different from the first program code.

[0016] The memory may be a three-dimensional (3D) memory, and each of the blocks may be a 3D block including a plurality of two-dimensional (2D) blocks, and each sub-block of a particular block may include one or more 2D blocks.

[0017] Prior to the second erase operation, states of memory cells in a second block of the plurality of blocks in the memory may be distributed between an erased state and one of a programmed state. The memory controller may be configured to apply the first erase operation to the second block in the memory.

[0018] Another embodiment of the present invention is characterized by a memory controller, which includes: at least one processor; and at least one non-temporary machine-readable storage medium, coupled to the at least one processor having machine-executable instructions stored thereon, wherein when the machine-executable instructions are executed by the at least one processor, the at least one processor performs operations including: performing a first erase operation on a specific block in the memory, the specific block including a plurality of sub-blocks each having respective storage cells, wherein, before the first erase operation, one or more storage cells in the specific block are in one or more programming states; and then performing a second erase operation on a first sub-block of the specific block, such that the first respective storage cells of the first sub-block are in an erased state after the second erase operation.

[0019] The operation may further include: performing a programming operation on a specific block so that at least one self-erased state in the memory cell is programmed to be in one of the programmed states, wherein the programming operation is performed after a first erase operation and before a second erase operation, and the programming operation is performed without a verification operation, wherein the verification operation is used to verify the state of the memory cell of the specific block.

[0020] Another aspect of the present invention is characterized by a method executed by a memory controller coupled to a memory, comprising: performing a first erase operation on a specific block in the memory, the specific block comprising a plurality of sub-blocks each comprising individual memory cells, wherein, before the first erase operation, one or more memory cells in the specific block are in one or more programming states; and then performing a second erase operation on a first sub-block of the specific block, so that the first individual memory cells of the first sub-block are in an erased state after the second erase operation.

[0021] The method may further include: performing a programming operation on a specific block so that at least one self-erased state in the memory cell is programmed to be in one of the programmed states, wherein the programming operation is performed after a first erase operation and before a second erase operation, and the programming operation is performed without a verification operation, wherein the verification operation is used to verify the state of the memory cell of the specific block.

[0022] The technology may be implemented for any type of controller to enhance the reliability of memory that is subject to read disturbance and / or other disturbances. The technology applies multi-stage erasure to a block and associated sub-blocks. Specifically, when a controller assigns a block for programming data, the controller may first coarsely erase the entire block to change the state distribution of the memory cells in the block so that more memory cells are in an intermediate state (e.g., a state between an erased state and a programmed state). The controller may then perform a fine erase on the sub-block to shift the state distribution from the intermediate state to the erased state before the controller begins programming the data in the sub-block. The fine erase may eliminate read disturbance issues from other sub-blocks on the sub-block. In some cases, after the coarse erase and before the fine erase, the controller may also perform soft programming (e.g., for shifting some memory cells away from the erased state) to prevent unrecoverable damage (e.g., due to keeping these memory cells blank for a long time). Operations on the block may be suspended and resumed. For example, after rough erasing, the controller may suspend soft programming or fine erasing operations to perform other operations, and then resume the performance of soft programming operations on blocks or fine erasing operations on sub-blocks. The controller may set different command codes for different operations (e.g., including normal erasing operations, rough erasing operations, fine erasing operations, soft programming operations, and normal programming operations). The controller may use a "set feature" command to reconfigure parameters inside the memory. By partially erasing a memory block, the technology also enables saving program / erase (P / E) cycles and increasing the life of the memory block.

[0023] The technology may be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices (e.g., 2-level cell devices), triple-level cell (TLC) devices, or quad-level cell (QLC) devices. The technology may be applied to various sizes of memory systems, such as two-dimensional (2D) memory systems or three-dimensional (3D) memory systems. The technology may be applied to various types of non-volatile memory systems, such as NAND flash memory, NOR flash memory, and the like. Additionally or alternatively, the technology may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSD), embedded systems, and the like.

[0024] The details of one or more disclosed embodiments are set forth in the accompanying drawings and the description below. Other features, embodiments, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A An example of a system including a memory device according to one or more implementations is described.

[0026] Figure 1B An example of a memory including memory blocks according to one or more implementations is described.

[0027] Figure 1C An example block of 2D memory is illustrated according to one or more implementations.

[0028] Figure 1D An example block of 3D memory is illustrated according to one or more implementations.

[0029] Figure 2 Examples of threshold voltage distributions and read voltages for memory cells in different states according to one or more embodiments are described.

[0030] Figure 3 Examples of threshold voltage distributions of memory cells after different operations on a memory block according to one or more embodiments are described.

[0031] Figure 4 Examples of erasing a memory block and programming data in sub-blocks of the memory block are shown according to one or more implementations.

[0032] Figure 5 Flowchart of a method of partially erasing a memory block in a memory according to one or more embodiments.

[0033]

Explanation of symbols

[0034] 100: System

[0035] 110: Installation

[0036] 112: Device controller / controller

[0037] 113: Processor

[0038] 114: Internal memory

[0039] 116: Memory

[0040] 118: Block

[0041] 120: Host device

[0042] 140: 2D memory block / block

[0043] 141, 157: Storage unit

[0044] 142, 152: Unit page

[0045] 143: Source select transistor (SST)

[0046] 144, 154: Unit string

[0047] 145: Ground select transistor (GST)

[0048] 146, 156: string selection line (SSL)

[0049] 148, 158: Ground selection line (GSL)

[0050] 149, 159: Common source line (CSL)

[0051] 150: 3D memory block / memory block / block

[0052] 160: Memory layer

[0053] 200: Example

[0054] 202, 204, 206, 208: Curve

[0055] 205: Point Line Curve

[0056] 500: Methods

[0057] 502, 504, 506: Steps

[0058] A, B, C: Status / Programming Status

[0059] BL0, BL1, BL n-1 BL n :row bit line

[0060] BL <n>< / n> BL <n+1> : Bit line

[0061] Er: Status / Erase Status

[0062] S0, S1, S2, S3: Status

[0063] V Disturb 、V Rd1 、V Rd2 、V Rd3 、V Rdpass : Read voltage

[0064] Vh0, Vh1, Vh2, Vh3, Vl0, Vl1, V12, Vl3: voltage

[0065] WL0, WL1, WL n-1 , WL n : Column word line

[0066] (a), (b), (c), (d): attached pictures DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0068] Figure 1A An example of a system 100 for erasing and / or programming data is illustrated. System 100 includes a device 110 and a host device 120. Device 110 includes a device controller 112 and a memory 116. Device controller 112 includes a processor 113 and an internal memory 114.

[0069] In some embodiments, device 110 is a storage device. For example, device 110 may be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid state disk drive (SSD), or some other suitable storage. In some embodiments, device 110 is a smart watch, a digital camera, or a media player. In some embodiments, device 110 is a client device coupled to host device 120. For example, device 110 is an SD card in a digital camera or a media player as host device 120.

[0070] Device controller 112 is a general purpose microprocessor or a special purpose microcontroller. In some implementations, device controller 112 is a memory controller for device 110. The following sections describe various techniques based on implementations where device controller 112 is a memory controller. However, the techniques described in the following sections are also applicable to implementations where device controller 112 is another type of controller other than a memory controller.

[0071] The processor 113 is configured to execute instructions and process data. The instructions include firmware instructions and / or other program instructions stored in the auxiliary memory as firmware code and / or other program code, respectively. The data includes program data corresponding to the firmware and / or other programs executed by the processor, plus other suitable data. In some embodiments, the processor 113 is a general-purpose microprocessor or a special-purpose microcontroller. The processor 113 is also called a central processing unit (CPU).

[0072] The processor 113 accesses instructions and data from the internal memory 114. In some embodiments, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the device 110 is an eMMC, an SD card, or a smart watch, the internal memory 114 is an SRAM. In some embodiments, when the device 110 is a digital camera or a media player, the internal memory 114 is a DRAM.

[0073] In some embodiments, the internal memory is a cache memory included in the device controller 112, such as Figure 1A The internal memory 114 stores scripts corresponding to instructions executed by the processor 113 and / or data requested by the processor 113 during runtime.

[0074] The device controller 112 transfers the script and / or data from the memory 116 to the internal memory 114. In some embodiments, the memory 116 is a non-volatile memory configured for long-term storage of instructions and / or data, such as a NAND flash memory device or some other suitable non-volatile memory device. In an embodiment where the memory 116 is a NAND flash memory, the device 110 is a flash memory device, such as a flash memory card, and the device controller 112 is a NAND flash controller. For example, in some embodiments, when the device 110 is an eMMC or SD card, the memory 116 is a NAND flash memory; in some embodiments, when the device 110 is a digital camera, the memory 116 is an SD card; and in some implementations, when the device 110 is a media player, the memory 116 is a hard disk drive. For illustration purposes only, the following description uses NAND flash memory as an example of the memory 116.

[0075] Figure 1B An example configuration of memory 116 is illustrated that includes a plurality of blocks 118. Memory 116 may be a two-dimensional (2D) memory or a three-dimensional (3D) memory.

[0076] Figure 1C An example configuration of a two-dimensional (2D) memory block 140 is illustrated when the memory 116 is a 2D memory. The block 140 may be the block 118. The block 140 includes memory cells 141 that are coupled in series to row bit lines BL0, BL1, . . . , BL n-1 and row bit line BL n To form a plurality of cell strings 144, and coupled to the column word lines WL0, WL1, . . . , WL n-1and column word lines WL n To form a plurality of unit pages 142 .

[0077] The block 140 may include multiple sub-blocks. Each sub-block may include one or more cell pages 142. Each sub-block may have the same number of cell pages 142 or a different number of cell pages 142. Each sub-block may have a start address and an end address that may be defined by the addresses of the cell pages in the sub-block.

[0078] The cell string 144 may include a plurality of memory cells 141 all connected in series, a source select transistor (SST) 143, and a ground select transistor (GST) 145. The gate of the SST 143 is connected to a string select line (SSL) 146. The gates of the SSTs in different strings are also connected to the same SSL. The gates of the memory cells 141 are respectively connected to word lines WL0, WL1, ..., WL2, ..., WL3, ..., WL4, ..., WL5, ..., WL6, ..., WL7, ..., WL8, ..., WL9, ..., WL10, ..., WL11, ..., WL12, ..., WL13, ..., WL14, ..., WL15, ..., WL16, ..., WL17, ..., WL18, ..., WL29, ..., WL30, ..., WL31, ..., W n-1 , word line WL n . The memory cell 141 is connected to a common source line (CSL) 149 via a GST 145. The gate of the GST 145 is connected to a ground selection line (GSL) 148. The gates of the GSTs in different strings are also connected to the same GSL. The cell page 142 may include a plurality of memory cells 141. The gates of the memory cells 141 in the cell page 142 are coupled in series to respective word lines (WL). When an input voltage is applied to the word line, the input voltage is also applied to the gates of the memory cells 141 in the cell page 142.

[0079] To read a specific cell page 142 in the block 140 in a read operation, a lower voltage is applied to a word line corresponding to the specific cell page 142. At the same time, a higher voltage is applied to other cell pages in the block 140. When the specific cell page 142 is read many times, the higher voltage may be repeatedly applied to other cell pages the same many times, which may cause read disturbance on the other cell pages.

[0080] The device 110 may include a Flash Translation Layer (FTL) to manage read, write, and erase operations. The FTL may be stored in the device controller 112, such as in the internal memory 114. The FTL uses a logical-to-physical (L2P) address mapping table that stores mappings from logical pages in a logical block to physical pages in a physical block.

[0081] Figure 1D An example 3D memory block 150 is illustrated when the memory 116 is a 3D memory. The memory block 150 may be the block 118. The memory cells 157 are arranged in three dimensions, such as an XYZ coordinate system, and are coupled to a plurality of word lines to form a plurality of cell pages 152 and to a plurality of bit lines (e.g., BL <n>< / n> and BL <n+1> ) to form a plurality of cell strings 154. The cell string 154 includes a plurality of memory cells 157 connected in series, wherein the memory cells 157 may be configured as SSTs coupled to a string selection line (SSL) 156, and the memory cells 157 may be configured as GSTs coupled to a ground selection line (GSL) 158. The memory cells 157 are connected to a common source line (CSL) 159 via the GSTs.

[0082] Memory block 150 may include multiple memory layers 160 stacked together vertically, such as in the Z direction. Each memory layer 160 may be a two-dimensional planar layer, such as in the XY plane, containing multiple cell pages 152. Each cell page 152 may be read and / or programmed individually.

[0083] To read a specific cell page 152 in the memory layer 160 in a read operation, a lower voltage is applied to the word line corresponding to the specific cell page 152. The lower voltage is also applied to other cell pages 152 in the memory layer 160. At the same time, a higher voltage is applied to other memory layers in the block 150. When the specific cell page 152 is read many times, the higher voltage will be applied to the other memory layers the same many times, which may cause read disturbance.

[0084] The memory block 150 may include multiple sub-blocks. Each sub-block may include one or more memory layers 160. Each sub-block may have the same number of memory layers 160 or a different number of memory layers 160. Each sub-block may have a start address and an end address that may be defined by the addresses of the memory layers 160 in the sub-block. Each sub-block may be erased and / or verified separately.

[0085] Figure 2 Describes the storage cells used for different states (e.g. Figure 1C 200 shows an example of a threshold voltage distribution and a read voltage of a memory cell 141 of FIG. 1 . The memory cell may be an MLC capable of storing two bits of data. The memory cell may be, for example, controlled by a memory controller (eg, Figure 1AThe memory cell is programmed or erased to have any one of four states S0, S1, S2, and S3. In some examples, state S0 is an erased state (1, 1), and states S1, S2, and S3 are programming states P1 (0, 1), programming states P2 (0, 0), and programming states P3 (1, 0). After programming or erasing, the memory cell has a corresponding threshold voltage. The threshold voltage is a characteristic of the memory cell. The memory cell may be a floating gate transistor or a charge trapping transistor. When a read voltage higher than or the same as the threshold voltage is applied to the gate of the memory cell, the memory cell may be turned on. When a read voltage lower than the threshold voltage is applied to the gate of the memory cell, the memory cell may be turned off. The read action is not a programming or erasing action, and it is not intended to change the state of the memory cell.

[0086] Each state corresponds to a distribution of threshold voltages between a range between a lower limit voltage and a higher limit voltage. A memory cell having a threshold voltage within a range is considered to be in a corresponding state. In other words, a memory cell in a state has a threshold voltage within a range. For example, if a memory cell has a threshold voltage between Vl0 and Vh0, the memory cell is in state S0; if a memory cell has a threshold voltage between Vl1 and Vh1, the memory cell is in state S1; if a memory cell has a threshold voltage between Vl2 and Vh2, the memory cell is in state S2; and if a memory cell has a threshold voltage between Vl3 and Vh3, the memory cell is in state S3. Curve 202, curve 204, curve 206, curve 208 respectively show the threshold voltage distributions of each state S0, state S1, state S2, state S3 of the memory cell.

[0087] During a normal programming operation, a memory cell is programmed from an erased state S0 to a desired programming state S1, programming state S2, or programming state S3 by applying a programming voltage to the memory cell and verifying whether the programmed memory cell is in the desired programming state. The verification action may use a verification voltage, such as a threshold voltage of a desired programming state, such as a voltage between Vl1 and Vh1 for S1, a voltage between Vl2 and Vh2 for S2, or a voltage between Vl3 and Vh3 for S3 to verify whether the memory cell is programmed to a desired programming state (e.g., S1, S2, or S3). The program / verify cycle may be repeated multiple times until the memory cell is programmed and verified to be in the desired programming state.

[0088] During a read operation, a read voltage may be applied to a word line coupled to the gate of a memory cell to determine whether the selected memory cell is in an on or off state. When a read voltage V greater than the threshold voltage of S0 but less than the threshold voltage of S1 is applied Rd1, the memory cell is turned on when it has state S0 and is turned off when it has state S1, state S2 or state S3; when a read voltage V greater than the threshold voltage of S1 but less than the threshold voltage of S2 is applied Rd2 , the memory cell is turned on when it has state S0 or state S1 and is turned off when it has state S2 or state S3; when a read voltage V greater than the threshold voltage of S2 but less than the threshold voltage of S3 is applied Rd3 When the memory cell is turned on when it has state S0, state S1 or state S2 and turned off when it has state S3. When a read voltage V greater than the threshold voltage of all states S0, state S1, state S2, state S3 is applied Rdpass , the memory cell is turned on regardless of its state.

[0089] Due to repeated read operations, a read disturbance phenomenon may occur. In the read disturbance phenomenon, the threshold voltage of a memory cell increases abnormally. Figure 2 As illustrated in FIG. 2 , in some cases, the distribution curve 204 for state S1 includes a higher threshold voltage (illustrated by dotted curve 205 ). For example, the new higher limit voltage Vh1 ′ is greater than the higher limit voltage Vh1 . Disturb When the memory cell with the threshold voltage in state S1 is turned off instead of on, it can be determined whether the memory cell is subjected to read disturbance by detecting whether the memory cell is turned on or off in a specific read state. In some cases, the memory cell in the state with the lower threshold voltage (e.g., S0 and S1) is subjected to read disturbance.

[0090] As noted above, memory cells in, for example, blocks, sub-blocks, or other cells may be erased in an erase operation prior to programming. In some embodiments, memory cells are erased by raising the p-well region of the memory cell to an erase voltage for a period of time and grounding the word line of the selected block or cell (which is connected to the gate of the memory cell) while the source and bit lines are floating. The erase voltage may be higher than the threshold voltage for the memory cell. In blocks or cells that are not selected for erasure, the word lines float. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source lines are also raised to a significant fraction of the erase voltage, thereby hindering erasure on the blocks that are not selected for erasure. In the blocks selected for erasure, a strong electric field is applied to the tunneling oxide layer of the selected memory cell, and the selected memory cell is erased as electrons from the floating gate are emitted to the substrate side, for example, by a Fowler-Nordheim tunneling mechanism. As electrons transfer from the floating gate to the p-well region, the threshold voltage of the selected cell decreases.

[0091] After applying an erase voltage to erase the memory cells, the erased memory cells in the block or unit may be in an erased state (e.g., S0) or in one or more programmed states (e.g., S1, S2, or S3). The state of the erased memory cells may have a distribution between the erased state and one of the programmed states (e.g., S1, S2, or S3). The memory controller may perform a verification or read reverse operation to verify whether the erased memory cells are in the erased state, for example, by applying a verification voltage Vh0. If the threshold voltage of a given memory cell is lower than Vh0, the memory controller may determine that the memory cell is properly erased to be in the erased state.

[0092] If the memory controller determines that not all erased memory cells are in the erased state, the memory controller may reapply the erase voltage to erase the memory cells and re-verify whether all erased memory cells are in the erased state. The erase-verify cycle may be repeated many times (e.g., 3, 4, or 5 times) until the memory cells are verified to be in the erased state.

[0093] Figure 3 An example of threshold voltage distribution of memory cells after different operations on a memory block according to one or more embodiments is illustrated. The operations may be performed by a memory controller, such as Figure 1A The memory block may be a 2D block, such as Figure 1C or a 3D block, such as Figure 1D The memory cell may be a multi-level cell (MLC). The memory cell may be erased or programmed to be in any of four states Er, state A, state B, and state C, for example Figure 2 The state of Er represents the erase state.

[0094] Figure 3 Figure (a) in FIG. 1 shows the state distribution of memory cells after programming of a memory block. A first number of memory cells are in an erased state Er, a second number of memory cells are in a programmed state A, a third number of memory cells are in a programmed state B, and a fourth number of memory cells are in a programmed state C.

[0095] As in Figure 5 As discussed in more detail in , a memory controller may perform a coarse erase operation on an entire block, then optionally perform a soft program operation on the entire block, and then perform a fine erase operation on the sub-blocks.

[0096] As noted above, during a normal erase operation, the memory controller may repeat the erase-verify cycle multiple times until the memory cells in the block or unit are properly erased to an erased state. A rough erase operation may include one or more steps of a normal erase operation. For example, a rough erase operation may include only a first step, such as applying an erase voltage to the memory cells of all blocks at once. A rough erase operation may be performed without a verify step, which is used to verify whether the memory cells are in an erased state. In some cases, a rough erase operation includes a verify step after the first erase step. A rough erase operation may include a second erase step after the verify step. Figure 3 Figure (b) in FIG. 1 shows the state distribution of memory cells after a rough erase operation on all blocks. Compared to being in the erased state Er or the programmed state A, more memory cells are in an intermediate state (including not only the erased state Er but also one or more programmed states). For example, in the case of QLC, due to the tight distribution, the intermediate state may include Er, A, B or other states. At least one of the memory cells may be in the programmed state A. In some cases, some memory cells may be in a deeper erased state than the necessary result of the rough erase operation.

[0097] Depending on the actual situation, the memory controller may perform a soft programming operation on all blocks. Similar to a rough erase operation relative to a normal erase operation, soft programming may include one or more steps of a normal programming operation. For example, soft programming may include only a first programming step of programming memory cells in all blocks by applying one or more programming pulses. Soft programming may be performed without a verification step.

[0098] The soft programming operation may be configured to apply one or more programming pulses to shift the threshold voltage of memory cells in the erased state to a threshold distribution in a programmed state (e.g., programmed state A), and / or shift the threshold voltage of deeper erased memory cells to a threshold distribution in the erased state. The soft programming operation is performed on all blocks without a subsequent erase operation. Figure 3 Figure (c) in FIG. 1 shows the state distribution of the memory cells after the soft programming operation on all blocks. Figure 3 The state distribution in the intermediate state shown in FIG. (b) is away from the erased state and moves toward the programmed state A. In this way, some memory cells having the erased state Er for a long time can be prevented from being irreversibly damaged.

[0099] Subsequently, the memory controller may select a sub-block in the entire block, for example, for programming data. The memory controller may perform a fine erase operation on the memory cells in the sub-block. The fine erase operation may include multiple erase-verify cycles until the memory cells in the sub-block are properly erased and verified to be in the erased state Er. Figure 3 Figure (d) in FIG. 1 shows the state distribution of the memory cells in the sub-block after the fine erase operation on the sub-block. The state distribution may be the same as the distribution of the erased state.

[0100] Figure 4 An example of erasing a memory block of a memory and programming data in a sub-block of the memory block is shown according to one or more embodiments. Erasing and programming may be performed by a memory controller, such as Figure 1A The memory block may be a 2D block, such as Figure 1C or a 3D block, such as Figure 1D The memory block may include n number of sub-blocks. Each sub-block may include z number of memory pages. Each memory page may include a plurality of memory cells.

[0101] The memory controller may issue different command codes for different operations. For example, the command code for a normal erase operation may be 60-address-D0; the command code for a rough erase operation may be 60-address-D8; the command code for a fine erase operation may be 60-address-DC; the command code for a normal programming operation may be 80-address-10; and the command code for a soft programming operation may be 88-address-10. The address may be a start address, an intermediate address, an end address, or an address range of a block or sub-block. The memory controller may also use a "set features" command to reconfigure parameters inside the memory.

[0102] like Figure 4 As described in , the memory controller first uses the command code "0x60-address-0xD8" to perform a rough erase operation on all blocks, where the address may be the starting address of all blocks. The memory controller may then suspend operations on all blocks and wait to prepare for other operations. After the other operations are completed, the memory controller resumes performing soft programming operations on all blocks by using the command code "0x88-address-0x10", where the address may be the starting address of all blocks. The memory controller then suspends operations on all blocks and uses the command code "0x60-address-0xDC" ​​to resume performing fine erase operations on sub-block X1 of all blocks, where the address may be the starting address of sub-block X1.

[0103] The memory controller may then use the command code "0x80-address-data-0x10" to perform a normal programming operation to program the data on the first memory page in sub-block X1, where address may be the starting address of the first memory page in sub-block X1. The memory controller may then repeat the normal programming operation (Z-1) times on the other (Z-1) memory pages of sub-block X1, respectively, until the memory pages in sub-block X1 are filled with programming data.

[0104] The memory controller may then use the command code "0x60-address-0xDC" ​​to perform a second fine erase operation on sub-block X2 of the entire block, where address may be the start address of sub-block X2. Similar to programming the Z memory pages in sub-block X1, the memory controller may sequentially program the data in the Z memory pages in sub-block X2.

[0105] Similarly, the memory controller may sequentially perform each fine erase operation on each of the other sub-blocks in the entire block (up to (n-1) iterations, where n=# of sub-blocks per block), and sequentially program the data in the Z memory pages in each of the other sub-blocks (up to (Z-1) iterations, where Z=# of pages per sub-block). The memory controller may, for example, partially erase the entire block sub-block by sub-block, and correspondingly program the data in the partially erased blocks. In this way, read disturbance caused by an operation on a previous sub-block may be eliminated by a fine erase operation on the current sub-block.

[0106] Figure 5 is a flow chart of a method 500 for erasing a portion of a memory block in a memory according to one or more embodiments. The method 500 may be performed by a memory controller, such as Figure 1A The controller 112 executes. The memory may be the memory 116 of FIG. 1A. The memory includes a plurality of blocks. Each block may be a 2D block, for example Figure 1C or a 3D block, such as Figure 1D Each block may include n number of sub-blocks. Each sub-block may include multiple memory pages. Each memory page may include multiple memory cells. Each memory cell may be in an erased state, for example Figure 2 S0; or in programming state, such as Figure 2 S1, S2 or S3.

[0107] A rough erase operation is performed on a specific block in a memory (502). A memory controller may select a specific block to be programmed. The specific block may be pre-programmed, and one or more memory cells in the specific block may be in one or more programming states. Thus, the specific block may be erased prior to programming.

[0108] As noted above, the rough erase operation may include one or more steps of a normal erase operation. In some examples, the rough erase operation may be performed by applying an erase voltage to the memory cells of a particular block. The rough erase operation may be performed without a verify operation for verifying whether the memory cells in the particular block are in an erased state. After the rough erase operation, the states of the memory cells in the particular block may have a distribution that includes not only an erased state but also one or more programmed states, such as Figure 3 At least one of the memory cells in a particular block may be in one of the programmed states, for example Figure 2 S1.

[0109] After the rough erase operation, a soft programming operation is optionally performed on the particular block (504). As noted above, the soft programming operation is configured to move the threshold voltage of the memory cells in the erased state or even in an erased state deeper than the normal erased state toward the programmed state. The soft programming operation may include one or more steps of a normal programming operation. The soft programming operation may be performed by applying one or more programming pulses to the memory cells in the particular block. The soft programming operation may be performed without a verification operation, which is used to verify whether the memory cells of the particular block are in the desired programming state. After the soft programming operation, the states of the memory cells of the particular block may have a distribution between the erased state and one of the programmed states. The distribution after the soft programming operation may be further away from the erased state than the distribution after the rough erase operation. At least one self-erased state in the memory cells in the particular block is programmed to one of the programmed states.

[0110] Subsequently, a fine erase operation is performed on the sub-block of the specific block (506). The memory controller may determine the data in the programming sub-block, and perform the fine erase operation on the sub-block in response to determining the data in the programming sub-block. Performing the fine erase operation causes the storage cells of the sub-block to be in an erased state. The fine erase operation on the sub-block is not performed on one or more other sub-blocks of the specific block. In some embodiments, before performing the fine erase operation on the sub-block of the selected specific block, a rough erase operation or other similar method (e.g., an ultraviolet (UV) erase operation) may also be applied to one of the other blocks in the memory, which causes the state of the storage cells in the block to be distributed between the erased state and one of the programmed states. In this way, these unselected blocks can be prevented from remaining blank (unprogrammed) for a very long time.

[0111] As noted above, the fine erase operation may include multiple erase-verify cycles until the memory cells in the sub-block are properly erased and verified to be in an erased state. For example, the fine erase operation may include applying an erase voltage to the memory cells of the sub-block and then verifying whether the state of the memory cells is in the erased state. If the memory controller determines that at least one of the memory cells in the sub-block is not in the erased state or in one of the programmed states, the memory controller applies the erase voltage to the memory cells of the sub-block again and verifies the state of the memory cells after applying the erase voltage again.

[0112] In some embodiments, after performing a fine erase operation on a sub-block, the memory controller may program the data in the memory cells of the sub-block. Figure 4 As described in , a sub-block includes a plurality of memory pages, and a memory controller may sequentially program data in the plurality of memory pages of the sub-block. For example, the memory controller may program a first portion of data in a first memory page of the sub-block, and program a second portion of data in a second memory page of the sub-block. In some cases, the memory controller may suspend programming the data after programming the first portion of data in the first memory page. After a period of time or other operations are completed, the memory controller may resume programming the second portion of data in the second memory page.

[0113] After the memory pages in the sub-block are filled with the programming data, the memory controller may continue to perform a fine erase operation on the next sub-block of the specific block so that the memory cells in the next sub-block are erased to be in an erased state. The fine erase operation on the next sub-block is not performed on other sub-blocks (including the sub-blocks with programming data) of the specific block. The memory controller may repeat the same operation on each sub-block until the specific block is completely programmed, such as Figure 4 As described in .

[0114] The disclosed and other examples may be implemented as one or more computer program products, such as one or more modules of computer program instructions encoded on a computer-readable medium, which are executed by a data processing device or control the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more thereof. The term "data processing device" covers all devices, means, and machines for processing data, including by means of an example programmable processor, a computer or multiple processors or computers. In addition to hardware, the device may include program code that forms an execution environment for the computer program in question, such as program code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or a combination thereof.

[0115] A system may encompass all devices, apparatuses, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may include program code forming an execution environment for the computer program in question, such as program code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or a combination thereof.

[0116] A computer program (also called a program, software, software application, script, or program code) may be written in any form of a programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language file), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of program code). A computer program may be deployed to be executed on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0117] The methods and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The methods and logic flows may also be performed by, and the apparatus may be implemented as, a special purpose logic circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0118] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic components of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include one or more mass storage devices for storing data, such as magnetic, magneto-optical or optical disks, or be operatively coupled to the one or more mass storage devices to receive data from them, or transfer data to the one or more mass storage devices, or both. However, the computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0119] Although this text may describe many characteristics, these characteristics should not be interpreted as limitations on the claimed or claimable scope of the present invention, but rather as describing features specific to a particular embodiment. Certain features described in this text in the context of an independent embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination. Similarly, although the operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring the operations to be performed in the particular order shown or in a sequential order, or requiring all described operations to be performed to achieve a desired result.

[0120] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory system, characterized in that: include: A memory, including a plurality of blocks; as well as a memory controller coupled to the memory and configured to: Performing a first erase operation on a specific block in the memory, the specific block comprising a plurality of sub-blocks each having individual memory cells, wherein before the first erase operation, one or more memory cells in the specific block are in one or more programming states; then performing a second erase operation on a first sub-block of the specific block, so that first individual memory cells of the first sub-block are in an erased state after the second erase operation; wherein the first erasing operation is performed without a verification operation, the verification operation being used to verify whether the storage unit of the specific block is in the erased state; The memory controller is further configured to: suspend the operation on the specific block after the first erase operation on the specific block; and resume the operation on the specific block, including performing the second erase operation on the first sub-block of the specific block.

2. The memory system according to claim 1, wherein: After the first erase operation and before the second erase operation, states of the memory cells in the specific block are distributed between the erased state and one of the programmed states.

3. The memory system according to claim 2, wherein: After the first erase operation, at least one of the memory cells in the particular block is in the one of the programmed states.

4. The memory system of claim 1, wherein the memory controller is configured to perform the second erase operation by applying an erase voltage to the first respective memory cells and then verifying states of the first respective memory cells.

5. The memory system of claim 1 , wherein the memory controller is configured to determine the data in the specific block to be programmed, and The first erase operation is performed on the specific block in response to the determination to program the data in the specific block.

6. The memory system of claim 1 , wherein the memory controller is configured to determine to program data in the first sub-block, and The second erase operation is performed on the first sub-block in response to the determination to program the data in the first sub-block.

7. The memory system of claim 1 , wherein the memory controller is configured to: After the second erasing operation, data in each of the first storage cells of the first sub-block is programmed.

8. The memory system of claim 7 , wherein the first sub-block comprises a plurality of memory pages, and The memory controller is configured to sequentially program data in the plurality of memory pages of the first sub-block.

9. The memory system of claim 8, wherein the memory controller is configured to: After programming a first portion of data in a first memory page of the plurality of memory pages, suspending programming of the data in the plurality of memory pages; and After the one or more other operations are completed, programming of the second portion of the data is resumed in a second memory page of the plurality of memory pages.

10. The memory system of claim 1, wherein the memory controller is configured to: performing a third erasing operation on the second sub-block of the specific block, so that each second storage unit of the second sub-block is in the erased state after the third erasing operation, The third erasing operation is still not performed on one or more second other sub-blocks of the specific block, and the one or more second other sub-blocks include the first sub-block. 11 . The memory system of claim 10 , wherein the third erase operation is performed on the second sub-block after the first sub-block is filled with program data.

12. The memory system of claim 1, wherein the memory controller is configured to: performing a programming operation on the specific block so that at least one of the memory cells is programmed from the erased state to one of the programmed states, The programming operation is performed after the first erasing operation and before the second erasing operation.

13. The memory system of claim 12, wherein the memory controller is configured to perform the programming operation by applying one or more programming pulses to the memory cells of the specific block, and The programming operation is performed without a verification operation, wherein the verification operation is used to verify the states of the memory cells of the specific block.

14. The memory system according to claim 13, wherein: After the programming operation, the states of the memory cells of the specific block are distributed between the erased state and the one of the programmed state.

15. The memory system of claim 1, wherein the memory controller is configured to: The first erasing operation is performed by issuing a first erasing command, wherein the first erasing command includes a first program code and an address of the specific block, and The second erase operation is performed by issuing a second erase command, the second erase command including a second program code and an address of the first sub-block of the specific block, the second program code being different from the first program code.

16. The memory system according to claim 1, wherein: Before the second erase operation, states of memory cells in a second block of the plurality of blocks in the memory are distributed between the erased state and one of the programmed states.

17. The memory system of claim 16, wherein the memory controller is configured to apply the first erase operation to the second block in the memory.

18. A memory controller, characterized in that: include: at least one processor; as well as At least one non-transitory machine-readable storage medium, coupled to the at least one processor having machine-executable instructions stored thereon, which, when executed by the at least one processor, cause the at least one processor to perform operations comprising: performing a first erase operation on a specific block in a memory, the specific block comprising a plurality of sub-blocks each having a respective memory cell, wherein before the first erase operation, one or more memory cells in the specific block are in one or more programmed states; and then Performing a second erasing operation on a first sub-block of the specific block, so that each first storage unit of the first sub-block is in an erased state after the second erasing operation; wherein the first erasing operation is performed without a verification operation, the verification operation being used to verify whether the storage unit of the specific block is in the erased state; After the first erasing operation on the specific block, the operation on the specific block is suspended; and the operation on the specific block is resumed, including performing the second erasing operation on the first sub-block of the specific block.

19. A method performed by a memory controller coupled to a memory, comprising: Performing a first erase operation on a specific block in the memory, the specific block comprising a plurality of sub-blocks each comprising a respective memory cell, wherein before the first erase operation, one or more memory cells in the specific block are in one or more programming states; then Performing a second erasing operation on a first sub-block of the specific block, so that each first storage unit of the first sub-block is in an erased state after the second erasing operation; wherein the first erasing operation is performed without a verification operation, the verification operation being used to verify whether the storage unit of the specific block is in the erased state; After the first erasing operation on the specific block, the operation on the specific block is suspended; and the operation on the specific block is resumed, including performing the second erasing operation on the first sub-block of the specific block.

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