Storage controller and storage device

Abstract

A storage controller and a storage device are disclosed. The storage device includes a non-volatile memory including a plurality of memory blocks, and a storage controller configured to control a read operation of the non-volatile memory. When the storage device switches from a power-off state to a power-on state, the storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off and power-on time information indicating a power-on time point at which the storage device is powered on. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.

Description

[0001] This patent application claims the benefit of priority to Korean Patent Application No. 10-2019-0053900, filed on May 8, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present inventive concept relates to a storage device, and more particularly, to a storage controller and a storage device including the same. BACKGROUND

[0003] As a non-volatile memory such as a flash memory, stored data can be maintained even when power is interrupted. Storage devices including a flash memory (e.g., embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Solid State Drive (SSD), and memory card) are being widely used. Such storage devices are used to store or transfer a large amount of data. A flash memory stores data by changing a threshold voltage of a memory cell and reads data by using a pre-set read level. However, deterioration of the memory cell changes the threshold voltage of the memory cell, causing a read error. Therefore, there is a need to improve the reliability of such a storage device. SUMMARY

[0004] At least one embodiment of the present inventive concept provides a storage controller capable of improving the reliability of a read operation of a storage device and a storage device including the same.

[0005] According to one exemplary embodiment of the present inventive concept, a storage device includes a non-volatile memory including a plurality of memory blocks, and a storage controller configured to control a read operation of the non-volatile memory. When the storage device switches from a power-off state to a power-on state, the storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off, and receives power-on time information indicating a power-on time point at which the storage device is powered on. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.

[0006] According to one exemplary embodiment of the present inventive concept, a storage device includes a non-volatile memory including a plurality of memory blocks, and a storage controller configured to control a read operation of the non-volatile memory by using at least one read level. The storage controller receives power-off time information indicating a time point at which the storage device is powered off from an external source, and receives power-on time information indicating a time point at which the storage device is powered on from the external source, and controls the read operation by using a power-off period calculated based on the power-off time information and the power-on time information.

[0007] According to an exemplary embodiment of the present inventive concept, there is provided a storage controller including a memory configured to store a power-off timestamp, a power-on timestamp, and a read level lookup table including information indicating a read level according to a power-off period, and a processor configured to control a read operation of a nonvolatile memory. The processor stores the power-off timestamp by using input power-off time information indicating a power-off time point, and stores the power-on timestamp by using input power-on time information indicating a power-on time point, and controls the read operation of the nonvolatile memory using a power-off period calculated based on the power-off timestamp and the power-on timestamp and the read level lookup table. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of the present inventive concept will become more fully understood from the detailed description given herein below, and accompanied by the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating a storage system according to an exemplary embodiment of the present inventive concept;

[0010] Figure 2 is a block diagram illustrating an example configuration of a storage controller according to an exemplary embodiment of the present inventive concept; Figure 1

[0011] Figure 3A and Figure 3B is a block diagram illustrating a nonvolatile memory according to an exemplary embodiment of the present inventive concept; Figure 1

[0012] Figure 4 is an equivalent circuit diagram of a first memory block of Figure 3A and Figure 3B

[0013] Figure 5 is a perspective view of an example of a first memory block of Figure 3A and Figure 3B

[0014] Figure 6 is a diagram illustrating an example of a distribution change due to deterioration of memory cells included in a nonvolatile memory of Figure 3A and Figure 3B

[0015] Figure 7A and Figure 7B is a diagram illustrating a read level lookup table corresponding to a threshold voltage distribution change of Figure 6

[0016] Figure 8 is a flowchart of a method of operating a storage device according to an exemplary embodiment of the present inventive concept;​​​​​​

[0017] Figure 9 is a diagram illustrating a structure of data stored in a page of a first memory block constituting a memory device according to an exemplary embodiment of the inventive concept; Figure 3A and Figure 3B is a diagram illustrating a structure of data stored in a page of a first memory block constituting a memory device according to an exemplary embodiment of the inventive concept;

[0018] Figure 10A is a diagram illustrating a structure of data stored in a page of a first memory block constituting a memory device according to an exemplary embodiment of the inventive concept;

[0019] Figure 10B is a diagram illustrating an exemplary time elapsed after a first data of Figure 9 is programmed in a first page according to an exemplary embodiment of the inventive concept;

[0020] Figure 11 is a flowchart of a method of operating a memory device according to an exemplary embodiment of the inventive concept;

[0021] Figure 12 is a diagram for describing a read recovery operation of a memory device according to an exemplary embodiment of the inventive concept;

[0022] Figure 13 is a flowchart of a method of operating a memory device according to an exemplary embodiment of the inventive concept; and

[0023] Figure 14 is a block diagram illustrating an example in which a memory device according to an exemplary embodiment of the inventive concept is applied to a solid state drive (SSD). DETAILED DESCRIPTION

[0024] Figure 1 is a block diagram of a memory system according to an exemplary embodiment of the inventive concept.

[0025] Referring to Figure 1 , the memory system 10 includes a memory device 100 and a host 200. The host 200 (e.g., a host device) can control an operation of the memory device 100.

[0026] In one exemplary embodiment, the memory device 100 includes one or more solid state drives (SSDs). When the memory device 100 includes an SSD, the memory device 100 can include a plurality of flash memory chips (e.g., NAND memory chips) for storing data.

[0027] Storage device 100 may correspond to a flash memory device including one or more flash memory chips. In one exemplary embodiment, storage device 100 is an embedded memory included in storage system 10. For example, storage device 100 may be an embedded multimedia card (eMMC) or an embedded universal flash memory (UFS) device. In one exemplary embodiment, storage device 100 is an external memory detachably attached to storage system 10. For example, storage device 100 may be a UFS memory card, a compact flash (CF) card, a secure digital card (SD) card, a micro secure digital card (SD) card, a mini secure digital card (SD) card, an extreme digital (xD) card, or a memory stick.

[0028] Storage device 100 receives time information IN_T from host 200. The time information IN_T may include information about the time at which it performs an operation. Storage device 100 may receive the time information IN_T from host 200 as data, and may also receive the time information IN_T as a request.

[0029] In one exemplary embodiment, storage device 100 stores a timestamp TS based on received time information IN_T. In another exemplary embodiment, storage device 100 stores the timestamp TS in non-volatile memory 120. Alternatively, storage device 100 may store the timestamp TS in memory within storage controller 110.

[0030] In one exemplary embodiment, the time information IN_T includes power-off time information CT_OFF and power-on time information CT_ON. The power-off time information CT_OFF indicates the time when the storage device 100 is powered off, and the power-on time information CT_ON indicates the time when the storage device 100 is powered on. In one embodiment, after switching the storage device 100 from a power-off state to a power-on state, the host 200 provides the power-off time information CT_OFF and the power-on time information CT_ON together to the storage device 100.

[0031] Storage device 100 can calculate the power outage periods during which the storage device 100 is powered off based on power-off time information CT_OFF and power-on time information CT_ON. Storage device 100 can store a read level lookup table (e.g., including information indicating read levels based on different power outage periods). Figure 2 The LUT (Read Level Lookup Table) can be used to determine the read level for the read operation. In an optional embodiment, the host 200 provides a power-off period to the storage device 100 after switching it from a power-off state to a power-on state. Therefore, in this optional embodiment, the storage device 100 does not need to calculate the power-off period.

[0032] As the period of time during which the storage device 100 is not powered (i.e., the power-off period) increases, the memory cells of the non-volatile memory 120 can deteriorate, and the threshold voltage distribution of the deteriorated memory cells can change. The storage device 100 according to exemplary embodiments of the inventive concept can calculate the power-off period based on the power-off time information CT_OFF and the power-on time information CT_ON. The storage device 100 can adjust the read level for reading data according to the power-off period, thereby reducing read errors. In addition, when the storage device 100 is powered on, the read level can be determined by calculating the power-off period without performing an operation (e.g., a read retry operation) for providing read voltages having different read levels to the memory cells of the non-volatile memory 120 to detect an appropriate read level, and thus the time elapsed from the power-on to the read operation can be reduced.

[0033] The storage device 100 can detect old data from data stored in the memory cell array 122 of the non-volatile memory 120 based on the power-off time information CT_OFF and the power-on time information CT_ON. When the time elapsed after the data is programmed to the storage device is equal to or greater than a reference time, the storage device 100 can determine the programmed data as old data, i.e., invalid data. The storage device 100 can perform a read recycling operation on a memory block including the old data. Accordingly, the storage device 100 can determine invalid data without performing an error correction operation or a redundant array of independent disks (RAID) recovery operation, and can reduce the time elapsed for the read recycling operation. For example, if data is programmed to a first memory block of the memory 120, and the amount of time elapsed before the storage device 100 is powered off exceeds the reference time, the data of the first memory block can be considered invalid, and then a recycling operation can copy valid data of the first memory block to a second memory block that is free and erase the first memory block. If the amount of time elapsed when the storage device 100 is powered off does not exceed the reference time, the time elapsed when the storage device 100 is powered on can be added to the power-off period determined from CT_OFF and CT_ON to produce a sum, and if the sum exceeds the reference time, the data of the first memory block can be considered invalid, and then a recycling operation can copy valid data of the first memory block to a second memory block that is free and erase the first memory block.

[0034] The storage device 100 can include a storage controller 110 (e.g., a control circuit) for controlling overall operations of the storage device 100 and a nonvolatile memory 120 for storing data. The storage device 100 can store or read data DATA in response to a memory access request from the host 200. Also, the storage device 100 can receive a logical address from the host 200 and access data DATA in a physical area corresponding to the logical address. For example, when a request from the host 200 corresponds to a read request Req_R, the storage device 100 can output read data DATA to the host 200 in response to the request. For example, the storage controller 110 can convert a logical address into a physical address of the memory device 120.

[0035] The storage controller 110 can control operations of the nonvolatile memory 120 through a channel CH. The storage controller 110 can receive a read request Req_R and a logical address from the host 200 and read data DATA written in the nonvolatile memory 120 through the channel CH.

[0036] The nonvolatile memory 120 can include a memory cell array 122. In one example embodiment, the memory cell array 122 can include flash memory cells. For example, the flash memory cells can be NAND flash memory cells. However, the inventive concept is not limited thereto, and the memory cells can be resistive memory cells (e.g., resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, and magnetic RAM (MRAM) cells).

[0037] Figure 2 is a block diagram of a storage controller according to an example embodiment of the inventive concept. Figure 1

[0038] Referring to Figure 1 and Figure 2 , the storage controller 110 includes a processor 111, a host interface 112, a memory 113, a timer 114, and a nonvolatile memory interface 115. The above-described components can communicate with each other via a bus 116, and the storage controller 110 can further include other peripheral devices.

[0039] The processor 111 can control overall operations of the storage controller 110. The processor 111 can include a central processor or a microprocessor. The processor 111 can execute a firmware for driving the storage controller 110. The firmware can be loaded into the memory 113 and executed.

[0040] ​The host interface 112 can perform communication with the host 200. For example, the host interface 112 can provide a physical connection between the host 200 and the storage device 100. The host interface 112 can adjust the size of data exchanged with the storage device 100, or convert the format of a command to be exchanged into a format corresponding to a bus of the host 200. In one example embodiment, the host interface 112 can include a universal serial bus (USB), a multimedia card (MMC), a PCI express (PCI-E), an AT attachment (ATA), a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0041] The memory 113 can operate under the control of the processor 111. The memory 113 can be used as an operation memory, a cache memory, or a buffer memory of the processor 111. Software (i.e., firmware) for controlling the memory controller 110 can be loaded into the memory 113. The memory 113 can be implemented by a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). Alternatively, the memory 113 can be implemented by a non-volatile memory such as a flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), or a magnetic random access memory (MRAM).

[0042] In one example embodiment, the memory 113 stores a read level lookup table LUT including information indicating a time stamp TS and a read level according to a power-off period of the storage device 100 which can be derived from the time stamp TS. In one example embodiment, the time stamp TS and the read level lookup table LUT can be read from the non-volatile memory 120 and temporarily stored in the memory 113. Alternatively, the time stamp TS and the read level lookup table LUT can be stored in a separate memory 113 included in the memory controller 110.

[0043] In one example embodiment, the time stamp TS includes a power-off time stamp TS_OFF corresponding to a time point at which the storage device 100 is powered off and a power-on time stamp TS_ON corresponding to a time point at which the storage device 100 is powered on. The processor 111 can determine a read level of the non-volatile memory 120 based on the time stamp TS and the read level lookup table LUT stored in the memory 113. For example, the processor 111 can determine a read level of the non-volatile memory 120 based on the power-off time stamp, the power-on time stamp, and the read level lookup table LUT stored in the memory 113.

[0044] The timer 114 can provide internal time information for the operation of the storage controller 110 to the processor 111. The timer 114 can generate an internal current time by counting an internal clock signal, e.g., can count pulses of the internal clock signal to generate a current time. The internal clock signal can be generated by an oscillator within the storage device 100. The timer 114 can be implemented by hardware, e.g., a timer circuit. However, the inventive concept is not limited thereto, as the timer 114 can alternatively be implemented by software or firmware.

[0045] In one exemplary embodiment, when the storage device 100 is powered off, the timer 114 is reset, and when the storage device 100 is switched from the powered-off state to the powered-on state, the timer 114 can newly set internal time information reflecting the powered-off period. In one exemplary embodiment, the timer 114 sets the new internal time information reflecting the powered-off period by using the powered-off timestamp TS_OFF and the powered-on timestamp TS_ON. Alternatively, the timer 114 can set the new internal time information reflecting the powered-off period by using the powered-off time information CT_OFF and the powered-on time information CT_ON.

[0046] The non-volatile memory interface 115 can exchange data DATA with the non-volatile memory 120. The non-volatile memory interface 115 can transmit a read level control signal (e.g., CTRL_R in FIG. 3) for changing a read level for a read operation to the non-volatile memory 120 through the channel CH.

[0047] The storage controller 110 can further include an error correction code (ECC) circuit and a RAID recovery circuit. The ECC circuit can perform an error correction operation on data of an error correction unit using an ECC parity. The RAID recovery circuit can perform a RAID recovery using data constituting a RAID stripe and a RAID parity. In one exemplary embodiment, the RAID recovery circuit can perform the RAID recovery based on an exclusive OR (XOR) operation using the data and the RAID parity.

[0048] Figure 3A and Figure 3B is a block diagram illustrating a non-volatile memory according to an exemplary embodiment of the inventive concept. Figure 1

[0049] Referring to Figure 3A The non-volatile memory 120 includes an array of memory cells 122, an address decoder 123 (e.g., a decoding circuit), a control logic block 124 (e.g., a control circuit), a page buffer 125, an input / output circuit 126, and a voltage generator 127. The non-volatile memory 120 can further include an input / output interface.

[0050] ​The memory cell array 122 can be connected to the word lines WL, the string selection lines SSL, the ground selection lines GSL, and the bit lines BL. The memory cell array 122 can be connected to the address decoder 123 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL, and can be connected to the page buffer 125 through the bit lines BL. The memory cell array 122 can include a plurality of memory blocks BLK1 to BLKn.

[0051] Each of the memory blocks BLK1 to BLKn can include a plurality of memory cells and a plurality of selection transistors. The memory cells can be connected to the word lines WL, and the selection transistors can be connected to the string selection lines SSL or the ground selection lines GSL. The memory cells of each of the memory blocks BLK1 to BLKn can be single-layer cells each storing 1-bit data or multi-layer cells each storing M-bit data (M is an integer of 2 or more).

[0052] The address decoder 123 can select one of the plurality of memory blocks BLK1 to BLKn of the memory cell array 122, can select one of the word lines WL of the selected memory block, and can select one of the string selection lines SSL.

[0053] The memory cell array 122 can store a read level lookup table LUT including a time stamp TS and information indicating a read level corresponding to a power-off period of the storage device. The time stamp TS can include a power-off time stamp indicating a point in time at which the storage device is powered off and a power-on time stamp indicating a point in time at which the storage device is powered on. For example, the information indicating the read level corresponding to the power-off period can be stored in the lookup table LUT in the memory cell array 122. The memory cell array 122 can include different first, second, and third regions, wherein the first region includes the memory blocks BLK1 to BLKn, the second region includes the time stamp TS, and the third region includes the LUT.

[0054] The control logic block 124 can output various control signals for performing a program operation, a read operation, and an erase operation on the memory cell array 122 based on the command CMD, the address ADDR, and the control signal CTRL. The control logic block 124 can provide a row address X-ADDR to the address decoder 123, a column address Y-ADDR to the page buffer 125, and a voltage control signal CTRL_Vol to the voltage generator 127.

[0055] In one exemplary embodiment, the control logic block 124 receives a command CMD, an address ADDR, and a control signal CTRL from a storage controller (e.g., a memory controller) (not shown) and outputs various control signals for performing a program operation, a read operation, and an erase operation on the memory cell array 122. Figure 2The read level control signal CTRL_R can be a control signal that changes a read level by considering a threshold voltage distribution of the memory cells that changes as the storage device is powered off. The control logic block 124 can provide a read voltage control signal CTRL_Vol_R to the voltage generator 127 based on the read level control signal CTRL_R. For example, the voltage generator 127 changes a level of a read voltage RL according to the read voltage control signal CTRL_Vol_R.

[0056] The page buffer 125 can function as a write driver or a sense amplifier according to an operation mode. During a read operation, the page buffer 125 can sense a bit line BL of a selected memory cell under the control of the control logic block 124. The sensed data can be stored in a latch provided in the page buffer 125. The page buffer 125 can dump the data stored in the latch to the input / output circuit 126 under the control of the control logic block 124.

[0057] The input / output circuit 126 can temporarily store a command CMD, an address ADDR, a control signal CTRL, and data DATA provided from the outside of the nonvolatile memory 120 through an input / output line I / O. The input / output circuit 126 can temporarily store read data read from the nonvolatile memory 120, and output the read data to the outside through the input / output line I / O at a designated time point.

[0058] The voltage generator 127 can generate various types of voltages used to perform a program operation, a read operation, and an erase operation on the memory cell array 122 based on a voltage control signal CTRL_Vol. In detail, the voltage generator 127 can generate a word line voltage VWL (e.g., a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage). Further, the voltage generator 127 can generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_Vol. The voltage generator 127 can generate an erase voltage to be provided to the memory cell array 122.

[0059] In one exemplary embodiment, the voltage generator 127 receives the read voltage control signal CTRL_Vol_R after the storage device is switched from a power-off state to a power-on state, and generates a read voltage RL used to perform a read operation on the memory cell array 122. For example, a level of the read voltage RL can change based on a state of the read voltage control signal CTRL_Vol_R.

[0060] Referring to Figure 3BThe non-volatile memory 120b includes a memory cell array 122b, an address decoder 123, a control logic block 124b, a page buffer 125, an input / output circuit 126, and a voltage generator 127.

[0061] The memory cell array 122b can store a timestamp TS and a read level lookup table (LUT). The timestamp TS may include a power-off timestamp corresponding to the time when the storage device is powered off and a power-on timestamp corresponding to the time when the storage device is powered on.

[0062] With the storage controller (e.g., Figure 2 110) Calculate the read level Figure 3A The implementation methods differ, in Figure 3B In this embodiment, control logic block 124b determines the read level of non-volatile memory 120b based on a timestamp TS stored in memory cell array 122b and a read level lookup table (LUT). Control logic block 124b can calculate the power-off period of non-volatile memory 120b based on the timestamp TS and determine the read level corresponding to the calculated power-off period based on the read level lookup table (LUT). Control logic block 124b can provide a read voltage control signal CTRL_Vol_R to voltage generator 127 according to the determined read level.

[0063] Figure 4 yes Figure 3A and Figure 3B The equivalent circuit diagram of the first memory block.

[0064] Reference Figure 4 The first memory block BLK1 may include NAND strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground select lines GSL1 to GSL3, string select lines SSL1 to SSL3, and a common-source line CSL. Each NAND string (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST connected in series. The string select transistor SST is connected to the corresponding string select line SSL1. The ground select transistor GST is connected to the corresponding ground select line GSL1. The string select transistor SST is connected to the corresponding bit lines BL1 to BL3, and the ground select transistor GST is connected to the common-source line CSL.

[0065] The NAND strings NS11, NS12, and NS13 in the first row among the NAND strings NS11 to NS33 are commonly connected to the first string select line SSL1 and can constitute a first plane. The NAND strings NS21, NS22, and NS23 in the second row are commonly connected to the second string select line SSL2 and can constitute a second plane. The NAND strings NS31, NS32, and NS33 in the third row are commonly connected to the third string select line SSL3 and can constitute a third plane. In this embodiment, the first memory block BLK1 shows three planes connected to three bit lines BL1 to BL3.

[0066] The memory cells MC are connected to the corresponding word lines WL1 to WL8, respectively. A group of memory cells MC connected to one word line and programmed at the same time is referred to as a page. The first memory block BLK1 can include multiple pages. In one example embodiment, multiple pages can be connected to one word line, and a word line (e.g., WL4) that is the same height from the common source line CSL can be commonly connected to three pages.

[0067] Each memory cell MC can store one bit of data or two bits of data or more.

[0068] Figure 4 The number of rows and the number of columns of the NAND strings shown in the first memory block BLK1 of FIG. 1 can be increased or decreased. As the number of rows of the NAND strings changes, the number of planes can change. As the number of columns of the NAND strings changes, the number of bit lines connected to the columns of the NAND strings and the number of NAND strings connected to one string select line can also change. The height of the NAND strings can increase or decrease. For example, the number of memory cells stacked on each NAND string can increase or decrease.

[0069] Figure 5 is Figure 3A and Figure 3B A perspective view of an example of the first memory block BLK1 of FIG. 1. In Figure 5 In FIG. 1, “NS” denotes a NAND string.

[0070] Referring to Figure 5The first memory block BLK1 can be disposed in a direction perpendicular to the substrate SUB. The substrate SUB has a first conductivity type (e.g., p-type), and a common source line CSL extending along the first direction Y and doped with impurities of a second conductivity type (e.g., n-type) is disposed in the substrate SUB. An insulating film IL extending along the first direction Y is sequentially disposed along the third direction Z in the region of the substrate SUB located between two adjacent common source lines CSL, and the insulating films IL can be spaced apart from each other along the third direction Z. Pillars P arranged sequentially along the first direction Y and passing through the insulating film IL along the third direction Z can be disposed in the region of the substrate SUB located between two adjacent common source lines CSL. For example, pillars P can contact the substrate SUB by penetrating the insulating film IL. In detail, the surface layer S of each pillar P may include a silicon-based material doped with impurities of the first conductivity type and used as a channel region. On the other hand, the inner layer I of each pillar P may include an insulating material, such as silicon oxide or an air gap.

[0071] A charge storage layer CS may be disposed in the region between two adjacent common-source lines CSL along the exposed surfaces of the insulating film IL, pillar P, and substrate SUB. The charge storage layer CS may include a tunneling insulating layer, a charge trapping layer, and a barrier insulating layer. Furthermore, gate electrodes GE (e.g., selected gate lines GSL and SSL, and word lines WL1 to WL8) may be disposed on the exposed surface of the charge storage layer CS in the region between two adjacent common-source lines CSL. Drain contacts DR may be disposed on pillar P. For example, drain contacts DR may comprise a silicon-based material doped with impurities of a second conductivity type. Bit lines BL1 to BL3, extending along a second direction X and spaced apart from each other along a first direction Y, may be disposed on drain contacts DR.

[0072] Figure 6 It is shown that because it is included Figure 3A and Figure 3B A diagram illustrating an example of distribution changes caused by the degradation of memory cells in a non-volatile memory.

[0073] Reference Figure 6 In the initial distribution BPF and the modified distribution APO, the horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. For example, when the memory cells are four-level cells (QLCs) programmed with four-bit data, the memory cells can have one of the first programming states P1 to the fifteenth programming states P15 and the erase state E. The initial distribution BPF can be the distribution of memory cells before the memory device is powered off, and the modified distribution APO can be the distribution of memory cells after the memory device is powered on from the power-off state. Although Figure 6 The illustration shows a QLC (Quadruple Cell) memory cell, but the inventive concept is not limited to this and can be applied to single-layer cells (SLC) or other multi-layer cells (MLC, TLC, etc.).

[0074] Before power failure, the storage device can use first prefetch levels VR1 to fifteenth prefetch levels VR15 to identify each of the first programming states P1 to fifteenth programming states P15 and the erase state E of the memory cells. Each of the first prefetch levels VR1 to fifteenth prefetch levels VR15 can be a voltage level used to identify the corresponding programming state from the first programming states P1 to fifteenth programming states P15. For example, the first prefetch level VR1 can be a voltage level used to identify the first programming state P1, and the fifteenth prefetch level VR15 can be a voltage level used to identify the fifteenth programming state P15.

[0075] When the storage device is powered off, the memory cells of the storage device may degrade, and the threshold voltage of the degraded memory cells may change from the threshold voltage of the initial distribution BPF and form a modified distribution APO. Specifically, as the power-off period of the storage device increases, the charge stored in the charge storage layer of the memory cells may leak to the substrate. As a result, the threshold voltage of the memory cells may gradually decrease, and the distribution of the erase state E and the first programming states P1 to the fifteenth programming states P15 of the memory cells may gradually widen. At this time, when a read operation is performed on the degraded memory cells using the first prefetch level VR1 to the fifteenth prefetch level VR15, read errors may occur for some memory cells programmed to programming states P1 to P15. For example, if the threshold voltage of the first memory cell has a level indicating the erase state, and the storage device is subsequently powered off for a certain period of time and then powered on again, the threshold voltage may change to a level indicating the first programming state P1, resulting in a read error.

[0076] In the comparative example, a read retry operation can be performed to modify the read level to eliminate read errors. The storage device can execute firmware-based recovery code to perform the read retry operation. However, executing the recovery code can take a considerable amount of time, thus degrading the performance of the storage device.

[0077] On the other hand, according to this exemplary embodiment of the invention, when the storage device is powered on from a power-off state, the storage device receives power-off time information and power-on time information from the host. The power-off time information indicates the time point at which the storage device was powered off, and the power-on time information indicates the time point at which the storage device was powered on. The storage device may include a read level lookup table containing information indicating the read level according to the power-off period. For example, the read level lookup table may include a first read level (e.g., voltage level) for a first power-off period and a second read level different from the first read level for a second power-off period different from the first power-off period. The storage device may directly calculate the power-off period and determine a modified read level (e.g., VR1a to VR15a) corresponding to the calculated power-off period. Therefore, since the storage device does not need to perform a read retry operation to read data, the time spent on read operations after power-on can be reduced. For example, based on the calculated power-off period, the first pre-read level VR1 may be changed to a different first read level VR1a, the second pre-read level VR1 may be changed to a different second read level VR2a, etc.

[0078] Figure 7A and Figure 7B This illustrates an exemplary embodiment of the concept according to the present invention. Figure 6 A diagram illustrating an embodiment of a lookup table for reading levels corresponding to changes in threshold voltage distribution.

[0079] Reference Figure 6 and Figure 7A Information indicating the changes in the first prefetch level VR1 to the fifteenth prefetch level VR15 (i.e., Δ read level) based on the power-off period of the storage device can be stored in a read level lookup table (LUT). For example, when the power-off period is equal to or less than a first time T1, the storage device can decrease the first prefetch level VR1 to the fifteenth prefetch level VR15 by a first voltage V1. When the power-off period is greater than the first time T1 and equal to or less than a second time T2, the storage device can decrease the first prefetch level VR1 to the fifteenth prefetch level VR15 by a second voltage V2. When the power-off period is greater than the (i-1)th time T(i-1) and equal to or less than the i-th time Ti, the storage device can decrease the first prefetch level VR1 to the fifteenth prefetch level VR15 by an i-th voltage Vi. Here, i can be a natural number of 3 or greater. In one embodiment, voltages V1 to Vi are different from each other.

[0080] In one exemplary embodiment, the longer the power-off period, the greater the difference between the pre-read level and the modified read level (i.e., the Δread level). In other words, the second voltage V2 can be greater than the first voltage V1, and the i-th voltage Vi can be greater than the (i-1)-th voltage V(i-1). In other words, as the power-off period increases, the read level used to read the same programming state can decrease.

[0081] In one exemplary embodiment, when the power outage period is the same, the degree to which the first prefetch level VR1 to the fifteenth prefetch level VR15 are changed is equal to that of each other. In other words, the same read level lookup table (LUT) can be applied to change the first prefetch level VR1 to the fifteenth prefetch level VR15 to the first modified read level VR1a to the fifteenth modified read level VR15a. For example, when the power outage period of the storage device 100 is less than a first time T1, the first modified read level VR1a can be configured to decrease the first voltage V1 from the first prefetch level VR1, and the fifteenth modified read level VR15a can be configured to decrease the first voltage V1 from the fifteenth prefetch level VR15.

[0082] Reference Figure 6 and Figure 7B The read level lookup table (LUT) may include a first read level lookup table (LUT1) through a fifteenth read level lookup table (LUT15). Each of the first read level lookup tables (LUT1) through the fifteenth read level lookup table (LUT15) may store information indicating changes in the corresponding read level from the first pre-read level to the fifteenth pre-read level. For example, the first read level lookup table (LUT1) may store information indicating changes in the first pre-read level VR1 (i.e., Δ read level_1) according to a power-off period of the storage device. The fifteenth read level lookup table (LUT15) may store information regarding changes in the fifteenth pre-read level VR15 (i.e., Δ read level_15) according to a power-off period of the storage device.

[0083] For example, when the power outage period is equal to or less than the first time T1, the storage device can reduce the first prefetch level VR1 to the first voltage V1_1. When the power outage period is greater than the first time T1 and equal to or less than the second time T2, the storage device can reduce the first prefetch level VR1 to the second voltage V2_1. And when the power outage period is greater than the (i-1)th time T(i-1) and equal to or less than the i-th time Ti, the storage device can reduce the first prefetch level VR1 to the i-th voltage Vi_1.

[0084] Furthermore, when the power outage period is equal to or less than the first time T1, the storage device can reduce the fifteenth prefetch level VR15 to the first voltage V1_15. When the power outage period is greater than the first time T1 and equal to or less than the second time T2, the storage device can reduce the fifteenth prefetch level VR15 to the second voltage V2_15. And when the power outage period is greater than the (i-1)th time T(i-1) and equal to or less than the i-th time Ti, the storage device can reduce the fifteenth prefetch level VR15 to the i-th voltage Vi_15.

[0085] In one exemplary embodiment, when the power outage period is the same, the degree to which at least some of the first prefetch level VR1 to the fifteenth prefetch level VR15 are changed may differ. In one exemplary embodiment, for the same power outage period, the degree of change in the prefetch level used to determine a relatively high programming state is greater than the degree of change in the prefetch level used to determine a relatively low programming state. For example, the higher the programming state, the greater the shift in the threshold voltage distribution with the power outage period. For example, when the power outage period is equal to or less than the first time T1, the first voltage V1_1, which is the difference between the first prefetch level VR1 and the first modified read level VR1a, is less than the first voltage V1_15, which is the difference between the fifteenth prefetch level VR15 and the fifteenth modified read level VR15a.

[0086] Figure 8 This is a flowchart of a method for operating a storage device according to an exemplary embodiment of the present invention.

[0087] Reference Figure 1 and Figure 8 The method for operating the storage device according to this embodiment can be used in... Figure 1 It is executed in a time-series manner in the storage device 100.

[0088] In operation S10, the storage device 100 receives power-off time information CT_OFF and power-on time information CT_ON from the host 200. In an exemplary embodiment, when the storage device 100 switches from a power-off state to a power-on state, the storage device 100 receives the power-off time information CT_OFF and the power-on time information CT_ON from the host 200. The storage device 100 can store the power-off time in the power-off time information CT_OFF and the power-on time in the power-on time information CT_ON as timestamps.

[0089] In operation S20, the storage device 100 calculates the power-off period of the storage device 100 based on the stored timestamp. For example, the difference between the power-on time and the power-off time can be calculated based on the power-off timestamp and the power-on timestamp.

[0090] In operation S30, storage device 100 determines the read level based on the calculated power-off period. Storage device 100 may determine the read level based on a pre-stored read level lookup table. When the memory cells included in memory cell array 121 are MLCs (e.g., QLCs), multiple read levels may be determined in operation S30.

[0091] In operation S40, the storage device 100 performs a data read operation based on a determined read level. The storage device 100, according to the present invention, receives power-off time information CT_OFF and power-on time information CT_ON from an external source (i.e., the host 200) and takes them into account during the read operation; therefore, the accuracy of the read operation can be improved.

[0092] Figure 9 It shows the storage in the structure Figure 3A and Figure 3B A diagram illustrating the structure of the data in the pages of the first memory block BLK1.

[0093] Reference Figure 9 The first memory block BLK1 comprises multiple pages PAGE1 to PAGEj. Each of pages PAGE1 to PAGEj corresponds to a unit used for programming or reading data in a memory block.

[0094] The first data DATA1 can be stored in the first page PAGE1, the second data DATA2 can be stored in the second page PAGE2, and the j-th data DATAj can be stored in the j-th page PAGEj. In this case, j can be a natural number of 3 or greater.

[0095] Each of the first data DATA1, the second data DATA2, and the j-th data DATAj may include user data, spare data, and ECC parity check. In one example embodiment, each of the first data DATA1, the second data DATA2, and the j-th data DATAj may be data from an ECC unit (or an ECC block).

[0096] Backup data may include metadata indicating attributes of user data, and programming time information may be stored in the backup data. For example, information indicating the time when the first data DATA1 was programmed to the first page PAGE1 may be stored as a timestamp in the backup data.

[0097] ECC parity checking can be used to correct errors that occur in data included in ECC cells. In one example embodiment, errors occurring in one or more bits during the reading of first data DATA1 stored in the first page PAGE1 can be corrected by using ECC parity checking for error correction.

[0098] Despite the above referencesFigure 9 The given description pertains to the first data DATA1 stored in the first page PAGE1 of the first memory block BLK1, but the same description can be applied to other data stored in other pages of the first memory block BLK1, and the same description can also be applied to memory blocks other than the first memory block BLK1.

[0099] Figure 10A This is a diagram illustrating an auxiliary lookup table stored in a storage device according to an exemplary embodiment of the present invention. Figure 10B It is used to describe in Figure 9 The first data is programmed into a graph showing the time elapsed after the first page.

[0100] Reference Figure 10A The auxiliary lookup table LUTa can also be stored in a storage device. The auxiliary lookup table LUTa can store information indicating the read level based on the elapsed time since the data was programmed during the power-on period. For example, the auxiliary lookup table LUTa may include an indication of the pre-read level based on the elapsed time since the data was programmed during the power-on period (e.g., Figure 6 The information pertains to the changes in the first prefetch level VR1 to the fifteenth prefetch level VR15. In an exemplary embodiment, the auxiliary lookup table LUTa may be stored in non-volatile memory (e.g., ...). Figure 1 In 120). Optionally, in another exemplary embodiment, the auxiliary lookup table LUTa may be stored in a storage controller (e.g., Figure 1 (of 110).

[0101] For example, when the time elapsed after data is programmed during the power-on period is equal to or less than a first time T1a, the storage device can decrease the read level from the pre-read level to a first voltage V1a; when the time elapsed after data is programmed during the power-on period is greater than the first time T1a and equal to or less than a second time T2a, the storage device can decrease the read level from the pre-read level to a second voltage V2a; and when the time elapsed after data is programmed during the power-on period is greater than the (k-1)th time T(k-1)a and equal to or less than the kth time Tka, the storage device can decrease the read level from the pre-read level to a kth voltage Vka. In this case, k can be a natural number of 3 or greater.

[0102] In one exemplary embodiment, when the elapsed time after data is programmed during the power-on period is the same, a prefetch level (e.g., ...) is used to determine different programming states. Figure 6 The degree of modification of VR1 to VR15 in the above can be the same. In another exemplary embodiment, when the time elapsed after the data is programmed during the power-on period is the same, the prefetch level (e.g., for determining different programming states) is used to determine different programming states. Figure 6At least some of VR1 to VR15 may be modified to different degrees. In one exemplary embodiment, the degree of change in the prefetch level used to determine a relatively high programming state may be greater than the degree of change in the prefetch level used to determine a relatively low programming state.

[0103] Reference Figure 9 , Figure 10A and Figure 10B The storage device calculates the time elapsed from T_PRO to T_RE after the first data DATA1 was programmed, based on the programming time information stored in the spare data of the first data DATA1. For example, the time elapsed after the first data DATA1 was programmed can refer to the time between the time T_PRO when the first data DATA1 was programmed and the time T_RE when the first data DATA1 was read. The past time may include the Power_OFF period between a first time during which the first data DATA1 was programmed and a second time during which the first data DATA1 was read.

[0104] This can be achieved by setting a timer on the storage controller (e.g., Figure 2 The current time provided by timer 114 is compared with the programming time information stored in the backup data to calculate the elapsed time T_PRO to T_RE after the data was programmed. Timer 114 of the storage controller can be reset in a power-off state, and new time information considering the power-off period can be set based on time information received from the host. For example, if timer 114 has created a count representing past times that have not reached a reference time before the power outage of storage device 100, and timer 114 is reset due to the power outage, then timer 114 can begin counting based on the time of the power-off period derived from the timestamp received from the host after the power-on of storage device 100. For example, timer 114 can begin counting from the sum of the created count of past times and the count corresponding to the power-off period.

[0105] After the first data DATA1 is programmed, the storage device can be powered off at power-off time T_OFF and powered on at power-on time T_ON. The storage device can calculate the power-off period between power-off time T_OFF and power-on time T_ON, and by using... Figure 7A or Figure 7B A read level lookup table (LUT) is used to calculate the change in read level caused by the power outage period.

[0106] Furthermore, the storage device can calculate the time period from the time point T_PRO when the first data DATA1 is programmed to the power-off time point T_OFF and the time period from the power-on time point T_ON to the time point T_RE when the first data DATA1 is read, and can be used... Figure 10AThe auxiliary lookup table LUTa calculates the change in read level based on the elapsed time since the data was programmed during the power-on period.

[0107] Therefore, the storage device according to an exemplary embodiment of the present invention can determine the read level for a read operation by considering both the change in the threshold voltage distribution of the memory cells due to power failure and the change in the threshold voltage distribution of the memory cells over time after data is programmed during the power-on period. Thus, the storage device can have reduced errors during read operations.

[0108] Figure 11 This is a flowchart of a method for operating a storage device according to an exemplary embodiment of the present invention.

[0109] Reference Figure 1 and Figure 11 The method for operating the storage device according to this embodiment can be used in... Figure 1 The execution is performed in a time-series manner within the storage device 100. In one exemplary embodiment, it can be performed... Figure 8 After operation S40, it is executed as Figure 11 The operation of the method.

[0110] In operation S51, when a read request is received from host 200, storage device 100 reads the requested user data and the corresponding ECC parity check, and performs error correction on the read user data using the ECC parity check. For example, it can be read from the first page (e.g., ...). Figure 9 Together with PAGE 1, the storage device 100 reads user data and ECC parity check. In operation S52, the storage device 100 determines whether the error correction operation is successful. If the error correction operation is successful, in operation S53, the storage device 100 outputs the error-corrected data.

[0111] When an ECC fault is detected in the first data DATA1 of the first page PAGE1, in operation S54, the storage device 100 performs a RAID recovery operation. The storage device 100 can read the data constituting the RAID stripe and the RAID parity from the cell area other than the first cell area including the first page PAGE1, and performs the RAID recovery operation using the read data and the read RAID parity. In operation S55, the storage device 100 outputs the data recovered through the RAID recovery operation.

[0112] Since the storage device 100 according to at least one embodiment of the present invention adjusts the read level according to the power outage period, read errors caused by retention can be reduced. Therefore, read errors caused by retention that make error correction operations using ECC parity and RAID recovery operations infeasible can be prevented. In other words, the range of data recovery for performing error correction operations and RAID recovery operations can be broadened.

[0113] Figure 12 This is a diagram illustrating the read and recycle operation of a storage device according to an exemplary embodiment of the present invention. Figure 13 This is a flowchart of a method for operating a storage device according to an exemplary embodiment of the present invention.

[0114] Reference Figure 1 , Figure 12 and Figure 13 The method for operating the storage device according to this embodiment can be used in... Figure 1 It is executed in a time-series manner in the storage device 100.

[0115] In operation S10, storage device 100 receives power-off time information CT_OFF and power-on time information CT_ON from host 200. Storage device 100 can store the power-off time in the power-off time information CT_OFF and the power-on time in the power-on time information CT_ON as timestamps. In operation S20, storage device 100 calculates the power-off period of storage device 100 based on the stored timestamps.

[0116] In operation S60, the storage device 100 determines the old data based on the power outage period. For example, the storage device 100 may determine the second data DATA2 stored in the second page PAGE2, which is included in the first memory block BLK1, as old data (i.e., invalid data).

[0117] Based on the programming time information of the first data DATA1 to the j-th data DATAj in the first memory block BLK1, the storage device 100 can calculate the time elapsed since each of the first data DATA1 to the j-th data DATAj was programmed. The power outage period can be included in the time elapsed since each of the first data DATA1 to the j-th data DATAj was programmed. In an exemplary embodiment, the storage device 100 compares the time elapsed since each of the first data DATA1 to the j-th data DATAj was programmed with a reference time, and when the elapsed time exceeds the reference time, the corresponding data is determined to be old data. For example, the storage device 100 can determine that the time elapsed since the second data DATA2 stored in the second page PAGE2 was programmed exceeds the reference time, and determine the second data DATA2 as old data. In other words, the reference time can be an upper limit time for the storage device to guarantee the validity of the programmed data.

[0118] In operation S70, the storage device 100 performs a read-and-reclaim operation on the first memory block BLK1 to which the second data DATA2 is programmed. Here, "read-and-reclaim" refers to the operation of moving data from the first memory block BLK1 to another block (e.g., the nth memory block BLKn), deleting data from the first memory block BLK1, and reusing the first memory block BLK1. Specifically, valid pages stored in the first memory block BLK1 can be read, and read data from valid pages can be programmed to another block (i.e., the nth memory block BLKn). For example, the first data DATA1 of the first memory block BLK1 can be programmed to the first page PAGE1 of the nth memory block BLKn, and the j-th data DATAj of the first memory block BLK1 can be programmed to the second page PAGE2 of the nth memory block BLKn. Therefore, the first memory block BLK1 in the mapping table can be changed to the nth memory block BLKn, and the page address can be changed according to the number of valid pages in the first memory block BLK1.

[0119] Therefore, the storage device 100 according to at least one embodiment of the present invention can determine old data as invalid data by calculating the time elapsed since the old data was programmed, without requiring error correction or RAID recovery operations. Thus, the storage device 100 can reduce the time required for read / reclaim operations.

[0120] Figure 14 This is a block diagram illustrating an example of applying a storage device according to an exemplary embodiment of the present invention to a solid-state drive (SSD).

[0121] Reference Figure 14 The SSD system 1000 includes a host 1100 and an SSD 1200. The SSD system 1000 can be...Figure 1 The storage system 10 and the host 1100 can be Figure 1 The host is 200, and the SSD is 1200. Figure 1 Storage device 100.

[0122] The SSD 1200 exchanges signals with the host 1100 via signal connector 1211 and receives power via power connector 1221. The SSD 1200 may include multiple non-volatile memories (e.g., flash memory) 1201 to 120m, an SSD controller 1210, and an auxiliary power supply 1220. The flash memory 1201 to 120m can be used as the storage medium of the SSD 1200. The SSD 1200 may include non-volatile memory devices such as PRAM, MRAM, ReRAM, or FRAM other than flash memory. The flash memory 1201 to 120m can be connected to the SSD controller 1210 via multiple channels CH1 to CHm. One channel can be connected to one or more flash memories. Flash memories connected to one channel can be connected to the same data bus.

[0123] The SSD controller 1210 exchanges signals SGL with the host 1100 via signal connector 1211. Here, signal SGL may include commands, addresses, data, etc. The SSD controller 1210 can write data to or read data from the corresponding flash memory according to commands from the host 1100.

[0124] Auxiliary power supply 1220 can be connected to host 1100 via power connector 1221. Auxiliary power supply 1220 can receive power PWR from host 1100 and use the received power PWR to charge a battery or capacitor. Auxiliary power supply 1220 can be located inside or outside SSD 1200. For example, auxiliary power supply 1220 can be located on the motherboard and can provide auxiliary power to SSD 1200.

[0125] When the SSD 1200, according to an exemplary embodiment of the present invention, receives power PWR from the host 1100 in a power-off state via power connector 1221 and is subsequently powered on, the SSD 1200 can receive power-off time information and power-on time information via signal connector 1211. The SSD 1200 can calculate the power-off period based on the power-off time information and power-on time information, and determine the read level based on the power-off period, or perform a read recovery operation. Therefore, the SSD 1200 can reduce read errors in read operations and reduce the time required for read recovery operations.

[0126] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A storage device, comprising: Non-volatile memory, comprising multiple memory blocks; as well as The memory controller is configured to control read operations on the non-volatile memory. Specifically, when the storage device switches from a power-off state to a power-on state, the storage controller receives power-off time information from the host indicating the power-off time of the storage device, and also receives power-on time information from the host indicating the power-on time of the storage device. Specifically, the storage controller stores the power-off timestamp corresponding to the power-off time and the power-on timestamp corresponding to the power-on time in non-volatile memory. The host is an external source of the storage device.

2. The storage device as claimed in claim 1, in, The non-volatile memory stores a read level lookup table containing information about the read level during a power-off period, and The storage controller adjusts at least one read level to be used in the read operation based on a read level lookup table, a power-off timestamp, and a power-on timestamp.

3. The storage device as claimed in claim 2, in, The non-volatile memory stores an auxiliary lookup table, which includes information indicating the read level based on the elapsed time since the data was programmed during the power-on period. The storage controller also adjusts the at least one read level based on an auxiliary lookup table.

4. The storage device as claimed in claim 1, in, The non-volatile memory stores a read level lookup table containing information about the read level based on the read level during a power-off period. The non-volatile memory adjusts at least one read level to be used in the read operation based on a read level lookup table, a power-off timestamp, and a power-on timestamp.

5. The storage device as claimed in claim 1, in, The storage controller determines whether data programmed into non-volatile memory is old data based on power-off and power-on timestamps, and A read and reclaim operation is performed on the memory block to which the old data was programmed.

6. The storage device as claimed in claim 1, in, The storage controller receives power-off time information and power-on time information after the storage device is supplied with external power and switched to the power-on state.

7. The storage device as claimed in claim 1, in, The storage controller uses parity checking of error-correcting codes from data read from non-volatile memory to perform error correction, and When the error correction operation fails, the storage controller performs the independent disk redundant array recovery operation by using the independent disk redundant array parity check to read the data.

8. The storage device according to claim 1, wherein, The storage device includes a solid-state drive.

9. The storage device according to claim 1, wherein, Non-volatile memory consists of four layers of cells, each programmed with 4 bits of data.

10. A storage device, comprising: Non-volatile memory, comprising multiple memory blocks; as well as The storage controller is configured to control read operations of a non-volatile memory performed using at least one read level. The storage controller receives power-off time information from the host indicating the time when the storage device is powered off, and also receives power-on time information from the host indicating the time when the storage device is powered on. The host is an external source for the storage device. The storage controller controls read operations by using a power outage period calculated based on power outage and power-on time information.

11. The storage device as claimed in claim 10, in, The non-volatile memory stores a read level lookup table containing information about the read level during a power-off period, and The storage controller determines the at least one read level by using a read level lookup table.

12. The storage device as claimed in claim 10, in, The storage controller determines multiple different read levels based on the power outage period, and Among these, the values ​​of at least some of the multiple different read levels are changed differently during the power-off period.

13. The storage device as claimed in claim 12, in, The higher the read level, the greater the degree to which it is altered during the power-off period.

14. The storage device as claimed in claim 10, in, The storage controller determines multiple different read levels based on the power outage period, and The multiple different read levels are changed to the same extent during the power-off period.

15. The storage device as claimed in claim 10, in, The storage controller stores a read level lookup table that includes information indicating the read level based on the power outage period, and determines the read level by using the read level lookup table.

16. The storage device as claimed in claim 10, in, The non-volatile memory stores an auxiliary lookup table, which includes information indicating the read level based on the elapsed time since the data was programmed during the power-on period. The storage controller determines the at least one read level by using an auxiliary lookup table.

17. The storage device as claimed in claim 10, in, The storage controller determines whether the data programmed into the non-volatile memory is old data based on the period of power failure, and The storage controller performs read and reclaim operations on the memory blocks where old data is programmed.

18. A storage controller, comprising: The memory is configured to store a power-off timestamp, a power-on timestamp, and a read level lookup table including information indicating the read level based on the power-off period; as well as The processor is configured to control read operations on non-volatile memory. Specifically, the processor stores a power-off timestamp by using input power-off time information indicating the power-off time point, and stores a power-on timestamp by using input power-on time information indicating the power-on time point. The processor uses a power-off period calculated based on power-off timestamps and power-on timestamps, along with a read level lookup table, to control read operations on the non-volatile memory.

19. The storage controller of claim 18, further comprising: A timer is configured to provide the processor with the internal time information required for operation, wherein the timer sets the internal time information based on the power-off timestamp and the power-on timestamp.

20. The storage controller according to claim 18, wherein, The processor controls read operations of non-volatile memory such that the read level used to read the same programming state decreases as the power-off period increases.

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