A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device and a semiconductor device. A stacked structure is formed on a substrate, wherein the substrate includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region; a guard ring trench surrounding the periphery of the cell array region is formed in the intermediate region; a first insulating material is deposited on the upper surface of a second dielectric layer in the stacked structure to form a second support layer, and a second insulating material is deposited on the bottom surface and sidewalls of the guard ring trench to form a guard ring structure; a capacitor structure is formed in the cell array region. By first forming the guard ring structure, this method can avoid etching of the peripheral circuit region when forming the capacitor structure in the cell array region subsequently. In addition, it can support the electrode structure in the cell array region, improve the stability of the structure, and physically isolate the cell array region and the peripheral circuit region to avoid current leakage, thereby greatly improving the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In the existing technology, in order to increase the integration degree of semiconductor devices, the area occupied by each semiconductor element in the semiconductor device is reduced. In order not to affect the capacitance of the capacitor, usually, the effective area of the lower electrode in the capacitor structure is increased. For example, a three-dimensional lower electrode is manufactured, and the three-dimensional lower electrode can be formed with a cylindrical structure, and the side wall of the lower electrode of the cylindrical structure extends in a direction perpendicular to the surface of the substrate to increase the height of the lower electrode and expand the effective area, so as to ensure that the capacitance required by the semiconductor device is achieved.

[0003] However, increasing the height of the lower electrode may cause the lower electrode to tilt. This problem can be solved by providing a support structure between the lower electrodes. However, the presence of the support structure will also introduce new problems. The support structure will apply stress to the lower electrode, causing the lower electrode to twist, and may also cause electrical connection between different circuit regions, resulting in current leakage, thereby affecting the performance of the semiconductor device. Summary of the Invention

[0004] The technical problem to be solved by the present invention is: how to improve the stability of the lower electrode to reduce the electrical connection between different circuit regions and improve the performance of the semiconductor device.

[0005] To solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device.

[0006] In a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, which includes:

[0007] Forming a stacked structure on a substrate, wherein the stacked structure includes a first dielectric layer, a first support structure, and a second dielectric layer formed in sequence on the substrate, and the substrate includes a unit array region, a peripheral circuit region, and an intermediate region located between the unit array region and the peripheral circuit region;

[0008] Forming a protection ring trench surrounding the periphery of the unit array region in the intermediate region;

[0009] Depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, and depositing a second insulating material on the bottom surface and side wall of the protection ring trench to form a protection ring structure;

[0010] Forming a capacitor structure in the unit array region.

[0011] Optionally, forming a protection ring trench surrounding the periphery of the unit array region in the intermediate region includes:

[0012] Deposit a photoresist layer on the second dielectric layer;

[0013] Pattern the photoresist layer to form at least one first etching window in the intermediate region;

[0014] Etch the first dielectric layer, the first support structure, and the second dielectric layer in the intermediate region based on the first etching window, and stop etching until the upper surface of the substrate of the semiconductor device is exposed, to form at least one first protection ring trench surrounding the periphery of the cell array region.

[0015] Optionally, forming a protection ring trench surrounding the periphery of the cell array region in the intermediate region further includes:

[0016] Pattern the photoresist layer to form a second etching window in the intermediate region;

[0017] Etch the intermediate region based on the second etching window to form a second protection ring trench surrounding the periphery of the cell array region, and the second protection ring trench has a different depth from the first protection ring trench.

[0018] Optionally, forming a second protection ring trench surrounding the periphery of the cell array region includes:

[0019] Form a plurality of second protection ring trenches surrounding the periphery of the cell array region, wherein the plurality of second protection ring trenches extend in a direction perpendicular to the substrate and have different extension depths.

[0020] Optionally, depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, and depositing a second insulating material on the bottom surface and side walls of the protection ring trench to form a protection ring structure, includes:

[0021] Synchronously deposit the first insulating material on the upper surface of the second dielectric layer, the bottom surface, and the side walls of the protection ring trench, and the first insulating material is the same as the second insulating material.

[0022] Optionally, forming a capacitor structure in the cell array region includes:

[0023] Pattern the second support layer in the cell array region;

[0024] Using the patterned second support layer as a mask, etch the first dielectric layer, the first support structure, and the second dielectric layer in the cell array region to form a lower electrode groove in the stacked structure composed of the first dielectric layer, the first support structure, and the second dielectric layer, and deposit a conductive material in the lower electrode groove to form a lower electrode;

[0025] Deposit a mask layer on the stacked structure formed with the lower electrode;

[0026] Pattern the mask layer to expose the upper surface of at least a part of the second support layer located in the cell array region;

[0027] Etch the first dielectric layer, the second dielectric layer, the exposed second support layer, and the first support structure located below the exposed second support layer;

[0028] Conformally deposit a capacitive dielectric layer covering the upper surfaces of the lower electrode, the second support layer, and the substrate in the cell array region; and

[0029] Deposit a conductive material on the capacitive dielectric layer to form an upper electrode.

[0030] Optionally, the capacitive dielectric layer also covers the protection ring structure and the capacitive dielectric layer covering at least a part of the upper surface of the second support layer in the peripheral circuit region.

[0031] Optionally, after depositing a first insulating material on the upper surface of the second dielectric layer to form the second support layer, the method further includes: depositing an oxide layer on the upper surface of the second support layer in the peripheral circuit region to form an ONONO structure composed of the first dielectric layer, the first support structure, the second dielectric layer, the second support layer, and the oxide layer.

[0032] Optionally, forming the stacked structure on the substrate includes:

[0033] Deposit a first dielectric layer, a first support structure, and a second dielectric layer on the substrate in sequence, where the first support structure includes a plurality of sub-support layers and insulating dielectric layers located between adjacent sub-support layers.

[0034] A second aspect of the present invention provides a semiconductor device, which includes:

[0035] A substrate, the substrate includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region;

[0036] A stacked structure is formed on the substrate, the stacked structure includes a plurality of capacitive structures and a protection ring structure, where the plurality of capacitive structures are formed on the cell array region, and there is a support structure between at least some adjacent capacitive structures, the support structure includes a first support structure and a second support layer; the protection ring structure is formed on the intermediate region and surrounds the capacitive structures on the cell array region.

[0037] Optionally, the guard ring structure includes a plurality of guard rings that extend in a direction perpendicular to the substrate and have different extension depths.

[0038] Optionally, the plurality of guard rings extend in a direction perpendicular to the substrate and have different extension depths, including:

[0039] The plurality of guard rings extend in a direction perpendicular to the substrate, wherein the bottom surface of at least one of the guard rings contacts the upper surface of the substrate of the semiconductor device.

[0040] Optionally, a stacked structure is formed on the substrate, the stacked structure includes a plurality of capacitor structures and a guard ring structure, and the capacitor structure includes:

[0041] A lower electrode;

[0042] The first support structure and the second support layer, wherein the first support structure and the second support layer support at least a part of the outer sidewall of the lower electrode, and the first support structure and the second support layer are disposed at different heights on the outer sidewall of the lower electrode;

[0043] A capacitor dielectric layer that covers the lower electrode, the second support layer, and the upper surface of the substrate in the cell array region;

[0044] An upper electrode that covers the capacitor dielectric layer.

[0045] Optionally, the capacitor structure further includes: a metal layer on the upper electrode.

[0046] Optionally, the first support structure includes a plurality of sub-support layers and insulating dielectric layers located between the respective sub-support layers.

[0047] Optionally, the semiconductor device further includes: an ONONO structure composed of a first dielectric layer, the first support structure, a second dielectric layer, the second support layer, and an oxide layer, on the substrate in the peripheral circuit region.

[0048] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0049] The method for manufacturing a semiconductor device and the semiconductor device of the present invention are applied. By forming a stacked structure on a substrate, wherein the stacked structure includes a first dielectric layer, a first support structure, and a second dielectric layer sequentially formed on the substrate, the substrate includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region; forming a guard ring trench surrounding the periphery of the cell array region in the intermediate region; depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, and depositing a second insulating material on the bottom surface and side walls of the guard ring trench to form a guard ring structure; forming a capacitor structure in the cell array region. This method can avoid etching the peripheral circuit region when forming the capacitor structure in the cell array region subsequently by first forming the guard ring structure in the intermediate region located between the cell array region and the peripheral circuit region, thereby protecting the device performance of the peripheral circuit region. In addition, it can support the electrode structure of the cell array region, avoid the tilting of the lower electrode, improve the stability of the structure, and at the same time play a role in physically isolating the cell array region and the peripheral circuit region to avoid current leakage, thus greatly improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The scope of the present disclosure can be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The accompanying drawings included are:

[0051] Figure 1 FIG. 1 shows a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0052] Figure 2 FIG. 2 shows a schematic cross-sectional structure diagram of forming a stacked structure on a substrate provided by an embodiment of the present invention;

[0053] FIG. 3(1) shows a top view schematic diagram of forming a guard ring trench surrounding the periphery of the cell array region in the intermediate region provided by an embodiment of the present invention; FIG. 3(2) shows a schematic cross-sectional structure diagram of forming a guard ring trench surrounding the periphery of the cell array region in the intermediate region provided by an embodiment of the present invention;

[0054] Figure 4 FIG. 4 shows a schematic cross-sectional structure diagram of forming a guard ring structure in the intermediate region provided by an embodiment of the present invention;

[0055] Figure 5 FIG. 5 shows a schematic flow chart of forming a capacitor structure in the cell array region provided by an embodiment of the present invention;

[0056] Figures 6 to 12 FIG. 6 shows a schematic cross-sectional structure diagram corresponding to each execution step of forming a capacitor structure in the cell array region provided by an embodiment of the present invention;

[0057] Figure 13The flowchart shows a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 14 The cross-sectional structure diagram shows the formation of a second protection ring trench provided by an embodiment of the present invention. Detailed implementation manners

[0059] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will describe in detail the implementation method of the present invention in conjunction with the accompanying drawings and embodiments, so as to fully understand how the present invention uses technical means to solve technical problems and achieve the implementation process of technical effects and implement accordingly.

[0060] In the prior art, in order to increase the integration degree of semiconductor devices, the area occupied by each semiconductor element in the semiconductor device is reduced. In order not to affect the capacitance of the capacitor, usually, the effective area of the lower electrode in the capacitor structure is increased. For example, a three-dimensional lower electrode is manufactured, and the three-dimensional lower electrode may be formed with a cylindrical structure, and the side wall of the lower electrode of the cylindrical structure extends in a direction perpendicular to the surface of the substrate to increase the height of the lower electrode and expand the effective area to ensure that the capacitance required by the semiconductor device is achieved.

[0061] However, increasing the height of the lower electrode may cause the lower electrode to tilt. This problem can be solved by providing a support structure between the lower electrodes. However, the presence of the support structure will also introduce new problems. The support structure will apply stress to the lower electrode, causing the lower electrode to twist, and may also cause electrical connection between different circuit regions, resulting in current leakage, thereby affecting the performance of the semiconductor device.

[0062] In view of this, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device. By forming a stacked structure on a substrate, wherein the stacked structure includes a first dielectric layer, a first support structure, and a second dielectric layer sequentially formed on the substrate, the substrate includes a unit array region, a peripheral circuit region, and an intermediate region located between the unit array region and the peripheral circuit region; forming a protection ring trench surrounding the periphery of the unit array region in the intermediate region; depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, and depositing a second insulating material on the bottom surface and side wall of the protection ring trench to form a protection ring structure; forming a capacitor structure in the unit array region. This method can avoid etching the peripheral circuit region when forming the capacitor structure in the unit array region subsequently by first forming a protection ring structure in the intermediate region located between the unit array region and the peripheral circuit region, which plays a role in protecting the device performance of the peripheral circuit region. In addition, it can also support the electrode structure in the unit array region, avoid the tilting of the lower electrode, improve the stability of the structure, and at the same time can also play a role in physically isolating the unit array region and the peripheral circuit region to avoid current leakage, thereby greatly improving the performance of the semiconductor device.

[0063] Embodiment 1

[0064] Refer to Figure 1 as shown Figure 1 As shown, a schematic flow diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present invention is shown, which includes the following steps:

[0065] Step S101: Form a stacked structure on the substrate 10. Among them, the stacked structure includes a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 sequentially formed on the substrate 10. The substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region.

[0066] Step S102: Form a guard ring trench 16 surrounding the periphery of the cell array region in the intermediate region.

[0067] Step S103: Deposit a first insulating material on the upper surface of the second dielectric layer 13 to form a second support layer 18, and deposit a second insulating material on the bottom surface and side walls of the guard ring trench to form a guard ring structure 17.

[0068] Step S104: Form a capacitor structure in the cell array region.

[0069] Refer to Figure 2 as shown Figure 2 As shown, a schematic cross-sectional structure diagram of forming a stacked structure on the substrate 10 provided by an embodiment of the present invention is shown. In the embodiment of the present invention, step S101 may specifically be to deposit a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 on the substrate in sequence by chemical vapor deposition or physical vapor deposition.

[0070] Among them, as an example, the substrate 10 may include a semiconductor substrate 101 and an interlayer insulating layer 102 located on the semiconductor substrate 101. As an example, the semiconductor substrate 101 may include an Si substrate, a Ge substrate, an SiGe substrate, etc. The interlayer insulating layer 102 may include borophosphosilicate glass, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and a carbon-containing low-k dielectric, etc. A gate structure 14 of a transistor is provided in the interlayer insulating layer 102 in the peripheral circuit region, and source / drain regions 15 of the transistor are formed in the semiconductor substrate 101 on both sides of the gate structure 14.

[0071] In the embodiment of the present invention, the first dielectric layer 11 or the second dielectric layer 13 may include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), plasma enhanced (PE)-tetraethyl orthosilicate (TEOS), high density plasma (HDP)-oxide, etc. The first dielectric layer 11 and the second dielectric layer 13 may be selected to be formed of the same material.

[0072] The first support structure 12 can be formed of a material different from that of the first dielectric layer 11 and the second dielectric layer 13 and capable of selective etching. As an example, the first support structure 12 may include at least one of silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, silicon oxide, silicon nitride, and silicon oxynitride. As another example, the first support structure 12 may also be provided to include a plurality of sub-support layers and insulating dielectric layers located between adjacent sub-support layers. Among them, the sub-support layers may include at least one of silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, silicon oxide, silicon nitride, and silicon oxynitride. The sub-support layers are spaced apart in a direction perpendicular to the substrate 10, and the insulating dielectric layer may be selected from the same material as the first dielectric layer 11 or the second dielectric layer 13. By spacing the plurality of sub-support layers, the stability of the lower electrode can be improved.

[0073] Referring to FIGS. 3(1) and 3(2) shown, FIG. 3(1) shows a top view schematic diagram of a protection ring trench 16 formed around the periphery of the unit array region in the middle region provided by the embodiment of the present invention; FIG. 3(2) shows a cross-sectional structure schematic diagram of the protection ring trench 16 formed around the periphery of the unit array region in the middle region provided by the embodiment of the present invention. As an example, forming the protection ring trench 16 around the periphery of the unit array region in the middle region may include: depositing a photoresist layer on the second dielectric layer 13, patterning the photoresist layer to form at least one first etching window in the middle region; etching the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13 in the middle region based on the first etching window, and stopping the etching until the upper surface of the substrate 10 of the semiconductor device is exposed, to form at least one first protection ring trench 161 around the periphery of the unit array region. As a specific example, a first protection ring trench 161 is formed around the periphery of the unit array region, and the width of the first protection ring trench is the same as the width of the middle region.

[0074] Referring to Figure 4 shown, Figure 4The cross-sectional structural schematic diagram of the protection ring structure 17 formed in the middle region provided by the embodiment of the present invention is shown. Specifically, step S103 may be to synchronously deposit a first insulating material on the upper surface of the second dielectric layer 13 and the bottom surface and side walls of the protection ring trench 16, and the first insulating material is the same as the second insulating material. After synchronously depositing the first insulating material on the bottom surface and side walls of the protection ring trench 16, the protection ring structure 17 is formed. It should be noted that when forming the protection ring structure 17, the protection ring trench 16 can be filled with the first insulating material; after depositing the first insulating material on the upper surface of the second dielectric layer 13, the second support layer 18 can be formed. Among them, the protection ring structure 17 on the periphery of the unit array region can play a role in physically isolating the unit array region and the peripheral circuit region, avoiding current leakage. In addition, the protection ring structure 17 and the second support layer 18 of the peripheral circuit region can protect the peripheral circuit region from etching. Specifically, it can avoid the etching of the peripheral circuit region during the subsequent process of forming the capacitor structure in the unit array region, which affects the device performance of the peripheral circuit region.

[0075] See Figure 5 as shown in the figure to Figure 5 The flowchart showing the formation of the capacitor structure in the unit array region provided by the embodiment of the present invention is shown.

[0076] Specifically, step S104 may include:

[0077] Step S1041: Pattern the second support layer 18 in the unit array region.

[0078] Step S1042: Using the patterned second support layer 18 as a mask, etch the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13 in the unit array region to form a lower electrode groove in the stacked structure composed of the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13, and deposit a conductive material in the lower electrode groove to form the lower electrode 19. See Figure 6 as shown.

[0079] Step S1043: Deposit a mask layer 20 on the stacked structure formed with the lower electrode 19.

[0080] Step S1044: Pattern the mask layer 20 to expose at least part of the upper surface of the second support layer 18 located in the unit array region.

[0081] Step S1045: Etch the first dielectric layer 11, the second dielectric layer 13, the exposed second support layer 18, and the first support structure 12 located below the exposed second support layer 18.

[0082] Step S1046: Conformally deposit a capacitor dielectric layer 21 covering the upper surface of the lower electrode 19, the second support layer 18, and the substrate of the unit array region.

[0083] Step S1047: Deposit a conductive material on the capacitive dielectric layer 21 to form the upper electrode 22.

[0084] Wherein, the second support layer 18 may include at least one of silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, silicon oxide, silicon nitride, and silicon oxynitride.

[0085] In an embodiment of the present invention, step S1042 may specifically be to etch the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13 in the unit array region by using a dry etching process or a wet etching process to form a plurality of lower electrode grooves in the stacked structure composed of the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13. And a deposition process with a good step coverage effect, such as: chemical vapor deposition process, is used to deposit a conductive material in the lower electrode grooves to form the lower electrode 19. As an example, a metal or a metal nitride may be used to form the lower electrode 19.

[0086] As an example, steps S1043 to S1045 may specifically be:

[0087] Refer to Figure 7 As shown, deposit a mask layer 20 on the stacked structure formed with the lower electrode 19. Specifically, a deposition process with a relatively poor step coverage effect may be selected to deposit the mask layer 20 on the stacked structure formed with the lower electrode, and then voids will be formed on the inner wall of the lower electrode.

[0088] Refer to Figure 8 As shown, pattern the mask layer 20 to expose at least a part of the upper surface of the second support layer 18 located in the unit array region. As an example, patterning the mask layer 20 may specifically be to deposit a photoresist layer with a target pattern on the mask layer 20, and use this photoresist layer as a mask to perform photolithography and development on the mask layer 20, thereby forming the patterned mask layer 20.

[0089] Refer to Figure 9 As shown, etch the first dielectric layer 11, the second dielectric layer 13, the exposed second support layer 18, and the first support structure 12 located below the exposed second support layer 18, and remove the mask layer 20 after the etching is completed. As an example, etching the first dielectric layer 11, the second dielectric layer 13, the exposed second support layer 18, and the first support structure 12 located below the exposed second support layer 18 may include etching the exposed second support layer 18 with the patterned mask layer 20 as a mask; then selecting a suitable etching solvent to selectively etch away the second dielectric layer 13 between adjacent lower electrodes 19; etching the first support structure 12 between the adjacent lower electrodes 19 where the second support layer 18 has been etched away; and finally, etching away the first dielectric layer 11.

[0090] In an embodiment of the present invention, step S1046 may specifically be to deposit the capacitor dielectric layer 21 by using a deposition process with a better stepped coverage effect. As an example, as shown in FIG. 10(1), the capacitor dielectric layer 21 conformally covers the upper surfaces of the lower electrode 19, the second support layer 18 in the cell array region, and a part of the guard ring structure 17; as another example, as shown in FIG. 10(2), the capacitor dielectric layer 21 conformally covers the lower electrode 19, the second support layer 18 in the cell array region, the guard ring structure 17, and the second support layer 18 in a part of the peripheral array region. In other embodiments of the present invention, it may also be that the capacitor dielectric layer 21 conformally covers the lower electrode 19, the guard ring structure 17, and the second support layer 18 in the cell array region and the entire peripheral circuit region. Among them, in the cell array region, contact windows may also be provided in the interlayer insulating layer 102 located below the lower electrode 19. As an example, the capacitor dielectric layer 21 may include at least one of an oxide, a nitride, or a high-k dielectric constant material.

[0091] Further, a conductive material is deposited on the capacitor dielectric layer 21 to form the upper electrode 22. As an example, a metal layer 23 may be further deposited on the upper electrode 22, and the metal layer 23 may be tungsten. Among them, the upper electrode 22 and the metal layer 23 may partially cover the capacitor dielectric layer 21, as shown in FIG. 10(1), or may completely cover the capacitor dielectric layer 21, as shown in FIG. 10(2).

[0092] In addition to conformally covering the capacitor dielectric layer 21, the upper electrode 22 may also fill the region between adjacent lower electrodes 19 provided with support structures. It should be noted that the capacitor dielectric layer 21 may also be formed on the lower surface of the second support layer 18 in the cell array region, and the upper electrode 22 is isolated from the lower electrode 19 and the support structure through the capacitor dielectric layer 21.

[0093] It should be noted that in an embodiment of the present invention, in order to reduce the step height between the peripheral array region and the cell array region, an oxide layer 24 may be further deposited. As an example, after depositing a first insulating material on the upper surface of the second dielectric layer 13 to form the second support layer 18, it may further include: depositing the oxide layer 24 on the upper surface of the second support layer 18 in the peripheral circuit region to form an ONONO structure composed of the first dielectric layer 11, the first support structure 12, the second dielectric layer 13, the second support layer 18, and the oxide layer 24, that is, an oxide-nitride-oxide-nitride-oxide structure. Among them, as shown in Figure 11 When depositing the oxide layer 24, the oxide layer 24 may be deposited on the metal layer 23 in the cell array region and the second support layer 18 in the peripheral circuit region at the same time, so that the structural heights of the peripheral circuit region and the cell array region are equal.

[0094] In addition, as shown in Figure 12As shown, the oxide layer 24 can be further etched to form contact holes exposing the metal layer 23 in the cell array region, and the oxide layer 24, the second support layer 18, the second dielectric layer 13, the first support structure 12, and the first dielectric layer 11 in the peripheral circuit region are etched to form contact holes exposing the conductive contact plugs in the interlayer insulating layer 102. The conductive contact plugs are not shown in the figure.

[0095] The above is a method for manufacturing a semiconductor device provided by an embodiment of the present invention. By forming a stacked structure on the substrate 10, wherein the stacked structure includes a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 sequentially formed on the substrate, the substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region; a protection ring trench 16 surrounding the periphery of the cell array region is formed in the intermediate region; a first insulating material is deposited on the upper surface of the second dielectric layer 13 to form a second support layer 18, and a second insulating material is deposited on the bottom surface and side walls of the protection ring trench 16 to form a protection ring structure 17; a capacitor structure is formed in the cell array region. This method can avoid etching the peripheral circuit region when forming the capacitor structure in the cell array region subsequently by first forming the protection ring structure 17 in the intermediate region located between the cell array region and the peripheral circuit region, which plays a role in protecting the device performance of the peripheral circuit region. In addition, it can also support the electrode structure of the cell array region, avoid the tilting of the lower electrode 19, improve the stability of the structure, and at the same time can also play a role in physically isolating the cell array region and the peripheral circuit region to avoid current leakage, thereby greatly improving the performance of the semiconductor device.

[0096] The above is a method for manufacturing a semiconductor device provided by the present invention. Different protection ring structures 17 can also be formed. For details, please refer to Embodiment 2.

[0097] Embodiment 2

[0098] Embodiment 2 provided by the present invention can be further implemented based on the semiconductor device manufacturing method shown in Embodiment 1. In this embodiment, the execution steps different from those in Embodiment 1 will be described in detail.

[0099] See Figure 13 As shown, Figure 13 shows a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, which includes:

[0100] Step S201: Form a stacked structure on the substrate 10, wherein the stacked structure includes a first dielectric layer 11, a first support structure 12, and a second dielectric layer 13 sequentially formed on the substrate, and the substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region.

[0101] Step S202: Deposit a photoresist layer on the second dielectric layer 13.

[0102] Step S203: Pattern the photoresist layer to form at least one first etching window in the middle region.

[0103] Step S204: Etch the first dielectric layer 11, the first support structure 12, and the second dielectric layer 13 in the middle region based on the first etching window, and stop etching until the upper surface of the substrate 10 of the semiconductor device is exposed, to form at least one first protection ring trench 161 surrounding the periphery of the cell array region.

[0104] Step S205: Pattern the photoresist layer to form a second etching window in the middle region.

[0105] Step S206: Etch the middle region based on the second etching window to form a second protection ring trench 162 surrounding the periphery of the cell array region, and the second protection ring trench 162 has a different depth from the first protection ring trench 161.

[0106] Step S207: Deposit a first insulating material on the upper surface of the second dielectric layer 13 to form a second support layer 18, and deposit a second insulating material on the bottom surface and side walls of the protection ring trench 16 to form a protection ring structure 17.

[0107] Step S208: Form a capacitor structure in the cell array region.

[0108] Among them, Step S201, Step S207 to Step S208 may be the same as Step S101, Step S103 to Step S104 in Embodiment 1. For the sake of brevity, they will not be elaborated here.

[0109] In the embodiment of the present invention, Step S203 to S204 may be executed first and then Step S205 to S206, or Step S203 and Step S205 may be executed simultaneously and then Step S204 and S206 are executed respectively, or Step S205 to S206 may be executed first and then Step S203 to S204. In the embodiment of the present invention, the execution order of Step S203 to S204 and S205 to S206 will not be particularly limited.

[0110] In Step S204, a schematic top view of forming at least one first protection ring trench 161 surrounding the periphery of the cell array region can be seen as shown in Fig. 3(1).

[0111] See Figure 14 as shown in Figure 14The figure shows a schematic cross-sectional structure of forming a second protection ring trench 162 surrounding the periphery of the unit array region by etching the intermediate region based on a second etching window provided by an embodiment of the present invention. Among them, the depth of the second protection ring trench 162 is different from that of the first protection ring trench 161. It should be noted that the second protection ring trench 162 may be located outside the first protection ring trench 161, or the first protection ring trench 161 may be located outside the second protection ring trench 162. As another example, forming the second protection ring trench 162 surrounding the periphery of the unit array region may include: forming a plurality of second protection ring trenches 162 surrounding the periphery of the unit array region, and the depths of the plurality of second protection ring trenches 162 extending in a direction perpendicular to the substrate are different. By providing at least one first protection ring trench 161 and a second protection ring trench 162 with a different depth from it, on the basis of supporting the structure of the unit array region, the physical isolation effect between the unit array region and the peripheral circuit region can be further improved, and current leakage can be avoided.

[0112] The above is a method for manufacturing a semiconductor device provided by another embodiment of the present invention. By patterning a photoresist reagent layer, in addition to forming at least one first etching window in the intermediate region and forming a first protection ring trench 161 surrounding the periphery of the unit array region based on the first etching window, a second etching window can also be formed in the intermediate region, and a second protection ring trench 162 surrounding the periphery of the unit array region is formed based on the second etching window, wherein the depth of the second protection ring trench 162 is different from that of the first protection ring trench 161. In addition to achieving the same beneficial effects as in Embodiment 1, by forming at least one first protection ring trench 161 and a second protection ring trench 162 with a different depth from it in the intermediate region located between the unit array region and the peripheral circuit region, the physical isolation effect between the unit array region and the peripheral circuit region can be further improved, and current leakage can be avoided, thereby greatly improving the performance of the semiconductor device.

[0113] Based on the method for manufacturing a semiconductor device provided by an embodiment of the present invention, on the other hand, the present invention also correspondingly provides a semiconductor device. For details, please refer to Embodiment 3.

[0114] Embodiment 3

[0115] See Figure 12 as shown Figure 12 The figure shows a schematic cross-sectional structure of a semiconductor device provided by an embodiment of the present invention, which includes:

[0116] A substrate 10, and the substrate 10 includes a unit array region, a peripheral circuit region, and an intermediate region located between the unit array region and the peripheral circuit region.

[0117] A stacked structure is formed on a substrate 10, and the stacked structure includes a plurality of capacitor structures and a guard ring structure 17. Among them, the plurality of capacitor structures are formed on a cell array region, and there is a support structure between at least some adjacent capacitor structures. The support structure includes a first support structure 12 and a second support layer 18; the guard ring structure 17 is formed on an intermediate region and surrounds the capacitor structures on the cell array region.

[0118] Among them, the guard ring structure 17 may include a plurality of guard rings. The plurality of guard rings extend in a direction perpendicular to the substrate 10, and the extension depths are different. As an example, the plurality of guard rings extend in a direction perpendicular to the substrate 10. Among them, the bottom surface of at least one guard ring is in contact with the upper surface of the substrate 10 of the semiconductor device.

[0119] As an example, in an embodiment of the present invention, the capacitor structure may include:

[0120] A lower electrode 19;

[0121] A first support structure 12 and a second support layer 18, wherein the first support structure 12 and the second support layer 18 support at least part of the outer sidewall of the lower electrode 19, and the first support structure 12 and the second support layer 18 are disposed at different heights on the outer sidewall of the lower electrode 19;

[0122] A capacitor dielectric layer 21, and the capacitor dielectric layer 21 covers the lower electrode 19, the second support layer 18, and the upper surface of the substrate of the cell array region;

[0123] An upper electrode 22, and the upper electrode 22 covers the capacitor dielectric layer 21.

[0124] In an embodiment of the present invention, the first support structure 12 may include a plurality of sub-support layers and insulating dielectric layers located between the respective sub-support layers. By providing a plurality of sub-support layers, the stability of the lower electrode can be improved.

[0125] As another example, the capacitor structure may further include: a metal layer 23 located on the upper electrode 22. Specifically, the metal layer 23 may be tungsten.

[0126] As another example, the semiconductor device may further include: an ONONO structure composed of a first dielectric layer 11, a first support structure 12, a second dielectric layer 13, a second support layer 18, and an oxide layer 24, located on the substrate 10 in the peripheral circuit region. This ONONO structure can meet the height requirements of the peripheral circuit region and reduce the height difference between the cell array region and the peripheral circuit region.

[0127] In other embodiments of the present invention, the capacitor dielectric layer 21 may further cover at least part of the upper surface of the guard ring structure 17 and the second support layer 18 located in the peripheral circuit region.

[0128] The above is a semiconductor device provided by an embodiment of the present invention, which includes a substrate 10. The substrate 10 includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region. A stacked structure is formed on the substrate 10. The stacked structure includes a plurality of capacitor structures and a guard ring structure 17. Among them, the plurality of capacitor structures are formed on the cell array region, and there is a support structure between at least some adjacent capacitor structures. The support structure includes a first support structure 12 and a second support layer 18. The guard ring structure 17 is formed on the intermediate region and surrounds the capacitor structures on the cell array region. By providing the guard ring structure 17 in the intermediate region, the electrode structure of the cell array region can be supported, the tilting of the lower electrode 19 can be avoided, the stability of the structure can be improved, and at the same time, it can also play a role in physically isolating the cell array region and the peripheral circuit region to avoid current leakage, thereby greatly improving the performance of the semiconductor device.

[0129] Although the embodiments disclosed in the present invention are as above, the above content is only an embodiment adopted for the convenience of understanding the present invention and is not intended to limit the present invention. Any person skilled in the art within the technical field to which the present invention pertains, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form of implementation and details, but the protection scope of the present invention must still be subject to the scope defined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that Including: Forming a stacked structure on a substrate, wherein the stacked structure includes a first dielectric layer, a first support structure, and a second dielectric layer sequentially formed on the substrate, and the substrate includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region; Forming a plurality of guard ring trenches surrounding the periphery of the cell array region in the intermediate region; Depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, and depositing a second insulating material on the bottom surface and sidewalls of the plurality of guard ring trenches to form a guard ring structure; the guard ring structure includes a plurality of guard rings, and the plurality of guard rings extend along a direction perpendicular to the substrate, and the extension depths are different; Forming a capacitor structure in the cell array region.

2. The method according to claim 1, wherein Forming a plurality of guard ring trenches surrounding the periphery of the cell array region in the intermediate region, including: Depositing a photoresist layer on the second dielectric layer; Patterning the photoresist layer to form at least one first etching window in the intermediate region; Etching the first dielectric layer, the first support structure, and the second dielectric layer in the intermediate region based on the first etching window, and stopping the etching until the upper surface of the substrate of the semiconductor device is exposed, to form at least one first guard ring trench surrounding the periphery of the cell array region.

3. The method according to claim 2, wherein Forming a plurality of guard ring trenches surrounding the periphery of the cell array region in the intermediate region, further including: Patterning the photoresist layer to form a second etching window in the intermediate region; Etching the intermediate region based on the second etching window to form a second guard ring trench surrounding the periphery of the cell array region, and the second guard ring trench has a different depth from the first guard ring trench.

4. The method according to claim 3, characterized in that Forming a second guard ring trench surrounding the periphery of the cell array region, including: Forming a plurality of second guard ring trenches surrounding the periphery of the cell array region, wherein the plurality of second guard ring trenches extend along a direction perpendicular to the substrate and the extension depths are different.

5. The method according to claim 1, wherein Depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, and depositing a second insulating material on the bottom surface and sidewalls of the guard ring trench to form a guard ring structure, including: Synchronously depositing the first insulating material on the upper surface of the second dielectric layer and the bottom surface and sidewalls of the guard ring trench, and the first insulating material is the same as the second insulating material.

6. The method according to any one of claims 1 to 5, characterized in that Forming a capacitor structure in the cell array region, including: Patterning the second support layer in the cell array region; Using the patterned second support layer as a mask to etch the first dielectric layer, the first support structure, and the second dielectric layer in the cell array region, to form a lower electrode groove in the stacked structure composed of the first dielectric layer, the first support structure, and the second dielectric layer, and depositing a conductive material in the lower electrode groove to form a lower electrode; Depositing a mask layer on the stacked structure formed with the lower electrode; Patterning the mask layer to expose at least a part of the upper surface of the second support layer located in the cell array region; Etch the first dielectric layer, the second dielectric layer, the exposed second support layer, and the first support structure located below the exposed second support layer; Conformally deposit a capacitive dielectric layer covering the lower electrode, the second support layer, and the upper surface of the substrate in the cell array region; and Deposit a conductive material on the capacitive dielectric layer to form an upper electrode.

7. The method according to claim 6, characterized in that, After depositing a conductive material on the capacitive dielectric layer to form an upper electrode, it further includes: depositing a metal layer on the upper electrode.

8. The method according to claim 1, wherein After depositing a first insulating material on the upper surface of the second dielectric layer to form a second support layer, the method further includes: depositing an oxide layer on the upper surface of the second support layer in the peripheral circuit region to form an ONONO structure composed of the first dielectric layer, the first support structure, the second dielectric layer, the second support layer, and the oxide layer.

9. The method according to claim 1, wherein Forming a stacked structure on the substrate includes: Sequentially deposit a first dielectric layer, a first support structure, and a second dielectric layer on the substrate, wherein the first support structure includes a plurality of sub-support layers and insulating dielectric layers located between adjacent sub-support layers.

10. A semiconductor device, characterized in that, Including: A substrate, the substrate includes a cell array region, a peripheral circuit region, and an intermediate region located between the cell array region and the peripheral circuit region, and at least one gate structure is included in the peripheral circuit region; A stacked structure is formed on the substrate, the stacked structure includes a guard ring structure and a plurality of capacitor structures, wherein the plurality of capacitor structures are formed on the cell array region, and there is a support structure between at least some adjacent capacitor structures, the support structure includes a first support structure and a second support layer; the guard ring structure is formed on the intermediate region and surrounds the capacitor structures on the cell array region, the guard ring structure includes a plurality of guard rings, the plurality of guard rings extend in a direction perpendicular to the substrate, and the extension depths are different.

11. The semiconductor device according to claim 10, wherein, The plurality of guard rings extend in a direction perpendicular to the substrate, and the extension depths are different, including: The plurality of guard rings extend in a direction perpendicular to the substrate, wherein the bottom surface of at least one guard ring contacts the upper surface of the substrate of the semiconductor device.

12. The semiconductor device according to claim 10, wherein, A stacked structure is formed on the substrate, the stacked structure includes a guard ring structure and a plurality of capacitor structures, and the capacitor structure includes: A lower electrode; The first support structure and the second support layer, wherein the first support structure and the second support layer support at least part of the outer sidewalls of the lower electrode, and the first support structure and the second support layer are disposed at different heights on the outer sidewalls of the lower electrode; A capacitive dielectric layer, the capacitive dielectric layer covers the lower electrode, the second support layer, and the upper surface of the substrate in the cell array region; An upper electrode, the upper electrode covers the capacitive dielectric layer.

13. The semiconductor device according to claim 12, wherein The capacitive dielectric layer also covers the guard ring structure and at least part of the upper surface of the second support layer in the peripheral circuit region.

14. The semiconductor device according to claim 10, wherein, The first support structure includes a plurality of sub-support layers and insulating dielectric layers located between each sub-support layer.

15. The semiconductor device according to claim 10, wherein The semiconductor device further includes an ONONO structure located on a substrate in the peripheral circuit region and composed of a first dielectric layer, the first support structure, a second dielectric layer, the second support layer, and an oxide layer.

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