Amorphous Metal Thin Film Transistor

Abstract

Various amorphous metal thin film transistors are described herein. Embodiments of such transistors include an amorphous metal gate and a channel conductor formed on a non-conductive substrate. Additional embodiments of such transistors include an amorphous metal source, an amorphous metal drain, and a channel conductor formed on a non-conductive substrate. Methods of forming such transistors are also described.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 651,014, filed on March 30, 2018, and U.S. Provisional Application No. 62 / 777,009, filed on December 7, 2018, under 35 U.S.C. §119(e), which are hereby incorporated by reference in their entirety. [Technical field]

[0003] The present disclosure relates to microelectronic devices incorporating one or more layers of amorphous metal films in thin film transistors. [Background technology]

[0004] Amorphous metals are rigid solid materials whose atomic structure lacks the long-range periodicity that characterizes crystalline materials. In amorphous metals, for example, by incorporating two or more components, the formation of crystal planes is suppressed. An example of an amorphous metal having four components - zirconium, copper, aluminum and nickel - is described in U.S. Patent No. 8,436,337. 55 Cu 30 Al 10 Ni5. Amorphous metals can be identified by their resistivity measurements, which show that while still conductive, amorphous metal materials have resistivities approximately ten times greater than their crystalline counterparts. Amorphous metals also have smoother surfaces than crystalline metals, as indicated by root mean square (RMS) surface roughness measurements.

[0005] Amorphous multi-component metal films (AMMFs) in the range of about 10-200 nm can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. These AMMFs can be formed using standard deposition processes. The exemplary amorphous metal Zr described above 55 Cu 30 Al 10 Ni5 is an AMMF that can be formed on a substrate by conventional sputtering deposition using four different metal targets. As a result, the electric field at the interface of the AMMF and the oxide film is more uniform.

[0006] This uniformity has produced excellent current-voltage (IV) characteristics for metal-insulator-metal (MIM) diodes and transistors that exhibit Fowler-Nordheim tunneling. Tunneling MIM diodes incorporate an AMMF as a lower electrode and a crystalline metal film as an upper electrode. The two electrodes are separated by a single dielectric barrier that provides a tunneling path for charge carriers to move between the electrodes. The single dielectric barrier results in a current response that depends on the polarity of the applied voltage. At a specific voltage, charge carriers in the device tunnel only in one direction, i.e., unidirectional tunneling. That is, tunneling occurs from the lower electrode to the upper electrode or from the upper electrode to the lower electrode, depending on the polarity of the applied voltage. Various diode and transistor applications of AMMF are discussed in U.S. Patents Nos. 8,436,337 and 8,822,978.

[0007] Amorphous metal thin film nonlinear resistors (AMNRs) with performance superior to existing thin film nonlinear resistors are discussed in U.S. Patent No. 9,099,230 and PCT Patent Application No. WO2014 / 074360. The current response of these AMNRs is independent of the polarity of the applied voltage, while other thin film resistors are not. This polarity independence is due to the presence of two dielectric barriers, where the charge carriers at each barrier are forced to tunnel in substantially opposite directions. AMNRs exhibit bidirectional tunneling because charge carriers in the device tunnel in both directions across the barriers in response to the applied voltage. That is, tunneling occurs from the upper electrode to the lower electrode and from the lower electrode to the upper electrode regardless of the polarity of the applied voltage. This polarity-symmetric AMNR can provide improved signal control in liquid crystal display (LCD) or organic light emitting diode (OLED) display technology and electromagnetic sensor arrays. [Summary of the invention]

[0008] The present disclosure is directed to devices and systems including amorphous metal thin film transistors (AMTFTs) and methods of forming the same.

[0009] These AMTFTs are thin, high-performance devices that can replace transistors in display technology, such as control transistors for pixels in flat-panel displays. Because these devices can be manufactured very efficiently, such as covering a smaller footprint relative to ordinary transistor technology, this will leave more than 50% of the pixel window area for light to pass through.

[0010] In various embodiments, the device of the present disclosure includes an amorphous metal thin film transistor (AMTFT) on a supporting substrate. The supporting substrate can be a non-conductive substrate that is more cost-effective than a silicon or semiconductor substrate. For example, the supporting substrate can be aluminoborosilicate glass, fused quartz, or other suitable non-conductive materials.

[0011] If the substrate is conductive, an insulator may be formed on the surface of the substrate between the surface of the substrate and the first electronic component on the substrate. For example, if a silicon or semiconductor substrate is used, a native oxide or other insulator is on the surface of the substrate to isolate the silicon from the first electronic component to ensure non-conductivity.

[0012] The supporting substrate can be any of a variety of materials, such as a glass substrate, a silicon or other semiconductor substrate, or a flexible substrate including a polymer (e.g., rubber or plastic). In various embodiments, the substrate is flexible. In some such embodiments, the transistor is made entirely of amorphous materials (i.e., amorphous metal gates, sources and drains, amorphous metal oxide insulators, and amorphous metal oxide semiconductors).

[0013] In an embodiment, the transistor of the present disclosure includes at least one amorphous metal layer. Any suitable amorphous metal can be used. In an embodiment, the amorphous metal used includes Zr, Cu, Ni, Al, or a combination thereof. For example, the amorphous metal layer can be an alloy of titanium and aluminum. In some embodiments, the alloy is TiAl3, TiAl7, TiAl, or a combination thereof. In a specific embodiment, the alloy is TiAl3. In a specific embodiment, the alloy is TiAl3, i.e., aluminum in which 25% of the atoms are replaced by titanium. In other embodiments, the amorphous metal layer is Cu, Zr, or an alloy of the two (e.g., CuZrB).

[0014] In various embodiments, an amorphous metal layer is formed on a supporting substrate. In some such embodiments, the surface of the supporting substrate onto which the amorphous metal layer is formed is a flat surface. This flat surface, combined with the uniform and smooth surface of the amorphous metal layer, allows the amorphous metal gate to have a uniform and smooth surface, which results in fewer surface defects. This is in comparison to crystalline metals. Surface defects in crystalline metals result in non-uniform electric fields, which can cause electronic devices to malfunction.

[0015] In some embodiments, the amorphous metal layer is or is formed as an amorphous metal gate structure. Therefore, in an embodiment, the AMTFT of the present disclosure includes an amorphous metal gate and a channel conductor. In various embodiments, the channel conductor is a semiconductor material. In some embodiments, the channel conductor is an oxide. In a specific embodiment, the channel conductor is InGaZnO.

[0016] In an embodiment, the AMTFT also includes a source and a drain. As will be appreciated by those skilled in the art, such electrodes may be crystalline, amorphous, multi-material stacks, etc. The source and drain may be crystalline metals or other suitable conductors. In some embodiments, the material may be a metal (e.g., Al, Mo, etc.) or a semiconductor material (e.g., polysilicon). In some embodiments, the material may be a highly conductive aluminum-based material. These electrodes may be very thin at the atomic level, such as a graphene layer. In an embodiment, the source / drain has the same thickness and material properties. In an alternative embodiment, the source is a conductive material different from the drain. In this embodiment, the source / drain may be formed in different steps. The source / drain may have different thicknesses, different material properties, and different sizes, depending on the product into which the transistor is incorporated.

[0017] In some embodiments, the amorphous metal layer is or is formed as a source and a drain. Therefore, in an embodiment, the AMTFT of the present disclosure includes an amorphous metal source and a drain and a channel conductor. Thus, in an embodiment, the AMTFT of the present disclosure includes a gate, a source and a drain of an amorphous metal.

[0018] In an embodiment, the transistor further comprises a first tunneling insulator.The first tunneling insulator is typically a very thin layer, for example no greater than about 20 nanometers (nm).

Brief Description of the Drawings

[0019] A detailed description is described with reference to the accompanying drawings. The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not drawn to scale, and some of these elements are enlarged and positioned to improve the legibility of the drawings. As will be appreciated by those skilled in the art, the shapes of particular elements may be modified (e.g., rounded, tapered, elongated, etc.) to suit a particular application.

[0020] Figure 1A is a cross-sectional view of an amorphous metal thin film transistor (AMTFT) according to one embodiment of the present disclosure. Figure 1B yes Figure 1A Top view of the features of an AMTFT.

[0021] Figure 2A is a cross-sectional view of an AMTFT according to another embodiment of the present disclosure. Figure 2B yes Figure 2A Top view of the features of an AMTFT.

[0022] Figure 3A is a cross-sectional view of an AMTFT according to another embodiment of the present disclosure. Figure 3B yes Figure 3A Top view of the features of an AMTFT.

[0023] Figure 4A is a cross-sectional view of an AMTFT according to another embodiment of the present disclosure. Figure 4B yes Figure 4A Top view of the features of an AMTFT.

[0024] Figure 5A is a cross-sectional view of an AMTFT according to another embodiment of the present disclosure. Figure 5B yes Figure 5A Top view of the features of an AMTFT.

[0025] Fig. 6A is a cross-sectional view of an AMTFT according to another embodiment of the present disclosure. Figure 6B yes Fig. 6A Top view of the features of an AMTFT.

[0026] Figure 7 A display formed in accordance with the present disclosure is shown.

[0027] Fig. 8A , Figure 8B and Figure 8C is an illustration of a pixel with coplanar conversion according to an embodiment of the present disclosure.

[0028] Fig. 9 Included are devices having screens with pixels and enhanced views of pixels formed according to the present disclosure.

[0029] Fig.10 is a top view of a shared selection line layout according to an embodiment of the present disclosure.

[0030] Fig.11 It is a transistor structure in array form used in displays.

[0031] Fig. 12A is a cross-sectional view of an AMTFT formed adjacent to an amorphous metal non-linear resistor (AMNR) according to an embodiment of the present disclosure. Fig. 12B yes Fig. 12A Top view of the characteristics of the AMTFT and AMNR.

[0032] Fig.13A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to an embodiment of the present disclosure. Fig. 13B yes Fig.13A Top view of the characteristics of the AMTFT and AMNR.

[0033] Fig.14A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to an embodiment of the present disclosure. Fig. 14B yes Fig.14A Top view of the characteristics of the AMTFT and AMNR.

[0034] Fig.15A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to an embodiment of the present disclosure. Fig. 15B yes Fig.15A Top view of the characteristics of the AMTFT and AMNR.

[0035] Fig.16A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to an embodiment of the present disclosure. Fig. 16B yes Fig.16A Top view of the characteristics of the AMTFT and AMNR.

[0036] Fig.17A is a cross-sectional view of an AMTFT formed adjacent to an AMNR according to an embodiment of the present disclosure. Fig. 17B yes Fig.17A Top view of the characteristics of the AMTFT and AMNR.

[0037] Fig.18A is a cross-sectional view of an AMTFT formed adjacent to an AMHET according to an embodiment of the present disclosure. Fig.18B yes Fig.18A Top view of the characteristics of the AMTFT and AMNR. Fig.18C and Fig.18D Shows Fig.18A and Fig.18B Performance data of AMTFT and AMNR.

[0038] Fig.19A An example of a circuit diagram of a reset / set flip-flop is shown. Fig.19B Measurements of various nodes comprising the reset / set flip-flop of the AMTFT are shown. Fig.19C A truth table is shown.

[0039] Fig. 20A A circuit diagram of an exemplary AMLCD or EPD circuit is shown. Fig. 20B is a top view of an exemplary matrix of AMLCDs of an EPD circuit. Fig. 20C A single pixel circuit of the array is shown, as Fig. 20B The rectangle indicated in .

[0040] Fig.21A A circuit diagram of an exemplary AMOLED circuit is shown. Fig. 21B A top view of an exemplary matrix of AMOLED structures is shown. Fig. 21C A single pixel circuit of the array is shown, as Fig. 21B The rectangle indicated in .

[0041] Fig. 22 A second exemplary AMOLED circuit is shown including six transistors and one capacitor.

[0042] Fig.23 A third exemplary AMOLED circuit is shown including five transistors and two capacitors.

[0043] Fig.24A An exemplary gate driver circuit block diagram is shown. Fig. 24B An exemplary gate driver shift register circuit is shown. Fig.24C An example of a gate driver buffer circuit in which an AMTFT can be used is shown.

[0044] Fig.25 An exemplary circuit diagram of a cascode amplifier circuit is shown.

[0045] Fig.26A and Fig.26B Schematic diagram showing angles that can be measured in a deformed flexible substrate. [Specific implementation method]

[0046] It will be appreciated that, although specific embodiments of the disclosure have been described for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure.

[0047] In this specification, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter can be practiced without these specific details. In some cases, well-known structures and methods of semiconductor processing including embodiments of the subject matter disclosed herein are not described in detail to avoid obscuring the description of other aspects of the disclosure.

[0048] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

[0049] The present disclosure is directed to various embodiments of transistors incorporating amorphous metal films. The amorphous metal films used in conjunction with a tunneling insulating layer perform transistor functions without the complexity of standard silicon-based transistors. Such amorphous metal transistors can be formed on any number of supporting substrates, which gives designers flexibility regarding the types of materials and products that can be incorporated with the transistors (i.e., active circuits). These amorphous metal transistors can be formed on flexible substrates because they can bend and change shape without damaging the circuits. These flexible substrates can be polymers, glass, or other materials.

[0050] Many aspects of people's lives benefit from the use of smaller and smaller electronic devices. These devices include televisions, mobile electronic devices (such as cell phones, smartphones, tablet computers), and wearable electronic devices such as smart watches and pedometers. Transistors built on semiconductor substrates are limited by the materials used to form these circuits, i.e., silicon or other semiconductor wafers. With flexible transistors, the potential uses of electronic devices can be further expanded and improved, such as lighter and faster displays, wearable displays, mobile or easily movable displays, integration into Internet of Things applications, or integration into medical devices.

[0051] These transistor structures can be used to form high performance analog devices or digital devices as dictated by the end application. Further, since these transistor structures do not use semiconductor materials, countless applications based on non-semiconductor transistors are possible. However, as will be described in the present disclosure, semiconductor materials can be utilized, and the transistor structures themselves are not based on doped silicon wafers, but rather incorporate amorphous metal films formed on any number of supporting substrates.

[0052] Figure 1A is a first embodiment of an AMTFT having a cross-sectional view of an AMTFT structure 100 formed on a supporting substrate 102 . Figure 1B yes Figure 1A 1 is a top view of an AMTFT structure 100. The structure 100 includes an amorphous metal gate 104 on a supporting substrate 102 and a first tunneling insulator 106 on the amorphous metal gate 104. Source / drain electrodes 108 and 110 (e.g., crystalline metal, amorphous metal, multi-material stack, etc.) are on the first tunneling insulator 106. The source / drain electrodes 108, 110 overlap the amorphous metal gate 104 by at least a first distance 105. A channel conductor 112 (which may be a semiconductor) overlaps the source / drain electrodes 108, 110 by at least a second distance 107. A second insulator 114 is optionally deposited on the channel conductor 112.

[0053] The substrate 102 can be a variety of materials, such as conductive, semiconductive, or nonconductive materials. Since the transistor structure has nonconventional materials, the substrate can have nonconventional properties. For example, the substrate can be deformable or bendable so that it can return to its resting shape. The transistor structure can also operate in a curved or bent configuration.

[0054] In some embodiments, the substrate is glass, polymer, plastic or other materials. In other embodiments, the substrate is rubber. As used herein, "rubber" includes the polymer of isoprene and the form of polyisoprene. In some such embodiments, the substrate is plastic. Any suitable plastic can be used. In some embodiments, the plastic is arylamide, acrylamide, polybenzimidazole (PBI), polyetherimide, polyetherketoneketone (PEKK), polyetheretherketone (PEEK), polyamide, polyimide, polyamide-imide, polystyrene (PS), polyphenylene oxide (PPO), polyphthalamide (PPA), polyvinyl alcohol (PVA), acrylonitrile butadiene styrene (ABS), polycarbonate (PC), thermosetting plastics, PBI-PEEK, urea, epoxy resin, polyurethane or any combination thereof. In some embodiments, the plastic is polyethylene. In a specific embodiment, the plastic is high-density polyethylene.

[0055] In other embodiments, the flexible substrate can be deformed (e.g., bent like a bow, rolled up, etc.) to form a curve having a center angle of at least about 5 degrees. In some embodiments, the flexible substrate can be deformed (e.g., bent like a bow, rolled up, etc.) to form a curve having a center angle of at least about 10 degrees. Unless otherwise specified, the center angle of the curve is measured relative to the vertex of the curve. In embodiments where the substrate is deformed in more than one location, such as Fig.26B As shown, a corresponding number of curves can be measured, including a first curve 2604 and a second curve 2602 corresponding to angle A and angle B, respectively. In some embodiments, the flexible substrate can be deformed (e.g., bent like a bow, rolled up, etc.) to form a curve with a central angle of at least about 10 degrees in each of the first curve and the second curve. In other words, the substrate can be bent, formed, or otherwise moved into a shape suitable for the end use. The transistor structure formed on the flexible substrate can be used in a bent or formed shape. It is also envisioned that if the end use is suitable for a non-flexible substrate, such a transistor can be formed on a rigid substrate.

[0056] In an embodiment, the AMTFT is formed when the flexible substrate is in a planar arrangement. In some such embodiments, the flexible substrate can then be deformed (eg, bent, rolled, curved, etc.) without damaging the AMTFT structure.

[0057] The material of the support substrate can be selected by the manufacturer based on the final application of the transistor structure and the final device being manufactured. For example, if the transistor structure is incorporated with an array of transistor structures, the array can be implemented within a liquid crystal display. Other end applications include wearable electronic devices. The support substrate can be transparent or opaque, such as substrates that can be used in certain reflective displays.

[0058] Fabrication on a non-conductive, flexible support substrate can significantly reduce manufacturing costs. Such a substrate could enable roll-to-roll manufacturing of transistors. This manufacturing change could redefine the electronics supply chain.

[0059] An amorphous metal layer is formed on the substrate. An amorphous metal gate 104 is formed by removing excess portions of the amorphous metal layer. The formation of the amorphous metal layer may include any film formation technique, such as sputtering, solution deposition, or electron beam deposition. For example, multi-source RF (or DC) magnetron sputtering using elemental or mixed component metal targets of Zr, Cu, Ni, and Al may be employed. Sputtering deposition has significant manufacturing advantages over similar smooth semiconductors deposited using advanced epitaxial techniques such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

[0060] As described above, portions of the amorphous metal layer may be etched or otherwise removed, such as by using masks, photolithography, and other techniques. In other embodiments, the amorphous metal layer may be deposited into a shape suitable for the application. The amorphous metal layer may be deposited at room temperature via sputtering, and may maintain amorphous and smooth properties during subsequent heating steps. The adaptability and flexibility of the amorphous metal layer in both the formation method and the use method makes possible applications endless.

[0061] In embodiments having an amorphous metal gate on a flexible substrate, it is contemplated that the flexible substrate deforms (e.g., bends) to an angle of at least about + / - 5 degrees from a plane 2601 formed by the substrate 102 in a flat or static position. Unless otherwise specified, all angles described in terms of measurements in degrees are measured from the plane 2601 (e.g., Fig.26A ).

[0062] The first tunneling insulator 106 is on the amorphous metal gate 104. In some embodiments, a portion of the first tunneling insulator 106 layer between the source / drain 108, 110 and the amorphous metal gate 104 may be thinner than other portions.

[0063] The first tunneling insulator 106 is formed as a conformal layer, which may be formed by blanket deposition. This is the simplest and most cost-effective manufacturing option, but the first tunneling insulator 106 may be patterned to suit the final application of the transistor structure.

[0064] The tunneling insulator can be any suitable insulator, including oxides, nitrides, silicon nitrides, metal oxides (e.g., aluminum oxide), etc. In an embodiment, the first tunneling insulator is a metal oxide (e.g., Al2O3) or a metal nitride that can be formed as a very thin layer. The first tunneling insulator is thin enough to enable tunneling and the generation of hot electrons. In some embodiments, the portion of the first tunneling insulator layer between the source / drain and the amorphous metal gate can be thinner than other portions. In a specific embodiment, the first tunneling insulator is an aluminum oxide layer not greater than 10 nm deposited by atomic layer deposition.

[0065] In various embodiments, the AMTFT of the present disclosure includes a second insulator. The second insulator can be any suitable insulator, including oxide, nitride, silicon nitride, metal oxide, etc.

[0066] Subsequently, source / drain electrodes 108, 110 are formed on the first tunnel insulator 106. Each of the source / drain electrodes overlaps the amorphous metal gate 104 by at least a distance 105. Figure 1A and Figure 1B One configuration of source / drain electrodes relative to the amorphous metal gate is shown. Other configurations and orientations are possible. To enable electron movement, the electrodes overlap the amorphous metal gate by a certain amount.

[0067] In one embodiment, the source and drain are formed simultaneously. This can be done by blanket deposition followed by an etching step. It can be seen that the source / drain have the same thickness and material properties. In an alternative embodiment, the source is a different conductive material than the drain and is formed in a different step. The source / drain can have different thicknesses, different material properties, and different sizes, depending on the product into which the transistor is incorporated.

[0068] The channel conductor 112 is on the source / drain 108 , 110 . The channel conductor 112 overlaps the source / drain 108 , 110 by a distance 107 . Figure 1A and Figure 1B One embodiment of a configuration of the channel conductor 112 relative to the source / drain 108, 110 and the first tunneling insulator 106 is shown. Other configurations and orientations are possible.

[0069] Some embodiments of the method of the present disclosure include forming a second insulator 114 on the source / drain 108, 110. The second insulator 114 covers all exposed surfaces and is ideally conformal. This layer can be a protection for the transistor structure. However, other structures can be formed on the transistor, and there are embodiments of these structures that are single-device layered structures. In other variations, openings can be formed in the second insulator 114 to expose the surfaces of the source / drain 108, 110 that can be electrically connected thereto. In a single-device layer embodiment, the electrical connections to the gate, source, and drain are in a straight line from the ends 109, 111, and 113.

[0070] The ultra-smooth amorphous metal gate used in this embodiment provides better electric field control across the AMTFT gate insulator compared to conventional thin film transistors that use a rough crystalline metal electrode for the gate.

[0071] Figure 2A Another embodiment of an AMTFT is shown in FIG. , which is a cross-sectional view of an AMTFT structure 200 formed on a supporting substrate 202 . Figure 2B yes Figure 2A FIG. 2 is a top view of an AMTFT structure 200 of FIG. 2. The structure 200 includes an amorphous metal gate 204 on a supporting substrate 202 and a first tunneling insulator 206 on the amorphous metal gate 204. A channel conductor 212 is on the first tunneling insulator 206. Source / drain electrodes 208, 210 are partially disposed on the channel conductor 212 and partially disposed on a surface of the first tunneling insulator 206. The source / drain electrodes 208, 210 overlap the amorphous metal gate 204. A second insulator 214 is optionally deposited over the source / drain electrodes 208, 210.

[0072] exist Figure 2A and Figure 2B 2, gate 204 is separated from channel conductor 212 by tunneling insulator 206. Source / drain 208 / 210 is separated from the channel conductor by tunneling insulator 206. There is an overlap region 219 between gate 204, channel conductor 212, and source / drain 208. Source / drain 208 / 210 may be formed in direct contact with channel conductor 212. Overlap region 219 is the region where electrons will flow during operation through the tunneling oxide.

[0073] Figure 3A and Figure 3B Another embodiment of an AMTFT is shown in FIG. Figure 3A is a cross-sectional view of an AMTFT structure 300 formed on a supporting substrate 302, Figure 3B yes Figure 3AFIG. 3 is a top view of an AMTFT structure 300 of FIG. 3. The structure is a gate-first device, where the gate is closest to the substrate compared to the other layers described below. The structure 300 includes a first amorphous metal gate 304 on a supporting substrate 302 and a first tunneling insulator 306 on the first amorphous metal gate 304. A channel conductor 312 is formed on the first tunneling insulator 306. Source / drain electrodes 308, 310 overlap the channel conductor 312 and the first amorphous metal gate 304. The overlapping region 301 of the gate, channel, and source / drain electrodes provides a path for electron movement.

[0074] Note that all channel conductors described herein can be formed from semiconductor materials using standard semiconductor processing techniques that are beneficial to the final application. Other conductive materials can be used as channels. The source / drain of the present disclosure can also be various materials. In some embodiments, the source / drain can be a crystalline material. In other embodiments, the source / drain can be an amorphous material, such as an amorphous metal. In yet other embodiments, the source / drain can be a multilayer stack of materials, such as a stack of metal layers.

[0075] In some embodiments, the portion of the first tunneling insulator layer 306 between the source / drain 308, 310 and the first amorphous metal gate 304 can be thinner than other portions. For example, the first tunneling insulator layer 306 can be thinned in the region 301 to reduce the distance between the source / drain 308, 310 and the gate 304. In this configuration, the insulating layer has recesses, and the channel conductor 312 is formed in these recesses. These recesses in the tunneling insulator can be applied to any of the embodiments described herein.

[0076] A second insulator 314 is deposited over the source / drain 308, 310. A second gate 316 is deposited over the second insulator 314. The second gate 316 can be a metal, such as a crystalline metal, an amorphous metal, or a multi-material stack. The second gate 316 is substantially aligned with the amorphous metal gate 304 and the channel conductor 312. The second gate 316 extends at least over the region 301. The second gate 316 can be incorporated into other embodiments. In this embodiment, the second gate 316 extends over the ends 303, 305. In some embodiments, the second gate 316 has ends 311, 313 positioned between the end 303 of the first gate and the end 307 of the channel conductor 312. In an embodiment, the second gate enhances device performance.

[0077] Figure 4A 4 shows another embodiment of an AMTFT, which is a cross-sectional view of an AMTFT structure 400 in a gate-last formation method. Figure 4B yes Figure 4A4. A top view of an AMTFT structure 400 of FIG. 4. Structure 400 includes a first insulator 414 on a supporting substrate 402. This can be formed by blanket deposition coating the entire substrate or the surface of the substrate to be processed to form the transistor. A channel conductor 412 is formed on the first insulator 414. Note that the sidewalls of the various layers are illustrated in an inclined configuration. These sidewalls can be oriented more vertically, more like perpendicular to the surface 411 of the first insulator. The sidewalls are transverse to the surface of the insulator. The sidewalls of the various layers of various embodiments can be at angles different from those illustrated.

[0078] The source / drain 408, 410 overlaps the channel conductor 412. In a preferred embodiment, the source / drain is an amorphous metal. A second insulator 406, a tunneling insulator, is formed on the source / drain 408, 410. The second insulator is in direct contact with the amorphous metal of the source / drain. A gate 416 is formed on the second tunneling insulator 406. The gate 416 can be a metal, such as a crystalline metal, an amorphous metal, or a multi-material stack. In an embodiment, the gate 416 is substantially aligned with the channel conductor 412. In an embodiment, the gate 416 is aligned between the source / drain 408, 410. The active area (i.e., the overlapping area 413) is at least between the end 417 of the gate 416 and the end 419 of the source / drain 408.

[0079] exist Figure 4A In the embodiment of FIG. 4 , the gate 416 is farthest from the substrate. The tunnel insulator 406 is between the gate and the source / drain 408 / 410. The channel is separated from the gate by the source / drain 408 / 410.

[0080] Figure 5A and Figure 5B Another embodiment of an AMTFT is shown in FIG. Figure 5A is a cross-sectional view of an AMTFT structure 500 formed on a supporting substrate 502, Figure 5B yes Figure 5A FIG. 5 is a top view of an AMTFT structure 500 of FIG. 5. This is a gate-last configuration. The structure 500 includes a first insulator 514 on a supporting substrate 502. Source / drain electrodes 508, 510 formed of an amorphous metal are formed on the first insulator 514. A channel conductor 512 overlaps the source / drain electrodes 508, 510 at a region 513. The channel conductor is in direct contact with the source / drain electrodes and may be a conformal layer that overlaps and covers all exposed locations during deposition.

[0081] A second tunneling insulator 506 is formed on the channel conductor 512 and on the source / drain 508, 510. A gate 516 is deposited over the second tunneling insulator 506. The gate 516 can be a metal, such as a crystalline metal, an amorphous metal, or a multi-material stack. Tunneling insulators work well when in direct contact with an amorphous metal, which in this embodiment is the source / drain. In an embodiment, the gate 516 is substantially aligned with the channel conductor 512, with an overlap region 517. In an embodiment, the gate 516 is aligned between the source / drain 508, 510 and overlaps the source / drain to some extent.

[0082] For each of the illustrated embodiments, the top view provides the ends of each component that are coupled to other components in the final product. These couplings can be through vias, other overlapping layers, or other coupling techniques that allow electrical signals to pass to these transistor structures. Fig. 6A and Figure 6B Another embodiment of an AMTFT is shown in FIG. Fig. 6A is a cross-sectional view of an AMTFT structure 600 formed on a supporting substrate 602, Figure 6B yes Fig. 6A FIG. 6 is a top view of an AMTFT structure 600. The structure 600 includes an amorphous metal gate 604 on a supporting substrate 602 and a first tunneling insulator 606 on the amorphous metal gate 604. A channel conductor 612 is formed on the first tunneling insulator 606. A second tunneling insulator 618 is deposited on the channel conductor 612. The channel conductor 612 and the gate 604 overlap at a region 611.

[0083] In an embodiment, the second tunneling insulator 618 is substantially aligned with and completely overlaps the middle region of the amorphous metal gate 604. The second gate 616 is on the second tunneling insulator 618. In an embodiment, the second gate 616 is substantially aligned with the amorphous metal gate 604 so that the respective midlines are aligned. Region 613 corresponds to the overlapping region of the first gate and the second gate. The second gate 616 can be a metal, such as a crystalline metal, an amorphous metal, or a multi-material stack.

[0084] The second dielectric layer 618 is patterned and removed or otherwise shaped to correspond to the size of the second gate 616. The third insulator 614 is on the second gate 616. In an embodiment, the third insulating layer 614 is discontinuous so that the channel conductor 612 is exposed in locations 615, 617. These locations or openings allow direct coupling to the channel conductor 612 through the source / drain 608, 610. The source / drain 608, 610 is formed over the third insulating layer 614 and overlaps the channel conductor 612. In some embodiments, the second gate and the source / drain 608, 610 can be formed simultaneously so that they are formed after the third insulating layer.

[0085] Figure 7 700 is a display that may include an AMTFT of the present disclosure. The display 700 includes a display area 702, which includes a plurality of pixels 704. The display may be on a flexible or rigid substrate 706. In some embodiments, the substrate is glass. The display may be a flat panel display that forms an image, such as a video, television program, or other digital media.

[0086] Each pixel of the flat panel display is controlled by a thin film transistor, such as an AMTFT or an amorphous metal non-linear resistor (AMNR) or a combination of the two. These pixels receive two signals, one signal to start the switch, i.e., AMFTF or AMNR, and the other signal to set the brightness when the switch is started. The selection driver 708 is coupled to the pixel and starts the switch. These selection drivers are sometimes called gate drivers. As shown in the figure, the selection driver is on the left side of the display area.

[0087] The data driver 710 controls the brightness of the pixel. In known systems, the data driver and the selection driver are large, individually packaged chips. These chipsets occupy a considerable area on the edge of the substrate 706. Since display manufacturers often purchase these chips from other silicon chip manufacturers, these chips also increase the cost. The selection driver of the present disclosure made with the AMTFT of the present disclosure is formed during the same processing step as the pixel, and the pixel is also formed by AMTFT or AMNR. This leads to a significant reduction in the border of the display. Compared with current display technology, the distance 712 between the edge of the display area 702 and the edge of the glass can be significantly reduced. Currently, this area must accommodate multiple integrated circuits that are welded or otherwise coupled to the substrate and the pixel. Note that in some embodiments, if desired, the pixel can be formed only by AMNR. It is also envisioned that the pixel can be formed only by AMTFT.

[0088] AMTFT allows the selection driver to be formed directly on the display glass. This allows the glass frame around the display area to be made thinner and eliminates a separate integrated circuit. In various embodiments, the sub-pixels in the display area are controlled by an amorphous metal film non-linear resistor (AMNR) device. In various embodiments, the sub-pixels in the display area are controlled by an amorphous hot electron transistor (AMHET). In various embodiments, the sub-pixels in the display area are controlled by an AMTFT device.

[0089] In some embodiments, both the selection driver and the data driver are formed directly on the glass during the manufacture of the pixel using AMNR, AMTFT and AMHET. As described above, amorphous metals provide very smooth surfaces. These smooth surfaces affect the electric field control across the gate insulator (such as tunneling insulator). In addition, the transistor of the present disclosure can be formed by amorphous materials, that is, the gate and source / drain are amorphous metals, the insulator is an amorphous metal oxide, and the channel is an amorphous metal oxide semiconductor. All these amorphous transistors and other circuits provide mechanical flexibility.

[0090] Fig. 8A , Figure 8B and Figure 8C 800 is a top view and a cross-sectional view of a pixel 800 including an AMNR device. These devices can be used for coplanar switching (IPS). As used in the present disclosure, a pixel can refer to a pixel or a sub-pixel. A selection driver or other transistor for controlling and driving pixels and sub-pixels can be formed as an AMTFT of the present disclosure. As described below, an AMTFT can be coupled to an AMNR device to control and drive various pixels.

[0091] Fig. 8A is a top view of a pixel 800 including a plurality of AMNR devices 802 . Figure 8B is a cross-sectional view of pixel 800 through line AA. Figure 8C 800 through line BB. Pixel 800 is formed on a substrate 802 that is transparent or otherwise capable of transmitting light from a light source, which can be any of the substrates discussed in the present disclosure. A first plurality of interconnects 804a-804f are formed on substrate 802. In this embodiment, the first plurality of interconnects 804a-804f are all formed of an amorphous metal film.

[0092] A first tunnel insulator 810 is formed over the first plurality of interconnects. A second plurality of interconnects 814a-814h are formed on the first tunnel insulator 810. Select lines 816 and 818 may be formed simultaneously with the second plurality of interconnects 814a-814h.

[0093] A second insulator 822 is formed on the second plurality of interconnects 814a-814h. The second insulator can be a different material than the first tunnel insulator. A plurality of coplanar electrodes 826a and 826b are formed on the second insulator. A top glass layer 828 is positioned above the LCD layer 830. Electrode 826a is also a data line. With this coplanar switching configuration, the data line is formed on the substrate, opposite to the top glass layer 828. Electrodes 826a and 826b are formed to have a comb shape. The number of combs can be less or more as dictated by the application of the pixel.

[0094] Fig. 9A device 900 is included having a screen 901 with an array 902 of pixels 904 formed according to the present disclosure. The device may be any electronic device including a display, such as a television, computer, mobile phone, tablet computer, or other device including pixels, such as Figure 7 Display in .

[0095] Each pixel 904 includes a red sub-pixel 906, a green sub-pixel 908, and a blue sub-pixel 910. Some embodiments will include a white sub-pixel 912. The sub-pixels are illustrated as having a vertical alignment configuration; however, any configuration can be envisioned so that a plurality of AMNR devices having at least one active area are used to form the sub-pixels. The illustrated configuration includes two AMNR devices for each color, wherein each AMNR device includes six active areas. Selection lines 914 and 916 are shared across adjacent pixels and sub-pixels. Top or second electrodes 918, 920, 922, 924 are coupled to other adjacent pixels in columns.

[0096] According to the vertical alignment (VA) pixel 906,908,910,912 of the embodiment of the present disclosure, comprises a first AMNR device 926 having six active areas and a second AMNR device 928 having six active areas. In other embodiments, the first AMNR device may have different numbers of active areas compared to the second AMNR device. The pixel may be formed with only two active areas per AMNR device. For example, if only two of the first interconnection are formed, the pixel will include an interconnection, wherein the extension of the electrode will overlap with the interconnection.

[0097] The first interconnects are formed on the first glass layer. These first interconnects are amorphous metal films, a very flat, smooth material that simplifies the manufacturing process. Next, a tunnel insulator is formed on the first interconnects.

[0098] The second interconnect is formed on the tunnel insulator. An additional signal line may be formed simultaneously with the second interconnect. Alternatively, the first electrode may be formed simultaneously with the second interconnect. A liquid crystal layer or other display material layer is formed on the first electrode and the second interconnect.

[0099] The second electrode is formed on the second glass layer. In this embodiment, the first electrode and the second electrode are staggered, but the electrodes can be aligned with each other so that from a top view, the second electrode will obscure at least the center portion of the first electrode. In this embodiment, the first electrode and the second electrode are generally square in shape, but other shapes are envisioned. The electrodes can also be comb-shaped.

[0100] In other words, the pixel may include the following: a first glass layer (substrate), first and second amorphous metal thin film interconnects (interconnects) on the first glass layer, a first electrode (electrode) on the first glass layer, a first electrode coupled between the first and second amorphous metal thin film interconnects, a second electrode (electrode 918), and a second glass layer, the second electrode being on the second glass layer. As pixel requirements change, the design may change so that various combinations of the number of interconnects and active areas may be achieved by combining different numbers of interconnects.

[0101] The process of constructing such a pixel with vertical alignment and two active areas per AMNR device is a simple process in which no semiconductor is required. When the pixel is used for a display, the process of constructing the pixel is called constructing a backplane. The backplane includes depositing and patterning amorphous metal thin film interconnects on a first glass layer. Next, a tunneling insulator is deposited. Next, a first electrode is deposited and patterned. A second electrode is formed on a second glass layer by deposition and patterning. The second glass layer can be a color filter glass. The second electrode can be indium tin oxide.

[0102] The selection line of the pixel may be formed simultaneously with the first electrode. In an alternative embodiment, the selection line is formed first, and then the first electrode is formed and coupled to the selection line. Fig. 9 The select lines are line 916 and line 914 and may include a second interconnect. The select lines may be coupled to the first electrode through a via, which will be described in more detail below.

[0103] If the second electrode is an opaque conductor, four mask steps are used in the process to form a pixel with two AMNR devices, each with two active areas. The pixel window material must be formed of a transparent conductive oxide. The process includes depositing and patterning an amorphous metal film to form first and second interconnects separated by a certain distance. This is the first mask step. The process includes forming a tunnel insulator, and then depositing and patterning a selection line on the first and second interconnects and overlapping the selection line with the first and second interconnects. This is the second mask step. An insulator is formed above the selection line. A via is formed through the insulator to provide access to one of the selection lines. A first electrode is then formed by depositing and patterning a conductive material, and the first electrode is coupled to one of the selection lines through the via. This is the third mask step. A second electrode is formed on the second glass layer using a conductive oxide. This is the fourth mask step. A liquid crystal layer is positioned between the first electrode and the second electrode. Alternatively, a two-tone mask can be used to reduce the number of mask steps. The two-tone mask can be used when forming the selection line and the first electrode.

[0104] After only two mask steps, the AMNR device can be fully formed. When formed with an AMTFT in a pixel or as a control circuit, there may be more than two mask steps because other layers will be incorporated for other amorphous circuits.

[0105] These amorphous metal thin film materials are very smooth, so they are excellent materials to start the manufacturing process, as subsequent steps are based on a consistent surface. These amorphous metal thin films are typically the first layer formed; however, other configurations are envisioned, as described further in this disclosure.

[0106] The total height of the AMNR device from the top surface of the substrate to the top surface of the second layer interconnect is about 200 nanometers. These are very thin, high-performance devices. The total height of the AMFTF can be in the range of 250 nanometers to 400 nanometers.

[0107] An AMNR device with only two active regions may be able to achieve a threshold voltage of about 5 volts, where a device with twelve active regions may be able to achieve a threshold voltage of about 30 volts, where each device has a tunneling insulator of similar or identical thickness.

[0108] The threshold voltage relationship between two AMNR devices with different numbers of active areas is:

[0109] V 阈值AMNR-X#2 =V 阈值AMNR-X#1 *(n AMNR-X#2 / n AMNR-X#1 )

[0110] Where AMNR-X#1 is the first AMNR device, AMNR-X#2 is the second AMNR device, and n is the number of active areas.

[0111] The capacitance relationship between two AMNR devices with different amounts of active area is:

[0112] Capacitance AMNR-X#2 =Capacitance AMNR-X#1 *(n AMNR-X#1 / n AMNR-X#2 )

[0113] Where AMNR-X#1 is the first AMNR device, AMNR-X#2 is the second AMNR device, and n is the number of active areas.

[0114] Fig.101 is a top view of a plurality of sub-pixels with a shared selection line layout according to an embodiment of the present disclosure. A first sub-pixel 1000 is positioned between the second and third sub-pixels 1002, 1004. Each sub-pixel has two selection lines. A first sub-pixel 1300 has a first selection line 1006 shared with a second sub-pixel 1002 and a second selection line 1008 shared with a third sub-pixel 1004. These pixels can be combined with AMTFT circuits on displays or other electronic devices developed for high performance on non-silicon-based substrates.

[0115] Fig.11 is available on displays such as Figure 7 An exemplary array of transistor structures used in a display area shown. The array can be incorporated into a display or can be integrated with a sensor, such as in an x-ray detector. Array 1100 includes multiple rows 1104 and multiple columns 1102. Each row can conduct a base signal to an AMHET 1101 of the array. Each column can conduct an emitter signal to the AMHET 1101. The AMHET 1101 includes an amorphous metal layer 1106. The emitter 1110 overlaps the amorphous metal layer 1106 and is coupled to the row 1102. The base 1108 overlaps the amorphous metal layer 1108 and is coupled to the column 1104. The collector and contact 1114 overlap the amorphous metal layer 1106 and the base 1108. The collector 1114 is coupled to other pixel or unit control elements. The collector 1114 can be coupled to a capacitor or other transistors. In various embodiments, the capacitor includes one or more amorphous metal layers. In some such embodiments, the amorphous metal in the capacitor is the same as the amorphous metal used in the AMTFT.

[0116] The AMHET transistor 1101 can be operated as a matrix switch in common base, common emitter or common collector mode. The specific example is a common emitter configuration. Such a matrix switch allows control of individual elements.

[0117] Multiple AMHET transistors 1101 can be incorporated into various active matrix display technologies, such as liquid crystal displays, organic light emitting diode displays, electrophoresis, electroluminescence, etc. Each specific active matrix application will have additional circuit elements forming displays. Certain elements, such as resistors, capacitors, diodes, other transistors or other electronic components, can be formed in the same processing steps as AMHET or in subsequent processing.

[0118] In an embodiment, the AMHET structure includes an amorphous metal interconnect on a supporting substrate and a first tunneling insulator on the amorphous metal interconnect. The first electrode and the second electrode are on the first tunneling insulator. The first electrode and the second electrode overlap with the amorphous metal interconnect. The third electrode overlaps with the second electrode and is separated from the second electrode by the second insulator. For example, an exemplary AMHET structure is described and shown in WO2018 / 009901, which is incorporated herein by reference for the purpose of the patent's teaching on the structure.

[0119] The structure includes a first terminal coupled to a first electrode. A second terminal is coupled to the second electrode. A third terminal may be included to couple the third electrode to another electronic device. The first terminal and the second terminal may be formed simultaneously with the third electrode. Alternatively, the first terminal and the second terminal are formed in a processing step subsequent to forming the third electrode.

[0120] By adjusting the electric field applied to the first electrode, the second electrode and the third electrode, the AMHET structure operates like a transistor. The first electrode can be an emitter, the second electrode can be a base, and the third electrode can be a collector. The transistor structure can operate in a common emitter mode, a common base mode, or a common collector mode.

[0121] Electrons tunnel from a first electrode, i.e., the emitter, to an amorphous metal interconnect through a first tunneling insulator in response to an applied voltage through a first terminal. Electrons travel through the amorphous metal interconnect and the first tunneling insulator to a second electrode, i.e., the base. When tunneling is complete, these electrons are considered "hot" because their energy is higher than the Fermi energy of the second electrode (i.e., the base). These principles apply to all embodiments described in this disclosure.

[0122] Unlike a typical transistor structure, the amorphous metal transistor structure can be operated in a reverse mode so that electrons move from the third electrode to the first electrode via the second electrode and the amorphous metal interconnect. In this reverse mode, the transistor structure functions like a tunneling diode with adjustable threshold voltage and asymmetry. The adjustable threshold voltage and asymmetry are achieved by combining the electric field applied from the first electrode 108 and the third electrode to modulate the electric field applied to the second electrode.

[0123] In another embodiment, the AMHET structure includes an amorphous metal layer formed on a non-conductive support substrate, or includes an insulator on the substrate to isolate the substrate from the amorphous metal layer. The tunneling oxide layer is formed on the amorphous metal layer. The first electrode and the second electrode are formed on the tunneling oxide and are coplanar on the tunneling oxide, and portions of the first electrode and the second electrode overlap with the amorphous metal layer.

[0124] A dielectric layer is formed on the first electrode and the second electrode. A third electrode and a fourth electrode are formed on the dielectric layer. Portions of the third electrode and the fourth electrode overlap and are aligned with the amorphous metal layer and the first electrode and the second electrode, respectively. The third electrode and the fourth electrode are simultaneously formed of the same material. A contact may also be formed simultaneously with the third electrode and the fourth electrode. The contact is coupled to the second electrode through the dielectric layer, and the contact is coupled to the first electrode through the dielectric layer.

[0125] The first overlapping region formed by the amorphous metal layer, the first electrode and the third electrode is where electrons can be transferred to and from the first electrode and the amorphous metal layer. There is a second active region corresponding to the overlap of the amorphous metal layer, the second electrode and the fourth electrode. The second active region is where electrons can be transferred to and from the second electrode and the amorphous metal layer.

[0126] The first electrode and the second electrode correspond to the emitter and the base, respectively. The third electrode and the fourth electrode are collectors. The two collectors form two transistors with a shared base-emitter structure. The two-transistor structure can be formed by the same method as the transistor structure, except that more conductive layers are left when forming the third electrode.

[0127] In another embodiment, the AMHET transistor structure includes an amorphous metal film formed on a substrate and a tunnel insulator on the amorphous metal film.

[0128] In one area, the tunneling insulator is thinned or otherwise patterned to have a different thickness than other areas of the tunneling insulator. The operating characteristics of the transistor structure are tuned by adjusting the thickness of the tunneling insulator. If the tunneling insulator is selectively thinned in one active area, there may not be symmetrical conduction through the emitter-base structure due to the different thicknesses. In certain end use cases, this may be acceptable.

[0129] The first electrode is formed to overlap the amorphous metal film and is separated from the amorphous metal film by a tunnel insulator having a first thickness. A second electrode is formed to overlap the amorphous metal film, and the second electrode may be the same material as the first electrode and formed in the same processing step, or may be a different material formed at a different time. The second electrode is spaced from the first electrode and is generally in a parallel orientation relative to the first electrode.

[0130] The second electrode is separated from the amorphous metal film by a tunneling insulator having a second thickness less than the first thickness. Due to the difference in thickness, the behavior of electrons transferred to and from the first electrode to the amorphous metal film will be different from the behavior of electrons transferred to and from the second electrode to the amorphous metal film. For example, the patterned tunneling insulator can minimize parasitic capacitance that can be formed at the overlap region of the first electrode and the second electrode with the amorphous metal film. Thus, the tunneling insulator can be patterned in the overlap region of either electrode as the manufacturing and final product may dictate.

[0131] An insulator is formed on the first electrode and the second electrode. A third electrode is formed on the first electrode and the second electrode. Contacts formed simultaneously with the third electrode are formed to be coupled to the second electrode and the first electrode, respectively.

[0132] In another embodiment, the AMHET transistor structure has a base and an emitter of different sizes. The transistor structure includes an amorphous metal interconnect on a planar substrate. The amorphous metal interconnect is rectangular from a top-down perspective and has a longest dimension extending in a first direction.

[0133] The tunneling insulator is on the interconnect. The emitter is on the tunneling insulator. The base is also on the tunneling insulator and is separated from the emitter. The emitter and the base are both at least partially on top of the interconnect and overlap the interconnect.

[0134] The base includes at least a portion above and aligned with the interconnect, the at least a portion having a first dimension that is smaller than a second dimension of the emitter. Having different dimensions changes the operating characteristics of the transistor, which gives the manufacturer an opportunity to adjust the transistor structure. For example, the gain of the transistor structure can be increased by making the base thinner. The base and emitter can be the same material or can be different materials.

[0135] The base can be formed to have a first thickness and then thinned as shown so that a first portion of the base is the first thickness and a second portion of the base is a second thickness that is less than the first thickness. Alternatively, the base can be formed in a different processing step from the emitter and formed to be thinner than the emitter. Instead of removing portions of the base once formed, the base can be formed as a thinner layer than the emitter.

[0136] A first dielectric layer is formed over the base and emitter. A collector is formed over the first dielectric layer. A contact to the base may be formed simultaneously with and from the same material as the collector. An opening is formed through the first dielectric layer to allow contact with the base. Another contact to the emitter may be formed in a similar manner.

[0137] A second dielectric layer may be formed over the collector and the contact. In some embodiments, a contact is formed through the second dielectric layer to couple the collector terminal to another device.

[0138] In another embodiment, the AMHET transistor structure includes an amorphous metal layer formed on a substrate. A tunneling oxide layer is formed on the amorphous metal layer. A barrier layer is formed on the tunneling oxide layer. The barrier layer can be an inorganic material such as a metal oxide or an organic material such as a polymer, or any suitable material. The barrier layer can minimize parasitic capacitance that may occur due to the overlap of the amorphous metal and the electrode.

[0139] A first opening is formed in the barrier layer. A first electrode is formed in the first opening. The first electrode overlaps the amorphous metal layer. A second opening is formed in the barrier layer, overlapping a portion of the amorphous metal layer. A second electrode is formed to overlap the amorphous metal layer, and a portion of the second electrode is in the second opening.

[0140] A dielectric layer is formed on the first electrode and the second electrode. A third electrode is formed on the dielectric layer. In an embodiment, no layer is planarized. In other embodiments, individual layers or some layers are planarized.

[0141] The fourth electrode and the fifth electrode are coupled to the first electrode and the second electrode, respectively. The fourth electrode and the fifth electrode may be formed simultaneously from the same material as the third electrode.

[0142] The first electrode and the second electrode of this or any embodiment of the present disclosure may be formed of an ultra-thin 2D conductor such as graphene, MoS2, W2, Ti3C2, GaN, BN, Ca2N, or other suitable material. In some embodiments, the first electrode is an atomically thin layer of a conductive material, while the second electrode is a significantly thicker layer of a conductive material. The conductive materials of these layers may be different types of conductors.

[0143] In an alternative embodiment, the AMHET transistor structure has an amorphous metal layer formed in a recess of the substrate. A first surface of the amorphous metal layer is coplanar with a first surface of the substrate.

[0144] A tunneling oxide layer is formed on the amorphous metal layer and the first surface of the substrate. A first electrode and a second electrode are formed on the tunneling oxide layer. The first electrode overlaps a first portion of the amorphous metal layer, and the second electrode overlaps a second portion of the amorphous metal layer.

[0145] The first dielectric layer is on the first electrode and the second electrode. The third electrode is formed on the flat surface of the first dielectric layer. The second dielectric layer is on the third electrode.

[0146] In yet another embodiment, the AMHET transistor structure includes an amorphous metal layer on a flat surface of a substrate. A tunneling oxide layer is on the amorphous metal layer. The side of the amorphous metal layer and the side of the tunneling oxide layer are coplanar. This can be achieved by forming an amorphous layer, forming a tunneling oxide layer, and then etching both layers simultaneously.

[0147] The first electrode and the second electrode are formed on the tunnel oxide layer. The dielectric layer is formed on the first electrode and the second electrode. The third electrode is formed on the dielectric layer.

[0148] Advantageously, the processing steps used to form the AMTFT of the present disclosure can also be used to form an AMNR and / or AMHET adjacent to the AMTFT. Fig. 12A and Fig. 12B As shown, AMTFT1200 is formed adjacent to AMNR 1220 on a supporting substrate 1202 ( Figure 1A and Figure 1B , and described above). As will be appreciated by one of ordinary skill in the art, FIG. 12A to FIG. 17B The AMNR shown may be replaced with an AMHET or any other suitable structure and similar processing advantages may be achieved.

[0149] In an embodiment, the amorphous metal gate 1204 and the amorphous metal interconnect 1224 are deposited and formed in the same processing step, which may include forming a first amorphous metal layer on the substrate 1202, patterning the first amorphous metal layer, and removing portions of the first amorphous metal layer.

[0150] AMTFT 1200 may be a transistor in a portion of a circuit where AMNR 1220 is a pixel in a display area such that the distance between the AMTFT and the AMNR is large. In such embodiments, the AMTFT and the AMNR may not be directly coupled together. In other embodiments, the AMTFT and the AMNR are part of a single pixel such that they may be directly coupled to each other.

[0151] A first tunneling insulator 1206 is deposited on the amorphous metal gate 1204 and the amorphous metal interconnect 1224. The first tunneling insulator can be a conformal layer that will be formed without any mask. Then, as described in accordance with other embodiments in the present disclosure, source / drain 1208, 1210 and first and second electrodes 1228, 1230 are deposited on the first tunneling insulator 1206. The source / drain 1208, 1210 and the first and second electrodes 1228, 1230 can be deposited as a single layer, such as an amorphous metal layer, patterned, and then etched to form an appropriate shape. For example, the source / drain 1208, 1210 has ends 1211, 1213 that extend away from the gate 1204 to couple to other devices or to ends 1215, 1217 of the first and second electrodes 1228, 1230.

[0152] The channel conductor 1212 is then deposited to overlap the source / drain 1208, 1210. Further, a second insulator 1214 is optionally deposited and formed on the channel conductor 1212, the source / drain 1208, 1210 and the first and second electrodes 1228, 1230. The channel conductor can be formed as a layer, such as an amorphous semiconductor layer, patterned, and then etched. The process can be a three-mask process. This AMTFT structure allows the AMNR to be fully formed before the semiconductor layer required for the AMTFT channel is deposited. This reduces the damage of the AMNR tunneling insulator during the channel deposition and formation.

[0153] Similarly, the processing steps used to form other AMTFTs of the present disclosure can also be used to form an AMNR adjacent to an AMTFT. Fig.13A (a cross-sectional view) and Fig. 13B As shown in FIG. 13 (a top view), an AMTFT 1300 is formed adjacent to an AMNR 1320 on a supporting substrate 1302. Figure 2A and Figure 2B 13 and described above). In such an embodiment, an amorphous metal gate 1304 and an amorphous metal interconnect 1324 are deposited and formed in the same processing steps. A first tunneling insulator 1306 is then deposited and formed on the amorphous metal gate 1304 and the amorphous metal interconnect 1324. A channel conductor 1312 is then deposited and formed on the first tunneling insulator 1306. Before completing the AMNR, a channel is formed, patterned, and etched to overlap the metal gate 1304.

[0154] Then, as described herein, source / drain 1308, 1310 is deposited and formed on channel conductor 1312 and first tunnel insulator 1306, and first and second electrodes 1328, 1330 are deposited and formed on first tunnel insulator 1306. Source / drain 1308, 1310 and first electrode 1328 and second electrode 1330 can be formed simultaneously with the same material. In some embodiments, if it is beneficial to the final product, they can be different materials formed in different processing steps. Further, second insulator 1314 is optionally deposited and formed on source / drain 1308, 1310, channel conductor 1312 and first and second electrodes 1328, 1330. Although not illustrated, AMNR and AMTFT will be coupled to each other and other circuits, which can be applied to other embodiments described.

[0155] In another example, Fig.14A (a cross-sectional view) and Fig. 14B As shown in FIG. 14A and FIG. 14B , an AMTFT 1400 is formed adjacent to an AMNR 1420 on a supporting substrate 1402. Figure 3A and Figure 3B ). In such an embodiment, an amorphous metal gate 1404 and an amorphous metal interconnect 1424 are deposited and formed in the same processing step. A first tunneling insulator 1406 is then deposited and formed on the amorphous metal gate 1404 and the amorphous metal interconnect 1424. A channel conductor 1412 is then deposited and formed on the first tunneling insulator 1406. Then, as described herein, source / drain 1408, 1410 is deposited and formed on the channel conductor 1412 and the first tunneling insulator 1406, and a first electrode and a second electrode 1428, 1430 are deposited and formed on the first tunneling insulator 1406. Further, a second insulator 1414 is optionally deposited and formed over the source / drain 1408, 1410, the channel conductor 1412, and the first and second electrodes 1428, 1430. Then, a second gate 1416 is deposited and formed on the second insulator 1414.

[0156] exist Fig.15A (a cross-sectional view) and Fig. 15B In another embodiment shown in FIG. 1 (a top view), AMTFT 1500 ( Figure 4A and Figure 4B1502 and described above) and AMNR 1520 are formed adjacent to each other. A first insulator 1514 is deposited and formed on a supporting substrate 1502. A channel conductor 1512 is then deposited and formed on the first insulator 1514. Source / drain 1508, 1510 is deposited and formed by an amorphous metal and overlaps with the channel conductor 1512. In the same step, an amorphous metal interconnect 1524 is deposited and formed on the first insulator 1514. Then, a second tunneling insulator 1506 is deposited and formed on the source / drain 1508, 1510 and on the amorphous metal interconnect 1524. Then, a gate 1516 and a first electrode 1528 and a second electrode 1530 are formed on the second tunneling insulator 1506, and can be formed in the same processing step. The AMTFT structure allows the AMNR to be fully formed after the semiconducting layer for the AMTFT channel conductor is deposited and formed. This reduces the possibility of damage to the AMNR tunneling insulator during channel deposition and formation.

[0157] exist Fig.16A (a cross-sectional view) and Fig. 16B In another embodiment shown in FIG. 1 (a top view), AMTFT 1600 ( Figure 5A and Figure 5B 1608 and described above) and AMNR 1620 are formed adjacent to each other. A first insulator 1614 is deposited and formed on the supporting substrate 1602. Source / drain 1608, 1610 are deposited and formed from amorphous metal on the first insulator 1614. In the same step, an amorphous metal interconnect 1624 is deposited and formed on the first insulator 1614. A channel conductor 1612 is then deposited and formed to overlap the source / drain 1608, 1610. A second tunneling insulator 1606 is then deposited and formed on the source / drain 1608, 1610, the channel conductor 1612, and the amorphous metal interconnect 1624. Then, a gate 1616 and a first electrode and a second electrode 1628, 1630 are formed on the second tunneling insulator 1606 in the same processing steps.

[0158] exist Fig.17A (a cross-sectional view) and Fig. 17B In another embodiment shown in FIG. 1 (a top view), AMTFT 1700 ( Fig. 6A and Figure 6B1702 and described above) and AMNR 1720 are formed adjacent to each other. A first amorphous metal gate 1704 and an amorphous metal interconnect 1724 are deposited and formed on a supporting substrate 1702. A first tunneling insulator 1706 is then formed on the amorphous metal gate 1704 and the amorphous metal interconnect 1724. A channel conductor is then formed on the first tunneling insulator 1712. A second tunneling insulator 1718 is deposited and formed on the channel conductor 1712. A second gate 1716 is deposited over the second tunneling insulator 1718. A third insulator 1714 is deposited over the second gate 1716 and the first tunneling insulator 1706. In an embodiment, the third insulating layer 1714 is deposited as a continuous layer and then portions are removed so that the channel conductor 1712 and the first tunneling insulator 1706 are exposed at one or more locations. In other embodiments, the third insulating layer 1714 is deposited as a discontinuous layer so that the channel conductor 1712 and the first tunneling insulator 1706 are exposed at one or more locations. Source / drain 1708 , 1710 and first and second electrodes 1728 , 1730 are formed over the third insulating layer 1714 at locations where the channel conductor 1712 and the first tunneling insulator 1706 are exposed.

[0159] Fig.17A and Fig. 17B The embodiment in is a top gate, self-aligned AMTFT with two gates. The first gate 1704 is the bottom gate, while the second gate 1716 is the last component formed.

[0160] Fig.18A and Fig.18B A specific embodiment of an AMTFT and an adjacent AMNR is shown in FIG. Fig.18A is a cross-sectional view of an AMTFT structure 1800 and an AMNR structure 1820, Fig.18B 18 is a top view thereof. AMTFT 1800 and AMNR 1820 are formed on a supporting substrate 1802. AMTFT 1800 includes an amorphous metal gate 1804 on a supporting substrate 1802, and AMNR 1820 includes an amorphous metal interconnect 1824. In an embodiment, the amorphous metal gate 1804 and the amorphous metal interconnect 1824 are deposited and formed in the same processing step. In some embodiments, the amorphous metal gate 1804 and the amorphous metal interconnect 1824 are formed of TiAl3. In some such embodiments, the thickness of the amorphous metal gate 1804 and the amorphous metal interconnect 1824 is about 60 nanometers (nm).

[0161] A first tunneling insulator 1806 is then deposited and formed on the amorphous metal gate 1804 and the amorphous metal interconnect 1824. In a specific embodiment, the first tunneling insulator 1806 includes Al2O3. In some such embodiments, the thickness of the first tunneling insulator 1806 is about 15 nm.

[0162] A channel conductor 1812 is then deposited and formed on the first tunnel insulator 1806. In some embodiments, the channel conductor 1812 is formed of InGaZnO. In some such embodiments, the thickness of the channel conductor 1812 is about 20 nm.

[0163] Then, as described herein, source / drain electrodes 1808, 1810 are deposited and formed on the channel conductor 1812 and the first tunnel insulator 1806, and first and second electrodes 1828, 1830 are deposited and formed on the first tunnel insulator 1806. In a specific embodiment, the source 1808, the drain 1810, the first electrode 1828, and the second electrode 1830 are made of aluminum and molybdenum. In some such embodiments, each electrode includes an aluminum layer about 300 nm thick and a molybdenum layer about 80 nm thick.

[0164] Source / drain 1808, 1810 are partially disposed on channel conductor 1812 and partially disposed on the surface of first tunneling insulator 1806. Source 1808 and drain 1810 overlap amorphous metal gate 1804. In a specific embodiment, source 1808 and drain 1810 overlap amorphous metal gate 1804 by approximately 1 μm.

[0165] In some embodiments, the width of source 1808 and drain 1810 is approximately 400 micrometers (μm). In a specific embodiment, source 1808 and drain 1810 are separated by approximately 100 μm.

[0166] The first electrode 1828 and the second electrode 1830 are disposed over the amorphous metal interconnect 1824. In a particular embodiment, the width of the first electrode 1828 and the second electrode 1830 is approximately 5 μm. In some such embodiments, the width of the amorphous metal interconnect 1824 is also approximately 5 μm.

[0167] Made and tested Fig.18A and Fig.18B AMTFT and AMNR. Fig.18C The resulting transfer curves and electron mobility diagrams are shown in . Fig.18D The current-voltage curve of AMNR is shown in . AMTFT is a bottom gate, top contact structure.

[0168] In various embodiments, the AMTFT structures described herein are used in circuit structures. Thus, embodiments of the present disclosure include circuits that include an AMTFT. For example, the AMTFT can be used in a reset / set flip-flop. Fig.19A An example of a circuit diagram of a reset / set flip-flop is shown in FIG. Fig.19B The timing diagram of the reset / set flip-flop including the AMTFT is shown in FIG. Fig.19C The truth table is shown in . Fig.19B The numbered lines in the input and output correspond to Fig.19C Phase column in .

[0169] In another embodiment, one or more AMTFTs are used in a display. In some such embodiments, the AMTFTs are used as switching TFTs in an active matrix liquid crystal display (AMLCD) or electrophoretic display (EPD) circuit. Fig. 20A A circuit diagram of an exemplary AMLCD or EPD circuit is shown. Fig. 20B is a top view of an exemplary matrix of AMLCDs of an EPD circuit. Fig. 20C A single pixel circuit of the array is shown, as Fig. 20B . In this embodiment, the AMTFT structure 2000 includes a metal gate 2004 and a first tunnel insulator (not shown) on the metal gate 2004. A channel conductor 2012 is formed on the first tunnel insulator 2006. Source / drain electrodes 2008, 2010 are partially arranged on the channel conductor 2012 and partially arranged on the surface of the first tunnel insulator. The source / drain electrodes 2008, 2010 overlap the metal gate 1904.

[0170] In another embodiment, the AMTFT structure is used in an active matrix organic light emitting diode (AMOLED) circuit. As will be appreciated, the AMOLED circuit can have various structures including different numbers of transistors and capacitors (e.g., 2 transistors and 1 capacitor, 5 transistors and 2 capacitors; 6 transistors and one capacitor; etc.). In various embodiments, any one or more transistors of the AMOLED circuit can be an AMTFT. In an embodiment, one of the transistors is an AMTFT. In an embodiment, two of the transistors are AMTFTs. In an embodiment, three of the transistors are AMTFTs. In an embodiment, four of the transistors are AMTFTs. In an embodiment, five of the transistors are AMTFTs. In an embodiment, six of the transistors are AMTFTs. In another embodiment, all transistors are AMTFTs.

[0171] Fig.21A A circuit diagram of an exemplary AMOLED circuit is shown. Fig.21AAs can be seen from FIG. 1 , the circuit includes two transistors and a capacitor. In various embodiments, the switch TFT, the drive TFT, or both are AMTFTs. Fig. 21B A top view of an exemplary matrix of AMOLED structures is shown. Fig. 21C A single pixel circuit of the array is shown, as Fig. 21B The rectangle indicated in .

[0172] Fig. 22 A second exemplary AMOLED circuit comprising six transistors and one capacitor is shown in FIG.

[0173] Fig.23 A third exemplary AMOLED circuit including five transistors and two capacitors is shown in FIG.

[0174] In yet other embodiments, the AMTFTs described herein are used in gate driver circuits. Fig.24A An exemplary gate driver circuit block diagram is shown in , including a shift register (G_SR), a clock line (CLK) and a buffer (BUF X5). Fig. 24B An exemplary gate driver shift register circuit is shown in FIG. In various embodiments, any one or more transistors shown are AMTFTs. In other words, any one of Tr1, Tr2, Tr3, Tr4, Tr5, Tr6 or a combination thereof is an AMTFT. Fig.24C An example of a gate driver buffer circuit in which an AMTFT can be used is shown.

[0175] In further embodiments, the source driver circuit includes one or more AMTFTs.

[0176] In further embodiments, the cascode amplifier circuit includes one or more AMTFTs. Fig.25 An exemplary circuit diagram of a cascade amplifier circuit is shown in FIG.

[0177] In embodiments where the substrate is deformed in more than one position, a corresponding number of angles may be measured. In some embodiments, the flexible substrate is deformed to an angle of at least + / -10 degrees. In some embodiments, the flexible substrate is deformed to an angle of at least + / -15 degrees. In some embodiments, the flexible substrate is deformed to an angle of at least + / -20 degrees. In some embodiments, the flexible substrate is deformed to an angle of at least + / -25 degrees. In some embodiments, the flexible substrate is temporarily (such as in use) or permanently deformed to an angle in the range of 45 degrees to 90 degrees. In some embodiments, the flexible substrate is deformed to an angle greater than 90 degrees.

[0178] As used herein, "approximately" means that the actual value may be slightly larger or smaller than the stated value or range, within ±20% of the stated value. In an embodiment, approximately means that the actual value is within ±15% of the stated value. In an embodiment, approximately means that the actual value is within ±10% of the stated value. In an embodiment, approximately means that the actual value is within ±5% of the stated value. In an embodiment, approximately means that the actual value is within ±1% of the stated value. In some embodiments, the first tunneling insulator is no greater than about 15 nanometers (nm). In some embodiments, the first tunneling insulator is no greater than about 10 nanometers. In some embodiments, the first tunneling insulator is about 20 nanometers. In some embodiments, the first tunneling insulator is about 15 nanometers. In some embodiments, the first tunneling insulator is about 10 nanometers.

[0179] The present disclosure is directed to embodiments including a non-conductive substrate, an amorphous metal gate on the substrate, and a channel conductor. Embodiments include a first tunneling insulator on the amorphous metal gate. In some embodiments, the source and drain are on the first tunneling insulator. The source and drain overlap the amorphous metal gate. In some embodiments, the source and drain are between the first tunneling insulator and the channel conductor.

[0180] The source and drain are on the first tunneling insulator and the channel conductor and overlap the amorphous metal gate. The second tunneling insulator can be on the channel conductor. The second insulator is on the first tunneling insulator. In some embodiments, the second gate is on the second tunneling insulator. The second tunneling insulator can be on the source and drain.

[0181] In some embodiments, the second gate is on the third insulator. The second tunneling insulator can be on the second gate and the channel conductor. The source and drain can be on the second tunneling insulator. In some embodiments, the source and drain abut against one or more portions of the exposed channel conductor. Other embodiments include an amorphous metal interconnect adjacent to the amorphous metal gate on the non-conductive substrate, wherein the amorphous metal interconnect is between the first tunneling insulator and the non-conductive substrate.

[0182] Some embodiments include a non-conductive substrate having an amorphous metal source, an amorphous metal drain, and a channel conductor. A first tunneling insulator is on the amorphous metal source and the amorphous metal drain. A gate is on the first tunneling insulator. A second tunneling insulator may be between the non-conductive substrate and the channel conductor.

[0183] The various embodiments described above may be combined to provide additional embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the Application Data Sheet are incorporated herein in their entirety by reference. If necessary, aspects of the embodiments may be modified to provide other embodiments using concepts from various patents, applications, and publications.

[0184] These and other changes can be made to the embodiments according to the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents that authorize such claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A thin film transistor device, comprising: Non-conductive substrate; Amorphous metal gate; a first tunneling insulator; Source and drain; as well as a channel conductor comprising a semiconductor material, wherein the first tunneling insulator is between the amorphous metal gate and the source and drain; and An overlapping area exists between the amorphous metal gate, the channel conductor and the source / the drain.

2. The device according to claim 1, wherein: The first tunneling insulator is on the amorphous metal gate.

3. The device according to claim 2, wherein: The source and the drain are on the first tunnel insulator, and the source and the drain overlap the amorphous metal gate.

4. The device according to claim 3, wherein: The source and drain are between the first tunneling insulator and the channel conductor. 5 . The device according to claim 2 , wherein the source and the drain are on the first tunneling insulator and the channel conductor, and the source and the drain overlap the amorphous metal gate.

6. The apparatus of claim 5, further comprising a second tunneling insulator over the channel conductor and the source and drain.

7. A thin film transistor device comprising: Non-conductive substrate; Amorphous metal source; Amorphous metal drain; a first tunneling insulator; Gate; as well as a channel conductor comprising a semiconductor material, wherein the first tunneling insulator is between the gate and the amorphous metal source and the amorphous metal drain, and There is an overlapping area between the amorphous metal source / the amorphous metal drain, the gate and the channel conductor.

8. The device according to claim 7, wherein: The first tunneling insulator is on the amorphous metal source and the amorphous metal drain.

9. The device according to claim 8, wherein: The gate is on the first tunneling insulator.

10. The apparatus of claim 9, further comprising a second insulator between the non-conductive substrate and the channel conductor.

11. The device according to claim 10, wherein: The second insulator is between the non-conductive substrate and the amorphous metal source and the amorphous metal drain.

12. The device according to claim 10, wherein: The channel conductor is between the non-conductive substrate and the amorphous metal source and the amorphous metal drain.

13. The device according to claim 10, wherein: The amorphous metal source and the amorphous metal drain are between the non-conductive substrate and the channel conductor.

14. A method of forming a thin film transistor device, comprising: forming an amorphous metal gate on a non-conductive substrate; forming a first tunneling insulator; forming a source and a drain; as well as A channel conductor comprising a semiconductor material is formed such that The first tunneling insulator is between the amorphous metal gate and the source and drain; and The amorphous metal gate, the channel conductor and the source / the drain have overlapping areas. The method of claim 14 , wherein the first tunneling insulator is formed on the amorphous metal gate.

16. The method according to claim 15, wherein: The source electrode and the drain electrode are formed on the first tunnel insulator, and the source electrode and the drain electrode overlap the amorphous metal gate.

17. The method according to claim 16, wherein: The channel conductor is at least partially formed on the source and drain.

18. The method according to claim 15, wherein: The source and the drain are formed on the first tunneling insulator and the channel conductor, and the source and the drain overlap the amorphous metal gate.

19. The method according to claim 18, further comprising: A second tunneling insulator is formed over the channel conductor and the source and drain.

20. A method of forming a thin film transistor device, comprising: forming an amorphous metal source electrode on a non-conductive substrate; forming an amorphous metal drain on the non-conductive substrate; forming a first tunneling insulator; forming a gate; as well as A channel conductor comprising a semiconductor material is formed such that The first tunneling insulator is between the gate and the amorphous metal source and the amorphous metal drain, and There is an overlapping area between the amorphous metal source / the amorphous metal drain, the gate and the channel conductor.

21. The method according to claim 20, wherein: The first tunneling insulator is formed on the amorphous metal source and the amorphous metal drain.

22. The method according to claim 21, wherein: The gate is formed on the first tunneling insulator.

23. The method according to claim 22, further comprising: A second tunneling insulator is formed on the non-conductive substrate, wherein the channel conductor is formed on the second tunneling insulator.

24. The method according to claim 23, wherein: The amorphous metal source and the amorphous metal drain are formed on the second tunneling insulator.

25. The method according to claim 23, wherein: The amorphous metal source and the amorphous metal drain are at least partially formed on the channel conductor, between the non-conductive substrate and the second tunneling insulator.

26. The method of claim 23, wherein: The channel conductor is at least partially formed on the amorphous metal source and the amorphous metal drain.

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