Radar signal reconnaissance and jamming signal generation calibration method and equipment

Abstract

The invention relates to a radar signal reconnaissance and interference signal generation calibration method and equipment, which comprises a host computer software module, an FPGA signal processing module and a vector signal transceiver module which are communicatively connected in sequence; the vector signal transceiver module realizes the transceiver processing of radar signals through a circulator; the vector signal transceiver module comprises a vector signal transmitting module and a vector signal receiving module; the signal receiving, transmitting, frequency conversion and analog-to-digital conversion functions are realized; the vector signal receiving module comprises a zero intermediate frequency receiver whose input end is communicatively connected to the circulator, and an analog-to-digital conversion module whose input end is communicatively connected to the output end of the zero intermediate frequency receiver; the invention has reasonable design, compact structure and convenient use.

Description

Technical Field

[0001] The invention relates to a radar signal reconnaissance and interference signal generation calibration method and equipment. Background Art

[0002] The modern battlefield is a battlefield with an increasingly complex electromagnetic environment, in which radar radiation signals and their counter signals are important components of the complex battlefield environment. Due to the application of a large number of information detection equipment such as radar, the battlefield has become increasingly transparent to both sides of the war. However, with the development of digital signal processing technology, radar can support better matching reception technology in hardware to suppress interference noise and clutter. At the same time, in key technologies such as target detection, recognition and tracking, the use of the target's Doppler frequency shift information can greatly improve performance. With the continuous development and innovation of radar systems, various new system radars have brought challenges to jamming technology. For example: pulse Doppler technology reduces the peak transmission power and increases the difficulty of long-distance detection. Phased array radar can randomly detect targets by adjusting the beam direction or shape through phase agility, and the pulse carrier, repetition rate, pulse width and even modulation style can be randomly agile, which brings huge challenges to radar jammers in radar signal extraction, identification, parameter estimation, etc.; multi-base collaborative combat radar is a typical application of radar networking, which improves the stealth of a single radar and can effectively prevent jammers from locating the radiation source; research on radar networking technology has also effectively prevented various jamming technologies from interfering with radar functions. Summary of the invention

[0003] The technical problem to be solved by the present invention is generally to provide a radar signal reconnaissance and interference signal generation calibration method and equipment.

[0004] To solve the above problems, the technical solution adopted by the present invention is:

[0005] A radar signal reconnaissance and interference signal generation calibration device, comprising a host computer software module, an FPGA signal processing module and a vector signal transceiver module which are sequentially connected in communication;

[0006] The vector signal transceiver module realizes the transceiver processing of radar signals through a circulator;

[0007] Vector signal transceiver module, including vector signal transmitting module and vector signal receiving module; realizes signal receiving, transmitting, frequency conversion and analog-to-digital conversion functions;

[0008] The vector signal receiving module includes a zero intermediate frequency receiver whose input end is communicatively connected to the circulator, and an analog-to-digital conversion module whose input end is communicatively connected to the output end of the zero intermediate frequency receiver;

[0009] The vector signal transmission module includes a zero intermediate frequency transmitter whose output end is communicatively connected to the circulator and a digital-to-analog conversion module whose output end is communicatively connected to the input end of the zero intermediate frequency transmitter;

[0010] The detected radar signal is received by the circulator, down-converted by the zero intermediate frequency receiver, and then sampled and stored to obtain an I / Q baseband signal; the I / Q baseband signal is converted into a digital signal by the digital-to-analog conversion module;

[0011] FPGA signal processing module, used for radar reconnaissance and radar jamming signal processing, with radar detection components, radar jamming components and parameter calculation and storage modules;

[0012] The radar detection component includes an input digital equalization module and a data extraction module;

[0013] After digital equalization and data extraction, the digital signal is used to calculate and store radar parameters through the parameter calculation and storage module;

[0014] Parameter calculation and storage module, used to calculate the radar amplitude parameters, generate antenna radiation pattern, calculate TOA parameter information, pulse information storage module, digital radio frequency memory and short-time Fourier transform module;

[0015] Short-time Fourier transform module is used to determine the frequency and phase of the radar signal and transmit it to the host computer software module;

[0016] The parameter calculation and storage module transmits the radar parameters to the host computer software module through the DMA channel and displays them;

[0017] The host computer software module displays radar parameters and identifies the radar model.

[0018] Radiation source database, connected to the host computer software module, receives external files, stores radar parameters and radar models; displays and saves pulse description word data;

[0019] The host computer software module generates interference signals and interacts with the radar interference component through DMA channels and registers to control interference data;

[0020] The radar jammer component includes a Doppler module, a noise generation module, a range delay module, a data difference module, and an output digital equalization module;

[0021] The radar jammer generates interference data based on the interference data generated by the host computer software module. After the Doppler module performs Doppler modulation processing and the distance delay module performs delay control, the noise signal generated by the noise generation module is output to the digital-to-analog conversion module through the data difference module and the output digital equalization module to generate an analog signal. The analog signal is up-converted into a radio frequency interference signal through a zero intermediate frequency transmitter and transmitted through a circulator.

[0022] The upper computer software module includes PDW display, signal sorting, map generation, sorting information storage, interference data generation and radar calibration.

[0023] A radar signal reconnaissance and interference signal generation calibration method, the steps are as follows:

[0024] The detected radar signal is received by the antenna, down-converted by the zero intermediate frequency receiver, and then sampled and stored to obtain the I / Q baseband signal. After ADC, digital equalization, and data extraction, it is handed over to the FPGA signal processing module for radar pulse parameter calculation and data storage; then, the radar signal parameters are transmitted to the host computer through DMA for display, and the radar model is identified and added to the radiation source database; secondly, when the interference signal is generated, the host computer and the FPGA signal processing module interact with each other through DMA and registers to control the interference data; thirdly, the FPGA signal processing module performs delay control, amplitude and Doppler modulation processing according to the interference data generated by the host computer software, and up-converts it into a radio frequency interference signal through digital difference, digital equalization, DAC, and zero intermediate frequency transmitter, and transmits it.

[0025] The present invention can realize three major functions of radar signal reconnaissance, radar interference signal generation, and radar detection function calibration. It can be used as a supporting invention for radar training, provide the radar with an electromagnetic interference environment close to actual combat, test and evaluate the anti-interference performance of radar equipment, and verify the detection performance of the calibrated radar.

[0026] Compared with the same type of radar jammers in the industry, the present invention integrates the three functions of radar signal reconnaissance, radar jammer signal generation, and radar calibration. The reconnaissance radar signal parameters can be generated by forwarding storage jammer signals to better realize the deceptive jamming effect on the radar, and the false track implemented on the radar is compared with the track received by the radar to realize the radar calibration function. The system features of the present invention are as follows: portable design, light weight, compact size, overall size not exceeding 400mm (L) × 300mm (W) × 60mm (H), overall weight not exceeding 5kg; convenient for field tests; wide frequency band coverage (supporting P band, S band, L band, C band); high bandwidth (200MHz); rich interface display; rich interference styles; support map function. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a system functional architecture diagram of the present invention.

[0028] Figure 2 It is the overall system architecture diagram of the present invention.

[0029] Figure 3 It is a flow chart of the SDIF signal sorting algorithm of the present invention.

[0030] Figure 4 It is a flow chart of the reconnaissance implementation of the present invention.

[0031] Figure 5 It is the interference signal flow chart of the present invention.

[0032] Figure 6 It is a reference diagram of the radar calibration result of the present invention.

[0033] Figure 7 It is a software design diagram of the present invention.

[0034] Figure 8 It is a flow chart of the reconnaissance design of the present invention.

[0035] Fig. 9 It is a schematic diagram of the noise interference design process of the present invention.

[0036] Fig.10 It is a flow chart of the dense false target interference design of the present invention.

[0037] Fig.11 It is a flow chart of multi-channel target interference simulation design of the present invention.

[0038] Fig.12 It is a schematic diagram of the sample or intermittent interference design process of the present invention.

[0039] Fig.13 It is a schematic diagram of the distance dragging interference design process of the present invention.

[0040] Fig.14 It is a schematic diagram of the separation target interference design process of the present invention.

[0041] Fig.15 It is a calibration design flow chart of the present invention. DETAILED DESCRIPTION

[0042] like Figure 1 As shown, in order to achieve the technical effects of convenience, flexibility, and integration requirements, the present invention includes a host computer software module, an FPGA signal processing module, and a vector signal transceiver module that are sequentially connected in communication; the vector signal transceiver module realizes the transceiver processing of the radar signal through a circulator;

[0043] Vector signal transceiver module, realizing signal receiving, transmitting, frequency conversion and analog-to-digital conversion functions; including vector signal transmitting module and vector signal receiving module;

[0044] The vector signal receiving module includes a zero intermediate frequency receiver whose input end is communicatively connected to the circulator, and an analog-to-digital conversion module whose input end is communicatively connected to the output end of the zero intermediate frequency receiver;

[0045] The vector signal transmission module includes a zero intermediate frequency transmitter whose output end is communicatively connected to the circulator and a digital-to-analog conversion module whose output end is communicatively connected to the input end of the zero intermediate frequency transmitter;

[0046] The detected radar signal is received by the circulator, down-converted by the zero intermediate frequency receiver, and then sampled and stored to obtain an I / Q baseband signal; the I / Q baseband signal is converted into a digital signal by the digital-to-analog conversion module;

[0047] FPGA signal processing module, used for radar reconnaissance and radar jamming signal processing, with radar detection components, radar jamming components and parameter calculation and storage modules;

[0048] The radar detection component includes an input digital equalization module and a data extraction module;

[0049] After digital equalization and data extraction, the digital signal is used to calculate and store radar parameters through the parameter calculation and storage module;

[0050] Parameter calculation and storage module, used to calculate the radar amplitude parameters, generate antenna radiation pattern, calculate TOA parameter information, pulse information storage module, digital radio frequency memory and short-time Fourier transform module;

[0051] Short-time Fourier transform module is used to determine the frequency and phase of the radar signal and transmit it to the host computer software module;

[0052] Parameter calculation and storage module: radar parameters are transmitted to the host computer software module through DMA channel and displayed;

[0053] The host computer software module displays radar parameters and identifies the radar model.

[0054] The radiation source database is connected to the host computer software module to store radar parameters and radar models;

[0055] The host computer software module generates interference signals and interacts with the radar interference component through DMA channels and registers to control interference data;

[0056] The radar jammer component includes a Doppler module, a noise generation module, a range delay module, a data difference module, and an output digital equalization module;

[0057] The radar jammer generates interference data based on the interference data generated by the host computer software module. After the Doppler modulation processing is performed by the Doppler module and the delay control is performed by the distance delay module, the interference data is output to the digital-to-analog conversion module through the data difference module and the output digital equalization module together with the noise signal generated by the noise generation module to generate an analog signal. The analog signal is up-converted into a radio frequency interference signal through a zero intermediate frequency transmitter and transmitted through a circulator.

[0058] The parameter calculation and storage module implements FFT operations based on Xilinx IP, and realizes digital signal processing and digital RF memory functions through custom IP;

[0059] The host computer software module is used to realize PDW display, signal sorting, map generation, sorting information storage, interference data generation and radar calibration.

[0060] The functions of the host computer software module are as follows: Figure 7 As shown:

[0061] Its main interface mainly displays the following parameters and information: radar parameters, interference parameters, control parameters, signal waveform and antenna radiation pattern, etc.

[0062] Directly import the radiation source library from external files to continuously enrich the content of the radiation source library. When interfering with a known radar, you can skip reconnaissance, select the radar parameters from the radiation source library, and directly perform interference operations, making the operation more efficient and convenient. Display and save the PA, RF, PW, and PRI data of the pulse description word (PDW) to better analyze radar characteristics and assist signal sorting functions.

[0063] The present invention can release various types of interference. The noise interference can select blocking interference, aiming frequency interference, and sweeping frequency interference; the point trace amplitude of dense false targets can be set to fixed or random, and at most 255 moving point traces can be released. The track target interference simulation can simulate a single target or multiple targets, a single interference or multiple interferences, and simulate a target + interference; sample interference or intermittent interference, and the noise amplitude is adjustable; distance dragging can simulate the release of false targets to get rid of radar tracking after the target is tracked by the radar; separation target can simulate the release of false targets after the target reaches a set distance, which is used to simulate the scene of enemy aircraft attacking positions.

[0064] Radar calibration includes interference data and radar track; through azimuth comparison and distance comparison, the radar's positioning and ranging performance is verified and calibrated to eliminate zero-position deviations caused by maintenance, component aging, appearance deformation and other factors.

[0065] The system workflow is as follows: the detected radar signal is received by the antenna, down-converted by the zero intermediate frequency receiver, and then sampled and stored to obtain the I / Q baseband signal. After ADC (analog-to-digital conversion), digital equalization, and data extraction, it is handed over to the FPGA for radar pulse parameter calculation and data storage. The radar signal parameters are transmitted to the host computer through DMA for display, and the radar model is identified and added to the radiation source database; when the interference signal is generated, the host computer and FPGA interact with each other through DMA and registers. The FPGA performs delay control, amplitude and Doppler modulation processing according to the interference data generated by the host computer software, and through digital difference, digital equalization, DAC (digital-to-analog conversion), it is up-converted to a radio frequency interference signal by the zero intermediate frequency transmitter and transmitted through the RF-OUT port. FPGA uses Xilinx IP to implement FFT operations, and uses custom IP to implement digital signal processing, DRFM and other functions.

[0066] like Figure 2 The hardware platform of the present invention is designed with the goal of being portable, small and low-power, and adopts a modular design concept. The present invention includes

[0067] Intelligent power supply module provides corresponding power supply for each functional module;

[0068] Embedded controller, using Intel's sixth-generation commercial CPU; memory supports dual-channel DDR4 memory interface; internal integrated high-speed SSD hard drive reserves at least one mSATA interface for external use, which can be connected to an external portable hard drive; graphics card, external display interface needs to reserve at least VGA interface and DVI interface; equipped with network card, the network card supports 10 / 100 / 1000Mbps Ethernet protocol, and reserves at least one Ethernet RJ45 interface for external use; equipped with serial port and serial port communication driver protocol, the serial port adopts DB9 form;

[0069] The FPGA signal processing module uses a PCIE SWITCH interconnection backplane and is connected to the embedded controller through a PCie×8 channel; it is connected to the vector signal transceiver module and the LO module of the frequency synthesizer and the clock and trigger synchronization module as the clock source and synchronization bus through a PCie×4 channel;

[0070] The vector signal transceiver module uses a VSA vector signal transceiver module based on a digital signal processor;

[0071] Among them, the VSA vector signal transmission module can provide fast and high-resolution spectrum measurement, demodulation and advanced time domain analysis functions. It can measure the amplitude and phase of the input signal at a specific frequency within a specified bandwidth, which is particularly suitable for characterizing complex radar pulses, transient or modulated signals. VGA has a wide frequency range, real-time signal analysis and advanced signal processing. With a high-performance programmable FPGA carrier board, it can provide a large use space for measurement applications. It can better measure dynamic signals. The VGA measurement process overcomes the scanning limitations by simulating a series of parallel filters through a signal "snapshot" or time record, and then processing all frequencies at the same time. Based on this, VGA is also called "dynamic signal analysis" or "real-time signal analysis". With excellent time capture capabilities, VGA can record the actual signal intact and replay it later for various data analysis. The captured signal can perform both spectrum analysis and vector modulation analysis to measure signal quality or identify signal defects. Digital signal processing (DSP) can provide measurement analysis in the time domain, frequency domain, modulation domain and code domain at the same time. VGA's FFT analysis can easily and accurately view time domain and frequency domain data. DSP provides vector modulation analysis, including analog and digital modulation analysis. VGA has an instantaneous RF bandwidth of up to 320 MHz, which can measure extremely wide bandwidth in a single acquisition, realize fast sampling, high linearity ADC and wideband internal calibration mechanism, and provide 80MHz, 160MHz and 320MHz instantaneous RF bandwidth with excellent measurement accuracy. Optimal dynamic range, floor noise and phase noise; wideband RF signal playback, up to 4GB / s bandwidth; with open onboard FPGA real-time signal processing unit and memory unit, support customization.

[0072] VGA vector signal receiving module can provide fast and high-resolution spectrum measurement, demodulation and advanced time domain analysis functions. It can measure the amplitude and phase of the input signal at a specific frequency within a specified bandwidth. It is particularly suitable for characterizing complex radar pulses, transient or modulated signals. VGA has a wide frequency range, real-time signal analysis and advanced signal processing. With a high-performance programmable FPGA carrier board, it can provide a large usage space for measurement applications. Specifically, it can better measure dynamic signals, excellent time capture capabilities, and large instantaneous bandwidth;

[0073] like Figure 3 , Step 1, signal sorting; SDIF algorithm is used as radar signal sorting algorithm. SDIF algorithm consists of two parts: PRI determination and sequence detection. PRI determination is the key to SDIF algorithm. Figure 3 As shown, the basic working process of the algorithm is as follows.

[0074] Step 1: First, read the positioning TOA sequence, the arrival sequence number is 1~P, and the span c=1; then, determine whether the number of pulses is greater than the set threshold; if not, perform a variance analysis and enter the radar library; if yes, execute step 1 and 2.

[0075] Step 1 and 2: First, calculate the difference between the TOA of two adjacent pulses to form the first-level difference histogram and calculate the detection threshold; then, after the sub-harmonic test, all values ​​exceeding the threshold are regarded as possible PRI values ​​for sequence retrieval; secondly, if the pulse sequence is successfully separated, repeat this process until all pulse trains are separated or there are pulses less than the set threshold number left; if the sequence retrieval cannot separate the pulse sequence, calculate the next level difference, set a new threshold, repeat the whole process, and finally complete the discrepancy identification;

[0076] Among them, the SDIF threshold is calculated as follows;

[0077] D_threshold (τ)=x(Ec)e^(-τ / kN)

[0078] In the formula, E is the total number of pulses; N is the total number of cells in the histogram; c is the difference series; x and k are constant coefficients, the values ​​of which are determined by experience, and the values ​​of x and k are positive numbers less than 1;

[0079] Step 2: Radar reconnaissance and sorting implementation process Figure 4 shown.

[0080] The upper computer software module obtains the TOA (i.e. pulse arrival time) data of the FPGA side through DMA for signal sorting. Step 2.1: First, after the signal sorting is completed efficiently through the SDIF algorithm, the parameter calculation and storage module of the FPGA performs STFT through the short-time Fourier transform module according to the result of signal sorting; then, after the intra-pulse feature analysis, the radar signal frequency, bandwidth, amplitude, type and other signal parameters are calculated, and the radar signal parameters are placed in the temporary radiation source table; secondly, for the temporary radiation source table, the radiation source library is continuously updated according to the similar results of the sorting, and the radar parameters with recognition credibility higher than the set threshold are stored in the radiation source library. The original radar radiation source parameters can also be imported into the radiation source library, and the reconnaissance sorting results are saved in the form of PDW data;

[0081] In order to better implement interference, radar parameters can be selected from a temporary radiation source table or a radiation source library to provide RF-related parameters for interference.

[0082] Step three, such as Figure 5 ,Step 3, perform interference signal generation, using DRFM technology mechanism;

[0083] First, when the system performs DRFM, after judging the arrival of the rising edge of the pulse, the I / Q data of the pulse is stored in the DRAM storage block, and the TOA and PDW of the pulse are written into the register; then, the host computer software module transfers the interference data to the FPGA through DMA, and the FPGA analyzes the parameters, extracts the speed information of each interference data, and generates Doppler data. A U64 counter is used in the FPGA to control the time. According to the speed and the distance set for each interference data, the number of counts required to be delayed is calculated and added to the TOA of the pulse arrival. When the counter value reaches this value, a trigger signal is generated. The pulse I / Q data is read from the DRAM in a handshake manner and stored in the FIFO. The data in the FIFO is taken out and modulated with the Doppler data and then sent out.

[0084] Step 4: System function calibration screen is as follows Figure 6 As shown. First, use the system to generate a set of interference points to interfere with the target radar. When the interference is over, the interference data is automatically generated and saved as a virtual track data file; then, the virtual track recorded by the target radar is saved as a radar data file; secondly, after entering the calibration mode, the virtual track data file and the radar data file are imported for data comparison. The configured interference data and the data of the radar to be calibrated will be displayed in the figure according to the distance and azimuth for calibration.

[0085] Step 5: The design process of reconnaissance is as follows Figure 8 As shown in the figure: Step 51, the interference control software of the upper computer software module obtains the TOA data of the FPGA end output by the radar detection component through DMA for signal sorting; the signal sorting uses the sequence difference histogram (SDIF) algorithm with low algorithm complexity and excellent performance, which can also efficiently complete the signal sorting function in a complex electromagnetic environment; Step 52, pulse feature analysis, FPGA performs short-time Fourier transform (STFT) according to the result of signal sorting, and calculates the frequency, bandwidth, radar signal type and other parameters according to the result of STFT, puts the radar parameters into the temporary radiation source table, and continuously updates the original content according to the similar results sorted out later. The radar parameters with high recognition credibility can be stored in the radiation source library, and the original radar radiation source parameters can also be imported into the radiation source library. Supports displaying and saving PDW data. Step 53, supports selecting radar parameters in the temporary radiation source table or radiation source library to provide RF-related parameters for interference.

[0086] Step 6: Fig. 9, the interference design is divided into noise interference design, dense false target design, multi-channel target interference simulation design, sample or intermittent interference design, distance dragging design and separated target design. The interference process includes interference or reconnaissance interference; interference: manually release interference after configuring the interference parameters; reconnaissance interference: after configuring the interference parameters, reconnaissance is first carried out, and after locking the radar in the electromagnetic environment, the interference is released; among them, noise interference: through high-power emission noise interference, the radar cannot detect the real target signal normally, thereby achieving the suppression effect on the radar. Blocking interference: 200MHz bandwidth suppression interference; aiming frequency interference: ~200MHz bandwidth suppression interference; sweeping frequency interference: the center frequency changes regularly, and the bandwidth 1~200MHz suppresses interference.

[0087] Among them, step 61, the dense false target interference design process is as follows Fig.10 As shown;

[0088] First, dense false target interference can release up to 255 false targets with fixed or random amplitudes, and control the false targets to move at a certain speed and acceleration, thereby realizing the radar's anti-interference ability against dense false targets; then, the radar interference component receives parameters such as distance, speed, acceleration, power, and number of false targets configured by the upper computer software module; secondly, dense false target interference is achieved through delay, Doppler modulation, amplitude control, and pulse storage followed by repeated forwarding technology.

[0089] Among them, step 62, the multi-batch target interference simulation design process is as follows Fig.11 As shown, it includes multi-channel target interference simulation and intermittent pattern interference;

[0090] Multi-channel target interference simulation can simulate various combinations of targets and interference as well as simulation of targets plus noise; the radar jammer component receives the host computer software module to configure the distance, speed, acceleration, upper speed limit, power, noise and other parameters of each channel, and realizes multi-channel target interference simulation through delay, Doppler modulation, amplitude control, pulse storage and repeated forwarding technology, and noise generation technology.

[0091] Among them, step six three, sample or intermittent interference design process is as follows Fig.12 As shown,

[0092] Sampling or intermittent interference includes sampling interference and intermittent interference, and the two interference processes are exactly the same; first, configure the simulated target and interference parameters; then, release the target; secondly, when the target is tracked, release the sampling or intermittent interference; thirdly, the radar jamming component receives the upper computer software module to configure the distance, speed, acceleration, upper speed limit, power, acquisition form and playback times of the target and interference channel; then, the sampling or intermittent interference is realized through delay, Doppler modulation, amplitude control, and pulse storage followed by repeated forwarding technology.

[0093] Among them, step 64, the distance drag interference design process is as follows Fig.13 As shown, the premise is that when Doppler is enabled and the speed is not zero, it is a range-speed combined drag interference;

[0094] First, the distance-drag interference configures the target and interference parameters; then, by timing the release of the target and the towed interference, the target releases the towed interference regularly during movement, and repeats the process until the distance-drag interference is exited; secondly, the radar jammer receives the upper computer software module to configure the distance, speed, acceleration, upper speed limit, power, timing and other parameters of the target and interference channel; thirdly, through delay, Doppler modulation, amplitude control, and pulse store-and-forward technology, the distance-drag interference is regularly realized.

[0095] Among them, step 65, separation target interference design process is as follows Fig.14 As shown,

[0096] First, separate target interference configures target and interference parameters; then, control the release timing of sub-target interference by distance, so that the target releases sub-target interference at a designated location during movement; secondly, the radar interference component receives the distance, speed, acceleration, upper speed limit, and power parameters of the target and interference channel configured by the host computer software module, and separates target interference through delay, Doppler modulation, amplitude control, and pulse store-and-forward technology;

[0097] Step 7: Calibration design process Fig.15 As shown,

[0098] First, release a false track interference to obtain the track file detected by the radar; then, import the interference data and radar detection data respectively; finally, compare the distance and azimuth of the two data point by point to show the difference between the two data.

[0099] Each part of the present invention adopts modular pluggable functional boards and is connected through a high-speed interconnection backplane. The system's high-precision synchronization unit adopts a star clock bus and a departure bus to provide synchronization accuracy up to picoseconds. The built-in TCXO / OCXO clock source can provide a high-precision and high-stability working clock; it supports the import / export of reference clocks and triggers, making it easy to realize multi-module collaborative work.

[0100] The functions of the present invention are as follows:

[0101] 1. Radar signal reconnaissance

[0102] It can automatically receive, analyze and identify various existing radar signals in the current electromagnetic environment, analyze their time domain, frequency domain, and PDW (pulse descriptor) parameters, display the signal's PDW pulse descriptor, waveform, spectrum, antenna pattern and other information, and identify the radiation source category based on the radar parameter database.

[0103] 2. Radar jamming signal generation

[0104] According to the reconnaissance radar signal parameters, the interference target speed, acceleration, power, number of targets, track and other parameters can be set automatically or manually, and various types of radar interference signals can be generated in real time, mainly including: multi-channel target interference, intensive false target interference, suppression interference, sample interference, intermittent interference, distance towing and target separation.

[0105] 3. Radar calibration

[0106] The relative distance and azimuth are determined by using the positions of the radar and the jammer. By comparing the system interference track data and the virtual track data recorded by the radar, the theoretical distance and azimuth are compared, and the positioning and ranging performance of the radar is verified and calibrated to eliminate the zero position deviation caused by maintenance, component aging, deformation and other factors.

[0107] The invention has a jamming technology system of digital radio frequency memory (DRFM); the jamming patterns of the specific implementation of the invention can be divided into multi-channel target jamming simulation, single-channel target jamming simulation, dense false target jamming, sampling, intermittent jamming, distance dragging, target separation, and noise suppression jamming; the adapted radar signal forms include simple pulse, linear frequency modulation, nonlinear frequency modulation, and phase coding; the radio frequency technical indicators include a frequency coverage range of 20MHz~6GHz, a bandwidth ≥160MHz, a backplane data bandwidth ≥4GB / s, a backplane slot number of not less than 4, and a single slot data bandwidth of not less than 3.2GB / s , the timing and synchronization accuracy between backplane slots ≤200ps, the frequency agility time of the vector signal receiving / transmitting module is <20us, the noise floor of the vector signal receiving / transmitting module is ≤-145dBm / Hz, the power range noise floor of the vector signal receiving / transmitting module is -60dBm~10dBm, the power accuracy of the vector signal receiving / transmitting module is better than ±2dB, the vector signal receiving module has built-in FPGA and onboard memory and the onboard memory depth is greater than 1GB, the resolution is ≥14bit, the vector signal transmitting module has built-in FPGA and onboard memory and the onboard memory depth is greater than 1GB, the resolution is ≥16bit.

Claims

1. A radar signal reconnaissance and interference signal generation calibration device, characterized in that: It includes a host computer software module, an FPGA signal processing module and a vector signal transceiver module which are sequentially connected in communication; The vector signal transceiver module realizes the transceiver processing of radar signals through a circulator; A vector signal transceiver module, including a vector signal transmitting module and a vector signal receiving module; Realize signal receiving, transmitting, frequency conversion and analog-to-digital conversion functions; The vector signal receiving module includes a zero intermediate frequency receiver whose input end is communicatively connected to the circulator, and an analog-to-digital conversion module whose input end is communicatively connected to the output end of the zero intermediate frequency receiver; The vector signal transmission module includes a zero intermediate frequency transmitter whose output end is communicatively connected to the circulator and a digital-to-analog conversion module whose output end is communicatively connected to the input end of the zero intermediate frequency transmitter; The detected radar signal is received by the circulator, down-converted by the zero intermediate frequency receiver, and then sampled and stored to obtain the I / Q baseband signal; The I / Q baseband signal is converted into a digital signal through a digital-to-analog conversion module; FPGA signal processing module, used for radar reconnaissance and radar jamming signal processing, with radar detection components, radar jamming components and parameter calculation and storage modules; The radar detection component includes an input digital equalization module and a data extraction module; After digital equalization and data extraction, the digital signal is used to calculate and store radar parameters through the parameter calculation and storage module; Parameter calculation and storage module, used to calculate the radar amplitude parameters, generate antenna radiation pattern, calculate TOA parameter information, pulse information storage module, digital radio frequency memory and short-time Fourier transform module; Short-time Fourier transform module is used to determine the frequency and phase of the radar signal and transmit it to the host computer software module; The parameter calculation and storage module transmits the radar parameters to the host computer software module through the DMA channel and displays them; The host computer software module displays radar parameters and identifies the radar model. Radiation source database, connected to the host computer software module, receives external files, stores radar parameters and radar models; displays and saves pulse description word data; The host computer software module generates interference signals and interacts with the radar interference component through DMA channels and registers to control interference data; The radar jammer component includes a Doppler module, a noise generation module, a range delay module, a data difference module, and an output digital equalization module; The radar jammer generates interference data based on the interference data generated by the host computer software module. After the Doppler module performs Doppler modulation processing and the distance delay module performs delay control, the noise signal generated by the noise generation module is output to the digital-to-analog conversion module through the data difference module and the output digital equalization module to generate an analog signal. The analog signal is up-converted into a radio frequency interference signal through a zero intermediate frequency transmitter and transmitted through a circulator. Host computer software module, including PDW display, signal sorting, map generation, sorting information storage, interference data generation and radar calibration; The noise generation module releases various types of interference, including sample interference or intermittent interference, noise interference, dense false targets, multi-channel target interference simulation, distance dragging and separation targets; Radar calibration includes interference data and radar tracks; the positioning and ranging performance of the radar is verified and calibrated through azimuth and distance comparisons; The parameter calculation and storage module implements FFT operations based on Xilinx IP, and realizes digital signal processing and digital RF memory functions through custom IP; Intelligent power supply module provides corresponding power supply for each functional module; Embedded controller, using Intel's sixth-generation commercial CPU; memory supports dual-channel DDR4 memory interface; internal integrated high-speed SSD hard drive reserves at least one mSATA interface for external portable hard drive; graphics card, external display interface needs to reserve at least VGA interface and DVI interface; equipped with network card, network card supports 10 / 100 / 1000Mbps Ethernet protocol, and reserves at least one Ethernet RJ45 interface for external use; equipped with serial port and serial port communication driver protocol, the serial port adopts DB9 form; The FPGA signal processing module uses a PCIE SWITCH interconnection backplane and is connected to the embedded controller through a PCie×8 channel; it is connected to the vector signal transceiver module and the LO module of the frequency synthesizer and the clock and trigger synchronization module as the clock source and synchronization bus through a PCie×4 channel.

2. The radar signal reconnaissance and interference signal generation calibration equipment according to claim 1 is characterized in that: The vector signal transceiver module uses a VSA vector signal transceiver module based on a digital signal processor; The VSA vector signal transmission module provides spectrum measurement, demodulation, and time domain analysis functions, measuring the amplitude and phase of the input signal at a specific frequency within a specified bandwidth; VGA has a programmable FPGA carrier board, The digital signal processor provides measurement analysis in the time domain, frequency domain, modulation domain, and code domain; the VGA's FFT analysis is used to view time and frequency domain data; Digital signal processors including analog and digital modulation analysis; The vector signal receiving module adopts a VGA vector signal receiving module, which has a programmable FPGA carrier board.

3. A radar signal reconnaissance and interference signal generation calibration method, characterized in that: By means of the radar signal reconnaissance and interference signal generation calibration device according to any one of claims 1 or 2; the method steps are as follows: The detected radar signal is received by the antenna, down-converted by the zero intermediate frequency receiver, and then sampled and stored to obtain the I / Q baseband signal. After ADC, digital equalization, and data extraction, it is handed over to the FPGA signal processing module for radar pulse parameter calculation and data storage; then, the radar signal parameters are transmitted to the host computer through DMA for display, and the radar model is identified and added to the radiation source database; secondly, when the interference signal is generated, the host computer and the FPGA signal processing module interact with each other through DMA and registers to control the interference data; thirdly, the FPGA signal processing module performs delay control, amplitude and Doppler modulation processing according to the interference data generated by the host computer software, and up-converts it into a radio frequency interference signal through digital difference, digital equalization, DAC, and zero intermediate frequency transmitter, and transmits it.

4. The radar signal reconnaissance and interference signal generation calibration method according to claim 3 is characterized in that: When the host computer processes the radar signal parameters, Step 1: The host computer performs signal sorting; the basic working process of using the SDIF algorithm as the radar signal sorting algorithm is as follows; Step 1: First, read the positioning TOA sequence, the arrival sequence number is 1~P, and the span c=1; then, determine whether the number of pulses is greater than the set threshold; If no, then conduct variance analysis and enter the radar library; if yes, execute steps one and two. Step 1 and 2: First, calculate the difference between the TOA of two adjacent pulses to form the first-order difference histogram and calculate the detection threshold; then, after the sub-harmonic test, all values ​​exceeding the threshold are regarded as possible PRI values ​​for sequence retrieval; second, if the pulse sequence is successfully separated, repeat this process until all pulse trains are separated or there are pulses less than the set threshold number left; If the sequence search cannot separate the pulse sequence, the next level difference is calculated, a new threshold is set, and the whole process is repeated to complete the difference identification. Among them, the SDIF threshold is calculated as follows; D_threshold (τ)=x(Ec)e^(-τ / kN) In the formula, E is the total number of pulses; N is the total number of cells in the histogram; c is the difference series; x and k are constant coefficients, the values ​​of which are determined by experience, and the values ​​of x and k are positive numbers less than 1; Step 2: perform radar reconnaissance and sorting; The host computer software module obtains TOA data from the FPGA through DMA for signal sorting; Step 2-1: First, after completing the signal sorting through the SDIF algorithm in step 1, the parameter calculation and storage module of the FPGA performs STFT through the short-time Fourier transform module according to the signal sorting result; then, after performing the intra-pulse feature analysis, the radar signal parameters are calculated and the radar signal parameters are placed in the temporary radiation source table; secondly, for the temporary radiation source table, the radiation source library is continuously updated according to the sorted similar results, and the radar parameters with recognition credibility higher than the set threshold are stored in the radiation source library or the original radar radiation source parameters are imported into the radiation source library, and the reconnaissance sorting results are saved in the form of PDW data; Step 3: Generate interference signal using DRFM technology mechanism; First, when the system performs DRFM, after judging the arrival of the rising edge of the pulse, the I / Q data of the pulse is stored in the DRAM storage block, and the TOA and PDW of the pulse are written into the register; then, the upper computer software module transfers the interference data to the FPGA through DMA, and the FPGA analyzes the parameters, extracts the speed information of each interference data, and generates Doppler data; secondly, the FPGA uses a counter to control the time, and calculates how many counts need to be delayed according to the speed and the distance set for each interference data, and adds it to the TOA of the pulse arrival. When the counter value reaches this value, a trigger signal is generated, and the pulse I / Q data is read from the DRAM in a handshake manner and stored in the FIFO. The data in the FIFO is taken out and modulated with the Doppler data and sent out; Step 4, execute the system function calibration screen; first, use the system to generate a set of interference points to interfere with the target radar. When the interference is over, the interference data is automatically generated and saved as a virtual track data file; then, the virtual track recorded by the target radar is saved as a radar data file; secondly, after entering the calibration mode, import the virtual track data file and the radar data file for data comparison. The configured interference data and the data of the radar to be calibrated will be displayed in the figure according to the distance and azimuth for calibration; Step 5, execute the design process of reconnaissance; Step 51, first, the interference control software of the upper computer software module obtains the TOA data of the FPGA end output by the radar detection component through DMA, and performs signal sorting; then, the signal sorting uses the SDIF algorithm to complete the signal sorting function; Step 52, first, the intra-pulse feature analysis, FPGA performs STFT according to the result of signal sorting; then, according to the result of STFT, the radar parameters are calculated, the radar parameters are put into the temporary radiation source table, and the original content is continuously updated according to the similar results sorted out later; Step 53, support the selection of radar parameters in the temporary radiation source table or radiation source library, and provide RF-related parameters for interference; Step 6: Conduct interference design; Among them, step six one, first, dense false target interference releases up to 255 false targets, the false target amplitude is fixed or random, and the false target is controlled to move at a certain speed and acceleration, so as to realize the radar's anti-interference ability against dense false targets; then, the radar interference component receives the distance, speed, acceleration, power, and number of false targets parameters configured by the upper computer software module; secondly, dense false target interference is realized through delay, Doppler modulation, amplitude control, and pulse storage followed by repeated forwarding technology; Among them, step 62, performing multi-batch target interference simulation design, including multi-channel target interference simulation and intermittent pattern interference; Among them, step six three, sample or intermittent interference design process; sample or intermittent interference includes sample interference and intermittent interference, and the two interference processes are exactly the same; first, configure the simulated target and interference parameters; then, release the target; secondly, when the target is tracked, release the sample or intermittent interference; thirdly, the radar interference component receives the upper computer software module to configure the distance, speed, acceleration, upper speed limit, power, acquisition form and playback number parameters of the target and interference channel; then, the sample or intermittent interference is realized through delay, Doppler modulation, amplitude control, and repeated forwarding technology after pulse storage; Among them, step 64, distance dragging interference design, the premise is that when Doppler is enabled and the speed is not zero, it is a distance-speed combined dragging interference; First, the distance dragging interference configures the target and interference parameters; then, by timing the release of the target and the dragging interference, the target releases the dragging interference regularly during the movement, and repeats the process until the distance dragging interference is exited; secondly, the radar jamming component receives the upper computer software module to configure the distance, speed, acceleration, upper speed limit, power, and timing parameters of the target and the interference channel, and again, through delay, Doppler modulation, amplitude control, and pulse store-and-forward technology, the distance dragging interference is implemented regularly; Among them, step six and five, separation target interference design process; First, separate target interference configures target and interference parameters; then, control the release timing of sub-target interference by distance, so that the target releases sub-target interference at a designated location during movement; secondly, the radar interference component receives the distance, speed, acceleration, upper speed limit, and power parameters of the target and interference channel configured by the host computer software module, and separates target interference through delay, Doppler modulation, amplitude control, and pulse store-and-forward technology; Step 7: Calibration design process; First, release a false track interference to obtain the track file detected by the radar; then, import the interference data and radar detection data respectively; finally, compare the distance and azimuth of the two data point by point to show the difference between the two data.

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