Semiconductor package

Abstract

Provided is a semiconductor package. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal member. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure and includes connection pads. The connection metal member is disposed on the connection structure and is electrically connected to the connection pads through the connection structure. The connection via layer includes connection vias having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects the connection metal member.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0055825, filed with the Korean Intellectual Property Office on May 13, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor package. Background Art

[0003] In the field of packages, one of the main trends in recent technological developments is to reduce the size of components, and it is necessary to implement a large number of pins with a small size. According to this technical requirement, vias for a redistribution member for redistributing connection pads (pads) of a semiconductor chip can recently be formed finely.

[0004] The latest problem in packaging technology relates to the reliability of vias of a redistribution member. The vias for redistributing connection pads of a semiconductor chip become finer, such that when the vias are exposed to a harsh environment, peeling occurs at the interface of the vias or cracks often occur. Therefore, it is advantageous to minimize the structural stress applied to the vias and to minimize defects due to interface peeling or rupture. Summary of the Invention

[0005] In one aspect, there is provided a semiconductor package that can effectively reduce the structural stress of connection vias of a connection structure.

[0006] According to an aspect of an exemplary embodiment, there is provided a semiconductor package including: a connection structure having a first surface and a second surface facing away from the first surface, the connection structure including a redistribution layer and a connection via layer; a semiconductor chip disposed on the first surface of the connection structure; and a plurality of connection metal members disposed on the second surface of the connection structure, wherein the connection via layer includes a plurality of connection vias, a first connection via of the plurality of connection vias is electrically connected to a first connection metal member of the plurality of connection metal members, and in a plan view, when C1 represents the center of the first connection metal member, C2 represents the center of the first connection via, L1 represents a line passing through C1 and C2, L2 represents a line intersecting L1 and passing through C2, D1 represents a distance between two points on L1 located on the edge of the first connection via, D2 represents a distance between two points on L2 located on the edge of the first connection via, and θ1 represents an angle formed by L1 and L2, the following relationship is satisfied: D1 < D2, 30° ≤ θ1 ≤ 90°.

[0007] According to another aspect of the exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a connection structure including a redistribution layer and a connection via layer; a semiconductor chip located on the connection structure; and a plurality of connection metal members located under the connection structure. The plurality of connection metal members include a first connection metal member and a second connection metal member. Wherein, the connection via layer includes: a first connection via electrically connected to the first connection metal member; and a second connection via electrically connected to the second connection metal member. In a plan view, the length of a first line passing through the center of the first connection via and between any two points on the edge of the first connection via is longer than the length of a second line passing through the center of the first connection via and between any other two points on the edge of the first connection via. In a plan view, the length of a third line passing through the center of the second connection via and between any two points on the edge of the second connection via is longer than the length of a fourth line passing through the center of the second connection via and between any other two points on the edge of the second connection via. And in a plan view, the angle formed by the first line and a fifth line is different from the angle formed by the third line and a sixth line. The fifth line passes through the center of the first connection via and the center of the semiconductor package. The sixth line passes through the center of the second connection via and the center of the semiconductor package.

[0008] According to another aspect of the exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a connection structure including a plurality of connection via layers; a semiconductor chip located on the connection structure; and a connection metal member located under the connection structure. Wherein, at least two of the plurality of connection via layers respectively include a first connection via electrically connected to the connection metal member. In a plan view, the length of a first line passing through the center of the first connection via and between any two points on the edge of the first connection via is longer than the length of a second line passing through the center of the first connection via and between any other two points on the edge of the first connection via. And each of the first connection vias in the at least two connection via layers is vertically stacked to at least partially overlap in a plan view.

[0009] According to another aspect of the exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a connection structure including a redistribution layer and a connection via layer; a semiconductor chip disposed on the connection structure. The semiconductor chip includes connection pads; a connection metal member disposed on the connection structure and electrically connected to the connection pads through the connection structure. Wherein, the connection via layer includes a connection via having a major axis and a minor axis. And in a plan view, the minor axis of the connection via intersects the connection metal member. Description of the Drawings

[0010] The above and other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic block diagram showing an example of an electronic device system;

[0012] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0013] Figure 3A and Figure 3B are schematic cross-sectional views showing the states of a fan-in type semiconductor package before and after being encapsulated;

[0014] Figure 4 is a schematic cross-sectional view showing the encapsulation process of a fan-in type semiconductor package;

[0015] Figure 5 is a schematic cross-sectional view showing a situation where a fan-in type semiconductor package is mounted on a printed circuit board and finally mounted on the main board of an electronic device;

[0016] Figure 6 is a schematic cross-sectional view showing a situation where a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device;

[0017] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package;

[0018] Figure 8 is a schematic cross-sectional view showing a situation where a fan-out type semiconductor package is mounted on the main board of an electronic device;

[0019] Figure 9 is a cross-sectional view schematically showing an example of a semiconductor package according to an example embodiment;

[0020] Figure 10 is schematically showing according to an example embodiment Figure 9 a plan view of the arrangement of connection vias of a connection structure of a semiconductor package with respect to connection metal parts;

[0021] Figure 11 is schematically showing according to an example embodiment Figure 10 a plane partial enlarged view of region A;

[0022] Figures 12A to 12B is schematically showing according to an example embodiment for Figure 9 a plan view of pads of various shapes of connection metal parts in the bottommost redistribution layer of a connection structure;

[0023] Figures 13A to 13BSchematically shows according to an exemplary embodiment Figure 9 various examples of the shape of the connection vias of the connection structure;

[0024] Figures 14A to 14D Schematically shows according to an exemplary embodiment Figure 9 various examples of the vertical stacking shape of the connection vias of the connection structure;

[0025] Figure 15 is a cross-sectional view schematically showing another example of a semiconductor package according to an exemplary embodiment;

[0026] Figure 16 is a cross-sectional view schematically showing another example of a semiconductor package according to an exemplary embodiment; and

[0027] Figure 17 is a cross-sectional view schematically showing another example of a semiconductor package according to an exemplary embodiment. Detailed Description

[0028] Hereinafter, embodiments will be described with reference to the accompanying drawings. For clarity, the shapes and sizes of the elements in the drawings may be exaggerated or reduced.

[0029] The exemplary embodiment introduces a non-circular via as a connection via of the connection structure such that the non-circular via is arranged to satisfy a specific relationship related to connection metal parts (such as solder balls).

[0030] First, the overall environment in which semiconductor packaging technology is established and the features of various types of semiconductor packaging technology will be described with reference to the accompanying drawings.

[0031] Electronic device

[0032] Figure 1 is a schematic block diagram showing an example of an electronic device system.

[0033] Referring to Figure 1 , the electronic device 1000 may accommodate the main board 1010 therein. The main board 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. physically or electrically connected thereto. These components may be connected to other components described below through various signal lines 1090.

[0034] The chip-related components 1020 may include: memory chips such as volatile memories (e.g., dynamic random access memories (DRAM)), non-volatile memories (e.g., read-only memories (ROM)), flash memories, etc.; application processor chips such as central processors (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips such as analog-to-digital converters (ADC), application-specific integrated circuits (ASIC), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0035] The network-related components 1030 may include components operating according to protocols such as: Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long-Term Evolution (LTE), Evolution-Data Only (Ev-DO), High-Speed Packet Access+ (HSPA+), High-Speed Downlink Packet Access+ (HSDPA+), High-Speed Uplink Packet Access+ (HSUPA+), Enhanced Data rates for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 may be combined with each other together with the above chip-related components 1020.

[0036] The other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above chip-related components 1020 or network-related components 1030.

[0037] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the main board 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disc (CD) drive (not shown), a digital versatile disc (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes depending on the type of the electronic device 1000, etc.

[0038] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television set, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0039] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0040] Referring to Figure 2 , the semiconductor package may be used for various purposes in the various electronic devices 1000 as described above. For example, the printed circuit board 1110 may be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 may be physically or electrically connected to the printed circuit board 1110. In addition, other components (such as a camera module 1130) that may or may not be physically or electrically connected to the printed circuit board 1110 may be accommodated in the body 1101. Some of the electronic components 1120 may be chip-related components (e.g., the semiconductor package 1121), but are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0041] Semiconductor package

[0042] Generally, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, etc. in a packaged state.

[0043] Here, in terms of electrical connection, due to the difference in circuit width between a semiconductor chip and the main board of an electronic device, a semiconductor package is required. Specifically, the size of the connection pads (pads, or also referred to as "bonding pads") of the semiconductor chip and the pitch between the connection pads of the semiconductor chip are very small, while the size of the component mounting pads of the main board used in the electronic device and the pitch between the component mounting pads of the main board are significantly larger than the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technology for alleviating the difference in circuit width between the semiconductor chip and the main board is required.

[0044] Semiconductor packages manufactured by packaging technology can be classified into fan-in semiconductor packages and fan-out semiconductor packages according to their structures and purposes.

[0045] Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the accompanying drawings.

[0046] Fan-in semiconductor package

[0047] Figure 3A And Figure 3B are schematic cross-sectional views showing the states of the fan-in semiconductor package before and after being packaged.

[0048] Figure 4 is a schematic cross-sectional view showing the packaging process of the fan-in semiconductor package.

[0049] Referring to Figures 3A to 4 , the semiconductor chip 2220 can be, for example, an integrated circuit (IC) in a bare state. The semiconductor chip 2220 includes: a main body 2221, including silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc.; connection pads 2222, formed on one surface of the main body 2221 and including a conductive material such as aluminum (Al), etc.; and a passivation layer 2223 (such as an oxide layer, a nitride layer, etc.), formed on one surface of the main body 2221 and covering at least a part of the connection pads 2222. In this case, since the connection pads 2222 may be very small, it may be difficult to mount the integrated circuit (IC) on a printed circuit board (PCB) of medium size grade and the main board of an electronic device, etc.

[0050] Therefore, according to the size of the semiconductor chip 2220, a connection structure 2240 can be formed on the semiconductor chip 2220 to redistribute the connection pads 2222. The connection structure 2240 can be formed through the following steps: forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, forming via holes 2243h that expose the connection pads 2222, and then forming a wiring pattern 2242 and vias 2243. Then, a passivation layer 2250 that protects the connection structure 2240 can be formed, an opening 2251 can be formed, and an under-bump metal layer 2260 etc. can be formed. For example, a fan-in type semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection structure 2240, the passivation layer 2250, and the under-bump metal layer 2260 can be manufactured through a series of processes.

[0051] As described above, the fan-in type semiconductor package can have a package form in which all connection pads (e.g., input / output (I / O) terminals) of the semiconductor chip are provided inside the semiconductor chip, and can have excellent electrical characteristics and can be produced at low cost. Therefore, many components installed in smart phones have been manufactured in the form of fan-in type semiconductor packages. Specifically, many components installed in smart phones have been developed to achieve fast signal transmission while having a compact size.

[0052] However, in the fan-in type semiconductor package, since all I / O terminals need to be provided inside the semiconductor chip, the fan-in type semiconductor package has significant space limitations. Therefore, it is difficult to apply such a structure to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a compact size. In addition, due to the above disadvantages, it may not be possible to directly mount and use the fan-in type semiconductor package on the main board of an electronic device. The reason is that even though the size of the I / O terminals of the semiconductor chip and the pitch between the I / O terminals of the semiconductor chip are increased through a redistribution process, the size of the I / O terminals of the semiconductor chip and the pitch between the I / O terminals of the semiconductor chip are still not sufficient to directly mount the fan-in type semiconductor package on the main board of the electronic device.

[0053] Figure 5 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is mounted on a printed circuit board and finally mounted on the main board of an electronic device.

[0054] Figure 6 is a schematic cross-sectional view showing a case where a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device.

[0055] Refer to Figure 5, in a fan-in semiconductor package 2200, connection pads 2222 (i.e., I / O terminals) of a semiconductor chip 2220 can be redistributed through a printed circuit board 2301, and in a state where the fan-in semiconductor package 2200 is mounted on the printed circuit board 2301, the fan-in semiconductor package 2200 can be finally mounted on a main board 2500 of an electronic device. In this case, solder balls 2270 etc. can be fixed through underfill resin 2280 etc., and the outside of the semiconductor chip 2220 can be covered with a molding material 2290 etc. Optionally, referring to Figure 6 , the fan-in semiconductor package 2200 can be embedded in a separate printed circuit board 2302. In a state where the fan-in semiconductor package 2200 is embedded in the printed circuit board 2302, connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 can be redistributed through the printed circuit board 2302, and the fan-in semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

[0056] As described above, it may be difficult to directly mount and use a fan-in semiconductor package on the main board of an electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate printed circuit board and then mounted on the main board of the electronic device through a packaging process, or the fan-in semiconductor package can be mounted and used on the main board of the electronic device in a state where the fan-in semiconductor package is embedded in the printed circuit board.

[0057] Fan-out semiconductor package

[0058] Figure 7 is a schematic cross-sectional view showing a fan-out semiconductor package.

[0059] Referring to Figure 7 , in a fan-out semiconductor package 2100, for example, the outside of a semiconductor chip 2120 can be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 can be redistributed to the outside of the semiconductor chip 2120 through a connection member 2140. In this case, a passivation layer 2150 can be further formed on the connection member 2140, and an under-bump metal layer 2160 can be further formed in an opening of the passivation layer 2150. Solder balls 2170 can be further formed on the under-bump metal layer 2160. The semiconductor chip 2120 can be an integrated circuit (IC) including a main body 2121, connection pads 2122, a passivation layer (not shown), etc. The connection member 2140 can include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and vias 2143 that electrically connect the connection pads 2122 and the redistribution layer 2142 to each other.

[0060] As described above, a fan-out type semiconductor package may have a form in which I / O terminals of a semiconductor chip are redistributed through connection members formed on the semiconductor chip and are disposed outside the semiconductor chip. As described above, in a fan-in type semiconductor package, all of the I / O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the balls need to be reduced, such that a standardized ball layout may not be usable in the fan-in type semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has a form in which I / O terminals of the semiconductor chip are redistributed through connection members formed on the semiconductor chip and are disposed outside the semiconductor chip. Therefore, even when the size of the semiconductor chip is reduced, the standardized ball layout may be used as it is in the fan-out type semiconductor package, such that the fan-out type semiconductor package may be mounted on a main board of an electronic device without using a separate printed circuit board (as described below).

[0061] Figure 8 is a schematic cross-sectional view showing a situation in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

[0062] Referring to Figure 8 , the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through solder balls 2170 or the like. For example, as described above, the fan-out type semiconductor package 2100 includes a connection member 2140 that is formed on the semiconductor chip 2120 and is capable of redistributing connection pads 2122 to a fan-out region outside the size of the semiconductor chip 2120, such that a standardized ball layout may be used as it is in the fan-out type semiconductor package 2100. As a result, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device without using a separate printed circuit board or the like.

[0063] As described above, since the fan-out type semiconductor package may be mounted on the main board of the electronic device without using a separate printed circuit board, the fan-out type semiconductor package may be implemented with a thickness smaller than that of a fan-in type semiconductor package using a printed circuit board. Therefore, the fan-out type semiconductor package may be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly suitable for mobile products. Therefore, the fan-out type semiconductor package may be implemented in a form more compact than a normal package-on-package (POP) type using a printed circuit board (PCB), and problems caused by the occurrence of a warping phenomenon may be solved.

[0064] In addition, a fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on a main board of an electronic device or the like as described above and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) or the like (having different specifications, uses, etc. from those of the fan-out semiconductor package, and having a fan-in semiconductor package embedded therein).

[0065] Hereinafter, a semiconductor package according to an exemplary embodiment will be described with reference to the accompanying drawings, which can effectively reduce the structural stress of the connection vias of the connection structure.

[0066] Figure 9 is a cross-sectional view schematically showing an example of a semiconductor package according to an exemplary embodiment.

[0067] Figure 10 is schematically showing according to an exemplary embodiment Figure 9 a plan view of the arrangement of the connection vias of the connection structure of the semiconductor package with respect to the connection metal members.

[0068] Figure 11 is schematically showing according to an exemplary embodiment Figure 10 a partial enlarged plan view of region A.

[0069] Referring to Figures 9 to 11 , the semiconductor package 100A may include: a connection structure 140 having an upper surface and a lower surface facing each other; a semiconductor chip 120 disposed on the upper surface of the connection structure 140; an encapsulant 130 disposed on the upper surface of the connection structure 140 to cover at least a part of the semiconductor chip 120; a passivation layer 150 disposed on the lower surface of the connection structure 140; a plurality of under-bump metals 160 disposed in a plurality of openings of the passivation layer 150; and a plurality of connection metal members 170 connected to the plurality of under-bump metals 160. The connection structure 140 may include a plurality of insulating layers 141a, 141b, and 141c, a plurality of redistribution layers 142a, 142b, and 142c, and a plurality of connection via layers 143a, 143b, and 143c. Each of the connection via layers 143a, 143b, and 143c may include a plurality of connection vias.

[0070] At least one of the plurality of connection via layers 143a, 143b, and 143c may include a first connection via 143-1 as one of the plurality of connection vias (preferably at Figure 11(observed in the middle). The first connection via 143-1 can be electrically connected to the first connection metal part 170-1 of the plurality of connection metal parts 170. Similarly, at least one of the plurality of connection via layers 143a, 143b, and 143c can include a second connection via 143-2 that is another one of the plurality of connection vias. The second connection via 143-2 can be electrically connected to the second connection metal part 170-2 of the plurality of connection metal parts 170.

[0071] In this case, in the plan view, if C1 represents the center of the first connection metal part 170-1, C2 represents the center of the first connection via 143-1, L1 represents the line passing through C1 and C2, L2 represents the line intersecting L1 and passing through C2, D1 represents the distance between two points on L1 located on the edge of the first connection via 143-1, D2 represents the distance between two points on L2 located on the edge of the first connection via 143-1, and θ1 represents the angle formed by L1 and L2 (as Figure 11 shown in), the following relationship is satisfied: D1 < D2, and 30° ≤ θ1 ≤ 90°. In some embodiments, the relationship: 50° ≤ θ1 ≤ 90° can be satisfied. Here, the term "edge" of the first connection via 143-1 represents the entire perimeter or outer circumference of the first connection via 143-1. Similarly, in the plan view, if C3 represents the center of the second connection metal part 170-2, C4 represents the center of the second connection via 143-2, L3 represents the line passing through C3 and C4, L4 represents the line intersecting L3 and passing through C4, D3 represents the distance between two points on L3 located on the edge of the second connection via 143-2, D4 represents the distance between two points on L4 located on the edge of the second connection via 143-2, and θ2 represents the angle formed by L3 and L4 (as Figure 11 shown in), the following relationship is satisfied: D3 < D4, and 30° ≤ θ2 ≤ 90°. In some embodiments, the relationship: 50° ≤ θ2 ≤ 90° can be satisfied. Here, the term "edge" of the second connection via 143-2 represents the entire perimeter or outer circumference of the second connection via 143-2. In some embodiments, D2 can be the distance of the longest major axis among the distances between any two points on the line passing through C2 on the edge of the first connection via 143-1. In addition, in some embodiments, D4 can be the distance of the longest major axis among the distances between any two points on the line passing through C4 on the edge of the second connection via 143-2. Unless the angles θ1 and θ2 are 0° and / or 90° respectively, they can be acute angles.

[0072] Generally, the stress S applied to the first connection via 143-1 and the second connection via 143-2 may be concentrated on the surfaces facing the centers of each of the first connection metal member 170-1 electrically connected to the first connection via 143-1 and the second connection metal member 170-2 electrically connected to the second connection via 143-2 (e.g., Figure 11 the darker shaded surfaces in). Therefore, compared with the case where the stress concentration surface has a circular shape, when the area of the stress concentration surfaces of the first connection via 143-1 and the second connection via 143-2 is widened, the stress applied to the first connection via 143-1 and the second connection via 143-2 can be dispersed. For example, when the first connection via 143-1 and the second connection via 143-2 satisfy the above-mentioned relationship related to the first connection metal member 170-1 and the second connection metal member 170-2, the first connection via 143-1 and the second connection via 143-2 may have a non-circular shape, and each of the major axes of the connection vias 143-1 and 143-2 may be arranged to be substantially perpendicular to each of the center lines (e.g., L1 or L3) of the first connection metal member 170-1 and the second connection metal member 170-2. Therefore, the stress applied to the first connection via 143-1 and the second connection via 143-2 can be effectively dispersed.

[0073] On a plane, if C0 represents the center of the semiconductor package 100A (preferably observed in Figure 10 ), L5 represents the line passing through C0 and C2, L6 represents the line passing through C0 and C4, θ3 represents the angle formed by L2 and L5, and θ4 represents the angle formed by L4 and L6 (as shown in Figure 11 ), then θ3 and θ4 may be different from each other. For example, when the first connection via 143-1 and the second connection via 143-2 are arranged to satisfy the above-mentioned relationship related to the centers of the first connection metal member 170-1 and the second connection metal member 170-2 (independent of the center of the semiconductor package 100A), the stress can be effectively dispersed. Unless the angles θ3 and θ4 are 0° and / or 90° respectively, they can be acute angles.

[0074] On a plane, the first connection via 143-1 is arranged not to overlap with the first connection metal member 170-1, and the second connection via 143-2 is arranged not to overlap with the second connection metal member 170-2. In this case, the stress transmitted from the first connection metal member 170-1 and the second connection metal member 170-2 to the first connection via 143-1 and the second connection via 143-2 respectively can be reduced while being transmitted along the connection path. Therefore, the stress applied to the first connection via 143-1 and the second connection via 143-2 can be more effectively dispersed.

[0075] The first connection via 143-1 and the second connection via 143-2 may be the connection vias of at least the lowest connection via layer 143c among the multiple connection via layers 143a, 143b, and 143c. In the paths respectively electrically connected to the first connection metal member 170-1 and the second connection metal member 170-2, the vias closest to each of the first connection metal member 170-1 and the second connection metal member 170-2 being the first connection via 143-1 and the second connection via 143-2 satisfying the above relationship are more effective for the above stress dispersion effect. As described above, the first connection via 143-1 and the second connection via 143-2 can also be applied to the connection via layers 143a and 143b at different heights. That is, the above relationship can also be applied to the connection vias of the connection via layers 143a and 143b at different heights.

[0076] Not only can the relationship between the first connection via 143-1 and the second connection via 143-2 and the first connection metal member 170-1 and the second connection metal member 170-2 satisfy the above relationship exemplarily shown in Figure 10 the above, but also the relationship between other connection vias and connection metal members can satisfy the above relationship exemplarily shown in Figure 10 the above.

[0077] Hereinafter, each configuration included in the semiconductor package 100A according to the exemplary embodiment will be described in more detail.

[0078] The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. The semiconductor chip 120 may be an application processor chip (specifically, an application processor (AP)) such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processing unit (e.g., a graphics processing unit (GPU)), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, and / or a processor chip (such as a microcontroller), but is not limited thereto. The semiconductor chip 120 may be: a memory chip such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM)), a flash memory, etc.; and a logic chip such as an analog-to-digital converter, an application specific integrated circuit (ASIC), etc.

[0079] The semiconductor chip 120 can be a chip formed on the basis of an active wafer, and silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. can be used as the substrate material of the main body 121. The main body 121 can have various circuits. The connection pads 122 can be used to electrically connect the semiconductor chip 120 to other components, and the forming material of the connection pads 122 can be a metal material such as copper (Cu), aluminum (Al), etc. The passivation film 123 that exposes the connection pads 122 can be formed on the main body 121, and the passivation film 123 can be an oxide film or a nitride film, or can be a bilayer of an oxide film and a nitride film. An insulating film (not shown) etc. can be further provided in positions as required. Each of the semiconductor chips 120 can be a die. Optionally, the semiconductor chip 120 can also be a packaged chip in which a separate redistribution layer (not shown) is further formed on the surface (e.g., the active surface) on which the connection pads 122 are provided.

[0080] The encapsulant 130 can be an additional structure for protecting the semiconductor chip 120. There is no specific limitation on the encapsulation form of the encapsulant 130. For example, the encapsulant 130 can cover at least a part of the semiconductor chip 120. There is no specific limitation on the material of the encapsulant 130. For example, an insulating material can be used. A thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of a thermosetting resin or a thermoplastic resin and an inorganic filler, or a material impregnated with a core material (such as glass fiber, glass cloth or glass fabric) and an inorganic filler (such as a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used as the insulating material. Optionally, a photosensitive encapsulant (PIE) resin can be used.

[0081] The connection structure 140 can redistribute the connection pads 122. Dozens to millions of connection pads 122 with various functions can be redistributed by the connection structure 140, and can be physically connected and / or electrically connected to the outside through the connection metal parts 170 according to their functions. The connection structure 140 can include: a plurality of insulating layers 141a, 141b, and 141c; a plurality of redistribution layers 142a, 142b, and 142c provided on the plurality of insulating layers 141a, 141b, and 141c; and a plurality of connection via layers 143a, 143b, and 143c penetrating the plurality of insulating layers 141a, 141b, and 141c. The plurality of insulating layers 141a, 141b, and 141c, the plurality of redistribution layers 142a, 142b, and 142c, and the plurality of connection via layers 143a, 143b, and 143c in the connection structure 140 can be provided with a number of layers more than the number of layers shown in the drawings. Optionally, they can be designed to have a number of layers less than the number of layers shown in the drawings. That is, the number of layers has no specific limitation.

[0082] The insulating material can be used as the material for the insulating layers 141a, 141b, and 141c. In this case, in addition to the above-mentioned insulating material, a photosensitive insulating material such as a photosensitive dielectric (PID) can also be used. For example, the insulating layers 141a, 141b, and 141c can be photosensitive insulating layers respectively. When the insulating layers 141a, 141b, and 141c have photosensitivity, the insulating layers 141a, 141b, and 141c can be formed thinner, and the fine pitch of the connection via layers 143a, 143b, and 143c can be more easily achieved. When the insulating layers 141a, 141b, and 141c have multiple layers, these materials can be the same as each other or different from each other as needed. When the insulating layers 141a, 141b, and 141c have multiple layers, since they are integrated according to the process, the boundaries may not be clear, but the inventive concept is not limited thereto.

[0083] The redistribution layers 142a, 142b, and 142c can be used to substantially redistribute the connection pads 122 and can provide the above-mentioned electrical connection paths. Metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys can be used as the materials for forming the redistribution layers. The redistribution layers 142a, 142b, and 142c can also perform various functions according to the layer. For example, a ground pattern, a power pattern, a signal pattern, etc. can be included. The ground pattern can also be the same as the signal pattern. In this case, the signal pattern can include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground pattern, the power pattern, etc. In this case, the pattern can be a concept including wiring and pads.

[0084] The connection via layers 143a, 143b, and 143c can electrically connect the redistribution layers 142a, 142b, and 142c, the connection pads 122, etc. formed on different layers to form a circuit path in the connection structure 140. Metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys can be used as the materials for forming the connection via layers 143a, 143b, and 143c. The connection vias in each of the connection via layers 143a, 143b, and 143c can also be of a filled type filled with a metal material or a conformal type in which the metal material is formed along the wall surface of the via hole. In addition, the connection vias can all have a tapered cross-sectional shape.

[0085] The passivation layer 150 may be an additional structure for protecting the connection structure 140 from external physical or chemical damage, etc. The passivation layer 150 may include a thermosetting resin. For example, the passivation layer 150 may be ABF, but is not limited thereto. The passivation layer 150 may have a plurality of openings respectively exposing at least a part of the bottommost redistribution layer 142c. The number of the openings may range from dozens to millions, or more or less. Although not specifically shown in the drawings, each of the openings may be formed using a plurality of holes.

[0086] The under-bump metal 160 may be an additional structure for improving the reliability of the connection metal 170. The under-bump metals 160 may be respectively disposed in the plurality of openings in the passivation layer 150 to be electrically connected to the exposed bottommost redistribution layer 142c respectively. The under-bump metal 160 may include a metal material such as copper (Cu).

[0087] The connection metal 170 may be a structure for physically and / or electrically connecting the semiconductor package 100A to the outside. For example, the semiconductor package 100A may be mounted on the main board of an electronic device through the connection metal 170. The connection metal 170 may be disposed on the lower surface of the passivation layer 150 and may be connected to the under-bump metal 160. For example, a plurality of connection metals 170 may be electrically connected to the bottommost redistribution layer 142c exposed through the plurality of under-bump metals 160 respectively according to their functions. As a result, the plurality of connection metals 170 may be electrically connected to the connection pads 122 of the semiconductor chip 120 according to their functions. The connection metal 170 may include a low melting point metal (e.g., tin (Sn) or a tin (Sn)-containing alloy). More specifically, the connection metal 170 may be formed using solder or the like, but this is only an example and its material is not specifically limited thereto.

[0088] The connection metal 170 may be a pad, a solder ball, a pin, etc. The connection metal 170 may be formed using multiple layers or a single layer. In the case of forming using multiple layers, the connection metal 170 may include copper pillars and solder. In the case of a single layer, the connection metal 170 may include solder or copper, but this is only an example and is not limited thereto. The number, pitch, arrangement type, etc. of the connection metals 170 are not specifically limited, and those skilled in the art may modify them sufficiently according to the design specifications. For example, according to the number of the connection pads 122, the number of the connection metals 170 may range from dozens to millions, and may be more or less.

[0089] At least one of the connection metal members 170 may be disposed in the fan-out region. The fan-out region refers to a region of the semiconductor package 100A other than the region in which the semiconductor chip 120 is disposed. For example, the semiconductor package 100A according to the example may be a fan-out type semiconductor package. The fan-out package may be more reliable than the fan-in package, may have a large number of I / O terminals, and may facilitate 3D interconnection. In addition, a package thinner than a ball grid array (BGA) package, a land grid array (LGA) package, etc. may be manufactured, and may be excellent in terms of price competitiveness.

[0090] Figures 12A to 12B is a plan view schematically showing pads of various shapes of connection metal members in the bottommost redistribution layer of a connection structure for Figure 9 according to an exemplary embodiment.

[0091] Referring to Figure 12A and Figure 12B , the connection metal pad 142cP may be a shape in which no corner is formed as shown in Figure 12A , or may be a shape in which a corner is added as shown in Figure 12B . For example, the shape of the pad 142cP may be changed according to the plating process.

[0092] Figures 13A to 13B Schematically shows various examples of the shapes of connection vias of a connection structure of Figure 9 according to an exemplary embodiment.

[0093] Referring to Figures 13A to 13B , the cross-section of each of the connection vias in the connection via layers 143a, 143b, and 143c of the connection structure 140 may be an oval shape as shown in Figure 13A , or may be a snowman shape as shown in Figure 13B (i.e., as shown in Figure 13B , a shape in which two circular arcs are connected to each other and which is a cross-sectional shape similar to a gourd). For example, each of the connection vias in the connection via layers 143a, 143b, and 143c may have the shapes and arrangements of the first connection via 143-1 and the second connection via 143-2 described with reference to Figure 11 . In this case, each of the connection vias may be an oval shape or a snowman shape having a specific shape. In other words, referring to Figure 10 , each of the connection vias may have an oval shape or a snowman shape independent of the other connection vias. In other words, the exemplary embodiments shown in Figure 10 and Figure 11 are only examples, and the exemplary embodiments are not limited to the shapes and arrangements shown in Figure 10 and Figure 11 .

[0094] Figures 14A to 14D Schematically shows various examples of the vertical stacking shapes of connection vias of the connection structure according to an exemplary embodiment. Figure 9

[0095] Referring to Figures 14A to 14D , as Figure 14A shown in, the connection via layers 143a, 143b, and 143c of the connection structure 140 may be vertically stacked to at least partially overlap each other in a plane, and may include, for example, stacked vias. Optionally, as Figure 14B shown in, the connection via layers 143a, 143b, and 143c of the connection structure 140 may be vertically stacked such that their central axes are staggered with respect to each other in a plane, and may include, for example, staggered vias. Optionally, as Figure 14C and Figure 14D shown in, the connection via layers 143a, 143b, and 143c of the connection structure 140 may include a structure in which at least two of the connection via layers 143a, 143b, and 143c are vertically stacked to at least partially overlap each other and at least two of the connection via layers 143a, 143b, and 143c are vertically stacked such that their central axes are staggered with respect to each other, and may include, for example, a hybrid structure of stacked vias and staggered vias. In this case, the connection vias of each of the connection via layers 143a, 143b, and 143c having such a hybrid structure may respectively have the shape, arrangement, etc. of the first connection via 143-1 and the second connection via 143-2 described with reference to Figure 11 . For example, in the case of Figure 14A , the connection vias of the connection via layers 143a, 143b, and 143c constituting the stacked vias may respectively have the shape, arrangement, etc. of the first connection via 143-1 and the second connection via 143-2 described with reference to Figure 11 . A similar manner as above will also be applied to Figures 14B to 14D .

[0096] Figure 15 FIG. is a cross-sectional view schematically showing another example of a semiconductor package according to an exemplary embodiment.

[0097] Referring to Figure 15, the semiconductor package 100B may further include a frame 110. The frame 110 is disposed on the upper surface of the connection structure 140 and has a through portion 110H. The semiconductor chip 120 may be disposed in the through portion 110H in a face-down manner such that the surface (i.e., the effective surface) on which the connection pads 122 are provided faces the upper surface of the connection structure 140. The encapsulant 130 may cover at least a portion of each of the frame 110 and the semiconductor chip 120, and may fill at least a portion of the through portion 110H. The metal layer 115 may be disposed on the wall surface of the through portion 110H of the frame 110, and the metal layer 115 may extend to the upper and lower surfaces of the frame 110.

[0098] The frame 110 may further enhance the rigidity of the semiconductor package 100B according to the specific material of the insulating layer 111 constituting the frame 110, and may serve to ensure the uniformity of the thickness of the encapsulant 130. The frame 110 may have a through portion 110H, and the through portion 110H may be formed to penetrate the insulating layer 111 of the frame 110. The semiconductor chip 120 may be disposed in the through portion 110H, and the side surface of the semiconductor chip 120 may be surrounded by the wall surface of the through portion 110H.

[0099] An insulating material may be used as the material of the insulating layer 111. A thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of a thermosetting resin or a thermoplastic resin and an inorganic filler, or a material impregnated with a core material (such as glass fiber, glass cloth, or glass fabric) and an inorganic filler (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) may be used as the insulating material. From the perspective of warp control, prepreg may be preferably used.

[0100] The metal layer 115 may be an additional structure for heat dissipation and electromagnetic wave shielding, and may cover the entire wall surface of the through portion 110H to surround the side surface of the semiconductor chip 120. Therefore, electromagnetic wave shielding of the semiconductor chip 120 can be effectively performed, and heat generated from the semiconductor chip 120 can be effectively dissipated. The metal layer 115 may include a known metal material such as copper (Cu).

[0101] Since other specific descriptions may be substantially the same as those described in the above semiconductor package 100A, their detailed descriptions will be omitted for the sake of brevity. For example, in various exemplary embodiments, the features of the semiconductor package 100A described with reference to Figures 10 to 1 3 may be applied to the semiconductor package 100B.

[0102] Figure 16 is a cross-sectional view schematically showing another example of a semiconductor package according to an exemplary embodiment.

[0103] Reference Figure 16 , the semiconductor package 100C may have different forms of the frame 110. Specifically, in another example, the frame 110 may include: a first insulating layer 111a; a first wiring layer 112a, which is in contact with the upper surface of the connection structure 140 and embedded in the first insulating layer 111a; a second wiring layer 112b, which is disposed on the side opposite to the side of the first insulating layer 111a in which the first wiring layer 112a is embedded; a second insulating layer 111b, which is disposed on the side of the first insulating layer 111a opposite to the side in which the first wiring layer 112a is embedded, and embeds the second wiring layer 112b; a third wiring layer 112c, which is disposed on the side of the second insulating layer 111b opposite to the side in which the second wiring layer 112b is embedded; a first wiring via layer 113a, which penetrates the first insulating layer 111a to electrically connect the first wiring layer 112a and the second wiring layer 112b; and a second wiring via layer 113b, which penetrates the second insulating layer 111b to electrically connect the second wiring layer 112b and the third wiring layer 112c. The frame 110 may include the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c to simplify the structure of the redistribution layers 142a, 142b, and 142c. The wiring layers 112a, 112b, and 112c may be electrically connected to one or more connection pads 122 through the redistribution layers 142a, 142b, and 142c according to their functions.

[0104] An insulating material may be used as the material of the insulating layers 111a and 111b. A thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of a thermosetting resin or a thermoplastic resin and an inorganic filler, or a material impregnated with a core material (such as glass fiber, glass cloth, or glass fabric) and an inorganic filler (such as prepreg, ABF, FR-4, BT, etc.) may be used as the insulating material. From the perspective of warpage control, prepreg may be preferably used.

[0105] The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c, together with the first wiring via layer 113a and the second wiring via layer 113b, can provide vertical electrical connection paths in the semiconductor package 100C. Metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their alloys can be used as the materials for forming the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c, respectively. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c can also perform various functions according to the layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. The ground pattern may also be the same as the signal pattern. In this case, the signal pattern may include various signal patterns (e.g., data signal patterns, etc.) other than the ground pattern, the power pattern, etc. In this case, the pattern can be a concept including wiring and pads.

[0106] The first wiring layer 112a may be recessed into the first insulating layer 111a. For example, the surface of the first insulating layer 111a that contacts the upper surface of the connection structure 140 may have a height difference from the surface of the first wiring layer 112a that contacts the upper surface of the connection structure 140. In this case, when encapsulating the frame 110 and the semiconductor chip 120 with the encapsulant 130, it is possible to prevent the encapsulant material from oozing out and contaminating the first wiring layer 112a. The thickness of each of the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be thicker than the thickness of each of the redistribution layers 142a, 142b, and 142c.

[0107] The first wiring via layer 113a and the second wiring via layer 113b can electrically connect the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c formed on different layers, thereby forming a circuit path in the frame 110. The first wiring via layer 113a and the second wiring via layer 113b can also be formed using the above metal materials. The wiring vias in each of the first wiring via layer 113a and the second wiring via layer 113b can be of a filled type filled with a metal material, or a conformal type in which the metal material is formed along the wall surface of the via hole.

[0108] When forming a hole for the first wiring via layer 113a, a part of the pad of the first wiring layer 112a can be used as a barrier. The wiring vias of the first wiring via layer 113a can be advantageous in terms of a tapered shape in which the width of the upper surface is wider than the width of the lower surface. For example, the wiring vias of the first wiring via layer 113a can become smaller from the second wiring layer 112b toward the first wiring layer 112a. In this case, the wiring vias of the first wiring via layer 113a can be integrated with the pad pattern of the second wiring layer 112b. Similarly, when forming a hole for the second wiring via layer 113b, a part of the pad of the second wiring layer 112b can be used as a barrier. The wiring vias of the second wiring via layer 113b can be advantageous in terms of a tapered shape in which the width of the upper surface is wider than the width of the lower surface. For example, the wiring vias of the second wiring via layer 113b can become smaller from the third wiring layer 112c to the second wiring layer 112b. In this case, the wiring vias of the second wiring via layer 113b can be integrated with the pad pattern of the third wiring layer 112c.

[0109] Since other specific descriptions can be substantially the same as those described above in the semiconductor package 100A, their detailed descriptions will be omitted for the sake of brevity. For example, in various exemplary embodiments, the features described with reference to Figures 10 to 1 3 can be applied to the semiconductor package 100C.

[0110] Figure 17 is a cross-sectional view schematically showing another example of a semiconductor package according to an exemplary embodiment.

[0111] Referring to Figure 17, the semiconductor package 100D according to another example may have a frame 110 in a different form. Specifically, in another example, the frame 110 may include: a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, respectively disposed on two surfaces of the first insulating layer 111a; a second insulating layer 111b and a third insulating layer 111c, respectively disposed on two surfaces of the first insulating layer 111a and embedding the first wiring layer 112a and the second wiring layer 112b therein; a third wiring layer 112c, disposed on a side of the second insulating layer 111b opposite to the side in which the first wiring layer 112a is embedded; a fourth wiring layer 112d, disposed on a side of the third insulating layer 111c opposite to the side in which the second wiring layer 112b is embedded; a first wiring via layer 113a, penetrating through the first insulating layer 111a and electrically connecting the first wiring layer 112a and the second wiring layer 112b; a second wiring via layer 113b, penetrating through the second insulating layer 111b and electrically connecting the first wiring layer 112a and the third wiring layer 112c; and a third wiring via layer 113c, penetrating through the third insulating layer 111c and electrically connecting the second wiring layer 112b and the fourth wiring layer 112d. Since the frame 110 has a larger number of wiring layers 112a, 112b, 112c, and 112d, the connection structure 140 can be further simplified.

[0112] The first insulating layer 111a may be thicker than each of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of wiring layers 112c and 112d. Similarly, the height and average diameter of the wiring vias of the first wiring via layer 113a penetrating through the first insulating layer 111a may be greater than the height and average diameter of each of the wiring vias of the second wiring via layer 113b penetrating through the second insulating layer 111b and the wiring vias of the third wiring via layer 113c penetrating through the third insulating layer 111c. In addition, the wiring vias of the second wiring via layer 113b and the wiring vias of the third wiring via layer 113c may have tapered shapes opposite to each other, while the wiring vias of the first wiring via layer 113a may have a hourglass shape or a cylindrical shape. For example, the wiring vias in the first wiring via layer 113a may become smaller from two surfaces of the first insulating layer 111a to the inside of the wiring vias. In addition, the wiring vias of the second wiring via layer 113b may become smaller from the third wiring layer 112c to the first wiring layer 112a. In addition, the wiring vias of the third wiring via layer 113c may become smaller from the fourth wiring layer 112d to the second wiring layer 112b. The thickness of each of the first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be thicker than the thickness of each of the redistribution layers 142a, 142b, and 142c.

[0113] Since other specific descriptions may be substantially the same as those described above in semiconductor package 100A, their detailed descriptions will be omitted for the sake of brevity. For example, in various exemplary embodiments, the features described with reference to Figures 10 to 1 3 can be applied to semiconductor package 100D according to another example.

[0114] Test example

[0115] [Table 1]

[0116] <![CDATA[θ1(=θ2)]]> Stress Interface delamination Crack <![CDATA * EE1]]> 90° 0.77 Good Good EE2 70° 0.80 Good Good EE3 50° 0.83 Good Good EE4 30° 0.87 Fair Fair EE5 10° 0.90 Poor Poor EE6 0° 0.91 Poor Poor

[0117] * EE: Test Example

[0118] In Table 1 above, the stress can be a relative value measured using simulation. The term "good" refers to a situation where almost no interfacial delamination and / or cracks occur and the reliability is good; the term "fair" refers to a situation where a certain degree of interfacial delamination and / or cracks occur but are generally acceptable and the reliability is average; and the term "bad" refers to a situation where interfacial delamination and / or cracks occur causing problems and the reliability is poor.

[0119] As can be seen from Table 1 above, when θ1 and / or θ2 satisfy 30° ≤ θ1 ≤ 90° and / or 30° ≤ θ2 ≤ 90°, the stress S applied to the first connection via 143-1 and / or the second connection via 143-2 can become small enough. For example, for 50° ≤ θ1 ≤ 90° and / or 50° ≤ θ2 ≤ 90°, the stress S can become small enough to produce a "good" value. In addition, it can be seen that the reliability is relatively good, for example, almost no interfacial delamination and / or cracks occur in the first connection via 143-1 and / or the second connection via 143-2, etc.

[0120] For convenience, in this specification, words such as "lower", "lower part", "lower surface", etc. are used to represent the downward direction with respect to the cross-section of the drawing, while words such as "upper", "upper part", "upper surface", etc. are used to represent the opposite direction. It should be understood that these definitions of directions are for convenient explanation, and the scope of the claims is not specifically limited by such descriptions of directions, and the concepts of upward / downward directions can change at any time.

[0121] In this specification, the terms "connect" or "connection" can not only be direct connection, but also concepts including indirect connection through an adhesive layer or the like. In addition, in this specification, the terms "electrically connect" or "electrical connection" are concepts including both physical connection and physical disconnection. Further, in this specification, expressions such as "first", "second", etc. are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, without departing from the spirit of the present disclosure, the "first" component may be referred to as the "second" component, and similarly, the "second" component may be referred to as the "first" component.

[0122] Except for the expression "example" related to the test example, the expression "example" used in this specification does not denote the same embodiments as each other, and may be provided to emphasize and explain different unique features. However, the above examples do not exclude the case where the features of the above examples are combined with those of other examples and implemented. For example, unless otherwise described in another example or contradictory to another example, the description in a specific example, even if not described in another example, can be understood as an explanation related to another example.

[0123] The terms used in the present disclosure are merely used to illustrate various examples and are not intended to limit the inventive concept. Unless otherwise clearly specified in the context, singular expressions include plural expressions.

[0124] According to aspects of various embodiments, a semiconductor package may be provided that can effectively reduce the structural stress of the connection vias of the connection structure.

[0125] Although the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor package, comprising: A connection structure having a first surface and a second surface opposite to the first surface, the connection structure including a redistribution layer and a connection via layer; A semiconductor chip disposed on the first surface of the connection structure; And A plurality of connection metal parts disposed on the second surface of the connection structure, Wherein, the connection via layer includes a plurality of connection vias, A first connection via among the plurality of connection vias is electrically connected to a first connection metal part among the plurality of connection metal parts, and In a plan view, when C1 represents the center of the first connection metal part, C2 represents the center of the first connection via, L1 represents the line passing through C1 and C2, L2 represents the line intersecting L1 and passing through C2, D1 represents the distance between two points on L1 located on the edge of the first connection via, D2 represents the distance between two points on L2 located on the edge of the first connection via, and θ1 represents the angle formed by L1 and L2, the following relationship is satisfied: D1 < D2, 30° ≤ θ1 ≤ 90°.

2. The semiconductor package according to claim 1, wherein D2 is the distance of the longest major axis passing through C2 among the distances between any two points on the edge of the first connection via.

3. The semiconductor package according to claim 1, wherein, In a plane, the first connection via does not overlap with the first connection metal part.

4. The semiconductor package according to claim 1, wherein, A second connection via among the plurality of connection vias is electrically connected to a second connection metal part among the plurality of connection metal parts, and In a plan view, when C3 represents the center of the second connection metal part, C4 represents the center of the second connection via, L3 represents the line passing through C3 and C4, L4 represents the line intersecting L3 and passing through C4, D3 represents the distance between two points on L3 located on the edge of the second connection via, D4 represents the distance between two points on L4 located on the edge of the second connection via, and θ2 represents the angle formed by L3 and L4, the following relationship is satisfied: D3 < D4, and 30° ≤ θ2 ≤ 90°.

5. The semiconductor package according to claim 4, wherein, D4 is the distance of the longest major axis passing through C4 among the distances between any two points on the edge of the second connection via.

6. The semiconductor package according to claim 5, wherein, In a plan view, when C0 represents the center of the semiconductor package, L5 represents the line passing through C0 and C2, L6 represents the line passing through C0 and C4, θ3 represents the angle formed by L2 and L5, and θ4 represents the angle formed by L4 and L6, θ3 and θ4 are different from each other.

7. The semiconductor package according to claim 1, wherein, The connection structure includes: a plurality of insulating layers disposed at different heights of the connection structure; a plurality of redistribution layers disposed on the plurality of insulating layers; and a plurality of connection via layers, each connection via layer penetrating the corresponding insulating layer among the plurality of insulating layers.

8. The semiconductor package according to claim 7, wherein, The connection via layer closest to the second surface of the connection structure among the plurality of connection via layers includes the first connection via.

9. The semiconductor package according to claim 7, wherein, Each of the plurality of connection via layers includes the first connection via, and Each of the first connection vias in the plurality of connection via layers is vertically stacked to at least partially overlap with each other in a plane.

10. The semiconductor package according to claim 7, wherein, Each of the plurality of connection via layers includes the first connection via, and at least two of the first connection vias in the plurality of connection via layers are vertically stacked such that the central axes of the at least two first connection vias are staggered relative to each other in a plane.

11. The semiconductor package according to claim 7, wherein, The plurality of connection via layers includes at least one of stacked vias and staggered vias.

12. The semiconductor package according to claim 1, wherein, The cross-section of the first connection via has an elliptical shape or a snowman shape.

13. The semiconductor package according to claim 1, the semiconductor package further comprising: a passivation layer disposed on the second surface of the connection structure and having a plurality of openings exposing at least a portion of the redistribution layer; and a plurality of under-bump metals disposed in the plurality of openings and electrically connected to the exposed redistribution layer, wherein the plurality of connection metals are respectively connected to the plurality of under-bump metals.

14. The semiconductor package according to claim 1, wherein, Each of the plurality of connection metals includes at least one low melting point metal selected from the group consisting of tin and tin-containing alloys.

15. The semiconductor package according to claim 1, the semiconductor package further comprising: a frame disposed on the first surface of the connection structure and having a through portion, the semiconductor chip being disposed in the through portion; and a potting compound respectively covering at least a portion of each of the frame and the semiconductor chip and filling at least a portion of the through portion, wherein the semiconductor chip is disposed in the through portion such that the surface on which the connection pads are disposed is disposed to face the first surface of the connection structure.

16. The semiconductor package according to claim 15, wherein, The frame includes: a first insulating layer; a first wiring layer embedded in the first insulating layer and in contact with the first surface of the connection structure; a second wiring layer disposed on a side of the first insulating layer opposite to the side in which the first wiring layer is embedded; a first wiring via layer penetrating the first insulating layer to electrically connect the first wiring layer and the second wiring layer; a second insulating layer disposed on a side of the first insulating layer opposite to the side in which the first wiring layer is embedded, the second insulating layer embedding the second wiring layer; a third wiring layer disposed on a side of the second insulating layer opposite to the side in which the second wiring layer is embedded; and a second wiring via layer penetrating the second insulating layer to electrically connect the second wiring layer and the third wiring layer, wherein the through portion penetrates the first insulating layer and the second insulating layer, wherein the size of the wiring vias of the first wiring via layer decreases from the second wiring layer to the first wiring layer, and wherein the size of the wiring vias of the second wiring via layer decreases from the third wiring layer to the second wiring layer.

17. A semiconductor package, comprising: a connection structure including a redistribution layer and a connection via layer; a semiconductor chip located above the connection structure; and a plurality of connection metals located below the connection structure, the plurality of connection metals including a first connection metal and a second connection metal, Wherein, the connection via layer includes: a first connection via electrically connected to the first connection metal member; and a second connection via electrically connected to the second connection metal member, In a plan view, the length of a first line passing through the center of the first connection via between any two points on the edge of the first connection via is longer than the length of a second line passing through the center of the first connection via between any other two points on the edge of the first connection via, In a plan view, the length of a third line passing through the center of the second connection via between any two points on the edge of the second connection via is longer than the length of a fourth line passing through the center of the second connection via between any other two points on the edge of the second connection via, In a plan view, the angle formed by the first line and a fifth line is different from the angle formed by the third line and a sixth line, the fifth line passes through the center of the first connection via and the center of the semiconductor package, the sixth line passes through the center of the second connection via and the center of the semiconductor package, and In a plan view, when C1 represents the center of the first connection metal member, C2 represents the center of the first connection via, L1 represents the line passing through C1 and C2, L2 represents the line intersecting L1 and passing through C2, D1 represents the distance between two points on the edge of the first connection via located on L1, D2 represents the distance between two points on the edge of the first connection via located on L2, and θ1 represents the angle formed by L1 and L2, the following relationship is satisfied: D1 < D2, 30° ≤ θ1 ≤ 90°.

18. The semiconductor package according to claim 17, wherein, The first line is the distance of the longest major axis passing through the center of the first connection via among the distances between any two points on the edge of the first connection via, and The third line is the distance of the longest major axis passing through the center of the second connection via among the distances between any two points on the edge of the second connection via.

19. A semiconductor package, comprising: A connection structure including a plurality of connection via layers; A semiconductor chip located on the connection structure; And Connection metal members located under the connection structure, Wherein, at least two of the plurality of connection via layers respectively include first connection vias electrically connected to the connection metal members, In a plan view, the length of a first line passing through the center of the first connection via between any two points on the edge of the first connection via is longer than the length of a second line passing through the center of the first connection via between any other two points on the edge of the first connection via, Each of the first connection vias in the at least two connection via layers is vertically stacked to at least partially overlap in a plan view, and In a plan view, when C1 represents the center of the connecting metal part, C2 represents the center of the first connecting via hole, L1 represents the line passing through C1 and C2, L2 represents the line intersecting L1 and passing through C2, D1 represents the distance between two points on L1 located on the edge of the first connecting via hole, D2 represents the distance between two points on L2 located on the edge of the first connecting via hole, and θ1 represents the angle formed by L1 and L2, the following relationships are satisfied: D1 < D2, 30° ≤ θ1 ≤ 90°.

20. The semiconductor package according to claim 19, wherein, In a plan view, the first connecting via hole has an elliptical shape or a snowman shape.

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