Field effect transistor and cell structure with the same gate-source doping

Abstract

The present invention discloses a field effect transistor and a cell structure with the same gate-source doping, wherein the cell structure comprises: a silicon carbide substrate, the doping type of the silicon carbide substrate material is a first conductive type, and a first conductive type semiconductor epitaxial layer and a first electrode are respectively arranged on the front and back sides of the silicon carbide substrate; a second conductive type suspension area, a first conductive type gate injection area, and a first conductive type source injection area are sequentially arranged on the first conductive type semiconductor epitaxial layer, a gate is arranged on the gate injection area, a source is arranged on the source injection area, and an inter-electrode medium is arranged between the gate injection area and the source injection area, and the inter-electrode medium is used to isolate the gate and the source, wherein the contact portion between the second conductive type suspension area and the first conductive type source injection area has the same structure as the first conductive type source injection area, and both are arranged to have terminal sharp angles.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a field effect transistor and a cell structure with the same gate-source doping. Background Art

[0002] With the development and maturity of material technology, the wide bandgap characteristics of SiC materials give it higher temperature characteristics and voltage resistance characteristics, which can break through the limitations of Si-based devices. Since the performance and reliability of the SiC / SiO2 interface still need to be further improved, the SiC junction field effect transistor (JFET) device structure has received widespread attention. In addition to avoiding the problems caused by SiC / SiO2 interface defects, SiC JFET is more likely to reduce the cell size and bring lower on-resistance. Since SiO2 will excite more interface states at high temperatures, SiC JFET devices can maximize the high temperature and high pressure characteristics of SiC materials.

[0003] Traditional SiC JFET is controlled by PN junction. After the carrier flows out from the source of the device, it passes through a narrow channel area, flows into the drift region of the device, and is finally collected by the drain of the device. The device channel is controlled by two PN junctions located between the gate and the source, thereby controlling the shutdown and opening of the device. However, the P-type gate of the traditional JFET has brought many adverse effects at the device application level: First, when the device is turned on, in order to avoid the PN junction from turning on, the device gate bias voltage Vgs cannot exceed the PN junction forward turn-on voltage V F0 (Take silicon carbide as an example, V F0 =2.6V, namely Vgs <V F0 ); at the same time, if the device is of normally-on type, when the gate is turned on with zero bias, the built-in potential formed between the P-type gate and the N-type channel (hereinafter referred to as "gate built-in potential") causes a certain degree of channel depletion, resulting in a higher channel resistance; when the device is operating at a large current (near the saturation region), the gate built-in potential causes the channel to enter the pinch-off state prematurely, resulting in premature current saturation and excessive conduction loss during this operation. Summary of the invention

[0004] In view of the above technical problems, the present invention is used to provide a field effect transistor and a cell structure with the same gate-source doping.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A first aspect of the present invention provides a field effect transistor cell structure with the same gate-source doping, comprising:

[0007] A silicon carbide substrate, wherein the doping type of the silicon carbide substrate material is a first conductivity type,

[0008] A first conductive type semiconductor epitaxial layer and a first electrode are respectively provided on the front side and the back side of the silicon carbide substrate;

[0009] A second conductive type floating region, a first conductive type gate injection region, and a first conductive type source injection region are sequentially arranged on the first conductive type semiconductor epitaxial layer, a gate is arranged on the gate injection region, a source is arranged on the source injection region, and an inter-electrode medium is arranged between the gate injection region and the source injection region, and the inter-electrode medium is used to isolate the gate and the source, wherein the contact portion between the second conductive type floating region and the first conductive type source injection region has the same structure as the first conductive type source injection region, and both are arranged to have terminal sharp angles.

[0010] Preferably, the terminal tip angle is 0 to 180 degrees.

[0011] Preferably, the first conductive type semiconductor epitaxial layer has a thickness of 5 to 250 um and a doping concentration of 1×10 14 cm -3 -5×10 18 cm -3 .

[0012] Preferably, the gate injection region on one side of the cell is connected to the gate, and the gate injection region and the source injection region on the other side of the cell are commonly connected to the source.

[0013] Preferably, the doping of the first conductivity type and the second conductivity type is 1×10 14 cm -3 -2×10 21 cm -3 uniform or non-uniform doping.

[0014] Preferably, the first conductivity type is N type, and the second conductivity type is P type.

[0015] Preferably, the first conductivity type is P type, and the second conductivity type is N type.

[0016] A second aspect of an embodiment of the present invention provides a field effect transistor with the same gate-source doping, characterized in that it includes a plurality of cellular structures and field-limiting ring junction terminals as described above, and when making the junction terminals, the etching and injection of the junction terminals and the second conductive type suspension region of the cellular structure are simultaneously etched and injected using the same photolithography mask.

[0017] A third aspect of an embodiment of the present invention provides a field effect transistor with the same gate-source doping, comprising a plurality of cellular structures as described above and junction terminal extensions and field limiting ring junction terminals, and when making the junction terminals, the etching and injection of the junction terminals and the second conductive type suspension region of the cellular structure are simultaneously etched and injected using the same photolithography mask.

[0018] The present invention has the following beneficial effects:

[0019] (1) Based on the traditional JFET, a gate having a first conductivity type and a second conductivity type floating region surrounding the gate are introduced to control the device channel, which can increase the forward bias of the device gate so that Vgs can be biased at a position greater than the forward turn-on voltage of the pn junction.

[0020] (2) When Vgs = 0 V, the device on-resistance is lower because there is no reverse bias introduced by the built-in potential at the PN junction at the channel.

[0021] (3) When a large current is conducted, the device enters a saturation state and can conduct a larger current.

[0022] (4) A gate is connected to the source, so that the structure can reduce Cgd and thus reduce switching losses.

[0023] (5) By introducing the second conductive type suspension region with a terminal sharp corner, the second conductive type suspension region can be injected in two directions, thereby solving the problem of gate-source short circuit when two directions are injected. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic cross-sectional structure diagram of a field effect transistor cell structure with the same gate-source doping according to an embodiment of the present invention;

[0025] Figure 2 It is a schematic diagram of the three-dimensional structure of a second conductive type semiconductor suspension region with a terminal sharp corner in a field effect transistor cell structure with the same gate-source doping according to an embodiment of the present invention;

[0026] Figure 3 It is a schematic cross-sectional structure diagram of a second conductive type semiconductor suspension region with a terminal sharp corner in a field effect transistor cell structure with the same gate-source doping according to an embodiment of the present invention;

[0027] Figure 4 A top view of the layout of the active region of the device having a terminal sharp corner cell layout cell;

[0028] Figure 5 It is a schematic diagram of a three-dimensional structure of a field effect transistor cell structure with the same gate-source doping having a rectangular second conductivity type semiconductor suspension region in an embodiment of the present invention;

[0029] Figure 6 It is a schematic cross-sectional structure diagram of a field effect transistor cell structure with the same gate-source doping having a rectangular second conductivity type semiconductor suspension region according to an embodiment of the present invention;

[0030] Figure 7 A top view of the layout of the device active area with rectangular cells. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] See also Figure 1 The embodiment of the present invention discloses a field effect transistor cell structure with the same gate-source doping, and the figure shows a cross-sectional view of the XY plane in the spatial rectangular coordinate system, including:

[0033] A silicon carbide substrate 001, wherein the doping type of the silicon carbide substrate material is a first conductivity type,

[0034] A first conductive type semiconductor epitaxial layer 002 and a first electrode 003 are respectively provided on the front and back sides of the silicon carbide substrate 001;

[0035] A second conductive type suspension region 005, a first conductive type gate injection region 006, and a first conductive type source injection region 007 are sequentially arranged on the first conductive type semiconductor epitaxial layer 002, a gate 008 is arranged on the first conductive type gate injection region 006, a source 009 is arranged on the first conductive type source injection region 007, an inter-electrode dielectric 010 is arranged between the first conductive type gate injection region 006 and the first conductive type source injection region 007, and the inter-electrode dielectric 010 is used to isolate the gate 008 and the source 009, wherein the contact portion between the second conductive type suspension region 005 and the first conductive type source injection region 007 has the same structure as the first conductive type source injection region 007, and both are arranged to have terminal sharp angles.

[0036] For the fabrication of devices with the above cross-sectional structures, square and rectangular layouts are often used for etching and implantation, see Figures 5 to 7 , Figure 5 is the three-dimensional diagram of the smallest half-cell structure, Figure 6 is the cross-sectional view of the YZ plane, Figure 7The top view of the layout of the active area of ​​the device with rectangular cells. The cell structure of the JFET device with the above structure, this trench device introduces a gate with a first conductivity type and a second conductivity type suspension area surrounding the gate to control the channel of the device. It is necessary to perform injection in four different directions including front, back, left and right to avoid gate-source short circuit, see Figure 7 As shown, each injection can only be injected into one side of the cell. If two directions of injection (including only the front and back) are used, the first conductivity type of the device will be penetrated at the edge of the device cell, thus causing the gate-source short circuit (see Figure 6 ). In order to reduce the production cycle and cost considerations, the number of injections will need to be minimized in the actual implementation process. The embodiment of the present invention avoids this problem by introducing a cell layout structure with a terminal sharp corner in the second conductive type suspension area 005. When performing forward injection, it can be injected into the three front faces of the cell structure at the same time, and when performing backward injection, it can also be injected into the three rear faces of the cell structure at the same time. See Figure 4 As shown, the injection direction can be reduced from four directions to two directions, which can shorten the injection production cycle by half. For example, Figures 5 to 7 The structure needs to be injected in four directions, each direction takes 2 hours, and a total of 8 hours. Figures 2 to 4 The structure needs to be injected, and only the injection in the front and back directions is needed. Each direction takes 2 hours, and the total time is only 4 hours. Figures 2 to 4 , Figure 2 is the three-dimensional diagram of the smallest half-cell structure, Figure 3 is the cross-sectional view of the YZ plane, Figure 4 The top view of the layout of the active area of ​​the device with terminal sharp-cornered cells.

[0037] Furthermore, in a specific application example, the terminal sharp angle is 0 to 180 degrees.

[0038] Those skilled in the art can understand that, in some specific application examples, the first conductivity type is N type and the second conductivity type is P type. In some other application examples, the first conductivity type is P type and the second conductivity type is N type.

[0039] In a preferred application example, the doping of the first conductivity type and the second conductivity type is 1×10 14 cm -3 -2×10 21 cm -3 uniform or non-uniform doping.

[0040] In a preferred application example, the first conductive type semiconductor epitaxial layer 002 has a thickness of 5 to 250 μm and a doping concentration of 1×10 14 cm-3 -5×10 18 cm -3 .

[0041] An embodiment of the present invention provides a field effect transistor with the same gate-source doping, comprising a plurality of cellular structures and field limiting ring terminal junctions as described above, and when manufacturing the junction terminal, the etch-injection junction terminal and the second conductive type suspension region of the cellular structure are etched and injected simultaneously using the same photolithography mask.

[0042] A field effect transistor with the same gate-source doping includes several cellular structures as above and junction terminal extensions and field limiting ring junction terminals. When making the junction terminals, the etching and implantation of the junction terminals and the second conductive type suspension area of ​​the cellular structure are simultaneously etched and implanted using the same photolithography mask.

[0043] It should be understood that the exemplary embodiments described herein are illustrative rather than restrictive. Although one or more embodiments of the present invention have been described in conjunction with the accompanying drawings, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A field effect transistor cell structure having the same gate-source doping, characterized in that: include: A silicon carbide substrate (001), wherein the doping type of the silicon carbide substrate material is a first conductivity type, A first conductive type semiconductor epitaxial layer (002) and a first electrode (003) are respectively provided on the front side and the back side of the silicon carbide substrate (001); A second conductive type suspension region (005), a first conductive type gate injection region (006), and a first conductive type source injection region (007) are sequentially arranged on the first conductive type semiconductor epitaxial layer (002); a gate (008) is arranged on the first conductive type gate injection region (006); a source (009) is arranged on the first conductive type source injection region; an inter-electrode dielectric (010) is arranged between the first conductive type gate injection region (006) and the first conductive type source injection region (007); and the inter-electrode dielectric (010) is used to electrically connect the gate electrode to the first conductive type gate injection region. (008) and the source (009) are isolated, wherein the contact portion between the second conductive type suspension region (005) and the first conductive type source injection region (007) has the same structure as the first conductive type source injection region (007), and both are configured to have a terminal sharp angle, wherein the terminal sharp angle is 0 to 180 degrees; the first conductive type gate injection region (006) on one side of the cell is connected to the gate (008), and the first conductive type gate injection region (006) and the first conductive type source injection region (007) on the other side of the cell are connected to the source (009) together.

2. The field effect transistor cell structure with the same gate-source doping as claimed in claim 1, characterized in that: The first conductive type semiconductor epitaxial layer (002) has a thickness of 5 to 250 um and a doping concentration of 1×10 14 cm -3 -5×10 18 cm -3 .

3. The field effect transistor cell structure with the same gate-source doping as claimed in claim 1, characterized in that: The doping of the first conductivity type and the second conductivity type is 1×10 14 cm -3 -2×10 21 cm -3 uniform or non-uniform doping.

4. The field effect transistor cell structure with the same gate-source doping as claimed in claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

5. The field effect transistor cell structure with the same gate-source doping as claimed in claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

6. A field effect transistor having the same gate-source doping, characterized in that: It comprises a plurality of cellular structures as claimed in any one of claims 1 to 5 and field limiting ring junction terminals, and when manufacturing the junction terminals, the etching and implantation of the junction terminals and the second conductive type suspension region of the cellular structure are simultaneously performed using the same photolithography mask.

7. A field effect transistor having the same gate-source doping, characterized in that: It comprises a plurality of cellular structures as claimed in any one of claims 1 to 5, as well as junction terminal extensions and field limiting ring junction terminals, and when making the junction terminals, the etching and implantation of the junction terminals and the second conductive type suspension region of the cellular structure are simultaneously performed using the same photolithography mask.

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