A CPU network interface adaptability test board, test system and test method

Abstract

The embodiments of the present application disclose a CPU network interface adaptability test board, test system and test method, which relate to the field of board technology and are invented to reduce the test cost of the adaptability of the CPU network interface and the physical layer network chip. The CPU network interface adaptability test board includes a printed circuit board, on which a first physical layer network chip, a first gold finger and a first group of network interfaces are provided; wherein the first gold finger is connected to the first physical layer network chip, and the first physical layer network chip is connected to the first group of network interfaces. The present application is suitable for testing the adaptability of the CPU network interface and the physical layer network chip.

Description

Technical Field

[0001] The present application relates to the field of CPU testing technology, and in particular to a CPU network interface adaptability testing board, testing system and testing method. Background Art

[0002] With the technological development of CPU chip design, the high-speed interface of the CPU can be configured into different protocol types through software to achieve different interface functions. That is, the same interface can be configured as a PCIE interface, a network interface, or a SATA storage interface, etc.

[0003] In order for the CPU to accurately receive and send network data, the adaptation between the CPU network interface and the physical layer network chip plays an especially important role. In the prior art, the physical layer network chip needs to be integrated on the motherboard for relevant testing. When testing physical layer network chips of different manufacturers and models, the motherboard needs to be redesigned, and the cost of redesigning the motherboard is high, which makes the cost of testing the adaptability of the CPU network interface and the physical layer network chip high. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a CPU network interface compatibility test board, a test system and a test method, which are convenient for reducing the test cost of the compatibility of the CPU network interface and the physical layer network chip.

[0005] An embodiment of the present application provides a CPU network interface adaptability test board, including: a printed circuit board, on which a first physical layer network chip, a first gold finger and a first group of network interfaces are provided; wherein the first gold finger is connected to the first physical layer network chip, and the first physical layer network chip is connected to the first group of network interfaces.

[0006] According to a specific implementation method of the embodiment of the present application, a first system management bus is also provided on the printed circuit board, and the first physical layer network chip is connected to the first system management bus; the first system management bus is also connected to a first conversion chip, and the first conversion chip divides the first system management bus into N paths and is respectively connected to each network interface in the first group of network interfaces.

[0007] According to a specific implementation method of an embodiment of the present application, a first I / O interface chip and a second I / O interface chip are also connected to the first system management bus; the I / O interface of the first I / O interface chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of network interfaces; the I / O interface of the second I / O interface chip is connected to the LED indicator light.

[0008] According to a specific implementation method of an embodiment of the present application, the first physical layer network chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of network interfaces.

[0009] According to a specific implementation of the embodiment of the present application, a first physical layer network chip configuration unit is also provided on the printed circuit board, and the physical layer network chip configuration unit is respectively connected to the first system management bus and the physical layer network chip.

[0010] According to a specific implementation method of the embodiment of the present application, one end of the first system management bus close to the first gold finger is connected to a first jump cap optional connector; on the printed circuit board, a second jump cap optional connector and a third jump cap optional connector are arranged adjacent to the first jump cap optional connector; wherein, the second jump cap optional connector is connected to the first pin of the first gold finger, the third jump cap optional connector is connected to the second pin of the first gold finger, the first pin of the first gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the first gold finger is used to connect to the CPU on the mainboard.

[0011] According to a specific implementation method of an embodiment of the present application, a second physical layer network chip, a second gold finger, and a second group of network interfaces are provided on the printed circuit board; wherein the second gold finger is connected to the second physical layer network chip, and the second physical layer network chip is connected to the second group of network interfaces.

[0012] According to a specific implementation method of the embodiment of the present application, a second system management bus is also provided on the printed circuit board, and the second physical layer network chip is connected to the second system management bus; the second system management bus is also connected to a second conversion chip, and the second conversion chip divides the second system management bus into N paths and is respectively connected to each network interface in the second group of network interfaces.

[0013] According to a specific implementation method of an embodiment of the present application, a third I / O interface chip and a fourth I / O interface chip are also connected to the second system management bus; the I / O interface of the third I / O interface chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the second group of network interfaces; the I / O interface of the fourth I / O interface chip is connected to the LED indicator light.

[0014] According to a specific implementation method of the embodiment of the present application, one end of the second system management bus close to the second gold finger is connected to a fourth jumper optional connector; on the printed circuit board, a fifth jumper optional connector and a sixth jumper optional connector are arranged adjacent to the fourth jumper optional connector; wherein the fifth jumper optional connector is connected to the first pin of the second gold finger, the sixth jumper optional connector is connected to the second pin of the second gold finger, the first pin of the second gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the second gold finger is used to connect to the CPU on the mainboard.

[0015] According to a specific implementation manner of the embodiment of the present application, the first group of network interfaces and the second group of network interfaces are respectively a plurality of SFP+ optical module connectors arranged side by side.

[0016] The present application also provides a CPU network interface adaptability test system, comprising: a mainboard and a CPU network interface adaptability test board, wherein the mainboard is provided with a CPU chip and a PCIE slot connected to the CPU chip, and the CPU network interface adaptability test board is inserted into the PCIE slot, wherein the CPU network interface adaptability test board is the CPU network interface adaptability test board described in any of the aforementioned implementation methods.

[0017] The present application also provides a CPU network interface adaptability testing method, comprising: a CPU network interface on a mainboard sends network test data to a test board inserted in a PCIE slot on the mainboard; wherein the test board is the CPU network interface adaptability testing board described in any of the aforementioned implementations; a first physical layer network chip or a second physical layer network chip on the test board receives the network test data, converts the network test data to obtain first converted network test data, and sends the first converted network test data to the first group of network interfaces or the second network interface; the first physical layer network chip or the second physical layer network chip receives the network test data returned from the first group of network interfaces or the second group of network interfaces, and converts the returned network test data to obtain second converted network test data; the physical layer network chip sends the second converted network test data to the CPU network interface; the CPU network interface receives the second converted network test data, and determines the adaptability of the CPU network interface with the first physical layer network chip or the second physical layer network chip based on the sent network test data and the second converted network test data.

[0018] According to a specific implementation method of the embodiment of the present application, it also includes: monitoring the status information of the first group of network interfaces or the second network interface.

[0019] The embodiment of the present application provides a CPU network interface adaptability test board, test system and test method, by providing a first physical layer network chip, a first gold finger and a first group of network interfaces on the printed circuit board; wherein the first gold finger is connected to the first physical layer network chip, and the first physical layer network chip is connected to the first group of network interfaces, and the CPU and physical layer network chip adaptability test can be realized by connecting the test board of this embodiment to the corresponding pins on the mainboard. For different physical layer network chips, the board can be redesigned and manufactured according to the structure of this embodiment, so that different types of physical layer network chips can be tested without redesigning the mainboard, thereby avoiding the need to redesign the mainboard when testing different physical layer network chips and CPUs in the prior art. The cost of redesigning the mainboard is much higher than the cost of redesigning the test board of this embodiment, thereby causing the problem of high cost when testing the adaptability of the CPU network port and the physical layer network chip. Through the application of the test board of this embodiment, it is convenient to reduce the test cost of the adaptability of the CPU network interface and the physical layer network chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 This is a schematic diagram of the structure of a CPU network interface adaptability test board according to an embodiment of the present application;

[0022] Figure 2 This is a SMBus link topology diagram in a test board according to an embodiment of the present application;

[0023] Figure 3 This is a SMBus link topology diagram in a test board in another embodiment of the present application;

[0024] Figure 4 A flowchart of a CPU network interface adaptability test method according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0026] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0027] See also Figure 1 , Figure 2 and Figure 3 The CPU network interface adaptability test board of this embodiment may include: a printed circuit board 1, on which a first physical layer network chip 2, a first gold finger 3 and a first group of network interfaces 4 are provided; wherein the first gold finger 3 is connected to the first physical layer network chip 2, and the first physical layer network chip 2 is connected to the first group of network interfaces 4.

[0028] Printed circuit boards (PCB boards), also known as printed circuit boards, are providers of electrical connections for electronic components. Printed circuit boards usually refer to bare boards, that is, circuit boards without components installed.

[0029] The first physical layer network chip 2 is a physical layer network chip (PHY chip, Port Physical Laye), which can connect a data link layer device (MAC) to a physical medium, such as an optical fiber or a copper cable; the PHY chip 2 can convert data that conforms to one protocol into data that conforms to another protocol.

[0030] The first gold finger 3 may be composed of a plurality of golden conductive contacts. Because its surface is gold-plated and the conductive contacts are arranged like fingers, it is called a "gold finger" or Finger, and the conductive contacts may also be called pins. The size and shape of the gold finger may be determined according to actual conditions. In an example, the gold finger 3 is a standard PCIE Finger gold finger shape.

[0031] The conductive contact on the first gold finger 3 can also be set as a network pin to transmit high-speed network data. In an example, the network pin on the gold finger 3 can be an XGBE pin. The number of network pins can be 1, 2, 4, 7, etc., which can be determined according to actual needs.

[0032] The first group of network interfaces is used to transmit data converted by the first PHY chip 2 to an external device, or to receive data sent by an external device, and can also be used to transfer the data converted by the PHY chip 2 to the test board of this embodiment. The first group of network interfaces may include one or more than two network interfaces.

[0033] The CPU network interface can be configured to the corresponding network protocol, such as KR, SFI protocol; the compatibility of the CPU network interface and the PHY chip can be determined by network performance. Specifically, it can be divided into the following situations: 1. A compatibility test can be performed when a network interface of a CPU receives and sends data; 2. A compatibility test can also be performed when two network interfaces of a CPU receive and send data. It can be understood that to perform this test, there are at least two network interfaces on the test board of this embodiment, and these two network interfaces are respectively connected to the two network ports of the CPU; 3. A compatibility test can also be performed when a network interface of a CPU sends data and a network interface of another CPU receives data.

[0034] In this embodiment, a first PHY chip, a first gold finger and a first group of network interfaces are provided on the printed circuit board; wherein the first gold finger is connected to the first PHY chip, and the first PHY chip is connected to the first group of network interfaces. By connecting the test board of this embodiment to the corresponding pins on the mainboard, the CPU and PHY chip compatibility test can be implemented. For different PHY chips, the board can be redesigned and manufactured according to the structure of this embodiment, so that different types of PHY chips can be tested without redesigning the mainboard, thereby avoiding the need to redesign the mainboard when testing different PHY chips and CPUs in the prior art. The cost of redesigning the mainboard is much higher than the cost of redesigning the test board of this embodiment, thereby causing a high cost problem when testing the compatibility of the CPU network port and the PHY chip. Through the application of the test board of this embodiment, the test cost of the CPU network interface and the PHY chip compatibility is reduced.

[0035] In order to configure the first PHY chip conveniently and flexibly, another embodiment of the present application is basically the same as the above embodiment, except that, in the test board of this embodiment, a first system management bus is also provided on the printed circuit board 1, and the first PHY chip 2 is connected to the first system management bus; a first conversion chip 5 is also connected to the first system management bus, and the first conversion chip 5 is respectively connected to each network interface in the first group of network interfaces 4 after dividing the first system management bus into N paths.

[0036] The first system management bus (SMBus) provides a control bus for system and power management tasks. In a system using SMBus, messages are sent and received between devices through SMBus instead of using separate control lines, which saves the number of device pins. In addition, using SMBus, the device can also provide its production information, tell the system its model, part number, etc., save its status for suspend events, report different types of errors, receive control parameters, and return its status, etc.

[0037] In this embodiment, the first PHY chip 2 is connected to the first system management bus, so that the first PHY chip 2 can be easily configured through the first system management bus.

[0038] The first conversion chip 5 can divide the first system management bus into N paths, where N is greater than or equal to 2; after being divided into N paths, they are respectively connected to the corresponding network interfaces in the first group of network interfaces 4, so that when in use, the internal data of each network interface, such as the working temperature of the network interface and other information, can be easily obtained.

[0039] In one example, the first conversion chip may be a system management bus expansion chip, and the specific model may be 9546.

[0040] In order to facilitate the monitoring of the status of the first network interface and to facilitate intuitive understanding of the status of the test board, another embodiment of the present application is basically the same as the above embodiment, except that, in the test board of this embodiment, a first I / O interface chip 6 and a second I / O interface chip 7 are also connected to the first system management bus; the I / O interface of the first I / O interface chip 6 is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of network interfaces 4; the I / O interface of the second I / O interface chip 7 is connected to the LED indicator light 8.

[0041] The first I / O interface chip 6 can be a chip with input and output expansion functions, specifically a 9555 chip. The IO interface of the first I / O interface chip can be connected to the in-place (MODABS), transmit enable control (TXDIS), transmit failure indication (TXFAULT) and receive loss indication (RXLOS) signal pins of the first group of network interfaces 4 to monitor the status of the first group of network interfaces 4.

[0042] The second I / O interface chip 7 can be a chip with input and output expansion functions, specifically a 9555 chip; the I / O interface of the second I / O interface chip 7 is connected to the LED indicator light 8, and the working status of the test board can be indicated by the on and off, color of one LED indicator light or the on and off, color of more than two LED indicator lights and their different combination states, such as whether the board is working properly and what fault occurs when a fault occurs. These states can be associated with the state of the indicator light, such as green when working normally, red when abnormal, or it can flash to indicate normal, and not flash to indicate abnormal.

[0043] In order to facilitate the first PHY chip to obtain the status of the first group of network interfaces, in another embodiment of the present application, the first PHY chip 2 is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of network interfaces 4.

[0044] In order to configure the first PHY chip conveniently and flexibly, another embodiment of the present application is basically the same as the above embodiment, except that the test board of this embodiment is further provided with a PHY chip configuration unit 9 on the printed circuit board 1, and the PHY chip configuration unit 9 is respectively connected to the first system management bus and the first PHY chip.

[0045] The PHY chip configuration unit 9 can be a microcontroller unit (MCU) or an electrically erasable programmable read only memory (EEPROM), wherein EEPROM is a storage chip in which data is not lost after power failure, and test data can be stored in EEPROM so as to read test information; the PHY chip configuration unit 9 can configure the working mode of the first PHY chip 2 to realize the conversion between different protocol data, such as converting KR protocol data into SFI protocol data. When using MCU for configuration, it can be connected to the first PHY chip through the MDC / MDIO interface to configure the first PHY chip. When using EEPROM to configure the first PHY chip, the configuration information of the first PHY is stored in the EEPROM, and the first PHY chip is automatically configured after the test board is powered on.

[0046] In order to flexibly select whether the CPU or the baseboard management controller performs configuration management on the devices connected to the first system management bus, the end of the first system management bus close to the first gold finger 3 is connected to the first jump cap optional connector 10; on the printed circuit board 1, a second jump cap optional connector 11 and a third jump cap optional connector 12 are arranged adjacent to the first jump cap optional connector 10; wherein, the second jump cap optional connector 11 is connected to the first pin of the first gold finger 3, the third jump cap optional connector 12 is connected to the second pin of the first gold finger 3, the first pin 30 of the first gold finger 3 is used to connect to the baseboard management controller on the mainboard, and the second pin 32 of the first gold finger 3 is used to connect to the CPU on the mainboard.

[0047] The PCIE Finger standard defines only one set of SMBUS signals, which can be connected to the CPU or the BMC. There are also multiple reserved (RSVD) but undefined pins on the PCIE Finger, and some motherboards define some RSVD pins as SMBUS. In one example, the first pin and the second pin on the test board of this embodiment define the RSVD pin on the gold finger as SMBUS signal pins.

[0048] The first jump cap optional connector 10, the second jump cap optional connector 11 and / or the second jump cap optional connector 12 may be 3-pin connectors.

[0049] The Baseboard Manager Controller (BMC) has monitoring and control functions. It operates on system hardware, such as monitoring the system's temperature, voltage, fan, power supply, etc., and making corresponding adjustments to ensure that the system is in a healthy state. It can also record various hardware information and log records to prompt users and locate subsequent problems; BMC is an independent system that does not rely on other hardware on the system (such as CPU, memory, etc.), nor does it rely on BIOS, OS, etc. (but BMC can interact with BIOS and OS, which can play a better role in platform management. There is system management software under OS that can work with BMC to achieve better management results).

[0050] The test board of this embodiment can be in the form of a PCIE plug-in card. In order to facilitate application inside a standard chassis, the test board of this embodiment can be designed according to the standard PCIE card size, such as the same size as a standard PCIE full-height half-length card. Further, in order to save costs, the compatibility test of two PHY chips and CPU network ports can be performed on one test board. See Figure 1, an embodiment of the present application is basically the same as the above embodiment, except that a second PHY chip 13, a second gold finger 14 and a second group of network interfaces 15 are provided on the printed circuit board; wherein the second gold finger 14 is connected to the second PHY chip 13, and the second PHY chip 13 is connected to the second group of network interfaces 15. The first group of network interfaces 4 and the second group of network interfaces 15 are respectively a plurality of SFP+ optical module connectors arranged side by side.

[0051] The SFP+ optical module is an enhanced small pluggable transceiver optical module. The SFP+ optical module has an interface for plugging in an optical cable, and an optical cable can be inserted into the interface to perform CPU port and PHY chip adaptability testing.

[0052] The first gold finger 3 and the second gold finger 14 may be the same gold finger. In this case, a jumper cap optional connector is provided between the gold finger and the first PHY chip 2 , and between the gold finger and the second PHY chip 13 .

[0053] In order to configure the second PHY chip 13 conveniently and flexibly, another embodiment of the present application is basically the same as the above embodiment, except that the test board of this embodiment is further provided with a second system management bus on the printed circuit board 1, and the second PHY chip 13 is connected to the second system management bus;

[0054] The second system management bus is also connected to a second conversion chip 16. The second conversion chip 16 divides the second system management bus into N paths and is respectively connected to each network interface in the second group of network interfaces.

[0055] The second system management bus (SMBus) provides a control bus for system and power management tasks. In systems using SMBus, messages are sent and received between devices through SMBus instead of using separate control lines, which saves the number of device pins. In addition, using SMBus, the device can also provide its production information, tell the system its model, part number, etc., save its status for suspend events, report different types of errors, receive control parameters, and return its status, etc.

[0056] In this embodiment, the second PHY chip 13 is connected to the second system management bus, so that the first PHY chip 2 can be configured through the second system management bus.

[0057] The second conversion chip 16 can divide the second system management bus into N paths, where N is greater than or equal to 2; after being divided into N paths, they are respectively connected to the corresponding network interfaces in the second group of network interfaces 15, so that when in use, the internal data of each network interface, such as the working temperature of the network interface and other information, can be easily obtained.

[0058] In one example, the second conversion chip 16 may be a system management bus expansion chip, and the specific model may be 9546.

[0059] In order to facilitate the monitoring of the status of the first network interface and to facilitate intuitive understanding of the status of the test board, another embodiment of the present application is basically the same as the above embodiment, except that, in the test board of this embodiment, a third I / O interface chip 17 and a fourth I / O interface chip 18 are also connected to the second system management bus; the I / O interface of the third I / O interface chip 17 is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the second group of network interfaces 15; the I / O interface of the fourth I / O interface chip 18 is connected to the LED indicator light 19.

[0060] The third I / O interface chip 17 can be a chip with input and output expansion functions, specifically a 9555 chip. The IO interface of the third I / O interface chip 17 can be connected to the in-position (MODABS), transmit enable control (TXDIS), transmit failure indication (TXFAULT) and receive loss indication (RXLOS) signal pins of the second group of network interfaces 15 to monitor the status of the second group of network interfaces 15.

[0061] The fourth I / O interface chip 18 can be a chip with input and output expansion functions, specifically a 9555 chip; the I / O interface of the fourth I / O interface chip 18 is connected to the LED indicator light 19, and the working status of the test board can be indicated by the on and off, color of one LED indicator light or the on and off, color of more than two LED indicator lights and their different combination states, such as whether the board is working properly and what fault occurs when a fault occurs. These states can be associated with the state of the indicator light, such as green when working normally, red when abnormal, or flashing to indicate normal, and non-flashing to indicate abnormal.

[0062] In order to flexibly select whether the CPU or the baseboard management controller performs configuration management on the devices connected to the second system management bus, the end of the second system management bus close to the second gold finger 14 is connected to the fourth jumper optional connector 20; on the printed circuit board 1, a fifth jumper optional connector 21 and a sixth jumper optional connector 22 are arranged adjacent to the fourth jumper optional connector 20; wherein the fifth jumper optional connector 21 is connected to the first pin 140 of the second gold finger 14, the sixth jumper optional connector 22 is connected to the second pin 142 of the second gold finger 14, the first pin 140 of the second gold finger 14 is used to connect to the baseboard management controller on the mainboard, and the second pin 142 of the second gold finger 14 is used to connect to the CPU on the mainboard.

[0063] The fourth jumper optional connector 20, the fifth jumper optional connector 21 and / or the sixth jumper optional connector 22 may be 3-pin connectors.

[0064] See also Figure 1 , an embodiment of the present application also provides a CPU network interface adaptability test system, including: a mainboard and a CPU network interface adaptability test board, the mainboard is provided with a CPU chip and a PCIE slot connected to the CPU chip, the CPU network interface adaptability test board is inserted in the PCIE slot, wherein the CPU network interface adaptability test board is the CPU network interface adaptability test board described in the aforementioned embodiment.

[0065] The motherboard is also called the mainboard, system board, or motherboard. The motherboard is generally a rectangular circuit board on which the main circuit systems that make up the computer are installed, generally including the BIOS chip, I / O control chip, keyboard and panel control switch interface, indicator light connectors, expansion slots, DC power supply connectors for the motherboard and plug-in cards, and CPU chip sockets; the CPU is installed in the CPU chip socket.

[0066] In one example, a PCIE slot on a motherboard has a configurable XGBE network interface.

[0067] In this embodiment, a CPU chip and a PCIE slot connected to the CPU chip are provided on the mainboard, and the CPU network interface adaptability test board is inserted into the PCIE slot, wherein the CPU network interface adaptability test board is the CPU network interface adaptability test board in any of the aforementioned embodiments, and can test the CPU network interface on the mainboard and the PHY chip on the test board, and can use the existing mainboard. When testing different PHY chips, there is no need to redesign the mainboard, which avoids the need to redesign the mainboard when testing different PHY chips and CPUs in the prior art. The cost of redesigning the mainboard is much higher than that of redesigning the test board in this embodiment, thereby causing the problem of high cost when testing the adaptability of the CPU network port and the PHY chip. Through the application of the test board in this embodiment, the cost of CPU network port and PHY chip adaptability testing can be reduced.

[0068] See also Figure 4 , the embodiment of the present application also provides a CPU network interface adaptability testing method, including:

[0069] Step 101, the CPU network interface on the mainboard sends network test data to a test board inserted into a PCIE slot on the mainboard; wherein the test board is the CPU network interface adaptability test board in the aforementioned embodiment.

[0070] The CPU network interface may be a CPU port configured with a network protocol; the network test data may include multiple data packets; the network test data sent by the CPU network interface of this embodiment may be data sent at a certain rate, such as XGBE, such as 1G, 10G, etc.

[0071] Step 102: The first physical layer network chip on the test board receives the network test data, converts the network test data to obtain first converted network test data, and sends the first converted network test data to the first group of network interfaces.

[0072] The first physical layer network chip is a physical layer network chip (PHY chip, Port Physical Laye), which can connect a data link layer device (MAC) to a physical medium, such as optical fiber or copper cable; the PHY chip can convert data that conforms to one protocol into data that conforms to another protocol. For example, the CPU network interface sends data that conforms to the KR protocol, which can be converted into data that conforms to another protocol through the PHY chip so that the data can be transmitted to an external device.

[0073] Step 103: The first PHY chip receives the network test data returned from the first group of network interfaces, and converts the returned network test data to obtain second converted network test data.

[0074] Step 104: The first PHY chip sends the second converted network test data to the CPU network interface.

[0075] Step 105: The CPU network interface receives the second converted network test data, and determines the compatibility of the CPU network interface with the first PHY chip according to the sent network test data and the second converted network test data.

[0076] Network performance indicators, such as bit error rate, delay and / or packet loss rate, etc., can be determined based on the sent network test data and the second converted network test data, and then the compatibility of the CPU network interface with the first PHY chip can be determined based on the network performance indicators.

[0077] In an example, the network test data sent by the CPU and the second converted network test data can be used to calculate the bit error rate and / or packet loss rate to determine the compatibility of the CPU network interface with the first PHY chip. Specifically, if the packet loss rate is less than a certain threshold, the CPU network interface and the first PHY chip are compatible; if the packet loss rate is greater than a certain threshold, the CPU network interface and the first physical layer network chip are less compatible, and the possible reason is that the performance of the first PHY chip is relatively low; or, if the bit error rate is less than a certain threshold, the CPU network interface and the first physical layer network chip are compatible; if the bit error rate is greater than a certain threshold, the CPU network interface and the first PHY chip are less compatible, and the possible reason is that the performance of the first PHY chip is relatively low.

[0078] Another embodiment of the present application is basically the same as the above embodiment, except that, after the CPU network interface on the mainboard sends the network test data to the test board inserted in the PCIE slot on the mainboard, the method of the present embodiment further includes: recording the first moment when the CPU network interface on the mainboard sends the network test data to the test board inserted in the PCIE slot on the mainboard;

[0079] After the CPU network interface receives the second conversion network test data, the method further includes: recording a second time at which the CPU network interface receives the second conversion network test data.

[0080] The compatibility of the CPU network interface with the first PHY chip is determined according to the first moment and the second moment.

[0081] In order to monitor the network interface when performing the CPU network interface and PHY chip compatibility test, the method of this embodiment further includes: monitoring the status information of the first group of network interfaces or the second network interface.

[0082] The above takes the first PHY chip and the first group of network interfaces as an example to illustrate the compatibility test between the CPU network interface and the first PHY chip. It can be understood that the above method is also applicable to the compatibility test between the second PHY chip and the second group of network interfaces and the CPU network interface and the second PHY chip.

[0083] The in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the first group of network interfaces or the second network interface can be monitored, and the internal state of the first group of network interfaces or the second network interface can also be monitored; specifically, it can be monitored through the first PHY chip or the second PHY chip, and it can also be monitored through the first conversion chip or the second conversion chip.

[0084] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0085] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0086] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A CPU network interface adaptability test board, characterized in that: include: A printed circuit board, on which a first physical layer network chip, a first gold finger and a first group of network interfaces are provided; wherein the first gold finger is connected to the first physical layer network chip, and the first physical layer network chip is connected to the first group of network interfaces; and the first gold finger is in the form of a standard PCIE Finger gold finger; A first system management bus is also provided on the printed circuit board, and the first physical layer network chip is connected to the first system management bus; The first system management bus is also connected to a first conversion chip, which divides the first system management bus into N paths and respectively connects to each network interface in the first group of network interfaces; wherein N is greater than or equal to 2.

2. The test board according to claim 1, characterized in that: The first system management bus is also connected to a first I / O interface chip and a second I / O interface chip; The I / O interface of the first I / O interface chip is connected to a presence signal terminal, a transmission enable control signal terminal, a transmission failure indication signal terminal, and / or a reception loss indication signal terminal of the first group of network interfaces; The I / O interface of the second I / O interface chip is connected to the LED indicator light.

3. The test board according to claim 1, characterized in that: The first physical layer network chip is connected to a presence signal terminal, a transmission enable control signal terminal, a transmission failure indication signal terminal, and / or a reception loss indication signal terminal of the first group of network interfaces.

4. The test board according to claim 1, characterized in that: A first physical layer network chip configuration unit is also provided on the printed circuit board, and the physical layer network chip configuration unit is respectively connected to the first system management bus and the physical layer network chip.

5. The test board according to claim 1, characterized in that: An end of the first system management bus close to the first gold finger is connected to a first jumper cap optional connector; On the printed circuit board, a second jumper cap optional connector and a third jumper cap optional connector are arranged adjacent to the first jumper cap optional connector; wherein the second jumper cap optional connector is connected to the first pin of the first gold finger, and the third jumper cap optional connector is connected to the second pin of the first gold finger, the first pin of the first gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the first gold finger is used to connect to the CPU on the mainboard.

6. The test board according to claim 1, characterized in that: A second physical layer network chip, a second gold finger and a second group of network interfaces are arranged on the printed circuit board; wherein the second gold finger is connected to the second physical layer network chip, and the second physical layer network chip is connected to the second group of network interfaces.

7. The test board according to claim 6, characterized in that: A second system management bus is also provided on the printed circuit board, and the second physical layer network chip is connected to the second system management bus; The second system management bus is also connected to a second conversion chip. The second conversion chip divides the second system management bus into N paths, and the N paths are respectively connected to the network interfaces in the second group of network interfaces.

8. The test board according to claim 7, characterized in that: The second system management bus is also connected to a third I / O interface chip and a fourth I / O interface chip; The I / O interface of the third I / O interface chip is connected to the in-place signal terminal, the transmission enable control signal terminal, the transmission failure indication signal terminal, and / or the reception loss indication signal terminal of the second group of network interfaces; The I / O interface of the fourth I / O interface chip is connected to the LED indicator light.

9. The test board according to claim 7, characterized in that: An end of the second system management bus close to the second gold finger is connected to a fourth jumper optional connector; On the printed circuit board, a fifth jumper optional connector and a sixth jumper optional connector are arranged adjacent to the fourth jumper optional connector; wherein the fifth jumper optional connector is connected to the first pin of the second gold finger, and the sixth jumper optional connector is connected to the second pin of the second gold finger, the first pin of the second gold finger is used to connect to the baseboard management controller on the mainboard, and the second pin of the second gold finger is used to connect to the CPU on the mainboard.

10. The test board according to claim 6, characterized in that: The first group of network interfaces and the second group of network interfaces are respectively a plurality of SFP+ optical module connectors arranged side by side.

11. A CPU network interface adaptability testing system, characterized in that: include: A mainboard and a CPU network interface adaptability test board, wherein the mainboard is provided with a CPU chip and a PCIE slot connected to the CPU chip, and the CPU network interface adaptability test board is inserted into the PCIE slot, wherein the CPU network interface adaptability test board is the CPU network interface adaptability test board as described in any one of claims 1 to 10.

12. A CPU network interface adaptability testing method, characterized in that: include: The CPU network interface on the mainboard sends network test data to a test board inserted in a PCIE slot on the mainboard; wherein the test board is the CPU network interface adaptability test board according to any one of claims 1 to 10; The first physical layer network chip on the test board receives the network test data, converts the network test data to obtain first converted network test data, and sends the first converted network test data to the first group of network interfaces; The first physical layer network chip receives the network test data returned from the first group of network interfaces, and converts the returned network test data to obtain second converted network test data; The first physical layer network chip sends the second conversion network test data to the CPU network interface; The CPU network interface receives the second converted network test data, and determines the compatibility of the CPU network interface with the first physical layer network chip according to the sent network test data and the second converted network test data.

13. The testing method according to claim 12, characterized in that: Also includes: Monitor status information of the first group of network interfaces.

14. A CPU network interface adaptability testing method, characterized in that: include: The CPU network interface on the mainboard sends network test data to a test board inserted in a PCIE slot on the mainboard; wherein the test board is the CPU network interface adaptability test board according to any one of claims 6 to 10; The second physical layer network chip on the test board receives the network test data, converts the network test data to obtain first converted network test data, and sends the first converted network test data to the second group of network interfaces; The second physical layer network chip receives the network test data returned from the second group of network interfaces, and converts the returned network test data to obtain second converted network test data; The second physical layer network chip sends the second conversion network test data to the CPU network interface; The CPU network interface receives the second converted network test data, and determines the compatibility of the CPU network interface with the second physical layer network chip according to the sent network test data and the second converted network test data.

15. The testing method according to claim 14, characterized in that: Also includes: Monitor status information of the second group of network interfaces.

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