Application processor, system-level chip, and method for operating memory management unit

Abstract

The present invention provides an application processor, a system-level chip, and a method for operating a memory management unit. The memory management unit in the application processor responds to an access request corresponding to a check request. The memory management unit includes a context cache, a translation cache, an invalidation queue, and an address translation manager. The context cache stores a context and an identifier of the stored context while avoiding duplication of the context. The translation cache stores a first address, a first context identifier, and a second address, the first address corresponds to a virtual address, the first context identifier corresponds to a first context, and the second address corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated among the context identifiers stored in the translation cache. The address translation manager controls the context cache, the translation cache, and the invalidation queue.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to a processor, and more particularly, to an application processor, a system-on-chip including the application processor, and a method of operating a memory management unit included in the application processor. Background Art

[0002] A memory management unit (MMU) is a hardware component that processes memory access requests issued by a direct memory access unit (eg, a central processing unit (CPU)). An MMU may also be referred to as a paged MMU (PMMU).

[0003] Generally, the MMU initially attempts to translate a virtual page address into a physical page address of a memory (e.g., instruction memory) using an associated cache called a Translation Lookaside Buffer (TLB). If a physical page address matching the virtual page address is not allocated in the TLB, the TLB performs a slower process of referencing a page table to determine the necessary physical page address. This can delay the MMU's channel activity. Summary of the invention

[0004] According to an exemplary embodiment of the inventive concept, an application processor includes a memory management unit (MMU). The MMU responds to an access request received from a master intellectual property (IP), and the access request includes a target context and a target virtual address. The access request corresponds to a check request to convert the target virtual address into a first target physical address. The MMU includes a context cache, a translation cache, an invalidation queue, and an address translation manager (ATM). The context cache stores a context and a context identifier of the stored context as a first tag and a first data, respectively, while avoiding duplication of the context, and the context is used in the check request. The translation cache stores a first address and a first context identifier as a second tag and stores a second address as a second data, the first address corresponding to a virtual address used in the check request, the first context identifier corresponding to a first context used in the check request, and the second address corresponding to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated among the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache, and the invalidation queue.

[0005] According to an exemplary embodiment of the inventive concept, a system-on-chip includes a master intellectual property (IP) that outputs an access request, an application processor, and a memory device. The application processor includes a memory management unit (MMU), and the MMU converts the target virtual address into a first target physical address in response to the access request including a target context and a target virtual address. The memory device is coupled to the MMU and includes a page table that stores mapping information between a virtual address and a first physical address. The MMU includes a context cache, a translation cache, an invalidation queue, and an address translation manager (ATM). The context cache stores a context and a context identifier (ID) of the stored context as a first tag and first data, respectively, while avoiding duplication of the context, and the context is used in the access request corresponding to a check request. The translation cache stores a first address and a first context identifier as a second tag and stores a second address as second data, the first address corresponding to a virtual address used in the check request, the first context identifier corresponding to a first context used in the check request, and the second address corresponding to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated among the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache, and the invalidation queue.

[0006] According to an exemplary embodiment of the inventive concept, in a method of operating a memory management unit (MMU) of an application processor, an access request is received by an address translation manager (ATM), the access request including a target context and a target virtual address. The ATM determines whether the target context matches at least one first entry in a first table entry in the context cache by checking a context cache, and the context cache stores a context and a context identifier of the stored context as a first tag and first data, respectively, while avoiding duplication of the context. The ATM determines whether a target context identifier corresponding to the target context matches at least one second entry in a second table entry in the translation cache by selectively checking a translation cache based on the checking of the context cache, and the translation cache stores the context identifier and a virtual address corresponding to the context identifier as a second tag and stores a physical address corresponding to the virtual address as second data. The target virtual address corresponding to the target physical address is converted into a corresponding target physical address based on the selective determination.

[0007] Therefore, the MMU in the application processor according to an exemplary embodiment can convert a virtual address into a physical address by mainly checking the context cache, which stores contexts, and selectively checking the translation cache based on the result of checking the context cache, while avoiding copying the contexts. Therefore, the size of the translation cache can be reduced. In addition, the performance of the application processor can be enhanced by processing the invalidation request when the invalidation request specifies context-based invalidation without using the translation cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0009] Figure 1 is a diagram of a system-on-chip (SoC) including a memory management unit (MMU) according to an exemplary embodiment.

[0010] Figure 2 is a diagram showing an exemplary embodiment Figure 1 A block diagram of an example of an application processor in FIG.

[0011] Figure 3 is a diagram showing the mapping between virtual addresses and physical addresses.

[0012] Figure 4A is used to explain the exemplary embodiment Figure 1 Diagram of the operation of the MMU.

[0013] Figure 4B According to an exemplary embodiment Figure 4A An instance of the translation cache in .

[0014] Figure 4C According to an exemplary embodiment Figure 4B An instance of the translation cache in .

[0015] Figure 4D According to an exemplary embodiment Figure 4B Another example of a translation cache in .

[0016] Figure 5 is a diagram showing an exemplary embodiment Figure 1 Block diagram of the MMU in the SoC shown.

[0017] Fig. 6A and Figure 6B According to exemplary embodiments, Figure 5 Part of the MMU in.

[0018] Figure 7 is a diagram showing an exemplary embodiment Figure 5 Flowchart of exemplary operation of the MMU in FIG.

[0019] Figure 8 It is used to explain Figure 7 Graph of the operations in .

[0020] Fig. 9A is a diagram showing an exemplary embodiment Figure 5 Flowchart of another exemplary operation of the MMU in .

[0021] Fig. 9B is a diagram showing an exemplary embodiment Figure 5 Flowchart of another exemplary operation of the MMU in .

[0022] Fig.10 Shown in Figure 7 A new context identifier is assigned in .

[0023] Fig.11 It is implemented Fig.10 Example operation of the MMU in operation.

[0024] Fig.12 According to an exemplary embodiment, Figure 7 A new context identifier is assigned in .

[0025] Fig.13A is a flow chart illustrating an exemplary method of invalidating entries in a context cache in an MMU according to an exemplary embodiment.

[0026] Fig. 13B is a flow chart illustrating an exemplary method of invalidating entries in a translation cache in an MMU according to an exemplary embodiment.

[0027] Fig.14 is a flow chart illustrating another exemplary method of invalidating entries in a translation cache in an MMU according to an exemplary embodiment.

[0028] Fig.15 According to an exemplary embodiment Figure 1 Another example of an application processor in a SoC.

[0029] Fig.16 is a diagram showing an exemplary embodiment Fig.15 A block diagram of an example of an MMU module in FIG.

[0030] Fig.17 According to an exemplary embodiment Fig.16 An instance of the address allocator in .

[0031] Fig.18 It is used to explain Fig.16 A conceptual diagram of the operation of the MMU module in FIG.

[0032] Fig.19 is a flowchart illustrating a method of operating an MMU in an application processor according to an exemplary embodiment.

[0033] Fig. 20 is a block diagram of a mobile device including a SoC according to an exemplary embodiment.

[0034] [Explanation of Symbols]

[0035] 10. 910: System-on-Chip (SoC);

[0036] 20: Display;

[0037] 30: memory device;

[0038] 40: page table;

[0039] 45: data / instruction storage block;

[0040] 50: input device;

[0041] 100, 100a, 920: application processor;

[0042] 110: Central Processing Unit (CPU);

[0043] 120: System peripheral circuit;

[0044] 121: Real-time clock (RTC);

[0045] 123: Phase-locked loop (PLL);

[0046] 125: watchdog timer;

[0047] 130: multimedia accelerator;

[0048] 131: Camera interface;

[0049] 133: Graphics engine;

[0050] 135: High Definition Multimedia Interface;

[0051] 140: Connect the circuit;

[0052] 141: audio interface;

[0053] 143: storage interface;

[0054] 145: connection interface;

[0055] 150: display controller;

[0056] 160: memory controller;

[0057] 170: cache;

[0058] 180: system bus;

[0059] 190: Master Intellectual Property (IP);

[0060] 200: Memory Management Unit (MMU);

[0061] 200a: Memory Management Unit (MMU) module;

[0062] 210, CC1, CC2, CCk: context cache;

[0063] 211, 217, 219a, 221, 251: Tag field;

[0064] 213, 219, 219b, 223, 253: data field;

[0065] 215: Translation Lookaside Buffer (TLB) / Traditional TLB;

[0066] 218, 218a, 218b, TC1, TC2, TCk: conversion cache;

[0067] 220: Translation Lookaside Buffer (TLB);

[0068] 230, IQ1, IQ2, IQk: invalidation queue;

[0069] 240: page table walker;

[0070] 250: walking cache;

[0071] 260: Address Translation Manager (ATM);

[0072] 261: first interface;

[0073] 263: Second interface;

[0074] 265: control register;

[0075] 267: storage interface;

[0076] 270: address allocator;

[0077] 271: register group;

[0078] 273: address comparator;

[0079] 275: first bus interface;

[0080] 281: Memory Management Unit (MMU) / MMU1;

[0081] 282: Memory Management Unit (MMU) / MMU2;

[0082] 28k: Memory Management Unit (MMU) / MMUk;

[0083] 290: second bus interface;

[0084] 900: mobile device;

[0085] 930: wide input and output memory;

[0086] 940: Low power double rate data x memory device;

[0087] 950: Image sensor;

[0088] 960: Display;

[0089] ASID: Address space identifier;

[0090] AT: authority information;

[0091] CID, CID1, CID11, CID12, CID13, CID14, CID1_a, CID1_b: context identifier;

[0092] CTL: control signal;

[0093] CTX11, CTX12: context;

[0094] DTA: data;

[0095] EL: exception level field;

[0096] FN: frame number;

[0097] FN0, FN1, FNn: frame;

[0098] FN2: frame / frame number;

[0099] INST: instruction;

[0100] MMU1~MMUk: memory management unit (MMU);

[0101] MMU_ID, ID1, ID2, IDk: Memory Management Unit (MMU) identity;

[0102] NS: non-security field;

[0103] OFF2: offset;

[0104] PA, PA1, PA11, PA12, PA13, PA1_a, PA1_b, PA1_c, PA1_d: physical address;

[0105] PA2: physical address / second physical address;

[0106] PN0, PN1, PN3, PN4, PNn: pages;

[0107] PN: page number;

[0108] PN2: page / page number;

[0109] pVA, pVA11, pVA12, pVA13: local virtual address;

[0110] REQ: access request;

[0111] S100, S105, S106, S107, S115, S117, S120, S123, S125, S130, S135, S140, S200, S200a, S200b, S210, S220, S230, S250, S280, S285, S290, S305, S310, S320, S330, S340, S350, S355, S360, S370, S380, S410, S415, S420, S430, S440, S450, S460, S470, S510, S520, S530, S540: operation;

[0112] VA, VA0, VA1, VA2, VA3, VA4, VA5, VAn-2, VAn-1, VAn, VA1_a, VA1_b, VA1_c, VA1_d: virtual address;

[0113] VALID: valid information;

[0114] VMID: Virtual machine identifier. DETAILED DESCRIPTION

[0115] Hereinafter, exemplary embodiments of the inventive concept will be explained more fully with reference to the accompanying drawings.Throughout the present application, the same reference numerals may refer to the same elements.

[0116] Figure 1 is a diagram of a system-on-chip (SoC) including a memory management unit (MMU) according to an exemplary embodiment.

[0117] Reference Figure 1SoC 10 may be implemented as any of a number of electronic devices, examples of which include personal computers (PCs), tablet personal computers, netbooks, e-readers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, and MP4 players. SoC 10 may include an application processor 100 that executes program instructions to control the overall operation of SoC 10. SoC 10 may also include a display 20, a memory device 30, and an input device 50.

[0118] For example, the application processor 100 may receive program instructions via the input device 50. In an exemplary embodiment, the application processor 100 executes the program instructions by reading data from the memory device 30 and displaying the data on the display 20. The input device 50 may include a keypad, a keyboard, and a point-and-touch device such as a touch pad and a computer mouse.

[0119] The memory device 30 may include a page table 40 that stores mapping information between virtual addresses and physical addresses.

[0120] Figure 2 is a diagram showing an exemplary embodiment Figure 1 A block diagram of an example of an application processor in FIG.

[0121] Reference Figure 2 The application processor 100 includes a central processing unit (CPU) 110 , a cache 170 , an MMU 200 , a system bus 180 , a system peripheral circuit 120 , a multimedia accelerator 130 , a connectivity circuit 140 , a display controller 150 and / or a memory controller 160 .

[0122] The CPU 110 executes the received program instructions. The cache 170 is a high-speed memory that stores selected data (e.g., frequently accessed data) to reduce the average delay of memory access operations performed by the CPU 110. The MMU 200 is a hardware component that processes a request from the CPU 110 to access the memory device 30.

[0123] The functions of the MMU 200 may include translating a virtual address into a physical address, performing memory protection, controlling the cache 170, performing bus arbitration, and / or performing bank switching.

[0124] The system peripheral circuit 120 , the multimedia accelerator 130 , the connection circuit 140 , the display controller 150 , and / or the memory controller 160 communicate data or instructions with one another via the system bus 180 .

[0125] System bus 180 may include multiple channels, such as a read data channel, a read address channel, a write address channel, and / or a write data channel.

[0126] The system peripheral circuit 120 includes a real-time clock (RTC) 121 , a phase-locked loop (PLL) 123 and / or a watch dog timer 125 .

[0127] The multimedia accelerator 130 includes a graphic engine 133. The multimedia accelerator 130 may also include a camera interface 131, a graphic engine integrated with a frame buffer or video display circuit system for performing graphic calculations, and / or a high-definition multimedia interface (HDMI) 135, which is an audio / video interface for transmitting uncompressed digital data. It should be noted here that the MMU 200 may be used to convert a virtual address output from the graphic engine 133 into a physical address.

[0128] Therefore, exemplary embodiments of the inventive concept may be applied to various memory devices and various applications to ensure operational stability and maintain or enhance operational performance.

[0129] The connection circuit 140 may include an audio interface 141 , a storage interface 143 (eg, an advanced technology attachment (ATA) interface), and / or a connection interface 145 . The connection circuit 140 may communicate with the input device 50 .

[0130] The display controller 150 controls data to be displayed in the display 20. The MMU 200 may be used to convert a virtual address output from the display controller 150 into a physical address.

[0131] The memory controller 160 enables the memory device 30 to be accessed according to the type of memory (eg, flash memory or dynamic random access memory (DRAM)).

[0132] Figure 3is a diagram showing the mapping between virtual addresses and physical addresses.

[0133] Reference Figures 1 to 3 , the virtual address space can be divided into multiple pages PN0 to PNn, where n is an integer greater than two.

[0134] Each of the pages PN0 to PNn is a block formed by adjacent virtual addresses. Each of the pages PN0 to PNn has a given data size, for example, 4 kilobytes (KB). However, the size of the pages PN0 to PNn is not limited and may be changed.

[0135] Like the virtual address space, the physical address space may also be divided into a plurality of frames FN0 to FNn. Each of the frames FN0 to FNn has a fixed size.

[0136] A virtual address (eg, VA2) includes a page number (eg, PN2) and an offset within the page (eg, OFF2). In other words, the virtual address can be expressed by Equation 1:

[0137] VAi=PNj+OFFx(1)

[0138] Wherein 'i', 'j' and 'x' are natural numbers of 1 or greater, VAi is a virtual address, PNj is a page number, and OFFx is an offset.

[0139] The page number PN2 is used as an index in the page table 40 .

[0140] The offset OFF2 is combined with a frame number (eg, FN2) that defines a physical address (eg, PA2). The physical address can be expressed by Equation 2:

[0141] PAr=FNs+OFFx(2)

[0142] Wherein 'r', 's' and 'x' are natural numbers of 1 or greater, PAr is the physical address, FNs is the frame number, and OFFx is the offset.

[0143] The page number PN2 may be referred to as a virtual page number and the frame number FN2 may be referred to as a physical page number.

[0144] The page table 40 has a mapping between the virtual address of the page and the physical address of the frame.

[0145] For ease of explanation, in the description, it is assumed that the processor (e.g., CPU 110), the graphics engine 133, and the display controller 150 that process data in each work group are all referred to as master intellectual property (IP). The master IP can operate for each work group and can process multiple work groups at a time. A work group is a data set stored in the memory device 30. The work group represents a group of pages in the memory device 30 that are frequently referenced by the master IP (e.g., exceeding a reference number of times in a reference time period), or represents the amount of pages that can be loaded from the master IP to the memory device 30. In an exemplary embodiment, in the master IP, each work group is managed independently of other work groups.

[0146] Figure 4A is used to explain the exemplary embodiments Figure 1 Diagram of the operation of the MMU.

[0147] Reference Figure 1 , Figure 2 and Figure 4A , the MMU 200 includes a translation cache (TC) 218, a context cache (CC) 210, and / or an invalidation queue (IQ) 230 and is connected to the master IP 190 and the memory device 30 through a plurality of channels.

[0148] The master IP 190 processes the work group. The master IP 190 outputs an access request corresponding to the work group to the MMU 200 or the cache 170. The access request may include a virtual address VA on the work group in the memory device 30 and a context on an attribute on the work group. The access request may include one of a check request and an invalidation request.

[0149] The MMU 200 calculates the physical address PA using the virtual address VA based on the access request of the master IP 190. Alternatively, the MMU 200 may invalidate at least one of the entries in the translation cache 218 based on the access request of the master IP 190.

[0150] The context cache 210 stores the context associated with the attribute of the access request as a first tag while avoiding duplication of the table entry, and / or stores the context identifier of the context as the first data. When the access request corresponds to an inspection request, the context cache 210 may store the context used in the inspection request as a first tag while avoiding duplication of the table entry, and may store the context identifier of the context as the first data.

[0151] The translation cache 218 may store the first address and the first context identifier as a second tag and may store the first address and the first context identifier as a second tag, and may store the second address as a second data. The first address corresponds to the virtual address used in the inspection request and the first context identifier corresponds to the first context used in the inspection request. The second address corresponds to the first address and the first context.

[0152] The translation cache 218 may include a translation lookaside buffer (TLB) or a walk cache.

[0153] The TLB is memory management hardware for improving the speed of virtual address translation. The TLB stores the mapping between the page number PN and the frame number FN. The TLB stores mapping information between the context identifier, the virtual address VA, and the physical address PA associated with the page referenced by the master IP 190. The TLB stores the context identifier and the virtual address as the second tag and stores the physical address corresponding to the virtual address as the second data.

[0154] The walk cache stores a portion of a virtual address and stores a physical address indicating a location of a page table corresponding to the portion of the virtual address.

[0155] When translating a virtual address into a physical address, the MMU 200 first checks the context cache 210. If the context associated with the virtual address VA corresponding to the request of the master IP 190 matches at least one of the entries in the context cache 210 (this is called a TC hit), the context cache 210 provides the context identifier corresponding to the matching context to the translation cache 218.

[0156] If the mapping information corresponding to the virtual address VA is in the translation cache 218 (this is called a TC hit), the MMU 200 directly processes the translation without accessing the memory device 30 and reading the mapping information from the memory device 30 .

[0157] If the context associated with the virtual address VA of the request corresponding to the primary IP 190 does not match any or all of the entries in the context cache 210 (this is called a CC miss), or if no match is found in the translation cache 218 for the matched context identifier and the virtual address VA (this is called a TC miss), a page table walk is performed.

[0158] The page table walk is a process of determining whether the page number PN and the frame number FN of the virtual address VA match the page table 40 stored in the memory device 30 when the context associated with the virtual address VA corresponding to the request of the main IP 190 does not match any or all of the entries in the context cache 210, or when the frame number FN of the virtual address VA does not match the page number PN in the translation cache 218 (i.e., the mapping information between the virtual address VA and the physical address PA is not found in the translation cache 218). The page table 40 stores the mapping information between the virtual address and the physical address of each data in the memory device 30.

[0159] When the master IP 190 attempts to read instruction INST or data DTA using physical address PA and the instruction or data corresponding to physical address PA is in cache 170, cache 170 may output the instruction INST or data DTA directly to the master IP 190 without accessing the memory device 30 (this is called a 'cache hit').

[0160] However, when the instruction INST or data DTA does not exist in the cache 170, the cache 170 may access the data / instruction storage block 45 in the memory device 30 to read the instruction or data (this is called a 'cache miss'). The data / instruction storage block 45 stores information about each of the data / instructions in the memory device 30.

[0161] The invalidation queue 230 may store at least one context identifier to be invalidated among the context identifiers stored in the translation cache 218 .

[0162] Figure 4B According to an exemplary embodiment Figure 4A An instance of the translation cache in .

[0163] Reference Figure 4B , the translation cache 218 includes a tag field 219a and a data field 219b.

[0164] The tag field 219a may store a context identifier CID1 and a virtual address VA1 and the data field 219b may store a physical address PA1 corresponding to the virtual address VA1.

[0165] For example, it is assumed that context identifiers CID1_a and CID1_b are used in the inspection request. In an exemplary embodiment, the context identifier CID1_a and the virtual addresses VA1_a, VA1_b, and VA1_c corresponding to the context identifier CID1_a are stored in the tag field 219a, and the context identifier CID1_b and the virtual address VA1_d are stored in the tag field 219a. In addition, the physical addresses PA1_a, PA1_b, PA1_c, and PA1_d corresponding to the virtual addresses VA1_a, VA1_b, VA1_c, and VA1_d, respectively, are stored in the data field 219b. The virtual addresses VA1_a, VA1_b, VA1_c, and VA1_d stored in the tag field 219a may be referred to as first addresses and the physical addresses PA1_a, PA1_b, PA1_c, and PA1_d stored in the data field 219b may be referred to as second addresses.

[0166] Figure 4C According to an exemplary embodiment Figure 4B An instance of the translation cache in .

[0167] Reference Figure 4C , the translation cache 218a may include a TLB 220. The configuration of the TLB 220 will refer to Fig. 6A To elaborate.

[0168] Figure 4D According to an exemplary embodiment Figure 4B Another example of a translation cache in .

[0169] Reference Figure 4D , the conversion cache 218b may include a walk cache (WC) 250. The configuration of the walk cache 250 will refer to Figure 6B To elaborate.

[0170] Figure 5 is a diagram showing an exemplary embodiment Figure 1 Block diagram of the MMU in the SoC shown.

[0171] Reference Figure 5 , the MMU 200 includes a first interface 261 , a second interface 263 , a storage interface 267 , an address translation manager (ATM) 260 , a context cache 210 , a translation cache 218 , an invalidation queue 230 , a page table walker (PTW) 240 , and / or a control register 265 .

[0172] The first interface 261 provides an interface with the master IP 190. The first interface 261 may have an interface structure corresponding to, for example, an advanced extensible interface (AXI) protocol.

[0173] The master IP 190 may transmit an access request REQ to the MMU 200 through the first interface 261 .

[0174] The second interface 263 is a separate slave interface for setting the control register 265. For example, the CPU 110 (see Figure 2 ) can control specific operations of the MMU 200 through the second interface 263. The second interface 263 can communicate with the CPU 110 according to, for example, an advanced peripheral bus (APB) protocol. The MMU 200 can receive a control signal CTL from the CPU 110.

[0175] The ATM 260 operates to convert the virtual address VA included in the access request REQ into a physical address PA.

[0176] The ATM 260 mainly checks (searches or looks up) the context cache 210 to convert the virtual address VA provided from the master IP 190 through the address channel into the physical address PA.

[0177] When the context associated with the virtual address VA exists in the context cache 210 (CC hit), the context cache 210 provides the context identifier corresponding to the context associated with the virtual address VA to the ATM 260. The ATM 260 checks the translation cache 218 based on the context identifier. When the context identifier provided from the context cache 210 exists in the translation cache 218 (TC hit, that is, if the context identifier provided from the context cache 210 matches at least one of the entries in the translation cache 218), the ATM 260 can generate the physical address PA by referring to the context identifier and the virtual address.

[0178] If there is no context associated with the virtual address VA in the context cache 210 (CC miss), or if the context identifier provided from the context cache 210 does not match any or all of the entries in the translation cache 218 (TC miss), the ATM 260 controls the page table walker 240 to perform a page table walk on the page table 40.

[0179] Information for controlling the operation of the MMU 200 is stored in the control register 265. The ATM 260 may control the context cache 210, the translation cache 218, the invalidation queue 230, and / or the page table walker 240 based on the information stored in the control register 265.

[0180] The storage interface 267 provides an interface for communicating with the memory device 30. The MMU 200 may read the page table 40 in the memory device 30 through the storage interface 267 or may access the data / instruction storage block 45 in the memory device 30 through the storage interface 267.

[0181] Fig. 6A and Figure 6B According to exemplary embodiments, Figure 5 Part of the MMU in.

[0182] Fig. 6A The implementation of TLB 220 is shown as Figure 5 The conversion cache 218 in Figure 6B The walk cache 250 is shown as implementing Figure 5 The conversion cache 218 in.

[0183] exist Fig. 6A , the context cache 210, TLB 220 and invalidation queue 230 are shown, and in Figure 6B , a walk cache 250 is shown. Fig. 6A Conventional TLB 215 is shown in FIG. 2 for comparison with TLB 220 .

[0184] Reference Fig. 6A , the context cache 210 includes a tag field 211 and a data field 213. The tag field 211 stores the context as a first tag, and the context is used in the check request of the master IP 190 while avoiding duplication of the context. Each of the contexts may include valid information (VALID), an address space identifier (ASID) for identifying an address space, a virtual machine identifier (VMID) for identifying a virtual machine, a non-security field NS associated with whether it is secure, and an exception level field EL associated with an exception field. The data field 213 includes a context identifier CID for each of the contexts.

[0185] For example, context CTX11 may have a VALID of 'Y', an ASID of '0xA', a VMID of '0xB', a NS of '1', an EL of '1', and a context identifier CID11 of '0x4'. In addition, context CTX12 may have a VALID of 'Y', an ASID of '0xC', a VMID of '0xB', a NS of '1', an EL of '1', and a context identifier CID12 of '0x6'.

[0186] The TLB 220 includes a tag field 221 and a data field 223. The tag field 221 stores a context identifier CID and a virtual address VA corresponding to the context identifier CID, and the data field 223 stores a physical address PA corresponding to the virtual address VA and permission information AT associated with whether read (R) / write (W) access is allowed. Each of the entries in the tag field 221 of the TLB 220 may also include valid information (VALID). The tag field 221 of the TLB 220 may store the virtual address (first address) used in the check request and the context identifier of the context as a second tag, and the data field 223 of the TLB 220 may store the physical address corresponding to the first address and the context identifier as a second address.

[0187] For example, context identifier CID11 may have virtual addresses of '0x1000', '0x6000', and '0x3000'. Context identifier CID12 may have a virtual address of '0x8000'.

[0188] A virtual address of '0x1000' may have a physical address of '0x9000' and an AT of 'R / W'. A virtual address of '0x6000' may have a physical address of '0xA000' and an AT of 'R / W'. A virtual address of '0x3000' may have a physical address of '0x0000' and an AT of 'R'. A virtual address of '0x8000' may have a physical address of '0x2000' and an AT of 'W'.

[0189] The invalidation queue 230 stores the context identifiers of '0x7' and '0x3' as invalidation entries.

[0190] The walk cache 250 includes a tag field 251 and a data field 253. The tag field 251 stores a context identifier CID and a local virtual address pVA corresponding to the context identifier CID, and the data field 253 stores a second physical address PA2 specifying a location of the page table 40 corresponding to the local virtual address pVA. Each of the entries in the tag field 251 of the walk cache 250 may also include valid information (VALID).

[0191] For example, context identifier CID11 may have local virtual addresses of 'pVA11' and 'pVA12'. Context identifier CID12 may have local virtual addresses of 'pVA13'. Local virtual addresses 'pVA11', 'pVA12' and 'pVA13' specify locations in page table 40, which are specified by physical addresses PA11, PA12 and PA12, respectively.

[0192] like Fig. 6A As described above, the context identifier CID11 has a different virtual address for one context identifier. Therefore, the ATM 260 can convert the virtual address VA into the physical address PA in the following manner: mainly checking the context cache 210 to determine whether the target context included in the access request of the master IP 190 matches at least one of the entries of the tag field 211 in the context cache 210 and selectively checking the TLB 220 based on the result of checking the context cache 210.

[0193] Since the context cache 210 stores the context and avoids duplication of the context, the occupied area of ​​the context cache 210 can be reduced. In addition, the TLB 220 does not store the ASID and VMID having relatively more bits, and the configuration of the TLB 220 can be simplified.

[0194] In addition, if the target context does not match any or all of the entries of the tag field 211 of the context cache 210 , a page table walk is performed without checking the TLB 220 , and thus the performance of the MMU 200 may be enhanced.

[0195] In contrast, since the conventional TLB 215 including the tag field 217 and the data field 219 stores ASID and VMID having relatively more bits, the size of the TLB 215 increases and more time is required to check the TLB 215 to determine whether the target context matches the entry of the TLB 215 .

[0196] Figure 7 is a diagram showing an exemplary embodiment Figure 5 A flowchart of an exemplary operation of the MMU in FIG. 1 , and Figure 8 It is used to explain Figure 7 Graph of the operations in .

[0197] Reference Figures 5 to 8 When the ATM 260 receives the access request REQ from the primary IP 190, the ATM 260 checks (searches) the context cache 210 based on the target context included in the access request REQ (operation S100), and determines whether the target context matches at least one of the first entries in the context cache 210 (CC tag hit in operation S115?).

[0198] If the target context does not match any or all of the first entries in the context cache 210 (No in S115), the ATM 260 assigns the target context to a new context identifier (ID) (operation S200) and controls the page table walker 240 to perform a page table walk on the page table 40 (operation S290).

[0199] If the target context matches one of the first entries (or at least one of the first entries) in the context cache 210 (Yes in S115), the ATM 260 obtains a context identifier (context ID) corresponding to the target context (S120). The ATM 260 checks the translation cache (TC) 218 ​​based on the obtained context identifier and the target virtual address (operation S125) and determines whether the obtained context identifier and the target virtual address match one of the second entries in the translation cache 218 (TC tag hit? in operation S130).

[0200] If the obtained context identifier and the target virtual address match all the second entries in the translation cache 218 (No in S130), the ATM 260 controls the page table walker 240 to perform a page table walk on the page table 40 (operation S290).

[0201] If the obtained context identifier and target virtual address match one of the second entries in the cache 218 (Yes in S130), the ATM 260 obtains the physical address PA corresponding to the target virtual address (operation S140) and performs address translation to provide the physical address PA to the primary IP 190 (operation S285).

[0202] Fig. 9A is a diagram showing an exemplary embodiment Figure 5 Flowchart of another exemplary operation of the MMU in .

[0203] Reference Figure 5 and Fig. 9A , the ATM 260 determines whether the currently used context has changed (operation S105).

[0204] If the currently used context has not changed (No in S105 ), the ATM 260 performs operation S105 .

[0205] If the currently used context is changed (Yes in S105), the ATM 260 checks the context cache 210 based on the changed context (operation S107).

[0206] The ATM 260 determines whether the changed context matches at least one of the first entries in the context cache 210 (operation S117). If the changed context does not match any or all of the first entries in the context cache 210 (No in S117), the ATM 260 assigns the changed context to a new context identifier (ID) (operation S200) and stores the changed context in the context cache 210.

[0207] If the changed context matches at least one of the first entries in the context cache 210 (Yes in S117 ), the ATM 260 updates the context cache 210 by assigning the matched entry as the first context identifier (operation S123 ).

[0208] Since the context rarely changes, operations S107, S120, and S123 may be skipped.

[0209] Fig. 9B is a diagram showing a method according to an exemplary embodiment Figure 5 Flowchart of another exemplary operation of the MMU in .

[0210] Reference Figure 5 and Fig. 9B , the ATM 260 determines whether a new request is received from the master IP 190 (operation S106). If a new request is not received from the master IP 190 (No in S106), the ATM 260 performs operation S106. If a new request is received from the master IP 190 (Yes in S106), the ATM 260 checks the translation cache 218 based on the most recently used context identifier and the virtual address VA included in the new request (operation S125).

[0211] The ATM 260 determines whether the most recently used context identifier and the virtual address VA match at least one of the second entries in the translation cache 218 (operation S135). If the most recently used context identifier and the virtual address VA do not match all of the second entries in the cache 218 (No in S135), the ATM 260 controls the page table walker 240 to perform a page table walk on the page table 40 (operation S290). The physical address PA may be obtained after the page table walk (operation S140). If the most recently used context identifier and the virtual address VA match one of the second entries (at least one of the second entries) in the second entries in the translation cache 218 (Yes in S135), the ATM 260 obtains the physical address PA (operation S140).

[0212] Fig.10Shown in Figure 7 A new context identifier is assigned to Fig.11 It is implemented Fig.10 Example operation of the MMU in operation.

[0213] Reference Figure 5 , Figure 7 , Fig.10 and Fig.11 To allocate a new context identifier to the target context (operation S200a), the ATM 260 determines whether the context cache 210 has available space, for example, whether the context cache 210 is full (operation S210).

[0214] If the context cache 210 has available space (No in S210 ), the ATM 260 controls the page table walker 240 to perform a page table walk on the page table 40 (operation S290 ).

[0215] If the context cache 210 does not have available space (Yes in S210), the ATM 260 invalidates at least one of the entries in the context cache 210 (selects at least one entry) based on the use history of the first entry and places (records) the context identifier to be invalidated of the selected entry in the invalidation queue 230 (operation S250). That is, the ATM 260 changes the valid information of the least recently used context identifier CID13 of '0x8' from 'Y' to 'N' and records '0x8' in the invalidation queue 230.

[0216] The ATM 260 stores the target context in the location in the context cache 210 where the context identifier CID13 was stored and allocates a new context identifier CID14 to the target context (operation S280).

[0217] Fig.12 According to an exemplary embodiment, Figure 7 A new context identifier is assigned in .

[0218] Reference Figure 5 , Figure 7 and Fig.12 To allocate a new context identifier to the target context (operation S200b), the ATM 260 determines whether the context cache 210 has available space, for example, whether the context cache 210 is full (operation S210).

[0219] If the context cache 210 does not have available space (Yes in S210), the ATM 260 determines whether the invalidation queue 230 has available space, for example, whether the invalidation queue 230 is full (operation S220). If the invalidation queue 230 has available space (No in S220), the ATM 260 invalidates (selects at least one entry) at least one of the entries in the context cache 210 based on the usage history of the first entry and places (records) the context identifier to be invalidated of the selected entry in the invalidation queue 230 (operation S250).

[0220] If the invalidation queue 230 does not have available space, for example, if the invalidation queue 230 is full (Yes in S220), the ATM 260 invalidates at least some of the entries in the translation cache 218 based on the invalidation queue 230 and dequeues (clears) at least some of the entries in the invalidation queue 230, so that the invalidation queue 230 has available space (operation S230).

[0221] The ATM 260 invalidates at least one of the entries in the context cache 210 (selects at least one entry) based on the usage history of the first entry and places (records) the context identifier to be invalidated of the selected entry in the invalidation queue 230 (operation S250). The ATM 260 stores the target context in the location in the context cache 210 where the context identifier was stored and allocates a new context identifier to the target context (operation S280).

[0222] Fig.13A is a flow chart illustrating an exemplary method of invalidating entries in a context cache in an MMU according to an exemplary embodiment.

[0223] Reference Figure 5 , Fig. 6A and Fig.13A , the ATM 260 determines whether the access request from the master IP 190 corresponds to a new invalidation request to invalidate at least one of the entries in the translation cache 218 (operation S305).

[0224] If the access request from the master IP 190 corresponds to a new context-based invalidation request (Yes in S305), the ATM 260 checks the context cache 210 based on the target context included in the invalidation request (operation S310), and determines whether the target context matches one or more entries in the context cache 210 (operation S320). If the target context does not match any or all of the entries in the context cache 210 (No in S320), the ATM 260 notifies the master IP 190 that the invalidation is completed (operation S330).

[0225] If the target context matches one or more entries in the context cache 210 (Yes in S320), the ATM 260 invalidates the entry corresponding to the target context in the context cache 210, records (places) the context identifier of the invalidated entry (operation S340) and notifies the master IP 190 that the invalidation is completed (operation S330).

[0226] Fig. 13B is a flow chart illustrating an exemplary method of invalidating entries in a translation cache in an MMU according to an exemplary embodiment.

[0227] Reference Fig. 13B , the ATM 260 determines whether the invalidation queue 230 has available space, for example, determines whether the invalidation queue 230 is not empty (operation S350). If the invalidation queue 230 is not empty (yes in S350), the ATM 260 determines whether the translation cache 218 is not used, for example, determines whether there is no activity in the translation cache 218 (operation S355). If the translation cache 218 is not used (yes in S355), the ATM 260 dequeues the context identifier from the invalidation queue 230 (extracts the context identifier) ​​and checks the translation cache 218 based on the dequeued context identifier (operation S360).

[0228] The ATM 260 determines whether the context identifier of the retired queue matches at least one of the entries in the translation cache 218 (operation S370). If the context identifier of the retired queue does not match any or all of the entries in the translation cache 218 (No in S370), the process ends. If the context identifier of the retired queue matches at least one of the entries in the translation cache 218 (Yes in S370), the ATM 260 changes the valid information of the matched entry (e.g., the matched context identifier) ​​from 'Y' to 'N' (operation S380).

[0229] Fig.13A and Fig. 13B 2 shows the context-based invalidation of entries of the translation cache 218. In addition, Fig. 13B The invalidation of entries of the translation cache 218 is shown being performed in the background when the translation cache 218 is not in use.

[0230] Fig.14 is a flow chart illustrating another exemplary method of invalidating entries in a translation cache in an MMU according to an exemplary embodiment.

[0231] Reference Figure 5 , Fig. 6A and Fig.14 , the ATM 260 determines whether the access request from the master IP 190 corresponds to a new invalidation request to invalidate at least one of the entries in the translation cache 218 (operation S410). In an exemplary embodiment, the access request may include a virtual address VA.

[0232] If the access request from the master IP 190 corresponds to a new virtual address-based invalidation request to invalidate an entry with a specific context (Yes in S410), the ATM 260 checks the context cache 210 based on the target context included in the invalidation request (operation S415), and determines whether the target context matches one or more entries in the context cache 210 (operation S420). If the target context does not match any or all of the entries in the context cache 210 (No in S420), the ATM 260 notifies the master IP 190 that the invalidation is complete (operation S470).

[0233] If the target context matches one or more entries in the context cache 210 (Yes in S420), the ATM 260 obtains a context identifier corresponding to the target context (operation S430), and checks the translation cache 218 based on the obtained context identifier and virtual address (operation S440). The ATM 260 determines whether the obtained context identifier and virtual address match at least one entry in the translation cache 218 (operation S450). If the obtained context identifier and virtual address do not match all entries in the translation cache 218 (No in S450), the ATM 260 notifies the master IP 190 that invalidation is complete (operation S470).

[0234] If the obtained context identifier and virtual address match at least one of the entries in the translation cache 218 (Yes in S450), the ATM 260 changes the valid information of the matching entry (e.g., the matching context identifier) ​​from 'Y' to 'N' (operation S460) and notifies the master IP 190 that the invalidation is completed (operation S470).

[0235] Fig.14 Virtual address based invalidation of entries of the translation cache 218 is shown.

[0236] The MMU 200 in the application processor 100 according to an exemplary embodiment may convert a virtual address into a physical address by mainly checking a context cache that stores contexts while avoiding copying the contexts, and selectively checking a translation cache based on the result of checking the context cache. Therefore, the size of the translation cache may be reduced. In addition, the performance of the application processor 100 may be enhanced by processing the invalidation request in the background during a period when the translation cache 218 is not used when the invalidation request specifies context-based invalidation.

[0237] Fig.15 According to an exemplary embodiment, Figure 1 Another example of an application processor in a SoC.

[0238] Reference Fig.15 , the application processor 100a may include an MMU module 200a.

[0239] The MMU module 200 a may include at least one MMU and may convert a virtual address included in a request from the master IP 190 into a physical address.

[0240] Fig.16 is a diagram showing an exemplary embodiment Fig.15 00a.

[0241] exist Fig.16 , for ease of explanation, the main IP 190 and the memory device 30 are shown.

[0242] Reference Fig.16 , the MMU module 200a includes an address distributor 270, a first bus interface 275, a plurality of MMUs 281 to 28k and / or a second bus interface 290. Fig.16 Although not shown, the MMU module 200a may further include a cache that stores data and / or instructions corresponding to the physical addresses.

[0243] MMU (MMU1) 281 includes context cache CC1, translation cache TC1 and / or invalidation queue IQ1. MMU (MMU2) 282 includes context cache CC2, translation cache TC2 and / or invalidation queue IQ2. MMU (MMUk) 28k includes context cache CCk, translation cache TCk and / or invalidation queue IQk. Each of translation caches TC1 to TCk may include a TLB or a walk cache.

[0244] The master IP 190 may operate for each work group and may process multiple work groups at a time. A work group is a data set stored in the memory device 30. A work group represents a group of pages that the master IP 190 frequently accesses (e.g., more than a reference number of times in a reference time period) or represents the amount of pages that can be loaded from the master IP 190 to the memory device 30. According to an exemplary embodiment of the inventive concept, each work group is managed independently of other work groups in the master IP 190.

[0245] When the master IP 190 performs operations for a plurality of work groups, the address allocator 270 may dynamically allocate an MMU to each of the work groups. The address allocator 270 stores MMU allocation information corresponding to each of the work groups.

[0246] When receiving a request for a work group from the master IP 190, the address distributor 270 may output the MMU identity MMU_ID of the MMU corresponding to the virtual address VA included in the request to the first bus interface 275 based on the MMU allocation information. The first bus interface 275 may transmit the request and data to the MMU corresponding to the MMU identity MMU_ID.

[0247] Fig.17 According to an exemplary embodiment Fig.16 An instance of the address allocator 270 in FIG.

[0248] Reference Fig.17 , the address distributor 270 includes a register set 271 and / or an address comparator 273 .

[0249] The register group 271 stores MMU allocation information corresponding to each of the work groups. In other words, the register group 271 stores MMU allocation information, in which the virtual address VA corresponding to each work group is mapped to the MMU ID. According to an exemplary embodiment, the MMU allocation information may include indicator information for distinguishing the virtual address VA of each work group. The indicator information may be, for example, the starting point and / or end point of the continuous virtual address VA of the work group.

[0250] The address comparator 273 may compare the virtual address VA of the request received from the master IP 190 with the MMU allocation information. The address comparator 273 may output an MMU identity MMU_ID corresponding to the request as a result of the comparison.

[0251] Fig.18 It is used to explain Fig.16 A conceptual diagram of the operation of the MMU module in FIG.

[0252] like Fig.18 As shown, the first to k-th work groups may include, for example, a plurality of pages in the memory device 30 that are frequently referenced (e.g., exceeding a reference number of times in a reference time period) by the master IP 190, i.e., a plurality of adjacent virtual addresses VA. For example, the first work group includes virtual addresses VA0 to VA2, the second work group includes virtual addresses VA3 to VA5, and the k-th work group includes virtual addresses VAn-2 to VAn. However, the work groups are managed independently of each other in the operation of the master IP 190. In other words, a single virtual address VA does not belong to two or more work groups. For example, virtual addresses VA0 to VAn may be arranged consecutively for the work groups, such as Fig.18 shown.

[0253] Each of the MMUs MMU1-MMUk converts a virtual address VA of a work group mapped to the MMU into a physical address PA including PA0 to PA2. The address conversion may be performed based on a TLB within the MMU. The physical address PA converted by an MMU may be different from or the same as the physical address converted by another MMU.

[0254] When it is assumed that the work group of data to be processed by the master IP 190 is mapped to MMU1 281, the first bus interface 275 receives the MMU ID ID1 of MMU1 281 from the address distributor 270 and transmits the request and data of the master IP 190 to MMU1 281. When it is assumed that the work group of data to be processed by the master IP 190 is mapped to MMU2 282, the first bus interface 275 receives the MMU ID ID2 of MMU2 282 from the address distributor 270 and transmits the request and data of the master IP 190 to MMU2 282. When it is assumed that the work group of data to be processed by the master IP 190 is mapped to MMUk 28k, the first bus interface 275 receives the MMU ID IDk of MMUk 28k from the address distributor 270 and transmits the request and data of the master IP 190 to MMUk 28k.

[0255] The MMU1 281 converts the virtual address VA of the request into the physical address PA. When the MMU1 281 converts the virtual address VA into the physical address PA, the MMU1 281 mainly checks the context cache CC1, and selectively checks the translation cache TC1 based on the result of checking the context cache CC1, and transmits the request to convert the virtual address VA into the physical address PA to the master IP 190 through the first bus interface 275. In addition, the MMU1 281 transmits the request and the data to the memory device 30 through the second bus interface 290. The second bus interface 290 accesses the physical address PA in the memory device 30 and performs an operation corresponding to the request on the data.

[0256] When the master IP 190 starts to operate on another work group while operating on the current work group, one of the MMUs of the MMU module 200a that is not assigned to the current work group is assigned to the new work group and operates independently. Therefore, compared with the situation where all the work groups used by the master IP 190 share only one MMU, TC misses are reduced. Therefore, during the data processing operation of the master IP 190, the hit rate increases, and the operating speed of the SoC 10 also increases, while the mutual influence between the work groups is minimized or reduced. In addition, since MMUs are assigned to each work group, the MMU operation is flexible.

[0257] Fig.19 is a flowchart illustrating a method of operating an MMU in an application processor according to an exemplary embodiment.

[0258] Reference Figures 1 to 14 and Fig.19 , in the method of operating the MMU 200 in the application processor 100, the ATM 260 in the MMU 200 receives an access request including a target context and a target virtual address from the master IP 190 (operation S510).

[0259] The ATM 260 determines whether the target context matches at least one of the first entries in the context cache 210 by checking the context cache 210 (operation S520). The context cache 210 stores the context and the context identifier of the stored context as a first tag and first data, respectively, while avoiding duplication of the context.

[0260] The ATM 260 selectively determines whether the target context identifier corresponding to the target context matches at least one of the second entries in the translation cache 218 by selectively checking the translation cache 218 based on checking the context cache 210 (operation S530). The translation cache 218 stores the context identifier and the virtual address corresponding to the context identifier as a second tag and stores the physical address corresponding to the virtual address as second data.

[0261] The ATM 260 converts the target virtual address into a target physical address based on the selective determination (step S540 ), and outputs the target physical address to the master IP 190 .

[0262] Fig. 20 is a block diagram of a mobile device including a SoC according to an exemplary embodiment.

[0263] Reference Fig. 20 , the mobile device 900 includes a SoC 910, a Low Power Double Data Rate x (LPDDRx) memory device 940, an image sensor 950 and / or a display 960. The SoC 910 includes an application processor 920 and / or a wide input output (WideIO) memory 930.

[0264] The data stored in the wide input output memory 930 or the LPDDRx memory device 940 may be displayed on the display 960 under the control of the SoC 910. The SoC 910 (particularly the application processor 920) may include Figure 5 MMU 200 or Fig.16 The MMU module 200a in.

[0265] Therefore, the MMU of the application processor 920 may include a context cache, a translation cache, an invalidation queue, and / or an ATM. The ATM may convert a virtual address included in an access request from the main IP into a physical address by mainly checking a context cache that stores contexts while avoiding duplication of contexts, and selectively checking the translation cache based on the result of checking the context cache. Therefore, the size of the translation cache may be reduced.

[0266] The SoC and the semiconductor device according to the inventive concept may be packaged into one of various types to be subsequently embedded. For example, the SoC according to the concept of the present invention can be packaged by one of the following: Package on Package (PoP), Ball grid arrays (BGA), Chip scale packages (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), etc. Package, SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package (WSP).

[0267] The above mentioned Figures 1 to 20The elements may be implemented in the following devices: processing circuit systems, such as hardware including logic circuits; hardware / software combinations, such as processors that execute software; or combinations thereof and memory. For example, the processing circuit systems may more specifically include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0268] The above is an explanation of the exemplary embodiments and should not be considered as a limitation of the exemplary embodiments. Although the exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims.

Claims

1. An application processor, comprising: A memory management unit is configured to respond to an access request received from a master intellectual property, the access request including a target context and a target virtual address, wherein the access request corresponds to a check request to convert the target virtual address to a first target physical address, and The memory management unit comprises: a context cache configured to store a context and a context identifier of the stored context as a first tag and first data, respectively, while avoiding duplication of the context, the context being used in the inspection request; a translation cache configured to store a first address and a first context identifier as a second tag and configured to store a second address as second data, the first address corresponding to a virtual address used in the inspection request, the first context identifier corresponding to a first context used in the inspection request, and the second address corresponding to the first address and the first context; an invalidation queue configured to store at least one context identifier to be invalidated among the context identifiers stored in the translation cache; a control register configured to store information controlling the operation of the memory management unit; and An address translation manager is configured to control the context cache, the translation cache and the invalidation queue based on information stored in the control register, The master intellectual property includes one of a processor for processing data, a graphics engine, and a display controller.

2. The application processor of claim 1, wherein the address translation manager is configured to translate the first address into the second address by checking the context cache in response to the check request and selectively checking the translation cache based on a result of checking the context cache.

3. The application processor of claim 2, wherein if the target context matches at least one of the first entries in the context cache, the address translation manager is configured to obtain a context identifier corresponding to the target context as the target context identifier.

4. The application processor of claim 3, wherein the translation cache comprises a translation lookaside buffer, wherein the translation lookaside buffer is configured to store the virtual address as the first address and is configured to store a physical address corresponding to the virtual address as the second address, and If the target context identifier and the target virtual address match one of the second entries in the translation lookaside buffer, the address translation manager is configured to control the translation lookaside buffer to provide a first physical address corresponding to the target virtual address as the first target physical address.

5. The application processor according to claim 4, wherein the memory management unit further comprises a page table walker, wherein if the target context identifier does not match any or all of the second entries in the translation lookaside buffer, the address translation manager is configured to control the page table walker to perform a page table walk on a page table that maps a virtual address to a corresponding physical address, and If the target context identifier does not match any or all of the first entries in the context cache, the address translation manager is configured to control the page table walker to perform a page table walk on the page table.

6. The application processor according to claim 3, wherein the memory management unit further comprises a page table walker, wherein the conversion cache comprises a walk cache, wherein the walk cache is configured to store a local virtual address of the virtual address as the first address and is configured to store a second physical address indicating a location of the page table corresponding to the first address, wherein the address translation manager is configured to control the page table walker to perform a page table walk on a page table that maps the target virtual address to the first target physical address, and Wherein if the target context identifier and the target virtual address match one of the second entries in the walk cache, the address translation manager is configured to control the walk cache to provide a second physical address corresponding to the first address to the page table walker.

7. The application processor of claim 3, wherein if the target context does not match any or all of the first entries in the context cache, the address translation manager is configured to assign a new context identifier to the target context and store the target context in the context cache.

8. The application processor according to claim 7, wherein: The address translation manager is configured to determine whether the context cache has available storage space, If the context cache does not have the available storage space, then The address translation manager is configured to record a context identifier of at least one first entry of the first entries in the invalidation queue based on a usage history of the first entries stored in the context cache, and is configured to store the target context and the new context identifier in the context cache.

9. The application processor according to claim 7, wherein: The address translation manager is configured to determine whether the context cache has first available storage space, If the context cache does not have the first available storage space, the address translation manager is configured to determine whether the invalidation queue has a second available space, If the invalidation queue does not have the second available space, then The address translation manager is configured to dequeue at least one of the context identifiers to be invalidated that are stored in the invalidation queue, is configured to invalidate zero or more of the second table entries in the translation cache based on the dequeued context identifiers, and is configured to store the target context and the new context identifier in the context cache.

10. The application processor of claim 2, wherein the address translation manager is configured to: determining whether the context has changed and if the context has changed, mainly checking the context cache; If, according to the result of the checking, the changed context does not match any or all of the first entries in the context cache, assigning a new context identifier to the changed context and storing the new context identifier as the first context identifier in the context cache; and If, according to the result of the checking, the changed context matches at least one of the first entries in the context cache, the matched context is stored in the context cache as the first context identifier.

11. The application processor of claim 10, wherein the address translation manager is configured in response to the inspection request to: checking the translation cache based on the first context identifier and the virtual address; and If at least one second entry of the second entries in the translation cache matches the first address corresponding to the first context identifier and the virtual address, the second address is obtained.

12. The application processor of claim 1 , wherein the access request corresponds to a context-based invalidation request to invalidate a second entry in the translation cache, and the translation cache stores a context identifier corresponding to the target context as the second tag, and The address translation manager is configured to: checking the context cache in response to the context-based invalidation request; selectively checking the translation cache based on a result of checking the context cache; as well as A notification is provided that invalidation of the second entry in the translation cache is completed.

13. The application processor of claim 12, wherein if the target context matches at least one of the first entries in the context cache, the address translation manager is configured to: invalidating a target context identifier corresponding to the target context; and recording the target context identifier to be invalidated in the invalidation queue, and Wherein if the target context does not match any or all of the first entries in the context cache, the address translation manager is configured to notify that the invalidation is complete.

14. The application processor according to claim 12, wherein: The address translation manager is configured to determine whether the invalidation queue has available storage space, If the invalidation queue does not have the available storage space, then The address translation manager is configured to determine whether the translation cache is used, If the translation cache is not in use, the address translation manager is configured to extract a context identifier recorded in the invalidation queue, to check the translation cache based on the extracted context identifier, and if the extracted context identifier matches at least one of the entries in the translation cache, to invalidate the matching entry.

15. The application processor of claim 1 , wherein the access request corresponds to a virtual address-based invalidation request to invalidate a second entry in the translation cache, and the translation cache stores a context identifier corresponding to the target context as the second tag, and The address translation manager is configured to: performing a first check of the context cache based on the target context; If, according to the result of the first checking, the target context matches at least one first entry in the first entries in the context cache, obtaining a target context identifier corresponding to the target context; performing a second check of the translation cache based on the virtual address and the target context identifier; as well as If, according to the result of the second check, the virtual address and the target context identifier match at least one second entry in the translation cache, the matching entry is invalidated.

16. The application processor of claim 1, wherein when operating a page table walk, the address translation manager is configured to translate the first address into the second address by mainly checking the context cache in response to the check request and performing the page table walk based on a result of checking the context cache.

17. The application processor of claim 16 , wherein if the target context matches at least one of the first entries in the context cache, the address translation manager is configured to obtain a context identifier corresponding to the target context as the target context identifier, and Wherein if the target context identifier and the target virtual address match at least one of the second entries in the walk cache, the address translation manager is configured to control the walk cache to provide a physical address corresponding to the first address as the target physical address.

18. A system-on-chip, comprising: The master IP is configured to output access requests; an application processor comprising a memory management unit configured to, in response to the access request comprising a target context and a target virtual address, convert the target virtual address into a first target physical address; as well as a memory device coupled to the memory management unit and comprising a page table storing mapping information between a virtual address and a first physical address, The memory management unit comprises: a context cache configured to store a context and a context identifier of the stored context as a first tag and first data, respectively, while avoiding duplication of the context, the context being used in an inspection request corresponding to the access request; a translation cache configured to store a first address and a first context identifier as a second tag and configured to store a second address as second data, the first address corresponding to a virtual address used in the inspection request, the first context identifier corresponding to a first context used in the inspection request, and the second address corresponding to the first address and the first context; an invalidation queue configured to store at least one context identifier to be invalidated among the context identifiers stored in the translation cache; a control register configured to store information controlling the operation of the memory management unit; and An address translation manager is configured to control the context cache, the translation cache and the invalidation queue based on information stored in the control register, The master intellectual property includes one of a processor for processing data, a graphics engine, and a display controller.

19. A method of operating a memory management unit of an application processor, the method comprising: An address translation manager receives an access request, the access request including a target context and a target virtual address; determining, by the address translation manager, whether the target context matches at least one first entry of first entries in the context cache by checking a context cache, wherein the context cache is configured to store a context as a first tag and a context identifier of the stored context as a first tag and first data, respectively, while avoiding duplication of the context; determining, by the address translation manager, whether a target context identifier corresponding to the target context matches at least one second entry of second entries in the translation cache by selectively checking the translation cache based on checking the context cache, wherein the translation cache is configured to store the context identifier and a virtual address corresponding to the context identifier as a second tag and is configured to store a physical address corresponding to the virtual address as second data; as well as Based on the determination by selectively examining the translation cache, the target virtual address is translated into a corresponding target physical address.

20. The method of claim 19, wherein translating the target virtual address into the corresponding target physical address comprises: If the target context matches at least one first entry in the first entries in the context cache, obtaining, by the address translation manager, a context identifier corresponding to the target context as a target context identifier; as well as If the target context identifier and the target virtual address match at least one of the second entries in the translation cache, a physical address corresponding to the target virtual address is output by the address translation manager as the target physical address.

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