Semiconductor memory device and method of operating semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell array, a bit line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word line, and each of the memory blocks includes memory cells. The bit line switch is connected between a first half local input / output (I / O) line of a first memory block and a second half local I / O line of the first memory block. The block switch is connected between the second half local I / O line of the first memory block and a first half local I / O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls the connections by applying a first switch control signal to the bit line switch and a second switch control signal to the block switch.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority from Korean Patent Application No. 10-2019-0056832 filed on May 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concept relate to memory devices, and more particularly, to semiconductor memory devices and methods of operating the same. Background Art

[0004] Semiconductor chips are manufactured through semiconductor manufacturing processes and then tested by test equipment in wafer, bare die, or packaged states. The defective portion of the defective chip is identified through testing, and if some memory cells are defective, repair is performed to save the semiconductor chip. Currently, semiconductor chips such as dynamic random access memory (DRAM) continue to reduce in size through fine processes, and accordingly, the possibility of errors occurring during the manufacturing process increases. In addition, if defects are not detected through the initial testing process, errors may occur during chip operation. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor memory device includes a memory cell array, at least one bit line switch, at least one block switch, and a column decoder. The memory cell array includes a plurality of memory blocks coupled to at least one word line, and each of the plurality of memory blocks includes a plurality of dynamic memory cells. The at least one bit line switch is connected between a first semi-local input / output (I / O) line of a first memory block of the plurality of memory blocks and a second semi-local I / O line of the first memory block, wherein the first semi-local I / O line is connected to a first group of bit lines among the plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block is connected to a second group of bit lines among the plurality of bit lines. The at least one block switch is connected between the second semi-local I / O line of the first memory block and the first semi-local I / O line of the second memory block among the plurality of memory blocks, and the first memory block and the second memory block are adjacent to each other. The column decoder includes a repair circuit, and the repair circuit controls a connection between a first semi-local I / O line of a first memory block and a second semi-local I / O line of the first memory block by applying a first switch control signal to at least one bit line switch, and controls a connection between the second semi-local I / O line of the first memory block and the first semi-local I / O line of the second memory block by applying a second switch control signal to at least one block switch.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes an array of memory cells, at least one bit line switch, at least one block switch, and a column decoder. The array of memory cells includes a plurality of memory blocks coupled to at least one word line, and each of the plurality of memory blocks includes a plurality of dynamic memory cells. The at least one bit line switch is connected between a first semi-local input / output (I / O) line of a first memory block of the plurality of memory blocks and a second semi-local I / O line of the first memory block, wherein the first semi-local I / O line of the first memory block is connected to a first group of bit lines of a plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block is connected to a second group of bit lines of the plurality of bit lines. The at least one block switch is connected between the second semi-local I / O line of the first memory block and a first semi-local I / O line of a second memory block of the plurality of memory blocks, and the first memory block and the second memory block are adjacent to each other. The column decoder repairs a first bit line of the first memory block by controlling the at least one bit line switch and the at least one block switch, using at least one spare bit line of the first memory block, or using a spare bit line of a memory block adjacent to the first memory block. The first bit line is coupled to a defective cell of the plurality of dynamic memory cells.

[0007] According to an exemplary embodiment of the inventive concept, in a method of operating a semiconductor memory device, the semiconductor memory device includes an array of memory cells including a plurality of memory blocks coupled to at least one word line, each of the plurality of memory blocks including a plurality of dynamic memory cells, at least one bit line switch coupled between a first semi-local input / output (I / O) line of a first memory block of the plurality of memory blocks and a second semi-local I / O line of the first memory block, and at least one block switch connected between the second semi-local I / O line of the first memory block and a first semi-local I / O line of a second memory block adjacent to the first memory block, the first semi-local I / O line of the first memory block being connected to a first group of bit lines of a plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block being connected to a second group of bit lines of the plurality of bit lines. In the method, a first bit line coupled to a defective cell in the first memory block is deactivated by a column decoder in response to a column address, and the defective cell is repaired by the column decoder by controlling the at least one bit line switch and the at least one block switch to activate a spare bit line of the first memory block or a spare bit line of the second memory block. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other features of the inventive concept will be better understood through a detailed description of exemplary embodiments of the inventive concept with reference to the drawings.

[0009] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0010] Figures 2A-2CA column repair performed in a semiconductor memory device according to an exemplary embodiment of the present inventive concept is shown.

[0011] Figure 3 A block diagram of a semiconductor memory device in Figure 1 according to an exemplary embodiment of the present inventive concept is shown.

[0012] Figure 4 A first memory block in a semiconductor memory device of Figure 3 according to an exemplary embodiment of the present inventive concept is shown.

[0013] Figure 5 A memory cell array, a row decoder, and a column decoder in a semiconductor memory device of Figure 3 according to an exemplary embodiment of the present inventive concept is shown.

[0014] Figure 6A A first row block fuse circuit of a row block fuse circuit in Figure 5 according to an exemplary embodiment of the present inventive concept is shown.

[0015] Figure 6B A row block information storage table in a first row block fuse circuit of Figure 6A according to an exemplary embodiment of the present inventive concept is shown.

[0016] Figure 7 A row address in Figure 6A according to an exemplary embodiment of the present inventive concept is shown.

[0017] Figure 8 A first repair circuit of a repair circuit in Figure 5 according to an exemplary embodiment of the present inventive concept is shown.

[0018] Figure 9 A first sub-column decoder of a sub-column decoder in Figure 5 according to an exemplary embodiment of the present inventive concept is shown.

[0019] Figure 10 A portion of a memory cell array in Figure 5 according to an exemplary embodiment of the present inventive concept is shown.

[0020] Figure 11 A portion of Figure 10 according to an exemplary embodiment of the present inventive concept is shown.

[0021] Figure 12 A circuit diagram of a bit line sense amplifier in Figure 10 according to an exemplary embodiment of the present inventive concept is shown.

[0022] Figure 13 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept. Figure 11

[0023] Figures 14A-14E is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0024] Figure 15 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0025] Figure 16 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0026] Figures 17A-17E is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0027] Figure 18 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept. Figure 1

[0028] Figure 19 is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0029] Figure 20 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0030] Figure 21 is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment of the present inventive concept. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the present inventive concept provide a semiconductor memory device capable of increasing flexibility of a column repair operation.

[0032] Exemplary embodiments of the present inventive concept also provide a method of operating a semiconductor memory device capable of increasing flexibility of a column repair operation.

[0033] Exemplary embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the application.

[0034] Figure 1 is a block diagram illustrating a storage system according to an exemplary embodiment of the present inventive concept.

[0035] Reference will now be made to​​Figure 1 The memory system 20 can include a memory controller 100 and a semiconductor storage device 200.

[0036] The memory controller 100 can control the overall operation of the memory system 20. The memory controller 100 can control the overall exchange of data between an external host and the semiconductor storage device 200. For example, the memory controller 100 can write data to or read data from the semiconductor storage device 200 in response to a request from the external host. In addition, the memory controller 100 can issue an operation command to the semiconductor storage device 200 for controlling the semiconductor storage device 200.

[0037] In an exemplary embodiment of the inventive concept, the semiconductor storage device 200 is a memory device including dynamic storage cells such as a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or an LPDDR5 SDRAM.

[0038] The memory controller 100 transmits a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor storage device 200, and exchanges data DQ with the semiconductor storage device 200.

[0039] The semiconductor storage device 200 includes a memory cell array (MCA) 300 storing the data DQ received from the memory controller 100 and an address decoder ADEC. The address decoder ADEC can include a row decoder (RD) 261 and a column decoder (CD) 271.

[0040] The memory cell array 300 can include a plurality of memory blocks, and each of the memory blocks can be divided into a plurality of row blocks by row block identification bits corresponding to a portion of bits of a row address included in the address ADDR. The memory cell array 300 can include at least one bit line switch and at least one block switch. The at least one bit line switch can be connected between a first semi-local input / output (I / O) line, which can be connected to a first group of bit lines among a plurality of bit lines of each of the memory blocks, and a second semi-local I / O line, which can be connected to a second group of bit lines among the plurality of bit lines. The at least one block switch can be connected between the second semi-local I / O line of a first memory block among the memory blocks and the first semi-local I / O line of a second memory block among the memory blocks, and the first memory block and the second memory block can be adjacent to each other.

[0041] The row decoder 261 compares a row address with a defective row address of a pre-stored defective cell, and outputs a row block match signal to the column decoder 271 if the row address matches the defective row address.

[0042] The column decoder 271 can repair the first bit line coupled to the defective cell by controlling at least one bit line switch and at least one block switch, using at least one spare bit line of the first memory block, or using a spare bit line of a second memory block adjacent to the first memory block. In other words, the address decoder ADEC can change a physical column address of a memory cell storing or outputting data based on a column address. Accordingly, the semiconductor memory device 200 can increase flexibility of a column repair operation.

[0043] Figures 2A-2C A column repair performed in a semiconductor memory device according to an exemplary embodiment of the present inventive concept is illustrated.

[0044] In Figures 2A-2C , it is assumed that the row blocks of the memory cell array 300 in Figure 1 include memory blocks MB1 to MBk, each of the memory blocks MB1 to MBk includes a bit line BL, a first spare bit line SBL0, and a second spare bit line SBL1, and the memory block MB2 includes a defective cell. Here, k is a natural number greater than three. Also, in Figures 2A-2C , "O" indicates a normal cell and "X" indicates a defective cell.

[0045] Referring to Figure 2A , it is noted that the bit line coupled to the defective cell in the memory block MB2 is repaired using the first spare bit line SBL0 in the memory block MB2, as indicated by reference numeral REP.

[0046] Referring to Figure 2B , it is noted that the bit line coupled to the defective cell in the memory block MB2 is repaired using the second spare bit line SBL1 in the memory block MB1, as indicated by reference numeral REP.

[0047] Referring to Figure 2C , it is noted that the bit line coupled to the defective cell in the memory block MB2 is sequentially repaired using a bit line in a memory block MB3 adjacent to the memory block MB2 and the second spare bit line SBL1 in the memory block MB3, as indicated by reference numerals REP1 and REP2.

[0048] As noted from Figure 2B and Figure 2C , the semiconductor memory device 200 equally allocates repair resources in the memory blocks MB1 to MBk, and can use a spare bit line in an adjacent memory block by controlling a bit line switch and a block switch. Accordingly, the semiconductor memory device 200 can increase flexibility of a column repair and can increase a yield.

[0049] Figure 3is shown illustrating an exemplary embodiment according to the inventive concept Figure 1 a block diagram of a semiconductor storage device in

[0050] Referring to Figure 3 The semiconductor storage device 200a includes a memory cell array 300a, a row decoder 261, a column decoder 271, and a peripheral circuit 201.

[0051] The memory cell array 300a can include a plurality of memory blocks MB1-MBk, and each of the memory blocks MB1-MBk includes memory cells coupled to a word line WL and a bit line BL, first spare cells coupled to the word line WL and a first spare bit line SBL0, and second spare cells coupled to the word line WL and a second spare bit line SBL1. The memory blocks MB1-MBk share the word line WL, but do not share the bit line BL, the first spare bit line SBL0, and the second spare bit line SBL1. Data associated with each of the memory blocks MB1-MBk can be input / output through a corresponding input / output pad of the memory cell array 300a.

[0052] The semiconductor storage device 200a can receive an activation command before receiving a write command or a read command from an external device (e.g., a memory controller). All memory cells connected to a word line WL of the semiconductor storage device 200a identified by the activation command can be selected based on the activation command. Next, if the semiconductor storage device 200a receives a write command or a read command, a plurality of bit lines BL can be selected. In an exemplary embodiment of the inventive concept, one or more of the bit lines BL shown in the memory blocks MB1-MBk can be selected by the write command or the read command. Data input / output can be performed on the memory cells coupled to the selected bit lines BL.

[0053] Parity data for error correction of data stored in at least one of the memory blocks MB1-MBk can be stored in some of the memory blocks MB1-MBk.

[0054] The column decoder 271 can be connected to the memory cell array 300a through a column selection line CSL and a spare column selection line SCSL. The column decoder 271 can select the column selection line CSL or the spare column selection line SCSL based on a write command or a read command. If the column decoder 271 selects the column selection line CSL, a corresponding bit line BL is selected. When the column decoder 271 selects the spare column selection line SCSL, the first spare bit line SBL0 and the second spare bit line SBL1 are selected.

[0055] The peripheral circuit 201 may include a command / address pad (CMD / ADD) 203, an input / output data (DQ) pad 205, and an error correction code (ECC) engine 280. In an exemplary embodiment of the present inventive concept, the ECC engine 280 may not be included in the peripheral circuit 201. The peripheral circuit 201 may receive a command CMD and an address ADDR from an external device (e.g., from the memory controller 100), and may exchange data DQ with the external device (e.g., with the memory controller 100). Based on the command CMD received from the external device (e.g., from the memory controller 100), the peripheral circuit 201 may provide a column address CADR to the column decoder 271 and may provide a row address RADDR to the row decoder 261. The peripheral circuit 201 may provide input data DQ to the column decoder 271 in response to a write command, or may receive output data DQ from the column decoder 271 in response to a read command. Input data DQ may be input to the peripheral circuit 201 through the input / output data (DQ) pad 205. Output data DQ may be output to the memory controller 100 through the input / output data (DQ) pad 205.

[0056] The ECC engine 280 may perform ECC encoding on the input data to generate parity data. The ECC engine 280 may store the input data DQ and the parity data in the memory blocks MB1-MBk. The ECC engine 280 may perform ECC decoding on the output data DQ read from the memory blocks MB1-MBk to correct at least one error in the read data. The ECC engine 280 may transmit the corrected data to the memory controller 100 via the input / output data (DQ) pads 205.

[0057] The row decoder 261 may activate a first word line WL in a first row block designated by the row address RADDR in response to the row address RADDR, and if the first row block includes at least one defective cell, the row decoder 261 may output a row block match signal RBMTH to the column decoder 271. The row decoder 261 may include a row block information circuit (RBIC) 400, and the row block information circuit 400 may store row block information of each row block of the memory blocks MB1 to MBk and may output the row block match signal RBMTH.

[0058] Figure 4 An exemplary embodiment according to the present inventive concept is shown. Figure 3 A first storage block in a semiconductor storage device.

[0059] refer to Figure 4The first memory block MB1 includes a plurality of memory cells MC coupled to a plurality of word lines WL1-WLm and a plurality of bit lines BL1-BLn, where m is a natural number greater than 2 and n is a natural number greater than 2. The first memory block MB1 may further include a plurality of spare cells SMC coupled to the word lines WL1-WLm, a first spare bit line SBL0, and a second spare bit line SBL1. If at least one of the memory cells MC has a defect, the defective memory cell may be repaired by the spare cell SMC.

[0060] The word lines WL1-WLm extend longitudinally along a first direction D1, and the bit lines BL1-BLn and the first and second spare bit lines SBL0 and SBL1 may extend longitudinally along a second direction D2 that intersects the first direction D1. The first and second spare bit lines SBL0 and SBL1 may be arranged in an edge portion of the first memory block MB1. The edge portion is located at an edge of the first memory block MB1 relative to the first direction D1.

[0061] Figure 5 An exemplary embodiment according to the present inventive concept is shown. Figure 3 A memory cell array, a row decoder, and a column decoder in a semiconductor memory device.

[0062] refer to Figure 5 In the memory cell array 300a, I sub-array blocks SCB may be arranged in columns 1 to 1 along a first direction D1, and J sub-array blocks SCB may be arranged in rows 1 to J along a second direction D2, the second direction being substantially perpendicular to the first direction D1. The sub-array blocks SCB arranged along the first direction D1 in any row 1 to J may be referred to as a row block. A plurality of bit lines, a first spare bit line, a second spare bit line, a plurality of word lines, a plurality of memory cells, and a plurality of spare cells may be arranged in each of the sub-array blocks SCB. Each of the sub-array blocks SCB may correspond to a memory block.

[0063] exist Figure 5 In the embodiment, one sub-array block SCB along the second direction D2 may correspond to a memory segment, and all sub-array blocks SCB along the first direction D1 may correspond to row blocks.

[0064] I+1 sub-word line driver regions SWB may be arranged between sub-array blocks SCB along a first direction D1. Sub-word line drivers may be arranged in the sub-word line driver regions SWB. J+1 bit line sense amplifier regions BLSAB may be arranged, for example, along a second direction D2 between sub-array blocks SCB. Bit line sense amplifiers for sensing data stored in memory cells may be arranged in the bit line sense amplifier regions BLSAB.

[0065] The plurality of connection regions CONJ can be arranged adjacent to the sub word line driver regions SWB and the bit line sense amplifier regions BLSAB. In an exemplary embodiment of the inventive concept, the plurality of connection regions CONJ can be adjacent to the sub word line driver regions SWB and the bit line sense amplifier regions BLSAB of the first row of the memory cell array 300a. A voltage generator is arranged in each of the connection regions CONJ.

[0066] The row decoder 261 includes a row block information circuit 400, and the row block information circuit 400 can include a plurality of row block fuse circuits (RBFCs) 401-40J corresponding to the row blocks in the second direction D2. The row block fuse circuits (RBFCs) 401-40J can output a row block match signal RBMTH to the column decoder 271 in response to row block identification bits of the row address RADDR.

[0067] The column decoder 271 can include a plurality of sub column decoders (SCDs) 551-55I and a plurality of repair circuits 501-50I. Each of the sub column decoders 551-55I can be connected to a corresponding one of the memory sub array blocks SCB, and each of the plurality of repair circuits 501-50I can correspond to one of the plurality of sub column decoders 551-55I. Each of the repair circuits 501-50I can selectively activate a first repair signal CREN1 and a second repair signal CREN2 in response to the column address CADDR and the row block match signal RBMTH to provide the first repair signal CREN1 and the second repair signal CREN2 to a corresponding one of the sub column decoders 551-55I. In addition, each of the repair circuits 501-50I can provide a first switch control signal SCS1 and a second switch control signal SCS2 to a corresponding one of the bit line sense amplifier regions BLSAB and a corresponding one of the connection regions CONJ in response to the column address CADDR and the row block match signal RBMTH.

[0068] Each of the sub column decoders 551-55I can select the column select line CSL or the spare column select line SCSL in response to the first repair signal CREN1 and the second repair signal CREN2. When the first repair signal CREN1 and the second repair signal CREN2 are deactivated by the repair circuits 501-50I, each of the sub column decoders 551-55I can select the column select line CSL.

[0069] When the first repair signal CREN1 is activated and the second repair signal CREN2 is deactivated, each of the sub-column decoders 551 to 55I may select the spare column select line SCSL to activate the first spare bit line SBL0. When the first repair signal CREN1 is deactivated and the second repair signal CREN2 is activated, each of the sub-column decoders 551 to 55I may select the spare column select line SCSL to activate the second spare bit line SBL1.

[0070] Figure 6A is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5 1 is a block diagram of a first row block fuse circuit of a row block fuse circuit.

[0071] Each configuration of the row block fuse circuits 402 ˜ 40J may be substantially the same as that of the first row block fuse circuit 401 .

[0072] refer to Figure 6A , the first row block fuse circuit 401 may include a pre-decoder 405 , a row block information storage table 410 , and a row block (address) comparator 425 .

[0073] The predecoder 405 decodes the row address RADDR to provide the decoded row address DRA to the corresponding sub-word line driver arranged in the sub-word line driver area SWB. In response to the decoded row address DRA provided by the predecoder 405, the corresponding sub-word line driver can activate the word line corresponding to the decoded row address DRA.

[0074] The row block information storage table 410 may store a defective row address FBRB associated with a defective row block including at least one defective cell and row block address information of the corresponding row block. The row block information storage table 410 may provide the defective row address FBRB to the row block comparator 425, and the row block comparator 425 may compare the row block identification bit BRB received from the pre-decoder 405 with the defective row block address FBRB to provide the row block information storage table 410 with a row block matching signal RBMTH indicating the comparison result between the row block identification bit BRB and the defective row block address FBRB. The row block identification bit BRB may include some upper bits of the row address RADDR. For example, as combined with Figure 7 For discussion, when the row address RADDR includes m bits, upper r bits of the row address RADDR may correspond to the row block identification bits BRB.

[0075] Figure 6B An exemplary embodiment according to the present inventive concept is shown. Figure 6A The row block information of the first row block fuse circuit is stored in the table.

[0076] refer to Figure 6BThe row block information storage table 410 includes an anti-fuse array 411, a control unit 412, a read unit 413, and a register unit 414.

[0077] The anti-fuse array 411 includes p*q anti-fuses (AFs) connected to intersections of p rows and q columns. The anti-fuse array 411 includes p word lines AWL1 to AWLp for accessing the anti-fuses (AFs) arranged in the p rows, and q bit lines ABL1 to ABLq arranged to correspond to the q columns, so as to transfer information read from the anti-fuses (AFs).

[0078] The control unit 412 programs a defective row block address FBRB in the anti-fuse array 411, or the control unit 412 reads the defective row block address FBRB from the anti-fuse array 411. The read unit 413 can read and amplify the defective row block address FBRB received from the anti-fuse array 411, and output an amplified result. The register unit 414 can temporarily store the defective row block address FBRB received from the read unit 413. The register unit 414 outputs the defective row block address FBRB to a row block comparator 425 (e.g., Figure 6A

[0079] Figure 7 A block diagram of a first repair circuit of a repair circuit in Figure 6A is shown according to an exemplary embodiment of the inventive concept.

[0080] In Figure 7 , it is assumed that the row address RADDR includes 16 bits A0 to A15.

[0081] Referring to Figure 7 , the upper 3 bits A15 to A13 of the row address RADDR can be designated as row block identification bits BRB. In this case, in the case where the row block identification bits BRB include 3 bits, Figure 3 The storage blocks MB1 to MBk in may be divided into eight row blocks arranged in a second direction D2.

[0082] Figure 8 A block diagram of a first repair circuit of a repair circuit in Figure 5 is shown according to an exemplary embodiment of the inventive concept.

[0083] Each of the repair circuits 502 to 50I can have substantially the same configuration as that of the first repair circuit 501.

[0084] Referring to Figure 8 , the first repair circuit 501 includes a defective address storage table 510, a column address comparator 515, a fuse circuit 520, a switch signal generator 530, and a repair signal generator 540.

[0085] The defect address storage table 510 can store defect column address information FCAI associated with column address information of a defective cell of a corresponding storage block, and can transmit the defect column address information FCAI to the column address comparator 515. The column address comparator 515 can compare the column address CADDR with the defect column address information FCAI received from the defect address storage table 510 to output a column match signal CMTH to the fuse circuit 520 and the repair signal generator 540. The column match signal CMTH can indicate whether the column address CADDR matches the defect column address information FCAI. The defect address storage table 510 can have a similar configuration to that of the row block information storage table 410. Figure 6B

[0086] The fuse circuit 520 includes a plurality of fuse groups 521, 522, and 523. The fuse groups 521, 522, and 523 can correspond to storage blocks constituting a row block. Each of the plurality of fuse groups 521, 522, and 523 can include a first area 521a and a second area 521b. The first area 521a can store spare bit line information SBI of a spare bit line to repair a defective cell in each of the storage blocks, and the second area 521b can store a main fuse bit MFB associated with availability of the spare bit line of the corresponding storage block (e.g., availability of the spare bit line in different storage blocks). In response to the column match signal CMTH, the fuse circuit 520 can provide the spare bit line information SBI and the main fuse bit MFB to the switch signal generator 530, and can provide the main fuse bit MFB to the repair signal generator 540.

[0087] The switch signal generator 530 can generate a first switch control signal SCS1 and a second switch control signal SCS2 based on the row block match signal RBMTH, the spare bit line information SBI, and the main fuse bit MFB. The first switch control signal SCS1 can control turning on / off of a bit line switch connected between a first half local I / O line and a second half local I / O line in one storage block. The second switch control signal SCS2 can control turning on / off of a block switch connected between a second half local I / O line and a first half local I / O line in two adjacent storage blocks.

[0088] The repair signal generator 540 can selectively activate each of a first repair signal CREN1 and a second repair signal CREN2 based on the column match signal CMTH and the main fuse bit MFB. For example, when the column match signal CMTH indicates that the column address CADDR does not match the defect column address information FCAI, the repair signal generator 540 deactivates both the first repair signal CREN1 and the second repair signal CREN2 by applying a low-level voltage signal. When both the first repair signal CREN1 and the second repair signal CREN2 are deactivated, Figure 5 ​The first sub-column decoder 551 in may activate the column selection line CSL.

[0089] For example, when the column match signal CMTH indicates that the column address CADDR matches the defective column address information FCAI and the master fuse bit MFB indicates that the first spare bit line in the corresponding memory block is to be used, the repair signal generator 540 activates the first repair signal CREN1 by applying a high-level voltage signal and deactivates the second repair signal CREN2 by applying a low-level voltage signal. In this case, Figure 5 The first sub-column decoder 551 in selects the spare column selection line SCSL, and the selected spare column selection line SCSL in turn selects the first spare bit line SBL0.

[0090] For example, when the column match signal CMTH indicates that the column address CADDR matches the defective column address information FCAI and the master fuse bit MFB indicates that the second spare bit line in the corresponding segment is to be used, the repair signal generator 540 deactivates the first repair signal CREN1 by applying a low-level voltage signal and activates the second repair signal CREN2 by applying a high-level voltage signal. In this case, Figure 5 The first sub-column decoder 551 in the MCU selects the spare column selection line SCSL, and the selected spare column selection line SCSL further selects the second spare bit line SBL1.

[0091] For example, when the column match signal CMTH indicates that the column address CADDR matches the defective column address information FCAI and the master fuse bit MFB indicates that the spare bit line in the corresponding segment is unavailable, the repair signal generator 540 deactivates the first repair signal CREN1 by applying a low-level voltage signal, and deactivates the second repair signal CREN2 by applying a low-level voltage signal. In this case, Figure 5 The first sub-column decoder 551 in selects the spare column selection line SCSL, the block switch is connected and the first spare bit line SBL0 in the memory block adjacent to the corresponding memory block is selected.

[0092] Figure 9 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5 Block diagram of a first sub-column decoder of the sub-column decoders in FIG.

[0093] The configuration of each of the sub-column decoders 551 ˜ 55I may be substantially the same as the configuration of the first sub-column decoder 551 .

[0094] refer to Figure 9 , the first sub-column decoder 551 may include a column select line (CSL) driver 560 and a spare column select line (SCSL) driver 565 .

[0095] The column selection line driver 560 can select one of the column selection lines CSL in response to the column address CADDR and the column match signal CMTH. When the column match signal CMTH is at a high level CMTH, the column selection line driver 560 does not select the column selection lines CSL. To this end, the column selection line driver 560 can first receive the column match signal CMTH before selecting any of the column selection lines CSL. The spare column selection line driver 565 can select one of the first spare column selection line SCSLO and the second spare column selection line SCSLl in response to the column match signal CMTH, the first repair signal CRENl, and the second repair signal CREN2.

[0096] Figure 10 A portion of a memory cell array in a memory device according to an example embodiment of the present inventive concept is shown. Figure 5

[0097] Referring to Figure 5 and Figure 10 In a portion 390 of the memory cell array 300a (390), Figure 5 the sub-array blocks SCBl and SCB2, the bit line sense amplifier regions BLSABl and BLSAB2, the sub-word line driver region SWB, and the connection region CONJ can be arranged.

[0098] The sub-array block SCBl includes a plurality of word lines WLl to WL4 extending in a row direction (first direction Dl) and a plurality of bit line pairs BLl to BL2 and BLBl to BLB2 extending in a column direction (second direction D2). The sub-array block SCBl includes a plurality of memory cells MC arranged at intersections between the word lines WLl to WL4 and the bit line pairs BLl to BL2 and BLBl to BLB2.

[0099] The sub-word line driver region SWB includes a plurality of sub-word line drivers (SWD) 571, 572, 573, and 574 that respectively drive the word lines WLl to WL4. The sub-word line drivers (SWD) 571, 572, 573, and 574 can be arranged in different regions with respect to the sub-array block SCB. For example, the sub-word line drivers 571 and 572 can be arranged in the sub-word line driver region SWB to the left (in this example) with respect to the sub-array block SCB. In addition, the sub-word line drivers 573 and 574 can be arranged in the sub-word line driver region SWB to the right (in this example) with respect to the sub-array block SCB.

[0100] ​The bit line sense amplifier region BLSAB1 includes a bit line sense amplifier BLSA 650 coupled to the bit line pair BL1~BL2 and BLB1~BLB2 and a local sense amplifier circuit 700. For example, the bit line sense amplifier BLSA 650 is coupled to the bit lines BL1 and BLB1 and can sense and amplify a voltage difference between the corresponding bit line pair BL1 and BLB1 to provide the amplified voltage difference to the corresponding local I / O line pair LIO1 and LIOB1. For example, in the case of the bit lines BL1 and BLB1, the amplified voltage difference can be provided to the local I / O line pair LIO1 and LIOB1 and in the case of the bit lines BL2 and BLB2, the amplified voltage difference can be provided to another local I / O line pair. The local sense amplifier circuit 700 controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1.

[0101] As shown in Figure 10 , the bit line sense amplifiers (such as the bit line sense amplifier 650) can be alternately arranged in the upper and lower portions of the bit line sense amplifier region BLSAB1. The connection region CONJ is arranged adjacent to the bit line sense amplifier regions BLSAB1 and BLSAB2, the sub word line driver region SWB, and the sub array blocks SCB1 and SCB2. The plurality of voltage generators 610 and 630 can be arranged in the connection region CONJ. In Figure 10 , the memory cells MC coupled to the word lines WL1~WL4 and the bit line pairs BL1~BL2 and BLB1~BLB2 are shown. The sub array block SCB1 can include spare cells coupled to the word lines WL1~WL4, a first spare bit line, and a second spare bit line.

[0102] Figure 11 A portion of Figure 10 , in accordance with the exemplary embodiments of this invention is shown.

[0103] Referring to Figure 11 , a portion 680 of the portion 390 includes the bit line sense amplifier regions BLSAB1 and BLSAB2 and a connection region CONJ arranged adjacent to the bit line sense amplifier regions BLSAB1 and BLSAB2.

[0104] The bit line sense amplifier region BLSAB1 can include a first set of bit line sense amplifiers BLSAG11 connected to a first set of bit lines (bit line pairs) BL1-BLB16 of a corresponding memory block, a second set of bit line sense amplifiers BLSAG12 connected to a second set of bit lines (bit line pairs) BLB17-BLB32 of the corresponding memory block, and a local sense amplifier circuit 700. The bit line sense amplifier region BLSAB1 can also include a first half local I / O line (line pair) LIO1_H1 and LIO1B_H1 connected to the first set of bit lines BL1-BLB16 through the first set of bit line sense amplifiers BLSAG11, a second half local I / O line (line pair) LIO1_H2 and LIO1B_H2 connected to the second set of bit lines BLB17-BLB32 through the second set of bit line sense amplifiers BLSAG12, bit line switches 681, 682, 683, and 684, and an inverter INV1.

[0105] The bit line switches 681 and 682 are connected between the first half local I / O line LIO1_H1 and the second half local I / O line LIO1_H2 and control the connection of the first half local I / O line LIO1_H1 and the second half local I / O line LIO1_H2 in response to a first switch control signal SCS1 and an inverted version of the first switch control signal SCS1, respectively. The local sense amplifier circuit 700 is connected to a first node N11 between the bit line switches 681 and 682, a second node N12 between the bit line switches 683 and 684, and global I / O lines GIO1 and GIO1B.

[0106] The bit line switches 683 and 684, the first half local I / O line LIO1B_H1, and the second half local I / O line LIO1B_H2 can be configured substantially the same as the bit line switches 681 and 682, the first half local I / O line LIO1_H1, and the second half local I / O line LIO1_H2.

[0107] The bit line sense amplifier region BLSAB2 can include a first group of bit line sense amplifiers BLSAG21 connected to a first group of bit lines (bit line pairs) BL1-BLB16 of a corresponding memory block, a second group of bit line sense amplifiers BLSAG22 connected to a second group of bit lines (bit line pairs) BLB17-BLB32 of the corresponding memory block, and a local sense amplifier circuit 700a. The bit line sense amplifier region BLSAB2 can also include a first half local I / O line (line pair) LIO2_H1 and LIO2B_H1 connected to the first group of bit lines BL1-BLB16 through the first group of bit line sense amplifiers BLSAG21, a second half local I / O line (line pair) LIO2_H2 and LIO2B_H2 connected to the second group of bit lines BLB17-BLB32 through the second group of bit line sense amplifiers BLSAG22, bit line switches 685, 686, 687, and 688, and an inverter INV2.

[0108] The bit line switches 685 and 686 are connected between the first half local I / O line LIO2_H1 and the second half local I / O line LIO2_H2 and control the connection of the first half local I / O line LIO2_H1 and the second half local I / O line LIO2_H2 in response to a first switch control signal SCS1 and an inverted version of the first switch control signal SCS1, respectively. The local sense amplifier circuit 700a is connected to a first node N21 between the bit line switches 685 and 686, a second node N22 between the bit line switches 687 and 688, and global I / O lines GIO2 and GIO2B.

[0109] The bit line switches 687 and 688, the first half local I / O line LIO2B_H1, and the second half local I / O line LIO2B_H2 can be configured substantially the same as the bit line switches 685 and 686, the first half local I / O line LIO2_H1, and the second half local I / O line LIO2_H2.

[0110] The connection region CONJ can include block switches 691 and 692. The block switch 691 is connected between the second half local I / O line LIO1_H2 and the first half local I / O line LIO2_H1 in two adjacent memory blocks and controls the connection of the second half local I / O line LIO1_H2 and the first half local I / O line LIO2_H1 in response to a second switch control signal SCS2. The block switch 692 is connected between the second half local I / O line LIO1B_H2 and the first half local I / O line LIO2B_H1 in the two adjacent memory blocks and controls the connection of the second half local I / O line LIO1B_H2 and the first half local I / O line LIO2B_H1 in response to the second switch control signal SCS2.

[0111] Figure 12is a circuit diagram illustrating a bit line sense amplifier in Figure 10

[0112] Referring to Figure 12 , a bit line sense amplifier (BLSA) 650 is coupled to bit lines BL1 and BLB1 of each of memory cells 660 and 670 in the memory cell array 300. The bit line sense amplifier 650 includes an N-type sense amplifier 651, a P-type sense amplifier 652, a pre-charge circuit 653, column selection switches 654a and 654b, an N-type sense amplifier (NSA) driver 655, and a P-type sense amplifier (PSA) driver 656.

[0113] The N-type sense amplifier 651 discharges low voltage bit lines of the bit lines (or bit line pair) BL1 and BLB1 to a low voltage during a sense operation. The N-type sense amplifier 651 includes two n-channel metal oxide semiconductor (NMOS) transistors NM1 and NM2. The gate of the NMOS transistor NM1 is connected to the bit line (second bit line) BLB1, and the drain of the NMOS transistor NM1 is connected to the bit line (first bit line) BL1, and the source of the NMOS transistor NM1 is connected to a sense enable line LAB. The NMOS transistor NM2 has a gate connected to the bit line BL1, a drain connected to the sense enable line LAB, and a source connected to the bit line BLB1.

[0114] The N-type sense amplifier 651 connects the low voltage bit lines to the sense enable line LAB.

[0115] The P-type sense amplifier 652 charges high voltage bit lines of the bit lines BL1 and BLB1 with a supply voltage VDD during a sense operation. The P-type sense amplifier 652 includes two p-channel metal oxide semiconductor (PMOS) transistors PM1 and PM2. The PMOS transistor PM1 has a gate connected to the bit line BLB1, a source connected to the bit line BL1, and a drain connected to a sense enable line LA. The PMOS transistor PM2 has a gate connected to the bit line BL1, a source connected to the sense enable line LA, and a drain connected to the bit line BLB1.

[0116] The P-type sense amplifier 652 charges the high voltage bit lines of the bit lines BL1 and BLB1 with the supply voltage VDD provided to the sense enable line LA.

[0117] The PSA driver 656 provides a charging voltage (e.g., the supply voltage VDD) to the sense enable line LA. Thus, because the gate of the transistor PM2 is coupled to the bit line BL1 with a voltage increased by charge sharing, the transistor PM2 is turned off. The PSA driver 656 includes a PMOS transistor P1.

[0118] ​The precharge circuit 653 precharges the bit lines BL1 and BLB1 with the half voltage VDD / 2 in response to a control signal PEQ in a read operation. When the control signal PEQ is activated, the precharge circuit 653 supplies a bit line precharge voltage VBL to the bit lines BL1 and BLB1. The bit line precharge voltage VBL can be the half voltage VDD / 2. The bit lines BL1 and BLB1 are connected such that their voltages are equal. If the bit lines BL1 and BLB1 are charged with the bit line precharge voltage VBL, the control signal PEQ is deactivated. The precharge circuit 653 includes NMOS transistors N3, N4, and N5.

[0119] The column selection switches 654a and 654b supply data read by the N-type read amplifier 651 and the P-type read amplifier 652 to the input / output lines LIO1 and LIOB1 in response to a column selection signal CSL. The column selection switches 654a and 654b are turned on so that the read data is transferred to the input / output lines LIO1 and LIOB1. For example, in a read operation, when the read levels of the N-type read amplifier 651 and the P-type read amplifier 652 are stabilized, the column selection signal CSL is activated. Then, the column selection switches 654a and 654b are turned on so that the read data is transferred to the local I / O line pair LIO1 and LIOB1. When the charges of the bit lines BL1 and BLB1 are shared with the input / output lines LIO1 and LIOB1, the voltages of the bit lines BL1 and BLB1 vary. The column selection switches 654a and 654b include NMOS transistors N6 and N7, respectively.

[0120] The NSA driver 655 supplies a driving signal to the read enable line LAB of the N-type read amplifier 651. The NSA driver 655 receives a control signal LANG. Based on the control signal LANG, the NSA driver 655 grounds the read enable line LAB. The NSA driver 655 includes a ground transistor N1 connected to a ground voltage VSS to control the voltage of the read enable line LAB. The PSA driver 656 supplies a power supply voltage VDD to the read enable line LA of the P-type read amplifier 652. The PSA driver 656 is controlled by a control signal LAPG. The control signals LAPG and LANG are complementary to each other.

[0121] Figure 13 A local read amplifier circuit according to an exemplary embodiment of the inventive concept is shown in Figure 11 .

[0122] Reference Figure 13 , the local read amplifier circuit 700 includes a local read amplifier 710 and a local I / O line controller 720.

[0123] The local sense amplifier 710 amplifies a voltage difference between the first half local I / O line pair LIO1_H1 and LIO1B_H1 or between the second half local I / O line pair LIO1_H2 and LIO1B_H2 in response to a local sense enable signal PLSAEN to provide the amplified voltage difference to the global I / O line pair GIO1 and GIOB1. The local I / O line controller 720 includes first to fourth NMOS transistors 721, 722, 723, and 724 and controls connection between the global I / O line pair GIO1 and GIO1B and one of the first half local I / O line pair LIO1_H1 and LIO1B_H1 and the second half local I / O line pair LIO1_H2 and LIO1B_H2 in response to first and second connection control signals PMUXON1 and PMUXON2.

[0124] The configuration of the local sense amplifier circuit 700a is substantially the same as that of the local sense amplifier circuit 700. The local sense amplifier circuit 700a amplifies a voltage difference between the first half local I / O line pair LIO2_H1 and LIO2B_H1 or between the second half local I / O line pair LIO2_H2 and LIO2B_H2 in response to a local sense enable signal PLSAEN to provide the amplified voltage difference to the global I / O line pair GIO2 and GIO2B. The local sense amplifier circuit 700a controls connection between the global I / O line pair GIO2 and GIO2B and one of the first half local I / O line pair LIO2_H1 and LIO2B_H1 and the second half local I / O line pair LIO2_H2 and LIO2B_H2 in response to first and second connection control signals PMUXON1 and PMUXON2.

[0125] Figures 14A-14E A semiconductor storage device performing column repair according to an example embodiment of the present inventive concept is shown.

[0126] In Figures 14A-14E , it is assumed that the memory cell array 300 or 300a includes memory blocks MB1 to MB4, and each of the memory blocks MB1 to MB4 includes eight bit lines, a first spare bit line selected by a spare column selection line SCSL0, and a second spare bit line selected by a spare column selection line SCSL1. In Figures 14A-14E , an × indicates a defective cell, a dashed arrow indicates an unused SCSL, and a solid arrow indicates a used SCSL.

[0127] Referring to Figure 14A , the memory block (first memory block) MB2 includes a defective cell × selected by a column selection line CSL0.

[0128] Referring to Figure 14Bcolumn decoder 271 Figure 5 The first spare bit line in the first memory block MB2 is used by the column decoder 271 to repair the first bit line coupled to the defective cell in the first memory block MB2. Four bits of data are output through the global data lines GIO1-GIO4 of the memory blocks MB1-MB4 when the column select line CSL0 is connected.

[0129] Referring to Figure 14C The second spare bit line (selected by SCSL1) in the memory block (second memory block) MB1, which is adjacent to the first memory block MB2 in the direction of the first half local I / O line, is used by the column decoder 271 to repair the first bit line coupled to the defective cell in the first memory block MB2, as indicated by reference numeral 731. In this case, the block switch between the first memory block MB2 and the second memory block MB1 connects the first half local I / O line in the first memory block MB2 and the second half local I / O line in the second memory block MB1. Four bits of data are output through the global data lines GIO1-GIO4 of the memory blocks MB1-MB4 when the column select line CSL0 is connected.

[0130] Referring to Figure 14D The second spare bit line (selected by SCSL1) in the memory block (second memory block) MB3, which is adjacent to the first memory block MB2 in the direction of the second half local I / O line, is used by the column decoder 271 to repair the first bit line coupled to the defective cell in the first memory block MB2. The column decoder 271 replaces the defective cell with a normal cell in the second memory block MB3, as indicated by reference numeral 741, and repairs the normal cell in the second memory block MB3 with the second spare bit line (selected by SCSL1) in the second memory block MB3, as indicated by reference numeral 742. In this case, the block switch between the first memory block MB2 and the second memory block MB3 connects the second half local I / O line in the first memory block MB2 and the first half local I / O line in the second memory block MB3. Four bits of data are output through the global data lines GIO1-GIO4 of the memory blocks MB1-MB4 when the column select line CSL0 is connected.

[0131] Referring to Figure 14Ecolumn decoder 271 employs a second spare bit line (selected by SCSL1) in a storage block (second storage block) MB3 adjacent to the first storage block MB2 in the direction of the second half local I / O line to repair the first bit line coupled to the defective cell in the first storage block MB2. The column decoder 271 employs a normal cell in the second storage block MB3 to replace the defective cell, as indicated by reference numeral 751, employs a normal cell in a storage block (third storage block) MB4 to replace the normal cell in the second storage block MB3, as indicated by reference numeral 752, and employs a second spare bit line (selected by SCSL1) in the third storage block MB4 to repair the normal cell in the third storage block MB4, as indicated by reference numeral 753. In this case, the block switch between the first storage block MB2 and the second storage block MB3 connects the second half local I / O line in the first storage block MB2 and the first half local I / O line in the second storage block MB3, and the block switch between the second storage block MB3 and the third storage block MB4 connects the second half local I / O line in the second storage block MB3 and the first half local I / O line in the third storage block MB4. Four-bit data is output through the global data lines GIO1 to GIO4 of the storage blocks MB1 to MB4 when the column selection line CSL0 is connected.

[0132] Figure 15 A semiconductor memory device performing column repair according to an exemplary embodiment of the inventive concept is illustrated.

[0133] In Figure 15 , x indicates a defective cell, a dashed arrow indicates an unused SCSL, and a solid arrow indicates a used SCSL. In Figure 15 , it is assumed that a first bit line, a second bit line, and a third bit line selected by column selection lines CL0, CSL1, and CSL4, respectively, are connected to defective cells in a first storage block MB2.

[0134] Referring to Figure 15 , the column decoder 271 employs a first spare bit line in the first storage block MB2 to repair the first bit line, as indicated by reference numeral 761, employs a second spare bit in the first storage block MB2 to repair the second bit line, as indicated by reference numeral 762, and employs a first bit line in a second storage block MB3 adjacent to the first storage block MB2 in the direction of the second half local I / O line to repair the third bit line, as indicated by reference numeral 763.

[0135] Figure 16 A semiconductor memory device performing column repair according to an exemplary embodiment of the inventive concept is illustrated.

[0136] In Figure 16In this case, x indicates a defective cell, a dotted arrow indicates an unused SCSL, and a solid arrow indicates a used SCSL. Figure 16 In this case, it is assumed that the first and second bit lines selected by the column selection lines CL0 and CSL1, respectively, are connected to the defective cell of each of the memory blocks MB1 and MB2.

[0137] Referring to Figure 16 , the column decoder 271 repairs the first bit line of each of the memory blocks MB1 and MB2 using the first spare bit line in each of the memory blocks MB1 and MB2, as indicated by reference numerals 771 and 773, and repairs the second bit line of each of the memory blocks MB1 and MB2 using the second spare bit line in each of the memory blocks MB1 and MB2, as indicated by reference numerals 772 and 774, respectively.

[0138] Figures 17A-17E A semiconductor memory device performing column repair according to an exemplary embodiment of the inventive concept is illustrated.

[0139] In Figures 17A-17E , it is assumed that the memory cell array 300 or 300a includes memory blocks MB1 to MB4, and each of the memory blocks MB1 to MB4 includes eight bit lines (denoted by 0 to 7). In Figures 17A-17E , x indicates a defective cell, a dotted arrow indicates an unused SCSL, and a solid arrow indicates a used SCSL.

[0140] Referring to Figure 17A , all of the bit lines of the memory block MB3 are connected to a defective cell.

[0141] Referring to Figure 17B , the column decoder 271 repairs the first bit line in the memory block MB3 using the second spare bit line (selected by SCSL1) in the adjacent memory block MB4, as indicated by reference numeral 782, repairs the second bit line in the memory block MB3 using the second spare bit line in the memory block MB3, as indicated by reference numeral 781, repairs the fifth bit line in the memory block MB3 using the first spare bit line (selected by SCSL0) in the memory block MB1, as indicated by reference numeral 783, and repairs the sixth bit line in the memory block MB3 using the first spare bit line in the memory block MB2, as indicated by reference numeral 784.

[0142] Referring to Figure 17C , the column decoder 271 repairs the third bit line in the memory block MB3 using the second spare bit line in the memory block MB2, as indicated by reference numeral 785, and repairs the seventh bit line in the memory block MB3 using the first spare bit line in the memory block MB4, as indicated by reference numeral 786.

[0143] Referring to Figure 17D The column decoder 271 repairs the fourth bit line in the memory block MB3 using the first spare bit line in the memory block MB3, as indicated by reference numeral 787.

[0144] Referring to Figure 17E The column decoder 271 repairs the eighth bit line in the memory block MB3 using the second spare bit line in the memory block MB1, as indicated by reference numeral 788, and swaps the fourth bit line in the memory block MB1 using the eighth bit line in the memory block MB1, as indicated by reference numeral 789.

[0145] Figure 18 is a block diagram illustrating a semiconductor memory device in a memory system according to an exemplary embodiment of the present inventive concept. Figure 1

[0146] Referring to Figure 18 The semiconductor memory device 200b includes a control logic circuit 210, an address register 220, a bank control logic 230, a refresh counter 245, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300b, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, an ECC engine 280, and a data I / O buffer 295.

[0147] The memory cell array 300b includes first to eighth bank arrays 310 to 380. The row decoder 260 includes first to eighth bank row decoders 260a to 260h coupled to the first to eighth bank arrays 310 to 380, respectively, the column decoder 270 includes first to eighth bank column decoders 270a to 270h coupled to the first to eighth bank arrays 310 to 380, respectively, and the sense amplifier unit 285 includes first to eighth bank sense amplifiers 285a to 285h coupled to the first to eighth bank arrays 310 to 380, respectively. The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h can form first to eighth banks. Each of the first to eighth bank arrays 310 to 380 includes a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BL.

[0148] ​The address register 220 receives an address ADDR, including a bank address BANK_ADDR, a row address RADDR, and a column address CADDR, from the memory controller 100. The address register 220 supplies the received bank address BANK_ADDR to the bank control logic 230, supplies the received row address RADDR to the row address multiplexer 240, and supplies the received column address CADDR to the column address latch 250.

[0149] The bank control logic 230 generates bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, one of the first to eighth bank row decoders 260a to 260h corresponding to the bank address BANK_ADDR is activated; and in response to the bank control signals, one of the first to eighth bank column decoders 270a to 270h corresponding to the bank address BANK_ADDR is activated.

[0150] The row address multiplexer 240 receives the row address RADDR from the address register 220 and receives a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 selectively outputs the row address RADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 240 is applied to the first to eighth bank row decoders 260a to 260h.

[0151] The activated one of the first to eighth bank row decoders 260a to 260h activated by the bank control logic 230 decodes the row address RA output from the row address multiplexer 240 and activates a word line WL corresponding to the row address RA. For example, the activated bank row decoder applies a word line drive voltage to the word line WL corresponding to the row address RA. In addition, the activated bank row decoder activates a spare word line corresponding to a spare row address SRA output from the activated bank row decoder's row block information circuit 400 (see, for example, Figure 3 ) substantially simultaneously with activating the word line corresponding to the row address RA.

[0152] The column address latch 250 receives the column address CADDR from the address register 220 and temporarily stores the received column address CADDR. For example, the column address latch 250 can temporarily store the received column address CADDR in an internal memory of the column address latch 250. In an exemplary embodiment of the inventive concept, in the burst mode, the column address latch 250 generates column addresses that are incremented from the received column address CADDR. The column address latch 250 applies the temporarily stored or generated column address CADDR to the first to eighth bank column decoders 270a to 270h.

[0153] One of the first to eighth bank column decoders 270a to 270h that is activated activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address CADDR through the I / O gate circuit 290. The I / O gate circuit 290 includes a circuit for gating input / output data, and further includes a read data latch for storing data output from the first to eighth bank arrays 310 to 380 and a write driver for writing data into the first to eighth bank arrays 310 to 380.

[0154] The codeword CW read from one of the first to eighth bank arrays 310 to 380 is read by a sense amplifier coupled to the one bank array from which data is to be read, and is stored in the read data latch of the I / O gate circuit 290. After ECC decoding of the codeword CW is performed by the ECC engine 280, the codeword CW stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295. After ECC encoding of the data DQ is performed by the ECC engine 280, the data DQ provided from the memory controller 100 to the data I / O buffer 295 is written into one of the first to eighth bank arrays 310 to 380 by the write driver of the I / O gate circuit 290.

[0155] The data I / O buffer 295 can provide the data DQ from the memory controller 100 to the ECC engine 280 in a write operation of the semiconductor memory device 200b based on the clock signal CLK, and can provide the data DQ from the ECC engine 280 to the memory controller 100 in a read operation of the semiconductor memory device 200b.

[0156] In a write operation, the ECC engine 280 can generate the parity bits based on the data DQ from the data I / O buffer 295 and can provide the codeword CW including the data DQ and the parity bits to the I / O gating circuit 290. The I / O gating circuit 290 can write the codeword CW to one of the bank arrays. In a read operation, the ECC engine 280 can receive the codeword CW read from one of the bank arrays from the I / O gating circuit 290. The ECC engine 280 can perform ECC decoding on the data DQ based on the parity bits in the codeword CW, can correct at least one error bit in the data DQ, and can provide the corrected data to the data I / O buffer 295.

[0157] The control logic circuit 210 can control the operation of the semiconductor memory device 200b. For example, the control logic circuit 210 can generate a control signal for the semiconductor memory device 200b to perform a write operation or a read operation. The control logic circuit 210 includes a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200b.

[0158] Each of the first to eighth bank arrays 310 to 380 can have substantially the same configuration as the memory cell array 300a in the semiconductor memory device 200a, and each of the first to eighth bank column decoders 270a to 270h can include a repair circuit, such as the repair circuit 501 to 50I in the semiconductor memory device 200a. Figure 5 Figure 5

[0159] Figure 19 FIG. 4 is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0160] Referring to FIG. 4, Figures 2A-19 ​​In a method of operating a semiconductor memory device 200, the semiconductor memory device 200 includes a memory cell array including a plurality of memory blocks coupled to at least one word line, each of the plurality of memory blocks including a plurality of dynamic memory cells, at least one bit line switch coupled between a first semi-local input / output (I / O) line of a first memory block among the memory blocks and a second semi-local I / O line of the first memory block, and at least one block switch connected between the second semi-local I / O line of the first memory block and a first semi-local I / O line of a second memory block adjacent to the first memory block. The first semi-local I / O line of the first memory block is connected to a first group of bit lines among the plurality of bit lines of the first memory block, and the second semi-local I / O line is connected to a second group of bit lines among the plurality of bit lines. In operation S100, a column decoder 271 deactivates a first bit line coupled to a defective cell of the first memory block in response to a column address CADDR. In operation S200, the column decoder 271 repairs the defective cell by controlling the at least one bit line switch and the at least one block switch to activate a spare bit line of the first memory block or a spare bit line of the second memory block.

[0161] The column decoder 271 can control a connection between the first semi-local I / O line of the first memory block and the second semi-local I / O line of the first memory block and a connection between the second semi-local I / O of the first memory block and the first semi-local I / O line of the second memory block by applying a first switch control signal to the at least one bit line switch and by applying a second switch control signal to the at least one block switch to repair the defective cell.

[0162] According to an exemplary embodiment of the inventive concept, the semiconductor memory device 200 equally allocates a redundancy resource in a memory block and can use a spare bit line in an adjacent memory block by controlling a bit line switch and a block switch. Accordingly, the semiconductor memory device 200 having a distributed redundancy architecture can improve performance by increasing column repair flexibility and repairing a block failure.

[0163] Figure 20 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0164] Reference Figure 20 The semiconductor memory device 800 can include a first group of dies 810 and a second group of dies 820.

[0165] The first group of dies 810 can include at least one buffer die 811. The second group of dies 820 can include a plurality of memory dies 820-1 through 820-s stacked on the first group of dies 810 and communicating data through a plurality of through-silicon via (TSV) lines extending from the memory die 820-s through intermediate memory dies 820-s-1 through 820-1 to the first group of dies 810.

[0166] Each of the storage dies 820-1 to 820-s can include a cell core 822 including storage blocks, and each of the storage blocks includes a storage cell coupled to a word line and a bit line and a spare cell coupled to the word line, a first spare bit line, and a second spare bit line. In addition, the cell core 822 includes the above-described bit line switch and the block switch.

[0167] The buffer die 811 can include an ECC engine 812 that uses transmission parity bits to correct a transmission error and generate error-corrected data when a transmission error is detected from transmission data received through the TSV lines. The ECC engine 812 can be referred to as a "via ECC engine." The buffer die 811 can further include an address decoder 814, and the address decoder 814 can employ row decoders 261 and column decoders 271 in the memory controller 810. Figure 3 The address decoder 814 can apply a switch control signal to the cell core 822.

[0168] The data TSV line group 832 formed at one of the storage dies 820-s can include a plurality of TSV lines L1 to Ls, and the parity TSV line group 834 can include a plurality of TSV lines L10 to Lt. The TSV lines L1 to Ls of the data TSV line group 832 and the parity TSV lines L10 to Lt of the parity TSV line group 834 can be connected to a micro bump MCB, which is formed correspondingly between the storage dies 820-1 to 820-s.

[0169] Each of the storage dies 820-1 to 820-s can include a DRAM cell including at least one access transistor and one storage capacitor.

[0170] The semiconductor storage device 800 can have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the memory controller through a data bus B10. The buffer chip 811 can be connected with the memory controller through the data bus B10.

[0171] The ECC engine 812, which is referred to as a via ECC engine, can determine whether a transmission error occurs in transmission data received through the data TSV line group 832 based on transmission parity bits received through the parity TSV line group 834. When a transmission error is detected, the ECC engine 812 can use the transmission parity bits to correct the transmission error in the transmission data. When the transmission error is uncorrectable, the ECC engine 812 can output information indicating that an uncorrectable data error occurs.

[0172] Figure 21is a diagram illustrating a semiconductor package including stacked memory devices according to an exemplary embodiment of the present inventive concept.

[0173] Referring to Figure 20 , the semiconductor package 900 can include one or more stacked memory devices 910 and a memory controller 920. The stacked memory devices 910 and the memory controller 920 can be mounted on an interposer 930, and the interposer 930 on which the stacked memory devices 910 and the memory controller 920 are mounted can be mounted on a package substrate 940. In an exemplary embodiment of the present inventive concept, one of the stacked memory devices 910 can employ the semiconductor memory device 800 in Figure 20 , and the memory controller 920 can employ the memory controller 100 in Figure 1 .

[0174] Each of the stacked memory devices 910 can be implemented in various forms, and can be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. Accordingly, each of the stacked memory devices 910 can include a buffer die and a plurality of memory dies.

[0175] As described above, the stacked memory devices 910 can be mounted on the interposer 930, and the memory controller 920 can communicate with the stacked memory devices 910. For example, each of the stacked memory devices 910 and the memory controller 920 can include a physical region, and communication can be performed between the stacked memory devices 910 and the memory controller 920 through the physical region. Meanwhile, when each of the stacked memory devices 910 includes a direct access region, a test signal can be provided to each of the stacked memory devices 910 through a conductive device (e.g., a solder ball 950) mounted under the package substrate 940 and the direct access region.

[0176] An exemplary embodiment of the present inventive concept can be applied to a system using a semiconductor memory device.

[0177] As described above, according to an exemplary embodiment of the present inventive concept, a semiconductor memory device equally allocates a redundant resource in a memory block, and can use a spare bit line in an adjacent memory block by controlling a bit line switch and a block switch. Accordingly, a semiconductor memory device having a distributed redundant architecture can improve performance by increasing column repair flexibility and repairing a block failure.

[0178] While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various modifications in form and details can be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor storage device comprising: a memory cell array comprising a plurality of memory blocks coupled to at least one word line, wherein each of the plurality of memory blocks comprises a plurality of dynamic memory cells; at least one bit line switch connected between a first semi-local input / output (I / O) line of a first memory block among the plurality of memory blocks and a second semi-local I / O line of the first memory block, wherein the first semi-local I / O line of the first memory block is connected to a first group of bit lines among the plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block is connected to a second group of bit lines among the plurality of bit lines; at least one block switch connected between a second half local I / O line of a first memory block and a first half local I / O line of a second memory block among the plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and A column decoder comprising a repair circuit, wherein the repair circuit is configured to control a connection between a first semi-local I / O line of a first memory block and a second semi-local I / O line of the first memory block by applying a first switch control signal to at least one bit line switch, and is configured to control a connection between the second semi-local I / O line of the first memory block and the first semi-local I / O line of the second memory block by applying a second switch control signal to at least one block switch, in, The first group of bit lines includes at least a first spare bit line coupled to a first spare cell among the plurality of dynamic memory cells. The second group of bit lines includes at least a second spare bit line, the second spare bit line is coupled to a second spare cell among the plurality of dynamic memory cells, The first set of bit lines is connected to the first half of the local I / O lines of the first memory block through a first bit line sense amplifier, and The second group of bit lines is connected to the second half of the local I / O lines of the first memory block through second bit line sense amplifiers.

2. The semiconductor memory device according to claim 1 , further comprising a local sense amplifier circuit corresponding to the first memory block, in, The local sense amplifier circuit is connected to a first half local I / O line of the first memory block and a second half local I / O line of the first memory block through at least one bit line switch, and Wherein, the local sense amplifier circuit is connected to the global I / O line.

3. The semiconductor memory device according to claim 1, wherein The repair circuit is configured to connect the second half local I / O line of the first memory block and the first half local I / O line of the second memory block by applying the second switch control signal to at least one block switch.

4. The semiconductor memory device according to claim 3, wherein If the second half local I / O line of the first memory block and the first half local I / O line of the second memory block are connected to each other, at least one spare bit line of the second memory block is connected to a local sense amplifier circuit corresponding to the first memory block.

5. The semiconductor memory device according to claim 1, wherein The at least one bit line switch comprises: a first bit line switch connected between the first semi-local I / O line of the first memory block and a first node; and A second bit line switch is connected between the first node and a second half local I / O line of the first memory block. The semiconductor memory device according to claim 5 , wherein: The repair circuit is configured to apply the first switch control signal to the first bit line switch, and is configured to apply an inverted version of the first switch control signal to the second bit line switch.

7. A semiconductor storage device comprising: a memory cell array comprising a plurality of memory blocks coupled to at least one word line, wherein each of the plurality of memory blocks comprises a plurality of dynamic memory cells; at least one bit line switch coupled between a first semi-local input / output (I / O) line of a first memory block among a plurality of memory blocks and a second semi-local I / O line of the first memory block, wherein the first semi-local I / O line of the first memory block is connected to a first group of bit lines among a plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block is connected to a second group of bit lines among the plurality of bit lines; at least one block switch connected between a second half local I / O line of the first memory block and a first half local I / O line of a second memory block among a plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and a column decoder configured to repair a first bit line of the first memory block using at least one spare bit line of the first memory block or a spare bit line of a memory block adjacent to the first memory block by controlling at least one bit line switch and at least one block switch; in, The first bit line is coupled to a defective cell among the plurality of dynamic memory cells, The first group of bit lines includes at least a first spare bit line coupled to a first spare cell among the plurality of dynamic memory cells. The second group of bit lines includes at least a second spare bit line coupled to a second spare cell among the plurality of dynamic memory cells, and Wherein, if the second bit line and the third bit line are connected to a defective cell, the column decoder is configured to: using a first spare bit line of the first memory block to repair a first bit line; repairing the second bit line using the second spare bit line of the first memory block; and The third bit line is repaired using the first spare bit line of the second memory block adjacent to the first memory block in the direction of the second half local I / O line of the first memory block.

8. The semiconductor memory device according to claim 7, wherein The column decoder includes a repair circuit, and Wherein, the repair circuit is configured to control the connection between the first semi-local I / O line of the first storage block and the second semi-local I / O line of the first storage block by applying a first switch control signal to at least one bit line switch, and is configured to control the connection between the second semi-local I / O line of the first storage block and the first semi-local I / O line of the second storage block by applying a second switch control signal to at least one block switch.

9. The semiconductor memory device according to claim 7, wherein The column decoder is configured to repair the first bit line of the first memory block using the first spare bit line of the first memory block.

10. The semiconductor memory device according to claim 7, wherein The column decoder is configured to repair the first bit line of the first memory block using a second spare bit line of a third memory block adjacent to the first memory block in a direction of a first half local I / O line of the first memory block.

11. The semiconductor memory device according to claim 7, wherein The column decoder is configured to repair the first bit line of the first memory block using a second spare bit line of a second memory block adjacent to the first memory block in a direction of a second half local I / O line of the first memory block.

12. The semiconductor memory device according to claim 7, wherein The column decoder is configured to repair the first bit line of the first memory block by using a second spare bit line of a third memory block adjacent to the second memory block in a direction of a second half local I / O line of the first memory block, and The second storage block is adjacent to the first storage block in a direction of the second half local I / O line of the first storage block.

13. A semiconductor storage device comprising: a memory cell array comprising a plurality of memory blocks coupled to at least one word line, wherein each of the plurality of memory blocks comprises a plurality of dynamic memory cells; at least one bit line switch coupled between a first semi-local input / output (I / O) line of a first memory block among a plurality of memory blocks and a second semi-local I / O line of the first memory block, wherein the first semi-local I / O line of the first memory block is connected to a first group of bit lines among a plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block is connected to a second group of bit lines among the plurality of bit lines; at least one block switch connected between a second half local I / O line of the first memory block and a first half local I / O line of a second memory block among a plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and a column decoder configured to repair a first bit line of the first memory block using at least one spare bit line of the first memory block or a spare bit line of a memory block adjacent to the first memory block by controlling at least one bit line switch and at least one block switch; in, The first bit line is coupled to a defective cell among the plurality of dynamic memory cells, The first group of bit lines includes at least a first spare bit line coupled to a first spare cell among the plurality of dynamic memory cells. The second group of bit lines includes at least a second spare bit line, the second spare bit line is coupled to a second spare cell among the plurality of dynamic memory cells, If a first bit line of the first memory block, a second bit line of the first memory block, a first bit line of the second memory block, and a second bit line of the second memory block are connected to a defective cell, the column decoder is configured to: repairing the first bit line of the first storage block by using the first spare bit line of the first storage block; repairing the second bit line of the first memory block by using the second spare bit line of the first memory block; repairing the first bit line of the second memory block using the first spare bit line of the second memory block; and The second spare bit line of the second memory block is used to repair the second bit line of the second memory block.

14. A semiconductor storage device comprising: a memory cell array comprising a plurality of memory blocks coupled to at least one word line, wherein each of the plurality of memory blocks comprises a plurality of dynamic memory cells; at least one bit line switch coupled between a first semi-local input / output (I / O) line of a first memory block among a plurality of memory blocks and a second semi-local I / O line of the first memory block, wherein the first semi-local I / O line of the first memory block is connected to a first group of bit lines among a plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block is connected to a second group of bit lines among the plurality of bit lines; at least one block switch connected between a second half local I / O line of the first memory block and a first half local I / O line of a second memory block among a plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and a column decoder configured to repair a first bit line of the first memory block using at least one spare bit line of the first memory block or a spare bit line of a memory block adjacent to the first memory block by controlling at least one bit line switch and at least one block switch; in, The first bit line is coupled to a defective cell among the plurality of dynamic memory cells, The first group of bit lines includes at least a first spare bit line coupled to a first spare cell among the plurality of dynamic memory cells. The second group of bit lines includes at least a second spare bit line, the second spare bit line is coupled to a second spare cell among the plurality of dynamic memory cells, If four or more bit lines of the first memory block are connected to a defective cell, the column decoder is configured to repair the four or more bit lines using spare bit lines of the first memory block, the second memory block, the third memory block, and the fourth memory block, The second storage block is adjacent to the first storage block in the direction of the second half local I / O line of the first storage block, wherein the third storage block is adjacent to the first storage block in the direction of the first half local I / O line of the first storage block, and The fourth storage block is adjacent to the third storage block in a direction of the first half local I / O line of the first storage block.

15. A method of operating a semiconductor memory device, wherein: The semiconductor memory device includes: a memory cell array including a plurality of memory blocks coupled to at least one word line, each of the plurality of memory blocks including a plurality of dynamic memory cells; at least one bit line switch coupled between a first semi-local input / output (I / O) line of a first memory block among the plurality of memory blocks and a second semi-local I / O line of the first memory block; and at least one block switch connected between the second semi-local I / O line of the first memory block and a first semi-local I / O line of a second memory block adjacent to the first memory block, the first semi-local I / O line of the first memory block being connected to a first group of bit lines among a plurality of bit lines of the first memory block, and the second semi-local I / O line of the first memory block being connected to a second group of bit lines among a plurality of bit lines, the method including: deactivating, by a column decoder in response to a column address, a first bit line coupled to a defective cell in the first memory block, and The column decoder controls at least one bit line switch and at least one block switch to activate the spare bit line of the first memory block or the spare bit line of the second memory block to repair the defective cell. in, The first group of bit lines includes at least a first spare bit line coupled to a first spare cell among the plurality of dynamic memory cells. The second group of bit lines includes at least a second spare bit line, the second spare bit line is coupled to a second spare cell among the plurality of dynamic memory cells, The first set of bit lines is connected to the first half of the local I / O lines of the first memory block through a first bit line sense amplifier, and The second group of bit lines is connected to the second half of the local I / O lines of the first memory block through second bit line sense amplifiers.

16. The method according to claim 15, further comprising: A column decoder controls a connection between a first semi-local I / O line of a first memory block and a second semi-local I / O line of the first memory block by applying a first switch control signal to at least one bit line switch, and controls a connection between the second semi-local I / O line of the first memory block and the first semi-local I / O line of the second memory block by applying a second switch control signal to at least one block switch.

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