Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a layer to be etched, the layer to be etched having a patterned first sacrificial layer on the layer to be etched, the patterned first sacrificial layer having a first opening and a second opening, the first opening having a first size in a direction parallel to the surface of the layer to be etched, the second opening having a second size in a direction parallel to the surface of the layer to be etched, the first size being smaller than the second size; forming a sidewall material layer on the exposed surface of the layer to be etched, and the sidewall surface and top surface of the first sacrificial layer, forming a third opening in the first opening, forming a fourth opening in the second opening, the aspect ratio of the third opening being greater than the aspect ratio of the fourth opening; etching back the sidewall material layer until the layer to be etched at the bottom of the fourth opening is exposed, forming a first mask structure at the bottom and sidewall surface of the third opening, and forming a second mask structure at the sidewall of the fourth opening. The performance of the semiconductor structure formed is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the increasing demand for high-capacity semiconductor memory devices, the integration density of semiconductor memory devices has attracted people's attention. In order to increase the integration density of semiconductor memory devices, many different methods are used in the prior art. Self-aligned multiple patterning technology is a solution that is widely accepted and applied in the process of semiconductor device preparation.

[0003] Currently, commonly used self-aligned multi-patterning technologies include self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Self-aligned multi-patterning can be used to prepare devices with smaller nodes under existing photolithography technology to provide smaller process fluctuations.

[0004] However, the existing self-aligned multiple patterning technology must introduce complex film layer stacking to achieve pattern transfer. When etching the film layer to form the target pattern on the semiconductor substrate, it is prone to poor graphic transfer quality and distortion of the target pattern, which has a negative impact on the robustness of the device.

[0005] Therefore, the performance of semiconductor devices formed using the existing self-aligned multi-patterning technology needs to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

[0007] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, wherein a patterned first sacrificial layer is provided on the layer to be etched, and a first opening and a second opening are provided in the patterned first sacrificial layer, wherein the first opening and the second opening expose a portion of the surface of the layer to be etched, and the first opening has a first size in a direction parallel to the surface of the layer to be etched, and the second opening has a second size in a direction parallel to the surface of the layer to be etched, and the first size is smaller than the second size; forming a sidewall material layer on the exposed surface of the layer to be etched, and on the sidewall surface and the top surface of the first sacrificial layer, forming a third opening in the first opening, and forming a fourth opening in the second opening, wherein the aspect ratio of the third opening is greater than the aspect ratio of the fourth opening; etching back the sidewall material layer until the layer to be etched at the bottom of the fourth opening is exposed, forming a first mask structure at the bottom and sidewall surface of the third opening, and forming a second mask structure on the sidewall of the fourth opening.

[0008] Optionally, the first size ranges from 20 to 60 nm.

[0009] Optionally, the second size ranges from greater than 60 nm.

[0010] Optionally, the aspect ratio of the third opening is greater than 5.

[0011] Optionally, the fourth opening has an aspect ratio less than or equal to 5.

[0012] Optionally, the process parameters for etching back the sidewall material layer include: the etching gas includes CH x F y , CH4, O2, He and Ar; gas flow range: CH x F y : 50 standard ml / min ~ 300 standard ml / min, CH4: 10 standard ml / min ~ 300 standard ml / min, O2: 5 standard ml / min ~ 200 standard ml / min, He and Ar total flow: 50 standard ml / min ~ 1000 standard ml / min; ion source bias range: 0 volts ~ 500 volts; gas pressure range: 4 mTorr ~ 500 mTorr.

[0013] Optionally, the process for forming the spacer material layer includes an atomic layer deposition process or a chemical vapor deposition process.

[0014] Optionally, the thickness of the sidewall material layer is in the range of 10 nm to 20 nm.

[0015] Optionally, the patterned first sacrificial layer further includes a first mask layer located on the first sacrificial layer.

[0016] Optionally, the method for forming the first sacrificial layer includes: forming a first sacrificial material layer on the layer to be etched; forming a first mask material layer and a graphic layer located on the first mask material layer on the first sacrificial material layer, the graphic layer exposing a portion of the surface of the first mask material layer; using the graphic layer as a mask, etching the first mask material layer and the first sacrificial material layer, and forming a first sacrificial layer and a first mask layer located on the sacrificial layer on the layer to be etched.

[0017] Optionally, the process of etching the first mask material layer and the first sacrificial material layer includes a dry etching process.

[0018] Optionally, before forming a spacer material layer on the surface of the layer to be etched, the sidewall surface and the top surface of the first sacrificial layer, the method further includes: removing the first mask layer.

[0019] Optionally, the method for removing the first mask layer includes: a wet etching process.

[0020] Optionally, after forming the first mask structure and the second mask structure, the method further includes: removing the first sacrificial layer.

[0021] Optionally, the process of removing the first sacrificial layer includes a wet etching process.

[0022] Optionally, the layer to be etched includes: a substrate; a second sacrificial material layer located on the substrate; and a second mask material layer located on the second sacrificial material layer.

[0023] Optionally, the method further includes: using the first mask structure and the second mask structure as masks, etching the second mask material layer and the second sacrificial material layer to form a second sacrificial layer and a second mask layer located on the second sacrificial layer on the substrate.

[0024] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by using any of the above methods.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] A sidewall material layer is formed on the surface of the layer to be etched, the sidewall surface and the top surface of the sacrificial layer, a third opening is formed in the first opening, and a fourth opening is formed in the second opening. When the sidewall material layer is back-etched, since the aspect ratio of the third opening is greater than the aspect ratio of the fourth opening, less etching gas enters the third opening, and the etching rate of the sidewall material layer in the third opening is slow, and more etching gas enters the fourth opening, and the etching rate of the sidewall material layer in the fourth opening is fast. Then, the sidewall material layer at the bottom and sidewall surface of the third opening forms a first sidewall, and the sidewall material layer at the sidewall of the fourth opening forms a second sidewall. To avoid the problem that when two layers of sidewall material layers are formed in the first opening and the second opening and etching is performed to form sidewalls in order to meet the process requirements of different line widths, the etching process damages the sidewall in the fourth opening and the bottom of the third opening. The first sidewall and the second sidewall formed have better morphology, which can meet the diversity of different sizes of semiconductor structures and improve the performance of semiconductor structures.

[0027] Further, when etching back the sidewall material layer at the bottom of the fourth opening, by adjusting CH x F y The flow rate and the total pressure of the reaction gas make the etching rate of the side wall material layer at the bottom of the fourth opening high and the etching rate of the side wall material layer of the third opening low, so that the second side wall can be formed on the side wall of the fourth opening, and the first side wall can be formed at the bottom and side wall of the third opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 4 It is a schematic diagram of the cross-sectional structure of a semiconductor device forming process;

[0029] Figures 5 to 8 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the performance of semiconductor devices formed using the existing self-aligned quadruple patterning technology needs to be improved. Now, an analysis is conducted in conjunction with a formation process of a semiconductor device.

[0031] Figures 1 to 4 It is a schematic diagram of the cross-sectional structure of a semiconductor device formation process.

[0032] Please refer to Figure 1, providing a layer to be etched 100, wherein the layer to be etched 100 has a patterned sacrificial layer 101, wherein a first opening 102 and a second opening 103 are provided between the sacrificial layers 101, wherein the first opening 102 and the second opening 103 expose the surface of the layer to be etched 100, and a size of the first opening 102 in a direction parallel to the surface X of the layer to be etched 100 is smaller than a size of the second opening 103 in a direction parallel to the surface X of the layer to be etched 100.

[0033] Please refer to Figure 2 A first spacer material layer 112 is formed on the layer to be etched, the side wall surface and the top surface of the sacrificial layer 101, a third opening 110 is formed in the first opening 102, and a fourth opening 111 is formed in the second opening 103, and the aspect ratio of the third opening 110 is greater than the aspect ratio of the fourth opening 111.

[0034] Please refer to Figure 3 A second spacer material layer 113 is formed in the third opening 110 , on the bottom surface and sidewall surface of the fourth opening 111 , and on the top surface of the sacrificial layer 101 .

[0035] Please refer to Figure 4 , removing the second spacer material layer 113 until the first spacer material layer 112 at the bottom of the fourth opening 111 is exposed, and forming an initial first spacer at the bottom and sidewall of the third opening 110 .

[0036] In the semiconductor structure formed by the method, in order to meet the process requirements of different line widths, the size of the first opening 102 in the X direction parallel to the surface of the layer to be etched 100 is smaller than the size of the second opening 103 in the X direction parallel to the surface of the layer to be etched 100. After the first spacer material layer 112 is formed on the layer to be etched, the side wall surface and the top surface of the sacrificial layer 101, the aspect ratio of the third opening 110 formed in the first opening 102 is greater than 5, and the aspect ratio of the fourth opening 111 formed in the second opening 103 is less than or equal to 5. The aspect ratio of the third opening 110 is much greater than the aspect ratio of the fourth opening 111.

[0037] When the second spacer material layer 113 is subsequently formed in the third opening 110, due to the large depth-width ratio of the third opening 110, the second spacer material is preferentially deposited at the top of the third opening 110, resulting in less reactive gas entering the bottom of the third opening 110, so the second spacer material layer 113 formed in the third opening 110 is loose in structure and has gaps. When the second spacer material layer 113 is continuously removed and the initial first spacer is formed at the bottom and sidewall of the third opening 110, due to the loose structure and gaps of the second spacer material layer 113 in the third opening 110, the second spacer material layer 113 in the third opening 110 is easily removed and the first spacer material layer 112 at the bottom is exposed. When the first spacer material layer 112 is subsequently etched back to form the first spacer at the bottom and sidewall of the third opening 110 and the second spacer is formed on the sidewall of the fourth opening 111, the first spacer material layer 112 at the bottom of the third opening 110 will also be etched so that the first spacer cannot be formed, thereby failing to meet the process requirements and affecting the performance of the semiconductor.

[0038] On the other hand, when the second side wall material layer 113 is removed, the side wall of the first side wall material layer 112 in the fourth opening 111 will be damaged. The surface morphology of the second side wall formed by the subsequent back etching of the first side wall material layer 112 is poor. When the etched layer 100 is further etched using the second side wall as a mask, the dimensional accuracy of the formed semiconductor structure cannot be controlled, thereby affecting the performance of the semiconductor structure.

[0039] In order to solve the above problems, the present invention provides a semiconductor structure and a formation method, by forming a sidewall material layer on the surface of the layer to be etched, the sidewall surface and the top surface of the sacrificial layer, forming a third opening in the first opening, and forming a fourth opening in the second opening, the sidewall material layer at the bottom of the fourth opening is completely removed by adjusting the etching process, so that the sidewall material layer at the bottom of the third opening is retained, thereby forming a second sidewall on the sidewall of the fourth opening, and forming a first sidewall at the bottom and sidewall of the third opening. The formed first and second sidewalls have good morphology, so that the dimensional accuracy of the semiconductor structure can be controlled, thereby improving the performance of the semiconductor structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 5 to 8 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0042] Please refer to Figure 5 , providing a layer to be etched.

[0043] A patterned first sacrificial layer 203 is disposed on the layer to be etched. A first opening 206 and a second opening 207 are disposed in the patterned first sacrificial layer 203. The first opening 206 and the second opening 207 expose the surface of the layer to be etched.

[0044] In this embodiment, the patterned first sacrificial layer 203 further includes a first mask layer 204 located on the first sacrificial layer 203. In other embodiments, the patterned first sacrificial layer 203 may not include the first mask layer 204.

[0045] The method for forming the first sacrificial layer 203 includes: forming a first sacrificial material layer (not shown) on the layer to be etched; forming a first mask material layer (not shown) and a graphic layer (not shown) located on the first mask material layer on the first sacrificial material layer, wherein the graphic layer exposes a portion of the surface of the first mask material layer; using the graphic layer as a mask, etching the first mask material layer and the first sacrificial material layer to form a first sacrificial layer 203 on the layer to be etched and a first mask layer 204 located on the sacrificial layer.

[0046] In this embodiment, the process of etching the first mask material layer and the first sacrificial material layer includes a dry etching process.

[0047] In this embodiment, the first opening 206 has a first size in the X direction parallel to the surface of the layer to be etched, and the second opening 207 has a second size in the X direction parallel to the surface of the layer to be etched, and the first size is smaller than the second size.

[0048] In this embodiment, the first size ranges from 20 nm to 60 nm; the second size ranges from more than 60 nm.

[0049] In this embodiment, the layer to be etched includes: a substrate 200; a second sacrificial material layer 201 located on the substrate; and a second mask material layer 202 located on the second sacrificial material layer.

[0050] The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0051] In this embodiment, the material of the first sacrificial layer 203 includes polysilicon.

[0052] In this embodiment, the material of the first mask layer 204 includes nitride or nitride carbide, and the nitride or nitride carbide includes silicon nitride or silicon nitride carbide.

[0053] In this embodiment, the material of the second sacrificial material layer 201 is the same as that of the first sacrificial layer 203 ; in other embodiments, the material of the second sacrificial material layer 201 may be different from that of the first sacrificial layer 203 .

[0054] In this embodiment, the material of the second mask material layer 202 is different from the material of the first mask material layer 204. The material of the second mask material layer 202 includes oxide, and the oxide includes silicon oxide.

[0055] The significance of the material of the second mask material layer 202 being different from that of the first mask layer 204 is that silicon oxide and silicon nitride have different etching ratios. When the first mask layer 204 is subsequently removed, the process of removing the first mask layer 204 is prevented from damaging the second mask material layer 202, thereby affecting the accuracy of pattern transfer.

[0056] In other embodiments, the material of the second mask material layer 202 can be the same as the material of the first mask material layer 204 .

[0057] Please refer to Figure 6 A sidewall material layer 208 is formed on the exposed surface of the layer to be etched, and on the sidewall surface and top surface of the first sacrificial layer 203, a third opening 306 is formed in the first opening 206, and a fourth opening 307 is formed in the second opening 207, wherein the aspect ratio of the third opening is greater than the aspect ratio of the fourth opening.

[0058] In this embodiment, before forming the spacer material layer 208 on the surface of the to-be-etched layer, the sidewall surface and the top surface of the first sacrificial layer 203 , the method further includes: removing the first mask layer 204 .

[0059] In this embodiment, the method for removing the first mask layer 204 includes: an isotropic wet etching process. In other embodiments, the method for removing the first mask layer 204 includes: an anisotropic dry etching process.

[0060] An isotropic wet etching process is used to remove the first mask layer 204, which causes less damage to the side walls and top of the first sacrificial layer 203. The surface morphology of the sidewall material layer subsequently formed on the side wall surface and top surface of the first sacrificial layer 203 is better, which can improve the accuracy of subsequent pattern transfer.

[0061] In this embodiment, the material of the spacer material layer 208 includes nitride or nitride carbide, and the nitride or nitride carbide includes silicon nitride or silicon nitride carbide.

[0062] In this embodiment, the thickness of the spacer material layer 208 is in the range of 10 nm to 20 nm.

[0063] The significance of the thickness range of the sidewall material layer 208 being 10nm to 20nm lies in that: the range of the first dimension is 20nm to 60nm, the range of the second dimension is greater than 60nm, and the sidewall material layer 208 with a thickness of 10nm to 20nm formed on both sides of the inner wall of the first opening 206 is smaller than the range of the first dimension, thereby a third opening 306 can be formed in the first opening 206; the sidewall material layer 208 with a thickness of 10nm to 20nm formed on both sides of the inner wall of the second opening 207 is smaller than the range of the second dimension, thereby a fourth opening 307 can be formed in the second opening 207.

[0064] Since the first size is smaller than the second size, the aspect ratio of the third opening 306 formed in the first opening 206 is greater than the aspect ratio of the fourth opening 307 formed in the second opening 207 .

[0065] In this embodiment, the aspect ratio of the third opening 306 is greater than 5; the aspect ratio of the fourth opening 307 is less than or equal to 5.

[0066] The process of forming the spacer material layer 208 includes an atomic layer deposition process or a chemical vapor deposition process. In this embodiment, the process of forming the spacer material layer 208 includes an atomic layer deposition process.

[0067] The thickness of the side wall material layer 208 is in the range of 10 nm to 20 nm, which is relatively small. The atomic layer deposition process is used to form the side wall material layer 208, so that a densely structured side wall material layer 208 can be obtained, and the thickness range of the side wall material layer 208 can be precisely controlled. The first mask structure and the second mask structure formed by the subsequent back etching of the side wall material layer 208 have good morphology and precise size, which is conducive to improving the robustness of pattern transfer.

[0068] Please refer to Figure 7 , the sidewall material layer 208 is etched back until the layer to be etched at the bottom of the fourth opening 307 is exposed, a first mask structure 209 is formed on the bottom and sidewall surface of the third opening 306, and a second mask structure 210 is formed on the sidewall of the fourth opening.

[0069] In this embodiment, the process parameters for etching back the sidewall material layer include: the etching gas includes CH x F y, CH4, O2, He and Ar; gas flow range: CH x F y : 50 standard ml / min ~ 300 standard ml / min, CH4: 10 standard ml / min ~ 300 standard ml / min, O2: 5 standard ml / min ~ 200 standard ml / min, He and Ar total flow: 50 standard ml / min ~ 1000 standard ml / min; ion source bias range: 0 volts ~ 500 volts; gas pressure range: 4 mTorr ~ 500 mTorr.

[0070] In this embodiment, by adjusting the gas CH x F y The hydrogen content ratio and the overall pressure of the gas make the gas CH x F y The hydrogen content is large and the total gas pressure is large. Since the aspect ratio of the third opening 306 is greater than 5, the etching gas entering the bottom of the third opening 306 is small and thus the energy is weak. The etching rate of the sidewall material layer at the bottom of the third opening 306 by the etching gas is low, so that the etching degree of the sidewall material layer at the bottom of the third opening 306 is small, thereby enabling the bottom and sidewall of the third opening 306 to form the first sidewall. At the same time, since the aspect ratio of the fourth opening 307 is less than or equal to 5, the aspect ratio of the fourth opening 307 is The aspect ratio of the fourth opening 307 is much smaller than that of the third opening 306, so more etching gas enters the bottom of the fourth opening 307 and thus has strong energy. The etching rate of the etching gas to the side wall material layer at the bottom of the fourth opening 307 is high, so that the side wall material layer at the bottom of the fourth opening 307 is etched away, thereby enabling the formation of a second side wall on the side wall of the fourth opening 307. The morphology of the first side wall and the second side wall formed is better, which can meet the diversity of different sizes of semiconductor structures and improve the performance of the semiconductor structure.

[0071] In this embodiment, after forming the first mask structure 209 and the second mask structure 210 , the process further includes: removing the first sacrificial layer 203 .

[0072] In this embodiment, the process of removing the first sacrificial layer 203 includes a wet etching process. In other embodiments, the process of removing the first sacrificial layer 203 includes a dry etching process.

[0073] Please refer to Figure 8After forming the first mask structure 209 and the second mask structure 210, the second mask material layer 202 and the second sacrificial material layer 201 are etched using the first mask structure 209 and the second mask structure 210 as masks to form a second sacrificial layer 301 and a second mask layer 302 located on the second sacrificial layer 301 on the substrate 200.

[0074] In this embodiment, the process of etching the second mask material layer 202 and the second sacrificial material layer 201 includes an anisotropic dry etching process. By using the anisotropic dry etching process to etch the second mask material layer 202 and the second sacrificial material layer 201, a second sacrificial layer 301 with good morphology and a second mask layer 302 located on the second sacrificial layer 301 can be obtained, which is conducive to the stable transfer of subsequent patterns.

[0075] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 8 , including: a substrate 200; a second sacrificial layer 301 located on the substrate 200; and a second mask layer 302 located on the second sacrificial layer 301.

[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein a patterned first sacrificial layer is disposed on the layer to be etched, wherein a first opening and a second opening are disposed in the patterned first sacrificial layer, wherein the first opening and the second opening expose a portion of the surface of the layer to be etched, and wherein the first opening has a first size in a direction parallel to the surface of the layer to be etched, and wherein the second opening has a second size in a direction parallel to the surface of the layer to be etched, and wherein the first size is smaller than the second size; A spacer material layer is formed on the exposed surface of the layer to be etched, and the sidewall surface and the top surface of the first sacrificial layer, a third opening is formed in the first opening, the bottom surface and the sidewall surface of the third opening expose the surface of the spacer material layer, and a fourth opening is formed in the second opening, wherein the aspect ratio of the third opening is greater than the aspect ratio of the fourth opening; The sidewall material layer is etched back until the layer to be etched at the bottom of the fourth opening is exposed, the sidewall material layer forms a first mask structure at the bottom and sidewall surface of the third opening, and the sidewall material layer forms a second mask structure at the sidewall of the fourth opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first size ranges from 20 to 60 nm.

3. The method for forming a semiconductor structure according to claim 1, wherein: The second size ranges from greater than 60 nm.

4. The method for forming a semiconductor structure according to claim 1, wherein: The aspect ratio of the third opening is greater than 5.

5. The method for forming a semiconductor structure according to claim 1, wherein: The fourth opening has an aspect ratio less than or equal to 5.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters for etching back the sidewall material layer include: the etching gas includes CH x F y , CH4, O2, He and Ar; gas flow range: CH x F y : 50 standard ml / min ~ 300 standard ml / min, CH4: 10 standard ml / min ~ 300 standard ml / min, O2: 5 standard ml / min ~ 200 standard ml / min, He and Ar total flow: 50 standard ml / min ~ 1000 standard ml / min; ion source bias range: 0 volts ~ 500 volts; gas pressure range: 4 mTorr ~ 500 mTorr.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the spacer material layer includes an atomic layer deposition process or a chemical vapor deposition process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the sidewall material layer is in the range of 10 nm to 20 nm.

9. The method for forming a semiconductor structure according to claim 1, wherein: The patterned first sacrificial layer further includes a first mask layer located on the first sacrificial layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: The method for forming the first sacrificial layer includes: forming a first sacrificial material layer on the layer to be etched; forming a first mask material layer and a graphic layer located on the first mask material layer on the first sacrificial material layer, wherein the graphic layer exposes a portion of the surface of the first mask material layer; etching the first mask material layer and the first sacrificial material layer using the graphic layer as a mask, and forming a first sacrificial layer and a first mask layer located on the sacrificial layer on the layer to be etched.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of etching the first mask material layer and the first sacrificial material layer includes a dry etching process.

12. The method for forming a semiconductor structure according to claim 9, wherein: Before forming a spacer material layer on the surface of the layer to be etched, the sidewall surface and the top surface of the first sacrificial layer, the method further includes: removing the first mask layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for removing the first mask layer includes: a wet etching process.

14. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first mask structure and the second mask structure, the method further includes: removing the first sacrificial layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The process of removing the first sacrificial layer includes a wet etching process.

16. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate; a second sacrificial material layer located on the substrate; and a second mask material layer located on the second sacrificial material layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: The second mask material layer and the second sacrificial material layer are etched using the first mask structure and the second mask structure as masks to form a second sacrificial layer and a second mask layer located on the second sacrificial layer on the substrate.

18. A semiconductor structure formed by the method according to any one of claims 1 to 17.

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