Semiconductor components with diodes and silicon-controlled rectifiers

Abstract

The present invention provides a semiconductor element with a diode and a silicon-controlled rectifier, comprising: a substrate with a first conductivity type, a well region with a second conductivity type, a first doped region with the first conductivity type, and a second doped region with the second conductivity type. The well region is arranged in the substrate. The first doped region is arranged in the substrate. The second doped region is arranged in the substrate. The well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third PN junction. The first PN junction, the second PN junction, and the third PN junction form a silicon-controlled rectifier, and the first doped region and the third PN junction form a diode.

Description

Technical Field

[0001] The invention relates to a semiconductor element with a diode and a silicon-controlled rectifier. Background Art

[0002] With the rapid development of current technology, integrated circuits are widely used in electronic devices. Electrostatic discharge (ESD) events are one of the main problems that lead to damage to integrated circuits.

[0003] In the existing technical field, transient voltage suppressors (TVS) are often used for electrostatic discharge protection. However, since transient voltage suppressors need to withstand high-power energy, their bypass diodes must be designed with a large-area PN junction to withstand high-power energy. The larger the area of ​​the PN junction, the larger its parasitic capacitance, which in turn causes the operation speed to slow down. On the other hand, if a small-area diode structure is selected to reduce the parasitic capacitance, the resistance value of the component will increase, causing the clamping voltage of the component to increase accordingly, thereby causing the ESD protection capability to decrease. Therefore, how to provide a semiconductor component with low capacitance, low clamping voltage and high ESD protection capability as a bypass diode in a transient voltage suppressor (TVS) will become an important topic. Summary of the invention

[0004] The invention provides a semiconductor element with a diode and a silicon-controlled rectifier, so that the semiconductor element of the invention has low capacitance, low clamping voltage and high ESD protection capability.

[0005] The present invention provides a semiconductor element with a diode and a silicon-controlled rectifier, comprising: a substrate with a first conductivity type, a well region with a second conductivity type, a first doped region with the first conductivity type, and a second doped region with the second conductivity type. The well region is arranged in the substrate. The first doped region is arranged in the substrate. The second doped region is arranged in the substrate. The well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third PN junction. The first PN junction, the second PN junction, and the third PN junction form a silicon-controlled rectifier, and the first doped region and the third PN junction form a diode.

[0006] In the semiconductor element provided by the present invention, a part of the first doped region is located in the well region.

[0007] In the semiconductor element provided by the present invention, the second doping region is separately arranged in the substrate from the well region and the first doping region.

[0008] The semiconductor element provided by the present invention has a substrate and a well region which are both electrically floating.

[0009] In the semiconductor element provided by the present invention, the second doped region, the substrate to the first doped region form a current path of a diode, and the second doped region, the substrate, the well region to the first doped region form a current path of a silicon-controlled rectifier.

[0010] In the semiconductor element provided by the present invention, the first doping region includes a first sub-doping region and a second sub-doping region. The second sub-doping region is located on the first sub-doping region. The doping concentration of the first sub-doping region is greater than the doping concentration of the second sub-doping region.

[0011] The semiconductor element provided by the present invention has a well region having a first well region and a second well region separated from each other, a first doped region located between the first well region and the second well region, respectively forming a PN junction with the first well region and the second well region, and the first doped region contacts the substrate.

[0012] The semiconductor element provided by the present invention also includes a third doping region located in the substrate and having the second conductivity type. The third doping region is separated from the well region by the substrate, and the first doping region is located between the second doping region and the third doping region.

[0013] Based on the above, the present invention integrates a diode and a silicon-controlled rectifier into a bypass diode structure in a transient voltage suppressor (TVS). This hybrid structure not only has the advantages of small area, low capacitance and fast conduction of the diode, but also has the characteristics of high current gain and low clamping voltage of the silicon-controlled rectifier, thereby achieving a high ESD protection effect.

[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0016] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0017] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to a third embodiment of the present invention.

[0018] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to a fourth embodiment of the present invention.

[0019] Figure 5 is a circuit diagram of an electrostatic discharge protection element according to an embodiment of the present invention.

[0020] Figure 6 is a cross-sectional schematic diagram of an electrostatic discharge protection component according to a fifth embodiment of the present invention.

[0021] Figure 7 FIG. 4 is a cross-sectional schematic diagram of an electrostatic discharge protection component according to a sixth embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the accompanying drawings are exaggerated for clarity and are not to scale. The same or similar reference numerals represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0023] In the following embodiments, when the first conductivity type is P type, the second conductivity type is N type; when the first conductivity type is N type, the second conductivity type is P type. In this embodiment, the first conductivity type is N type and the second conductivity type is P type. However, the present invention is not limited thereto.

[0024] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0025] Please refer to Figure 1 The semiconductor device 10 of the first embodiment includes a substrate 100, a well region 102, a first doping region 104, and a second doping region 106. In one embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate on an insulating layer (Semiconductor Over Insulator, SOI). In this embodiment, the substrate 100 may have a first conductivity type, which may be, for example, an N-type silicon substrate, and is electrically floating.

[0026] The well region 102 may have the second conductivity type and is disposed in the substrate 100. In one embodiment, the dopant of the well region 102 is, for example, boron or boron difluoride. For example, the well region 102 may be a P-type well region and be electrically floating.

[0027] The first doped region 104 may have a first conductivity type and is disposed in the substrate 100 next to the well region 102. Figure 1As shown, a portion of the first doping region 104 is located in the well region 102 and is in (physical) contact with the well region 102. Another portion of the first doping region 104 is located outside the well region 102 or exposed to the well region 102, and is in (physical) contact with the substrate 100. In the present embodiment, the first doping region 104 includes a first sub-doping region 103 and a second sub-doping region 105 located on the first sub-doping region 103. The bottom surface of the first sub-doping region 103 may be lower than the bottom surface of the well region 102, but the present invention is not limited thereto. In another embodiment, the doping concentration of the first sub-doping region 103 is greater than the doping concentration of the second sub-doping region 105. In an alternative embodiment, the dopants of the first sub-doping region 103 and the second sub-doping region 105 are, for example, phosphorus or arsenic.

[0028] The second doping region 106 may have a second conductivity type and is disposed in the substrate 100 separately from the well region 102 and the first doping region 104. In one embodiment, the dopant of the second doping region 106 is, for example, boron or boron difluoride. Figure 1 As shown, the second doping region 106 is separated from the well region 102 by the substrate 100, and the well region 102 is located between the first doping region 104 and the second doping region 106. In other words, the second doping region 106 of the same conductivity type as the well region 102 will not contact the well region 102; while the first doping region 104 of a different conductivity type from the well region 102 will contact the well region 102.

[0029] It is worth noting that the well region 102 and the first doping region 104 form a first PN junction, the well region 102 and the substrate 100 form a second PN junction, and the substrate 100 and the second doping region 106 form a third PN junction. Figure 1 As shown, the first PN junction, the second PN junction and the third PN junction form a silicon-controlled rectifier structure 140 with three PN junctions, while the first doped region 104 and the third PN junction form a diode structure 130 with a single PN junction. In this embodiment, the first doped region 104 is coupled to the input / output terminal IO; and the second doped region 106 is coupled to the ground terminal G. In this case, the second doped region 106, the substrate 100 to the first doped region 104 can form a current path 110 of the diode 130; and the second doped region 106, the substrate 100, the well region 102 to the first doped region 104 form a current path 120 of the silicon-controlled rectifier structure 140. In an alternative embodiment, the current path 120 of the silicon-controlled rectifier structure 140 is closer to the top surface of the substrate 100 than the current path 110 of the diode structure 130.

[0030] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0031] Please refer to Figure 2The semiconductor device 20 of the second embodiment includes a substrate 100 having a first conductivity type, a well region 102 having a second conductivity type, a first doping region 104 having the first conductivity type, a second doping region 106 having the second conductivity type, and a third doping region 116 having the second conductivity type.

[0032] Specifically, the first doping region 104 separates the well region 102 into a first well region 102a and a second well region 102b. That is, the well region 102 has a first well region 102a and a second well region 102b that are separated from each other, the first doping region 104 is located between the first well region 102a and the second well region 102b, and the first doping region 104 forms a PN junction with the first well region 102 and the second well region 102b respectively. The sidewalls of the first doping region 104 extend into the first well region 102a and the second well region 102b respectively, so that the first well region 102a and the second well region 102b cover or enclose the sidewalls and a portion of the bottom surface of the first doping region 104, and another portion of the bottom surface of the first doping region 104 is exposed. Figure 1 As shown, another portion of the bottom surface of the first doped region 104 exposed in the first well region 102a and the second well region 102b is in (physical) contact with the substrate 100. In one embodiment, the bottom surface of the first doped region 104 is higher than the bottom surfaces of the first well region 102a and the second well region 102b, but the invention is not limited thereto.

[0033] like Figure 2 As shown, the second doping region 106 is located on one side of the first doping region 104 adjacent to the first well region 102a, and the third doping region 116 is located on the other side of the first doping region 104 adjacent to the second well region 102b. That is, the first doping region 104 is located between the second doping region 106 and the third doping region 116, and is disposed in the substrate 100 separately from the second doping region 106 and the third doping region 116. The second doping region 106 and the third doping region 116 of the same conductivity type as the well region 102 will not contact the well region 102; while the first doping region 104 of a different conductivity type from the well region 102 will contact the well region 102. In one embodiment, the dopant of the third doping region 116 is, for example, boron or boron difluoride. In an alternative embodiment, the doping concentration of the third doping region 116 is the same as the doping concentration of the second doping region 106.

[0034] In the present embodiment, the first doped region 104 is coupled to the input / output terminal IO; the second doped region 106 is coupled to the ground terminal G; and the third doped region 116 is coupled to the power terminal V. In this case, the second doped region 106, the substrate 100 to the first doped region 104 can form a current path 110a of the diode 130a; and the second doped region 106, the substrate 100, the first well region 102a to the first doped region 104 form a current path 120a of the silicon-controlled rectifier 140a. Similarly, the third doped region 116, the substrate 100 to the first doped region 104 can form a current path 110b of another diode 130b; and the third doped region 116, the substrate 100, the second well region 102b to the first doped region 104 form a current path 120b of another silicon-controlled rectifier 140b. In the present embodiment, the semiconductor device 20 can be regarded as a multi-channel structure, which is arranged in a mirror-symmetrical manner with the first doped region 104 as the central axis.

[0035] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to a third embodiment of the present invention.

[0036] Please refer to Figure 3 , the semiconductor device 30 of the third embodiment is similar to the semiconductor device 20 of the second embodiment. The difference between the two is that the first doping region 104 of the semiconductor device 30 of the third embodiment includes a first sub-doping region 103 and a second sub-doping region 105 located on the first sub-doping region 103. The bottom surface of the first sub-doping region 103 can be lower than the bottom surfaces of the first well region 102a and the second well region 102b. In other words, the first sub-doping region 103 (or the first doping region 104) protrudes from the bottom surfaces of the first well region 102a and the second well region 102b to contact the substrate 100. Under this structure, the current of the ground terminal G can flow from the current path 110a of the diode 130a or from the current path 120a of the silicon-controlled rectifier 140a to the input and output terminal IO. The current of the power supply terminal V can flow from the current path 110b of the diode 130b or from the current path 120b of the silicon-controlled rectifier 140b to the input and output terminal IO.

[0037] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to a fourth embodiment of the present invention.

[0038] Please refer to Figure 4, the semiconductor device 40 of the fourth embodiment is similar to the semiconductor device 20 of the second embodiment. The difference between the two is that the first doped region 404 of the semiconductor device 40 of the fourth embodiment is only adjacent to the first well region 102a and the second well region 102b. In other words, the sidewalls of the first doped region 404 do not extend into the first well region 102a and the second well region 102b. Therefore, the first well region 102a and the second well region 102b only cover or are adjacent to the sidewalls of the first doped region 404, but do not cover or enclose the bottom surface of the first doped region 404. In this case, Figure 4 As shown, the entire bottom surface of the first doped region 404 is exposed to the first well region 102 a and the second well region 102 b , and the entire bottom surface of the first doped region 404 is in contact with the substrate 100 .

[0039] Based on the above, Figures 1 to 4 Any of the semiconductor elements 10, 20, 30, and 40 in the embodiment is a hybrid configuration that integrates a diode 130 and a silicon-controlled rectifier 140. In this hybrid configuration, when electrostatic discharge (ESD) or surge occurs, the ESD current can be quickly turned on through the diode 130 to achieve the first level of protection. Then, when the ESD energy continues to increase, the silicon-controlled rectifier 140 will be triggered to achieve the second level of high protection effect.

[0040] Figure 5 1 is a circuit diagram of an electrostatic discharge protection device according to an embodiment of the present invention. The electrostatic discharge protection device of this embodiment is described by taking a transient voltage suppressor (TVS) as an example, but the present invention is not limited thereto.

[0041] Please refer to Figure 5 The electrostatic discharge protection element of this embodiment includes: a power supply terminal V, a ground terminal G, an input / output terminal IO, a Zener diode ZD, and a diode string 200. The diode string 200 includes diode structures UD and DD connected in series. The Zener diode ZD and the diode string 200 are coupled in parallel between the power supply terminal V and the ground terminal G. Figure 5 As shown, the two ends of the Zener diode ZD are respectively coupled to the power supply terminal V and the ground terminal G; the two ends of the diode structure UD are respectively coupled to the power supply terminal V and the diode structure DD; the two ends of the diode structure DD are respectively coupled to the diode structure UD and the ground terminal G; and the input-output terminal IO is coupled between the diode structures UD and DD. In one embodiment, the anode of the diode structure UD is coupled to the cathode of the diode structure DD, and is coupled to the input-output terminal IO. Although Figure 5Only a single diode structure UD and a single diode structure DD are shown to be connected in series, but the present invention is not limited thereto. In other embodiments, the number of diode structures UD or diode structures DD may be greater than one. In addition, the number of diode strings 200 may also be adjusted according to actual needs.

[0042] In this embodiment, Figures 1 to 4 Any of the semiconductor elements 10, 20, 30, 40 can replace the diode structure UD or the diode structure DD in the diode string 200 to achieve low capacitance, low on-resistance (low Ron) and reduced clamping voltage, thereby enhancing the ESD and surge protection capabilities of the electrostatic discharge protection element.

[0043] Figure 6 The fifth embodiment of the present invention is a cross-sectional view of an electrostatic discharge protection device. The electrostatic discharge protection device of this embodiment is described by taking a semiconductor device with a diode and a silicon-controlled rectifier to improve the bypass diode structure in a transient voltage suppressor (TVS), but the present invention is not limited thereto.

[0044] Please refer to Figure 6 The electrostatic discharge protection element 50 of the fifth embodiment includes a diode string 200. The diode string 200 includes a diode structure UD and a diode structure DD. Although the present embodiment applies any one of the semiconductor elements 10, 20, 30, and 40 to the diode structure DD, the present invention is not limited thereto. In other embodiments, any one of the semiconductor elements 10, 20, 30, and 40 may also be applied to the diode structure UD, or may be applied to both the diode structures UD and DD at the same time.

[0045] Specifically, the diode structure DD includes: a substrate 100 having a first conductivity type, a well region 102 having a second conductivity type, a first doping region 504 having the first conductivity type, and a second doping region 106 having the second conductivity type. The well region 102, the first doping region 504, and the second doping region 106 are all disposed in the substrate 100. The well region 102 is located between the first doping region 504 and the second doping region 106. The well region 102 is adjacent to and (physically) in contact with the first doping region 504; the well region 102 is separately disposed and does not contact with the second doping region 106.

[0046] On the other hand, the diode structure UD includes: a substrate 100 having a first conductivity type, a well region 202 having a second conductivity type (hereinafter referred to as a P-type well region 202), a well region 203 having a first conductivity type (hereinafter referred to as an N-type well region 203), a fourth doping region 204 having a first conductivity type, and a fifth doping region 206 having a second conductivity type. Specifically, Figure 6As shown, the N-type well region 203, the fourth doping region 204 and the fifth doping region 206 are all disposed in the P-type well region 202. That is, the P-type well region 202 covers the N-type well region 203, the fourth doping region 204 and the fifth doping region 206 to isolate the diode structure UD from the diode structure DD. The N-type well region 203 is located between the fourth doping region 204 and the fifth doping region 206. The N-type well region 203 and the fifth doping region 206 are adjacent and (physically) in contact; while the N-type well region 203 and the fourth doping region 204 are separately disposed and do not contact.

[0047] In this embodiment, the first doping region 504 and the fifth doping region 206 are coupled to the input / output terminal IO; the second doping region 106 is coupled to the ground terminal G; and the fourth doping region 204 is coupled to the power terminal V. In this case, the second doping region 106, the substrate 100 to the first doping region 504 can form a current path 110 of the diode 130; and the second doping region 106, the substrate 100, the well region 102 to the first doping region 504 form a current path 120 of the silicon-controlled rectifier 140. Therefore, the electrostatic discharge protection element 50 of this embodiment can not only quickly conduct the ESD current through the diode 130, but also trigger the silicon-controlled rectifier 140 to achieve a high ESD protection effect.

[0048] Figure 7 FIG. 4 is a cross-sectional schematic diagram of an electrostatic discharge protection component according to a sixth embodiment of the present invention.

[0049] Please refer to Figure 7 , the electrostatic discharge protection element 60 of the sixth embodiment is similar to the electrostatic discharge protection element 50 of the fifth embodiment. The difference between the above two is that the electrostatic discharge protection element 60 of the sixth embodiment also includes an isolation structure 602 configured in the substrate 100 between the diode structure UD and the diode structure DD to separate the diode structure UD from the diode structure DD. In one embodiment, the isolation structure 602 can be a shallow trench isolation structure (STI), a deep trench isolation structure (DTI) or a combination thereof. The material of the isolation structure 602 can be, for example, silicon oxide, silicon nitride or a combination thereof. In an alternative embodiment, the isolation structure 602 can also be an isolation doped region having a second conductivity type, such as a P-type doped region.

[0050] In summary, the present invention integrates a diode and a silicon-controlled rectifier into a bypass diode structure in a transient voltage suppressor. This hybrid approach not only has the advantages of a small area, small capacitance, and fast turn-on of a diode, but also has the characteristics of a high current gain and low clamping voltage of a silicon-controlled rectifier, thereby achieving a high ESD protection effect.

[0051] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A semiconductor device having a diode and a silicon-controlled rectifier, characterized in that: include: A substrate having a first conductivity type; a well region having a second conductivity type and disposed in the substrate; A first doped region, having the first conductivity type and disposed in the substrate; as well as a second doped region having the second conductivity type and disposed in the substrate, wherein the well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third PN junction, The first PN junction, the second PN junction and the third PN junction form the silicon controlled rectifier, and the first doped region is connected to the third PN junction to form the diode. The silicon controlled rectifier is coupled in parallel with the diode.

2. The semiconductor device according to claim 1, characterized in that A portion of the first doped region is located in the well region.

3. The semiconductor device according to claim 1, wherein: The second doping region is separately arranged in the substrate from the well region and the first doping region.

4. The semiconductor device according to claim 1, wherein: The substrate and the well region are both electrically floating.

5. The semiconductor device according to claim 1, wherein: in The second doping region, the substrate and the first doping region form a current path of the diode. The second doped region, the substrate, the well region and the first doped region form a current path of the silicon-controlled rectifier.

6. The semiconductor device according to claim 1, characterized in that The first doping region includes a first sub-doping region and a second sub-doping region, the second sub-doping region is located on the first sub-doping region, and the doping concentration of the first sub-doping region is greater than the doping concentration of the second sub-doping region.

7. The semiconductor device according to claim 1, wherein: The well region has a first well region and a second well region separated from each other, the first doped region is located between the first well region and the second well region, and forms a PN junction with the first well region and the second well region respectively, and the first doped region contacts the substrate.

8. The semiconductor device according to claim 7, characterized in that Also includes: A third doped region, having the second conductivity type, is located in the substrate, wherein the third doped region is separated from the well region by the substrate, and the first doped region is located between the second doped region and the third doped region.

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