Memory element and method of forming the same

Abstract

The present invention discloses a memory element and a method for forming the same. The memory element comprises a substrate, a stacked structure, a plurality of memory structures, a plurality of isolation structures and a plurality of common source poles. The stacked structure comprises a plurality of conductive layers and a plurality of insulating layers alternately stacked on the substrate. The memory structure is formed on the substrate and passes through the stacked structure. The isolation structure is formed on the substrate and passes through the stacked structure, wherein the isolation structure divides the memory structure into a plurality of first memory structures and a plurality of second memory structures. The common source pole is formed on the substrate and passes through the stacked structure, wherein the common source pole is directly in contact with the isolation structure.

Description

Technical Field

[0001] The present invention relates to a memory element and a forming method thereof, and in particular to a three-dimensional (3D) memory element and a forming method thereof. Background Art

[0002] A three-dimensional memory device (such as a three-dimensional non-volatile memory (NVM)) has a multi-layer stacked structure, can achieve a higher storage capacity, and has excellent electronic properties, such as good data retention reliability and operating speed, which can be used to provide excellent memory device needs.

[0003] However, as the applications increase, there is still a need to provide memory devices with improved performance and to increase memory density. Summary of the invention

[0004] The present invention relates to a memory element and a manufacturing method thereof. In the present invention, a first memory structure and a second memory structure are separated by an isolation structure directly contacting a common source column. Therefore, the memory density per unit area can be increased and the efficiency of the memory array can be improved.

[0005] According to one embodiment of the present invention, a memory element includes a substrate, a stacked structure, a plurality of memory structures, a plurality of isolation structures, and a plurality of common source poles. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on the substrate. The memory structure is formed on the substrate and passes through the stacked structure. The isolation structure is formed on the substrate and passes through the stacked structure, wherein the isolation structure divides the memory structure into a plurality of first memory structures and a plurality of second memory structures. The common source pole is formed on the substrate and passes through the stacked structure, wherein the common source pole is directly in contact with the isolation structure.

[0006] According to one embodiment of the present invention, a method for forming a memory element includes the following steps. A substrate is formed. A stacked structure is formed, the stacked structure including a plurality of conductive layers and a plurality of insulating layers alternately stacked on the substrate. A plurality of memory structures are formed on the substrate, and the memory structures pass through the stacked structure. A plurality of isolation structures are formed on the substrate, and the isolation structures pass through the stacked structure, wherein the isolation structures divide the memory structures into a plurality of first memory structures and a plurality of second memory structures. A plurality of common source poles are formed on the substrate, and the common source poles pass through the stacked structure, wherein the common source poles are directly in contact with the isolation structures.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 9B FIG. 4 is a schematic diagram illustrating a method for forming a memory device according to an embodiment of the present invention.

[0009] Fig. 10A A top view is shown of an operating method of a memory device according to an embodiment of the present invention.

[0010] Fig. 10B FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell in a memory device according to an embodiment of the present invention.

[0011] Fig. 10C FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell in a memory device according to an embodiment of the present invention.

[0012] Fig. 10D FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell in a memory device according to an embodiment of the present invention.

[0013] Fig. 10E FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell in a memory device according to an embodiment of the present invention.

[0014] [Description of Reference Numerals]

[0015] 100: Memory components

[0016] 110: Substrate

[0017] 110a: Upper surface

[0018] 112: Epitaxial structure

[0019] 120: Laminated structure

[0020] 120': Stacking body

[0021] 122: Insulation layer

[0022] 123: Sacrificial Layer

[0023] 124: Conductive layer

[0024] 120a: First ridge structure

[0025] 120b: Second ridge structure

[0026] 130: Memory Structure

[0027] 130a: First group memory structure

[0028] 130b: Second group memory structure

[0029] 130p: First opening

[0030] 132: Storage material layer

[0031] 134: Channel layer

[0032] 135: Dielectric Materials

[0033] 136: Dielectric Column

[0034] 138: Contact structure

[0035] 140p: Second opening

[0036] 142: Dielectric Materials

[0037] 143: Overlay

[0038] 144: Isolation Structure

[0039] 144a: First isolation structure

[0040] 144b: Second isolation structure

[0041] 150: Common source column

[0042] 150a: first common source column

[0043] 150b: Second common source column

[0044] 151: Conductive materials

[0045] 152: Oxide materials

[0046] 154: Conductive column

[0047] 150a: first common source column

[0048] 150b: Second common source column

[0049] 150p: Replacement holes

[0050] 130p1: The first group, the first opening

[0051] 130p2: The second group's first opening

[0052] 1301, 1301a, 1301b: first memory structure

[0053] 1302, 1302a, 1302b: Second memory structure

[0054] 144a1, 144b1: Part 1

[0055] 144a2, 144b2: Part 2

[0056] 144a3, 144b3: Part 3

[0057] 150p1: First displacement hole

[0058] 150p2: Second displacement hole

[0059] a, a', b, b': End points of the section line

[0060] AR: Array Area

[0061] BL1~BL7: bit lines

[0062] GSL: Ground Select Line

[0063] LR: Landing Zone

[0064] M A 、M B 、M C 、M D : Storage unit

[0065] PV: Region

[0066] S1: First side

[0067] S2: Second side

[0068] SP: Space

[0069] ST: ladder structure

[0070] SSL1~SSL5: Serial selection lines

[0071] V CC : Supply voltage

[0072] V pass : On-state voltage

[0073] V PGM : Programming voltage DETAILED DESCRIPTION

[0074] It must be noted that the following preferred embodiments are not intended to limit the present invention. The present invention may still be implemented using other features, components, methods and parameters. The preferred embodiments are only intended to illustrate the technical features of the present invention and are not intended to limit the scope of the present invention. A person of ordinary skill in the art will be able to make equal modifications and changes based on the description of the following specification without departing from the spirit of the present invention. In addition, the drawings do not necessarily have to be drawn according to actual proportions. In different embodiments and drawings, the same components will be represented by the same component symbols.

[0075] Figures 1A to 9B FIG. 1 is a schematic diagram illustrating a method for forming a memory device 100 according to an embodiment of the present invention.

[0076] Figure 1A A top view of a method for forming a memory device 100 according to an embodiment of the present invention is shown. Figure 1B Draw along Figure 1A Cross-sectional view of the line a-a'.

[0077] Please refer to Figure 1A and Figure 1B , a substrate 110 is provided. Thereafter, a stacking body 120' is formed on the upper surface 110a of the substrate 110. The stacking body 120' may include a plurality of insulating layers 122 and a plurality of sacrificial layers 123 alternately stacked on the substrate 110. Next, a plurality of first openings 130p are formed on the substrate 110. Each first opening 130p extends along a first direction (e.g., the Z-axis direction) and passes through the stacking body 120', as shown in FIG. 1B. In the present embodiment, the first opening 130p passes through a portion of the substrate 110, but the present invention is not limited thereto. The substrate 110 includes an array region AR and two landing regions LR adjacent to the array region AR, and the array region AR may be disposed between the landing regions LR. The first openings 130p are formed in the array region AR and include a first group of first openings 130p1 and a second group of first openings 130p2. The first group of first openings 130p1 and the second group of first openings 130p2 are separated by a space SP. The space SP can be used to form replacement holes in subsequent steps (such as Figure 6 shown).

[0078] For example, the substrate 110 is a semiconductor substrate and may be subjected to an implantation process (e.g., an n-type implant). In the present embodiment, the insulating layer 122 may be disposed at the bottom and top of the stack body 120', but the present invention is not limited thereto. The insulating layer 122 may be formed of a dielectric material, such as silicon dioxide (SiO2) or other suitable materials. The sacrificial layer 123 may be formed of a dielectric material, such as silicon nitride (SiN) or other suitable materials. The material of the insulating layer 122 may be different from the material of the sacrificial layer 123. The thickness of each insulating layer 122 and the thickness of each sacrificial layer 123 may be between approximately 20 nanometers and 40 nanometers. In some embodiments of the present invention, the insulating layer 122 and the sacrificial layer 123 may be fabricated by, for example, a low pressure chemical vapor deposition (LPCVD) process.

[0079] Figure 2A A plurality of memory structures 130 are shown formed on Figure 1A Top view of the resultant structure shown. Figure 2B Draw along Figure 2A Cross-sectional view of the line a-a'.

[0080] Please refer to Figure 2A and Figure 2B , a plurality of memory structures 130 are formed in the first openings 130 p , and then a plurality of contact structures 138 are formed on the memory structures 130 .

[0081] In this embodiment, the memory structure 130 is formed on the substrate 110 and passes through the stack body 120' along a first direction (eg, Z direction). Figure 2B As shown. Each memory structure 130 may include a storage material layer 132, a channel layer 134 and a dielectric pillar 136. The storage material layer 132 is formed on the sidewall of the first opening 130p. The channel layer 134 is formed on the storage material layer 132. The dielectric pillar 136 is formed on the channel layer 134. That is, the storage material layer 132 may be formed on the insulating layer 122 and contact the insulating layer 122 and the sacrificial layer 123. In one embodiment, the storage material layer 132 may include a composite layer (i.e., an ONO layer) composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer through an LPCVD process. However, the structure of the storage material layer 132 is not limited thereto. In some embodiments, the composite layer of the storage material layer 132 may also be selected from a group consisting of an oxide-nitride-oxide-nitride-oxide (ONONO) structure, a silicon-silicon oxide-nitride-oxide-silicon (SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, a tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure, and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure.

[0082] In some embodiments, a plurality of epitaxial structures 112 may be formed on the substrate 110 along a first direction (eg, Z direction). Figure 2BEach epitaxial structure 112 may be surrounded by a memory material layer 132 . The epitaxial structure 112 may be disposed between the substrate 110 and the memory structure 130 .

[0083] Figure 3A The second opening 140p is shown formed at Figure 2A Top view of the resultant structure shown. Figure 3B Draw along Figure 3A Cross-sectional view of line b-b'.

[0084] Please refer to Figure 3A and Figure 3B The second opening 140p is formed on the substrate 110 and passes through the stack body 120' along the first direction (eg, the Z direction). Then, the dielectric material 142 is filled into the second opening 140p and formed on the stack body 120'. Thereafter, a capping layer 143 is formed on the dielectric material 142.

[0085] exist Figure 3A In the top view of , part of the second opening 140p extends along the second direction (for example, the Y direction), and part of the second opening 140p extends along the third direction (for example, the X direction) to divide the stack body 120' into a plurality of first ridge structures 120a and a plurality of second ridge structures 120b. The first ridge structures 120a and the second ridge structures 120b are interlaced with each other along a direction parallel to the upper surface 110a of the substrate 110 (for example, the second direction (Y direction)). In some embodiments, the dielectric material 142 may include any dielectric material, such as silicon dioxide (SiO2) or other suitable materials. The cover layer 143 may include a dielectric material, such as silicon nitride (SiN) or other suitable materials. The material of the dielectric material 142 may be different from the material of the cover layer 143.

[0086] Figure 4A The step structure ST is formed in Figure 3A Top view of the result after the structure is shown. Figure 4B Draw along Figure 4A Cross-sectional view of the line a-a'.

[0087] Please refer to Figure 4A and Figure 4B The stack body 120' is patterned to form a staircase structure ST located in the landing area LR. Landing platforms for string select lines and word lines may be defined in the landing area LR. For example, the upper layers of some staircase structures ST are provided as landing platforms for string select lines. The lower layers of some staircase structures ST are provided as landing platforms for word lines.

[0088] Figure 5A Draw for Figure 4A The structure shown is a top view of the result after a planarization process. Figure 5B Draw along Figure 5A Cross-sectional view of the line a-a'. Figure 5C Draw along Figure 5A Cross-sectional view of line b-b'.

[0089] Please refer to Figure 5A , Figure 5B and Figure 5C , the dielectric material 142 and the capping layer 143 located on the stack body 120' are removed by a planarization process (e.g., chemical mechanical polishing (CMP)), and the dielectric material 142 is retained in the second opening 140p to form an isolation structure 144. The dielectric material 135 may be, for example, deposited on the step structure ST. The dielectric material 135 may include silicon dioxide (SiO2) or other suitable materials. The memory structure 130 may be divided into a plurality of first memory structures 1301 and a plurality of second memory structures 1302. In some embodiments, each memory material layer 132 of the first memory structure 1301 has a first cross section F1 along the second direction (e.g., the Y direction) and the third direction (e.g., the X direction), and each memory material layer 132 of the second memory structure 1302 has a second cross section F2 along the second direction (e.g., the Y direction) and the third direction (e.g., the X direction). The first cross section F1 is complementary to the second cross section F2, and is, for example, C-shaped or U-shaped.

[0090] Figure 6 Draw on Figure 5A A top view of the result after forming the replacement hole 150p in the structure is shown.

[0091] Please refer to Figure 6 , through an etching process, for example, a replacement hole 150p is formed along a first direction (for example, the Z direction) through the stack body 120'. The replacement holes 150p include some first replacement holes 150p1 formed in the array area AR and some second replacement holes 150p2 formed in the landing area LR. The memory structure 130 includes a first group of memory structures 130a and a second group of memory structures 130b separated from the first group of memory structures 130a by a space SP, and the first replacement hole 150p1 is disposed in the space SP between the first group of memory structures 130a and the second group of memory structures 130b. The replacement hole 150p is connected to the second opening 140p, and the isolation structure 144 is separated into a plurality of first isolation structures 144a and a plurality of second isolation structures 144b by the first replacement hole 150p1.

[0092] The isolation structure 144 (including the first isolation structure 144a and the second isolation structure 144b) divides the memory structure 130 into a plurality of first memory structures 1301 and a plurality of second memory structures 1302. That is, each first group of memory structures 130a is separated into a first memory structure 1301a and a second memory structure 1302a by one of the first isolation structures 144a, and each second group of memory structures 130b is separated into a first memory structure 1301b and a second memory structure 1302b by one of the second isolation structures 144b. Each first isolation structure 144a and each second isolation structure 144b may have a U-shaped cross section along the second direction (e.g., the Y direction) and the third direction (e.g., the X direction). The U-shaped cross section of the first isolation structure may be complementary to the U-shaped cross section of the second isolation structure 1440b.

[0093] Fig. 7A The sacrificial layer 123 is removed and the conductive material 151 is formed on Figure 6 Top view of the result after the structure in . Figure 7B Draw along Fig. 7A Cross-sectional view of the line a-a'. Figure 7C Draw along Fig. 7A Cross-sectional view of line b-b'.

[0094] Please refer to Figure 7A to Figure 7C The sacrificial layer 123 can be removed by, for example, an etching process through the replacement hole 150p, and then the conductive material 151 is filled into the space occupied by the sacrificial layer 123 through the replacement hole 150p. The conductive material 151 is also formed in the replacement hole 150p and formed on the insulating layer 122. For example, the conductive material 151 includes a metal material, such as tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable materials. In this way, the insulating layer 122 and the conductive layer 124 are alternately stacked on the substrate 110 to form a stacked structure 120. Compared to the comparative example in which the conductive layer in the stacked structure uses polysilicon material, the conductive layer 124 of this embodiment includes a metal material, which can have a lower resistance and can improve the problem of resistance-capacitance delay (RC delay).

[0095] Fig. 8A The conductive material 151 in the replacement hole 150p is removed and the oxide material 152 is formed. Fig. 7A Top view after the structure is shown. Figure 8B Draw along Fig. 8A Cross-sectional view of the line a-a'.

[0096] Please refer to Fig. 8A and Figure 8B, the conductive material 151 disposed in the replacement hole 150p and on the uppermost insulating layer 122 is removed. Next, an oxide material 152 is deposited on the stacked structure 120 and filled in the replacement hole 150p. Thereafter, a portion of the oxide material 152 is removed by, for example, an oxide etch-back process, while the oxide material 152 disposed on the sidewall of the replacement hole 150p remains.

[0097] Fig.9A The conductive pillar 154 is formed in Fig. 8A Top view of the result after the structure is in . Fig. 9B Draw along Fig.9A Cross-sectional view of the line a-a'.

[0098] Please refer to Fig.9A and Fig. 9B , a conductive material is filled in the replacement hole 150p to form a conductive column 154 in the replacement hole 150p, and each conductive column 154 is formed on the oxide material 152 and surrounded by the oxide material 152. In one embodiment, the material of the conductive column 154 may be the same as the material of the conductive layer 124, but the present invention is not limited thereto. In this way, a plurality of common source columns 150 including the oxide material 152 and the conductive column 154 are formed on the substrate 110. The conductive column 154 of the common source column 150 is electrically connected to the substrate 110. In some embodiments, a planarization process may be performed after the conductive column 154 is formed.

[0099] The common source column 150 is in direct contact with the isolation structure 144. The first isolation structure 144a corresponds to the first group of memory structures 130a, and the second isolation structure 144b corresponds to the second group of memory structures 130b. The common source column 150 includes a first common source column 150a corresponding to the array area AR and a second common source column 150b corresponding to the landing area LR. The first common source column 150a is disposed between the first isolation structure 144a and the second isolation structure 144b. Each first common source column 150a includes a first side S1 and a second side S2 relative to the first side S1. One of the first isolation structures 144a is in direct contact with the first side S1 of the first common source column 150a, and one of the second isolation structures 144b is in direct contact with the second side S2 of the first common source column 150a.

[0100] One of the first isolation structures 144a may include a first portion 144a1 extending along a third direction (e.g., the X direction), a second portion 144a2 extending along a second direction (e.g., the Y direction), and a third portion 144a3 extending along the third direction (e.g., the X direction). The second portion 144a2 is connected to the first portion 144a1 and the third portion 144a3, and the second portion 144a2 is disposed between the first portion 144a1 and the third portion 144a3. The first portion 144a1 and the third portion 144a3 are directly in contact with two adjacent first common source pillars 150a, respectively, and the second portion 144a2 is directly in contact with the second common source pillar 150b. One of the second isolation structures 144b may include a first portion 144b1 extending along a third direction (e.g., the X direction), a second portion 144b2 extending along a second direction (e.g., the Y direction), and a third portion 144b3 extending along the third direction (e.g., the X direction). The second portion 144b2 is connected to the first portion 144b1 and the third portion 144b3, and is disposed between the first portion 144b1 and the third portion 144b3. The first portion 144b1 and the third portion 144b3 are directly in contact with two adjacent first common source columns 150a, respectively, and the second portion 144b2 is directly in contact with the second common source column 150b.

[0101] The stacked structure 120 may include a plurality of first ridge structures 120a and a plurality of second ridge structures 120b. The first ridge structures 120a and the second ridge structures 120b may be separated from the common source column 150 by an isolation structure 144, and the first ridge structures 120a are interlaced with the second ridge structures 120b along a direction (e.g., a Y direction) parallel to the upper surface 110a of the substrate 110. The first ridge structures 120a may include odd-numbered lines, and the second ridge structures 120b may include even-numbered lines. Alternatively, the first ridge structures 120a may include even-numbered lines, and the second ridge structures 120b may include odd-numbered lines. Each first common source column 150a is disposed between one of the first ridge structures 120a and one of the adjacent second ridge structures 120b. The storage material layer 132 and the channel layer 134 intersect with the conductive layer 124 of each layer of the stacked structure 120, and memory cells are formed at these intersection points, respectively.

[0102] In some embodiments, a plurality of bit lines (not shown) may be formed on the stacked structure 120 and electrically connected to the memory structure 130. Subsequent processes are similar or identical to those of a general memory device and will not be described in detail herein.

[0103] In the present invention, since the multiple common source columns are not in direct contact along the direction parallel to the upper surface of the substrate, the common source columns do not form a continuously extending structure along the second direction or the third direction, and the space P1 occupied by the common source columns of the present invention is smaller than the space P2 occupied by the common source columns in the comparative example in which the common source columns extend along the second direction or the third direction, that is, P1<P2. Furthermore, since the isolation structure of the present invention is in direct contact with the common source column, the space used to form the memory structure is increased compared to the comparative example in which the common source line is separated from the isolation structure. Therefore, in the present invention, the memory density per unit area can be increased, the storage space is increased, and the array efficiency of the present invention is higher than the comparative example in which the common source line extends along the direction parallel to the upper surface of the substrate and / or the isolation structure is separated from the common source column.

[0104] Fig. 10A A top view of the memory device 100 is shown. In particular, Fig. 10A Plot corresponding to Fig.9A Partial schematic diagram of the regional PV in FIG. Fig. 10B FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell MA in a memory device 100 according to an embodiment of the present invention. Fig. 10C FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell MB in a memory device 100 according to an embodiment of the present invention. Fig. 10D FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell MC in a memory device 100 according to an embodiment of the present invention. Fig. 10E FIG. 4 is an equivalent circuit diagram illustrating an operation method of a memory cell MD in a memory device 100 according to an embodiment of the present invention.

[0105] Please refer to FIG. 10A to FIG. 10E , the bit lines BL1-BL7 are electrically connected to the first memory structure 1301a and the second memory structure 1302a in the corresponding first group of memory structures 130a. The stacked structure 120 is separated into a first ridge structure 120a and a second ridge structure 120b by the isolation structure 144 and the common source column 150. The first memory structure 1301a and the second memory structure 1302a are separated by the first isolation structure 144a, and the first common source column 150a is directly in contact with the first isolation structure 144a.

[0106] For example, Fig. 10AThe memory cell MA in the first group memory structure 130a is shown to be programmed, but the present invention is not limited thereto. Each of the first memory structure 1301a / 1301b and the second memory structure 1302a / 1302b can be independently controlled, and one of the memory cells in the first memory structure 1301a / 1301b and the second memory structure 1302a / 1302b can be read, erased, programmed, and inhibited. Please refer to FIG. 10B to FIG. 10E , which exemplarily illustrates a ground selection line GSL, two word lines WL formed on the ground selection line GSL, and a series selection line SSL having a stacked structure on the word line WL. However, the number of the ground selection line GSL, the word line WL, and the series selection line SSL is not limited thereto.

[0107] In this embodiment, 0 volt (V) is applied to the bit line BL2 corresponding to the memory cell MA, and a power supply voltage (V CC ) to bit lines BL1 and BL3 to BL7. Apply power supply voltage (V CC ) to the string selection line SSL2 corresponding to the memory cell MA, and 0V is applied to the other string selection lines SSL1 and SSL3-SSL5. Apply the conduction voltage (V pass ) to the upper word line WL, applying a programming voltage (V PGM ) to the lower word line WL. 0V is applied to the ground selection line GSL. In this way, the memory cell MA can be programmed, and the memory cells MB, MC and MD can be inhibited.

[0108] Since the first memory structure 1301 and the second memory structure 1302 are separated by the isolation structure 144 and the common source pillar 150, the word lines WL and the ground selection lines GSL corresponding to the first memory structure 1301 and the second memory structure 1302 can be independently controlled.

[0109] In an experimental example, the memory element has no replacement holes in the array region and has an array efficiency of 100%. In some embodiments of the present invention, the area of ​​the replacement holes (used to form the common source column) is twice the area of ​​the first openings (used to form the memory structure), then the number of first openings corresponding to the number of replacement holes can be 5:1 or 8:1, and compared to the experimental example, the array efficiency of the memory element can be 71% or 80%. In other words, even if there are replacement holes in the array region, the memory element of the present invention still has a good array efficiency.

[0110] According to the above embodiments, the present invention provides a memory element and a method for manufacturing the same. The memory element includes a substrate, a stacked structure, a plurality of memory structures, a plurality of isolation structures, and a plurality of common source poles. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on the substrate. The memory structure is formed on the substrate and passes through the stacked structure. The isolation structure is formed on the substrate and passes through the stacked structure, wherein the isolation structure divides the memory structure into a plurality of first memory structures and a plurality of second memory structures. The common source pole is formed on the substrate and passes through the stacked structure, wherein the common source pole is directly in contact with the isolation structure.

[0111] Since the memory element includes an isolation structure and a common source column directly contacting the isolation structure, the string selection lines, word lines and ground selection lines corresponding to the first memory structure and the second memory structure can be independently controlled, for example, each memory string in a hemi-cylindrical vertical channel (HCVC) memory element can be independently controlled. Moreover, compared with a comparative example in which the common source column extends continuously along a direction parallel to the upper surface of the substrate and / or the isolation structure is separated from the common source column, the memory element according to an embodiment of the present invention includes a plurality of common source columns separated from each other along a direction parallel to the upper surface of the substrate and an isolation structure directly contacting the common source column, and the memory density per unit area can be increased, the storage space can be increased, and a higher array efficiency can be achieved. Furthermore, the conductive layer in the stacked structure can include a metal material, which has a lower resistance than a polysilicon material. Compared to the comparative example in which the conductive layer in the stacked structure uses polysilicon, when the conductive material in the stacked structure includes a metal material, the resistance generated in the memory element can be reduced and the problem of resistance-capacitance delay (RC delay) can be improved, thereby improving the performance of the memory element while maintaining a small size and high density memory.

[0112] In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the attached claims.

Claims

1. A memory element, comprising: a substrate; a stacked structure comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked on the substrate; A plurality of memory structures formed on the substrate and passing through the stacked structure; A plurality of isolation structures formed on the substrate and passing through the stacked structure, wherein the isolation structures partially fill the memory structures and divide the memory structures into a corresponding plurality of first memory structures and a plurality of second memory structures; as well as A plurality of common source poles are formed on the substrate and pass through the stacked structure, wherein the common source poles are in direct contact with the isolation structures; The stacked structure includes a plurality of first ridge structures and a plurality of second ridge structures, wherein the first ridge structures and the second ridge structures are separated by the isolation structures and the common source poles, and the first ridge structures are staggered with the second ridge structures along a direction parallel to an upper surface of the substrate; Each of the common source columns comprises: An oxide material is formed on these conductive layers; as well as A conductive column is formed on the oxide material, and the conductive column is electrically connected to the substrate.

2. The memory element of claim 1 , wherein the substrate comprises an array region and a landing region, the landing region is adjacent to the array region, and the memory structures comprise a first group of memory structures and a second group of memory structures, the first group of memory structures is separated from the second group of memory structures, the common source columns comprise a plurality of first common source columns arranged in the array region and a plurality of second common source columns arranged in the landing region, and the first common source columns are arranged between the first group of memory structures and the second group of memory structures.

3. The memory element as claimed in claim 2, wherein the isolation structures include a plurality of first isolation structures and a plurality of second isolation structures, the first isolation structures correspond to the first group of memory structures, the second isolation structures correspond to the second group of memory structures, and the first common source columns are arranged between the first isolation structures and the second isolation structures.

4. A method for forming a memory element, comprising: providing a substrate; forming a stacked structure comprising a plurality of conductive layers and a plurality of insulating layers alternately stacked on the substrate; forming a plurality of memory structures on the substrate, and the memory structures pass through the stacked structure; forming a plurality of isolation structures on the substrate, and the isolation structures pass through the stacked structure, wherein the isolation structures partially fill the memory structures and divide the memory structures into a corresponding plurality of first memory structures and a plurality of second memory structures; as well as Forming a plurality of common source columns on the substrate, and the common source columns pass through the stacked structure, wherein the common source columns directly contact the isolation structures; The stacked structure includes a plurality of first ridge structures and a plurality of second ridge structures, wherein the first ridge structures and the second ridge structures are separated from the common source poles by the isolation structures, and the first ridge structures are staggered with the second ridge structures along a direction parallel to an upper surface of the substrate; The step of forming each common source column includes: depositing an oxide material on the conductive layers; as well as A conductive column is formed on the oxide material, wherein the conductive column is electrically connected to the substrate.

5. A method for forming a memory element as described in claim 4, wherein the substrate includes an array area and a landing area, the landing area is adjacent to the array area, and wherein the memory structures include a first group of memory structures and a second group of memory structures, the second group of memory structures are separated from the first group of memory structures, the common source columns include a plurality of first common source columns configured in the array area and a plurality of second common source columns configured in the landing area, and the first common source columns are configured between the first group of memory structures and the second group of memory structures.

6. The method for forming a memory element as described in claim 5, wherein the isolation structures include a plurality of first isolation structures and a plurality of second isolation structures, the first isolation structures correspond to the first group of memory structures, the second isolation structures correspond to the second group of memory structures, and the first common source columns are arranged between the first isolation structures and the second isolation structures.

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