Vertical memory device and method of manufacturing the same

Abstract

Example embodiments disclose a vertical memory device and a method of manufacturing the same. The device can include a plurality of gate electrodes and a plurality of insulating patterns and a channel penetrating the first gate electrode and the first insulating pattern. The device can have a charge storage structure including a tunnel insulating pattern, a charge trapping pattern, and a blocking pattern sequentially stacked from an outer sidewall of the channel. The device can have a buried pattern structure surrounded by the tunnel insulating pattern and the charge trapping pattern. The charge trapping pattern can include a first vertical portion having a first thickness in a horizontal direction and a second vertical portion having a second thickness in the horizontal direction, and the first thickness can be less than or equal to the second thickness.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0058112, filed on May 17, 2019, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to vertical storage devices. More specifically, this invention relates to non-volatile storage devices having vertical channels. Background Technology

[0004] As the number of vertically stacked layers in vertical memory devices increases, reducing the thickness of each layer is crucial for miniaturizing the devices. However, as the thickness of each layer decreases, coupling can occur between vertically adjacent cells, potentially degrading the electrical characteristics of the vertical memory device. Summary of the Invention

[0005] An example embodiment provides a vertical storage device with improved electrical characteristics.

[0006] An example embodiment provides a method for manufacturing a vertical storage device with improved electrical characteristics.

[0007] According to an example embodiment, a vertical memory device is provided. The vertical memory device may include a plurality of gate electrodes spaced apart from each other and sequentially stacked in a vertical direction substantially perpendicular to the upper surface of a substrate. The plurality of gate electrodes may include a first gate electrode and a second gate electrode. The vertical memory device may include a plurality of insulating patterns, the plurality of insulating patterns including a first insulating pattern located at a height between the first gate electrode and the second gate electrode and a channel extending in the vertical direction on the substrate. The channel may penetrate at least the first gate electrode and the first insulating pattern. The vertical memory device may include a charge storage structure extending in the vertical direction and covering the outer walls of the channel. The charge storage structure may include a tunnel insulating pattern, a charge trapping pattern, and a blocking pattern sequentially stacked from the outer walls of the channel in a horizontal direction substantially parallel to the upper surface of the substrate. The vertical memory device may have a plurality of buried pattern structures including a first buried pattern structure, wherein each buried pattern structure is surrounded by the tunnel insulating pattern and the charge trapping pattern between the channel and a corresponding insulating pattern. Each buried pattern structure may include an inner wall in contact with the tunnel insulating pattern and an outer wall in contact with the charge trapping pattern. The maximum thickness of the first portion of the charge trapping pattern is less than or equal to the maximum thickness of the second portion of the charge trapping pattern. The first portion has a vertical sidewall relative to the upper surface of the substrate and is located in the horizontal direction between the channel and the first gate electrode. The second portion has a vertical sidewall relative to the upper surface of the substrate and is located in the horizontal direction between the channel and the first insulating pattern.

[0008] According to an example embodiment, a vertical memory device is provided. The vertical memory device may include a support pattern and a channel connection pattern on a substrate, and a plurality of gate electrodes on the support pattern and the channel connection pattern. The gate electrodes may be spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate. The vertical memory device may include a plurality of insulating patterns, the plurality of insulating patterns including a first insulating pattern on the substrate at a height between a respective gate electrode and a plurality of channels, each of the channels extending along the vertical direction and penetrating the gate electrode and the insulating pattern. The vertical memory device may include a charge storage structure extending along the vertical direction and covering the outer walls of the channels. The charge storage structure may include tunnel insulating patterns, charge trapping patterns, and blocking patterns sequentially stacked from the outer walls of the channels along a horizontal direction substantially parallel to the upper surface of the substrate. The vertical memory device may include a plurality of buried pattern structures, wherein each buried pattern structure is surrounded by the tunnel insulating pattern and the charge trapping pattern between the channels and the respective insulating pattern. Each buried pattern structure may include inner sidewalls and outer sidewalls, as well as a lower surface and an upper surface. The inner sidewall may contact the tunnel insulation pattern, and the outer sidewall, the lower surface, and the upper surface may contact the charge trapping pattern. The plurality of channels may be electrically connected to each other through the channel connection pattern, and the charge trapping pattern may have a constant thickness.

[0009] According to an example embodiment, a method for manufacturing a vertical memory device is provided. The method may include alternately and repeatedly forming a plurality of insulating layers and a plurality of sacrificial layers on a top of a substrate, and forming channel vias that penetrate the plurality of insulating layers and the plurality of sacrificial layers to expose an upper surface of the substrate. The method may further include partially removing portions of each insulating pattern exposed through the channel vias to form a first recess extending continuously from the channel vias, and forming a barrier layer, a charge trapping layer, a first buried layer, and a second buried layer on the sidewalls of the channel vias and the inner walls of the first recess. The method may further include performing a first oxidation process on the surface of the second buried layer, then removing the oxidized portion of the second buried layer by a first etching process, and performing a second oxidation process on the remaining portion of the second buried layer, then removing the oxidized portion of the second buried layer by the second oxidation process and a portion of the first buried layer by a second etching process to form a buried pattern. The method may further include forming a tunnel insulating layer and a channel layer sequentially stacked on the buried pattern and the charge trapping layer.

[0010] A vertical memory device according to an example embodiment may include a charge storage structure having tunnel insulating patterns, charge trapping patterns, and blocking patterns sequentially stacked from the outer sidewall of a channel, the channel penetrating gate electrodes and insulating patterns that are alternately and repeatedly stacked in a vertical direction substantially perpendicular to the upper surface of the substrate. Additionally, the vertical memory device may further include a buried pattern structure formed between the tunnel insulating patterns and the charge trapping patterns, and the portion of the charge storage structure in contact with the insulating patterns may have a shape that protrudes from the channel. Therefore, the coupling rate between adjacent gate electrodes can be reduced, thereby improving the electrical characteristics of the vertical memory device. Attached Figure Description

[0011] Figure 1 , Figure 2A and Figure 2B These are top views and cross-sectional views illustrating a vertical storage device according to an example embodiment.

[0012] Figures 3 to 22 This is a cross-sectional view illustrating the stages of a method for manufacturing a vertical storage device according to an example embodiment.

[0013] Figure 23 This is a cross-sectional view showing a vertical storage device according to an example embodiment.

[0014] Figures 24 to 26 This is a cross-sectional view illustrating the stages of a method for manufacturing a vertical storage device according to an example embodiment.

[0015] Figure 27 This is a cross-sectional view showing a vertical storage device according to an example embodiment.

[0016] Figures 28 to 33 This is a cross-sectional view illustrating the stages of a method for manufacturing a vertical storage device according to an example embodiment.

[0017] Figures 34 to 37 These are top views and cross-sectional views illustrating a vertical storage device according to an example embodiment.

[0018] Figures 38 to 48 This is a cross-sectional view illustrating the stages of a method for manufacturing a vertical storage device according to an example embodiment. Detailed Implementation

[0019] The vertical storage device and its manufacturing method according to an exemplary embodiment will be described more fully below with reference to the accompanying drawings.

[0020] Figure 1 , Figure 2A and Figure 2B These are plan and cross-sectional views illustrating a vertical storage device according to an example embodiment. Figure 1 It's a floor plan. Figure 2A It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 2B yes Figure 2A An enlarged cross-sectional view of region X.

[0021] In the following text, a vertical direction substantially perpendicular to the upper surface of the substrate is defined as the first direction, and two intersecting horizontal directions substantially parallel to the upper surface of the substrate are defined as the second and third directions, respectively. Directions described as parallel or perpendicular should be understood to include acceptable variations that may occur, for example, due to manufacturing processes, measuring tools, and / or surfaces that are not always 100% horizontal. The term "substantially" used with "parallel" or "perpendicular" can include orientations that are perfectly parallel or perfectly perpendicular, or orientations with these acceptable variations. Unless explicitly conveyed as having an alternative meaning, the term "substantially" should be understood through the context. In example embodiments, the second and third directions may be orthogonal to each other.

[0022] Reference Figure 1 , Figure 2A and Figure 2B The vertical memory device may include: an insulating pattern 115 on a substrate 100, gate electrodes 343, 345 and 347, a channel 245, a charge storage structure and a buried pattern structure 210. Furthermore, the vertical memory device may also include a semiconductor pattern 150, a third buried pattern 250, a pad 270, a second barrier pattern 310, a second spacer 350, a common source line (CSL) 360, first to fourth insulating interlayers 130, 280, 370 and 390, a contact plug 380 and a bit line 400.

[0023] The substrate 100 may comprise silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0024] Insulating patterns 115 may be formed on substrate 100 in multiple layers spaced apart from each other along a first direction. As used herein, the term "layer" may refer to height or distance, for example, relative distance from substrate 100 or relative height above substrate 100 in the first direction. Individual insulating patterns 115 may have different thicknesses in the first direction depending on the layer level at which they are formed. For example, in Figure 2AIn this embodiment, insulating patterns 115 may be formed along a first direction at the lowest layer (measured from the upper surface of substrate 100) and may have a fourth thickness T4. Insulating patterns 115 formed at the second layer may have a third thickness T3, insulating patterns 115 formed at the highest layer may have a second thickness T2, and each insulating pattern 115 formed at the remaining intermediate layers may have a first thickness T1. In an example embodiment, the fourth thickness T4 may be less than the first thickness T1, the second thickness T2, and the third thickness T3, the first thickness T1 may be less than the second thickness T2 and the third thickness T3, and the second thickness T2 and the third thickness T3 may be the same, similar, or different from each other. As used herein, unless the context explicitly prohibits it, the term "thickness" is intended to be used in its conventional usage. For example, thickness means the distance between opposite surfaces of a component or layer.

[0025] Gate electrodes 343, 345, and 347 can be formed between insulating patterns 115, and thus can be formed in multiple layers to be spaced apart from each other. That is, insulating patterns 115 and gate electrodes 343, 345, and 347 can be alternately and repeatedly stacked (sequentially stacked) on substrate 100 along a first direction. Gate electrodes 343, 345, and 347 can all extend along a second direction, and multiple gate electrodes 343, 345, and 347 can be formed along a third direction. In other words, each gate electrode 343, 345, and 347 extending along the second direction can be formed through a second opening 290 extending along the second direction (see...). Figure 1 The second spacer 350 and CSL 360 in the third direction are spaced apart from each other.

[0026] The upper surface, lower surface, and sidewalls of each gate electrode 343, 345, and 347 may be covered by a second barrier pattern 310. Additionally, the second barrier pattern 310 may cover the sidewalls of the insulating pattern 115, the sidewalls of the first insulating intermediate layer 130 and the second insulating intermediate layer 280, and a portion of the upper surface of the substrate 100. The second barrier pattern 310 may extend along a first direction and be generally convex-concave.

[0027] The channel 245 may extend along a first direction on the semiconductor pattern 150 formed on the substrate 100 and may penetrate the alternately stacked insulating pattern 115 as well as the second gate electrode 345 and the third gate electrode 347.

[0028] The semiconductor pattern 150 can be cylindrical, for example, cylindrical.

[0029] In one embodiment, the upper surface of the semiconductor pattern 150 may be disposed between the upper and lower surfaces of an insulating pattern 115 (among a plurality of insulating patterns 115) having a third thickness T3.

[0030] The channel 245 can penetrate the insulating pattern 115 above the first gate electrode 343 and the insulating patterns 115 above and below the second gate electrode 345 and the third gate electrode 347. In an example embodiment, the channel 245 can be cup-shaped, and the interior space of the cup shape can be filled by a cylindrical third buried pattern 250. Alternatively, the channel 245 can also be cylindrical, in which case the third buried pattern 250 (not shown) may not be formed. A plurality of channels 245 can be formed along the second direction and the third direction respectively, thus defining a channel array.

[0031] The charge storage structure may have a cup shape with its lower surface penetrated at the center, and this cup shape may surround the outer wall of the channel 245 and extend along a first direction. The charge storage structure may include a tunnel insulating pattern 225, a charge trapping pattern 185, and a first blocking pattern 175 sequentially stacked along a third direction between the channel 245 and each of the second gate electrode 345 and the third gate electrode 347. In some example embodiments, the charge storage structure may also include one or more buried pattern structures 210, as described below.

[0032] Multiple buried pattern structures 210 may be formed along a first direction between the trench 245 and each insulating pattern 115, and may be surrounded by tunnel insulating patterns 225 and charge trapping patterns 185 to contact each tunnel insulating pattern 225 and charge trapping pattern 185. Each buried pattern structure 210 may include an inner wall contacting the tunnel insulating pattern 225 and an outer wall contacting the charge trapping pattern 185. Both the inner and outer walls of the buried pattern structure 210 may have a concave shape facing the trench 245.

[0033] In an example embodiment, the buried pattern structure 210 may include a first buried pattern 196 and a second buried pattern 206 stacked sequentially in a third direction from the inner sidewall of the charge trapping pattern 185. The first buried pattern 196 may cover the outer sidewall, upper surface, and lower surface of the second buried pattern 206, and the inner sidewall of the first buried pattern 196 may be covered by the tunnel insulation pattern 225.

[0034] It should be understood that, in the example embodiments, the terms "internal" and "external" are relative terms with meanings understood through context. For example, at least relative to... Figure 2A and Figure 2B The inner wall refers to the sidewall closest to the third burial pattern 250, while the outer wall refers to the sidewall furthest from the third burial pattern 250. Similarly, it should be understood that in the example embodiment, the terms "upper" and "lower" are relative terms with meanings understood from the context. For example, at least relative to... Figure 2A and Figure 2BThe upper surface refers to the surface furthest from the substrate 100, while the lower surface refers to the surface closest to the substrate 100. Additionally, the relative term "upper surface" can also refer to the surface located above the "lower surface" of the same element.

[0035] In an example embodiment, the first buried pattern 196 may include, for example, an oxide of silicon oxide, while the second buried pattern 206 may include, for example, silicon oxide or silicon oxynitride. Therefore, when the first buried pattern 196 and the second buried pattern 206 are formed of the same material and / or composite material, they can fuse together. For example, when the first buried pattern 196 is formed of silicon oxide and the second buried pattern 206 is also formed of silicon oxide, patterns 196 and 206 fuse; while when the first buried pattern 196 is formed of silicon oxide and the second buried pattern 206 is formed of silicon oxynitride, patterns 196 and 206 do not fuse.

[0036] In an example embodiment, the buried pattern structure 210 may be formed in the space between the tunnel insulating pattern 225 and the charge trapping pattern 185 adjacent to the insulating pattern 115 having a first thickness T1, and may not be formed in the space between the tunnel insulating pattern 225 and the charge trapping pattern 185 adjacent to the insulating pattern 115 having a second thickness T2, a third thickness T3, and a fourth thickness T4. In other example embodiments, the buried pattern structure 210 may be formed in the space between the tunnel insulating pattern 225 and the charge trapping pattern 185 adjacent to the insulating pattern 115 having a third thickness T3.

[0037] In an example embodiment, the charge storage structure may extend along a first direction and contact the outer sidewall (adjacent sidewall) of the channel 245, and for each portion of the charge storage structure formed between the channel 245 and one of the second gate electrode 345 and the third gate electrode 347, this portion (referred to as the "gate electrode adjacent portion") may have inner and outer sidewalls perpendicular to the upper surface of the substrate 100. Furthermore, for each portion of the charge storage structure formed between the insulating pattern 115 and the channel 245 (referred to as the "insulating pattern adjacent portion"), this portion may each have an outer sidewall perpendicular to the upper surface of the substrate 100.

[0038] In an example embodiment, the maximum thickness of a first portion of the charge trapping pattern 185 is less than or equal to the maximum thickness of a second portion of the charge trapping pattern 185, the first portion having a vertical sidewall relative to the upper surface of the substrate 100 and located in the horizontal direction between the channel 245 and the gate electrode 345, and the second portion having a vertical sidewall relative to the upper surface of the substrate 100 and located in the horizontal direction between the channel 245 and the insulating pattern 115.

[0039] In an example embodiment, the charge storage structure may include multiple portions having vertical sidewalls (e.g., see...). Figure 2A (Region X). It should be understood that the term "vertical" is a relative term with a meaning understood through context. In this example, the term "vertical sidewall" means a sidewall that is perpendicular to the upper surface of substrate 100. That is, substrate 100 may extend horizontally upwards in a third direction, while another element with a "vertical sidewall" may extend in a first direction perpendicular to the upper surface of substrate 100. Additionally, in the example embodiment, the thickness of the charge trapping pattern 185 may be constant throughout the pattern, i.e., the internal thickness from the immediately adjacent and corresponding surface. A first insulating interlayer 130 may be formed on a first structure including buried pattern structure 210, charge storage structure, channel 245, and uppermost insulating pattern 115. Pad 270 may penetrate the first insulating interlayer 130 to contact the upper surface of the first structure. A second insulating interlayer 280 may be formed on the first insulating interlayer 130 and pad 270.

[0040] The second spacer 350 may be formed on the sidewall of the second opening 290, which penetrates the insulating pattern 115 and the gate electrodes 343, 345 and 347 to expose the upper surface of the substrate 100. The second spacer 350 may extend along a second direction, and the CSL 360 may fill the remainder of the second opening 290.

[0041] A third insulating interlayer 370 may be formed on the second insulating interlayer 280, CSL 360, second spacer 350, and second barrier pattern 310. A contact plug 380 may penetrate the second insulating interlayer 280 and the third insulating interlayer 370 to contact the upper surface of the pad 270. A bit line 400 may penetrate the fourth insulating interlayer 390 to contact the upper surface of the contact plug 380. In an example embodiment, the bit line 400 may extend along a third direction, and multiple bit lines 400 may be formed along a second direction.

[0042] As described above, the buried pattern structure 210 can be formed on each portion of the charge storage structure located between the insulating pattern 115 and the channel 245, and each portion of the charge trapping pattern 185 adjacent to the first buried pattern structure 210 between the insulating pattern 115 and the channel 245 can have a curved shape, thereby reducing lateral charge loss of the charge trapping pattern 185. For example, the portion of the charge trapping pattern 185 located between the insulating pattern 115 and the channel 245 can have a more curved shape (greater curvature) than other vertically inclined portions (or less prominent portions) of the charge trapping pattern 185.

[0043] Furthermore, since the second gate electrode 345 and the third gate electrode 347, as well as the insulating pattern 115 (alternatingly and repeatedly stacked on the substrate 100), can be formed with an uneven shape, the outer walls of the charge storage structure that contact the second gate electrode 345 and the third gate electrode 347, as well as the insulating pattern 115, can also be formed entirely with an uneven shape. Therefore, since the charge storage structure can be at least partially arranged between the second gate electrode 345 and the third gate electrode 347, interference between the second electrode 345 and the third electrode 347 can be minimized, and the coupling rate between the second electrodes 345 used as word lines can be reduced, thereby improving the electrical characteristics of the vertical memory device.

[0044] Figures 3 to 22 This is a cross-sectional view illustrating the various stages of a method for manufacturing a vertical storage device according to an example embodiment. Specifically, Figures 3 to 7 , Figure 9 , Figure 15 and Figures 17 to 22 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 8 , Figures 10 to 14 and Figure 16 It is an enlarged cross-sectional view of region X in each corresponding cross-sectional view.

[0045] Reference Figure 3 The insulating layer 110 and the sacrificial layer 120 can be stacked alternately and repeatedly on the substrate 100. Therefore, multiple insulating layers 110 and multiple sacrificial layers 120 can be stacked alternately along the first direction. Figure 3 Eight insulating layers 110 and seven sacrificial layers 120 are shown alternately formed on the substrate 100; however, the inventive concept is not limited thereto, and more or fewer of each of the insulating layers 110 and sacrificial layers 120 may be formed.

[0046] The insulating layer 110 and the sacrificial layer 120 can be formed by processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). In particular, the insulating layer 110 can also be formed on the upper surface of the substrate 100 directly on the upper surface of the substrate 100 by a thermal oxidation process.

[0047] The insulating layer 110 may include silicon oxide, such as PE-TEOS, HDP oxide, PEOX, etc. The sacrificial layer 120 may include a material that has etch selectivity relative to the insulating layer 110, such as silicon nitride.

[0048] Reference Figure 4After the first insulating intermediate layer 130 is formed on the uppermost insulating layer 110, an etching process using an etching mask (not shown) can be performed to etch the first insulating intermediate layer 130, the insulating layer 110 and the sacrificial layer 120 below the etching mask, thereby forming a channel hole 140 to penetrate the first insulating intermediate layer 130, the insulating layer 110 and the sacrificial layer 120 and expose the upper surface of the substrate 100.

[0049] Reference Figure 5 Semiconductor patterns 150 can be formed to partially fill the channel holes 140.

[0050] For example, a selective epitaxial growth (SEG) process can be performed, using the upper surface of the substrate 100 exposed through the channel via 140 as a seed crystal, to form a semiconductor pattern 150 that partially fills the channel via 140. Thus, the semiconductor pattern 150 may include monocrystalline silicon or monocrystalline germanium depending on the material of the substrate 100, and may be doped with impurities.

[0051] Alternatively, after forming an amorphous silicon layer to fill the channel hole 140, a laser epitaxial growth (LEG) process or a solid phase epitaxial growth (SPE) process can be performed on the amorphous silicon layer to form a semiconductor pattern 150.

[0052] In an example embodiment, the upper surface of the semiconductor pattern 150 may be disposed in the insulating layer 110 between the upper and lower surfaces of the insulating layer 110 formed at a second level from the upper surface of the substrate 100 along the first direction.

[0053] Semiconductor pattern 150 can be used as a follow-up channel 245 (see Figure 17 Similar to a trench, it can therefore be called a lower trench.

[0054] Reference Figure 6 The sidewalls of each insulating layer 110 exposed by the channel hole 140 can be partially removed to form a first recess 160, a second recess 165, and a third recess 167.

[0055] In the example embodiment, the first recess 160, the second recess 165 and the third recess 167 can be formed by a dry etching process or a wet etching process.

[0056] The first recess 160, the second recess 165, and the third recess 167 can all be formed by incompletely (partially) removing each insulating layer 110, and the recesses 160, 165, and 167 can have, for example, a constant depth in the third direction. Since each insulating layer 110 can have a constant depth in the third direction, the insulating layers 110 and the sacrificial layer 120 are stacked alternately and repeatedly, and the first insulating intermediate layer 130 can generally have an uneven shape along the first direction.

[0057] In an example embodiment, a first recess 160 having a first width W1 and a second recess 165 having a second width W2 can be formed on an insulating layer 110 having a first thickness T1 and an insulating layer 110 having a second thickness T2, respectively. The first thickness T1 and the second thickness T2 can be substantially the same as the first width W1 and the second width W2, respectively. A third recess 167 having a third width W3 can be formed on an insulating layer 110 having a third thickness T3 that can be larger than the third width W3, and the recess may not be formed on an insulating layer 110 having a fourth thickness T4. That is, the recess may not be formed on the bottommost insulating layer 110, the sidewalls of the bottommost insulating layer 110 may be covered by a semiconductor pattern 150 that may be formed on the lower part of the channel hole 140, and a third recess 167 having a third width W3 that may be less than the third thickness T3 may be formed on such an insulating layer 110: the insulating layer 110 is formed at a second level from the upper surface of the substrate 100, and the sidewalls of the insulating layer 110 may be partially covered by the semiconductor pattern 150.

[0058] Reference Figure 7 and Figure 8 A first barrier layer 170, a charge trapping layer 180, and a first buried layer 190 may be sequentially formed on the sidewall of the channel hole 140, the inner wall of the first to third recesses 160, 165 and 167, the upper surface of the semiconductor pattern 150, and the upper surface of the first insulating intermediate layer 130.

[0059] The first barrier layer 170, charge trapping layer 180, and first buried layer 190 can be sequentially formed along the surfaces of the alternately and repeatedly stacked insulating layer 110 and sacrificial layer 120, as well as the surface of the first insulating intermediate layer 130. Since the alternately and repeatedly stacked insulating layer 110, sacrificial layer 120, and first insulating intermediate layer 130 can generally have an uneven shape along the first direction, the first barrier layer 170, charge trapping layer 180, and first buried layer 190 can also generally have a corresponding uneven shape along the first direction.

[0060] Depending on the properties of the material and / or the characteristics of the process used to form the first barrier layer 170, it may be formed to further fill the inner edge portion of each of the first to third recesses 160, 165, and 167. However, both the charge trapping layer 180 and the first buried layer 190 may be conformally formed to have a constant thickness.

[0061] In an example embodiment, a portion of the first barrier layer 170, a portion of the charge trapping layer 180, and a portion of the first buried layer 190 (each having a varying slope relative to the upper surface of the substrate 100) may have non-uniform thicknesses; however, at least a portion thereof (each having a vertical inclination relative to the upper surface of the substrate 100) may have a uniform thickness.

[0062] Fourth to sixth recesses 193, 195, and 197, corresponding to the first to third recesses 160, 165, and 167 on the insulating layer 110, may be formed on the first buried layer 190. The widths of the fourth to sixth recesses 193, 195, and 197 may be smaller than the widths of the first to third recesses 160, 165, and 167, respectively.

[0063] The first barrier layer 170 and the first buried layer 190 may both comprise oxides, such as silicon oxide, and the charge trapping layer 180 may comprise nitrides, such as silicon nitride. In one embodiment, the first barrier layer 170 and the first buried layer 190 may both comprise the same material as the insulating layer 110, and thus may be fused with the insulating layer 110.

[0064] Reference Figure 9 and Figure 10 A second burial layer 200 may be conformally formed on the first burial layer 190. The second burial layer 200 may include a first portion adjacent to each sacrificial layer 120 along a third direction and a second portion adjacent to each insulating layer 110 along a third direction.

[0065] With the fourth recess 193 and the fifth recess 195 on the first buried layer 190 (see...) Figure 7 The corresponding seventh recess 203 and eighth recess 205 can be formed in the second part of the second buried layer 200. (See also: seventh recess 203 and eighth recess 205) Figure 9 The width of the recess 193 and the fifth recess 195 can be smaller than the width of the fourth recess 193 and the fifth recess 195, respectively. Figure 9 It is shown that no recess corresponding to the sixth recess 197 on the first buried layer 190 is formed on the second buried layer 200. However, the inventive concept is not limited to this, and a ninth recess corresponding to the sixth recess 197 may also be formed on the second buried layer 200.

[0066] In an example embodiment, the portion of the second buried layer 200 having vertical sidewalls relative to the upper surface of the substrate 100 may have a constant thickness.

[0067] The second buried layer 200 may include nitrides, such as silicon nitride.

[0068] Reference Figure 11A first oxidation process can be performed on the second buried layer 200, and the first portion of the second buried layer 200 adjacent to each sacrificial layer 120 and the second portion adjacent to each insulating layer 110 can be oxidized respectively. Therefore, a first oxide layer 202 can be formed on the second buried layer 200, and the thickness of the second buried layer 200 can be reduced.

[0069] Since a seventh recess 203 or an eighth recess 205 can be formed on the second portion of the second buried layer 200, the surface of the second portion of the second buried layer 200 can be less exposed than the surface of the first portion, and is less affected by the first oxidation process. Therefore, the thickness of the fourth portion of the first oxide layer 202 formed by oxidizing the surface of the second portion of the second buried layer 200 can be smaller than the thickness of the third portion of the first oxide layer 202 formed by oxidizing the surface of the first portion of the second buried layer 200. For example, as... Figure 11 As shown, the thickness of the portion of the first oxide layer 202 in the middle region between the two diagonal dashed lines (the fourth portion) is less than the thickness of the portion of the first oxide layer 202 outside the middle region between the two diagonal dashed lines (the third portion).

[0070] In an example embodiment, the thickness of the fourth portion of the first oxide layer 202 may decrease as its surface exposed by the channel hole 140 approaches each insulating layer 110.

[0071] The first oxide layer 202 may include, for example, silicon oxide or silicon oxynitride.

[0072] Reference Figure 12 A first etching process can be performed to selectively remove only the first oxide layer 202, thus exposing the surface of the second buried layer 200 to the via 140. Since the third and fourth portions of the first oxide layer 202 can have different thicknesses, the first and second portions of the second buried layer 200 can also have different thicknesses.

[0073] In an example embodiment, a first portion of the second buried layer 200 may have a constant thickness, while a second portion of the second buried layer 200 may have a thickness that increases toward the insulating layer 110.

[0074] The first etching process may include a wet etching process or a dry etching process.

[0075] Reference Figure 13 A second oxidation process can be performed to oxidize all the first and second portions of the second buried layer 200, thereby forming a second oxide layer 204 on the first buried layer 190.

[0076] The second oxide layer 204 may include, for example, silicon oxide or silicon oxynitride, and the second oxide layer 204 may be fused with the first buried layer 190 if the second oxide layer 204 and the first buried layer 190 may include the same or substantially the same material as each other.

[0077] Reference Figure 14 A second etching process can be performed until the surfaces of the charge trapping layer 180 that are horizontally adjacent to each sacrificial layer 120 can be exposed, and the second oxide layer 204 and the first buried layer 190 of a predetermined thickness can be removed from the charge trapping layer 180. For example, as Figure 14 As shown, the second etching process completely removes the portion of the second oxide layer 204 and the portion of the first buried layer 190 horizontally adjacent to the sacrificial layer 120. Therefore, the first buried pattern 196 and the second buried pattern 206 can be formed, and they can together form the buried pattern structure 210. Additionally, the portion of the charge trapping layer 180 horizontally adjacent to each sacrificial layer 120 can be selectively etched, thereby giving the corresponding portions of the charge trapping layer 180 alternating thicknesses. For example, the thickness of the portion of the charge trapping layer 180 horizontally adjacent to the sacrificial layer 120 can be less than the thickness of the portion of the charge trapping layer 180 horizontally adjacent to the insulating layer 110.

[0078] The portions of the second buried layer 200 and the first buried layer 190 adjacent to each sacrificial layer 120 may each have a constant thickness; however, the portions of the second buried layer 200 and the first buried layer 190 adjacent to each insulating layer 120 may each have a thickness that increases toward the insulating layer 110 (see [link]). Figures 12 to 13 Therefore, the relatively thin portions of the second buried layer 200 and the first buried layer 190 adjacent to each sacrificial layer 120 can be completely removed, while the relatively thick portions of the second buried layer 200 and the first buried layer 190 adjacent to the insulating layer 110 can be retained to form the buried pattern structure 210.

[0079] In an example embodiment, the surface of the buried pattern structure 210 exposed by the channel aperture 140 may have a slope that varies relative to the upper surface of the substrate 100, and the thickness of the buried pattern structure 210 may decrease as its exposed surface approaches each insulating layer 110. For example, the sidewalls of the buried pattern structure 210 may be curved away from the channel aperture 140, and thus may have a non-uniform thickness, with its minimum thickness corresponding to the midpoint between adjacent sacrificial layers 120.

[0080] The second etching process may include a wet etching process or a dry etching process.

[0081] Reference Figure 15 and Figure 16A tunnel insulation layer 220 and a first spacer layer 230 can be sequentially formed on the charge trapping layer 180 and the buried pattern structure 210.

[0082] The tunnel insulation layer 220 may include, for example, silicon oxide, and the first spacer layer 230 may include, for example, silicon nitride.

[0083] Reference Figure 17 The first spacer layer 230 can be etched anisotropically to form a first spacer 235 that can be formed only on the sidewall of the channel hole 140 and expose the tunnel insulating layer 220 underneath. The first spacer 235 can be used as an etching mask to etch the tunnel insulating layer 220, the charge trapping layer 180 and the first barrier layer 170.

[0084] Therefore, portions of the tunnel insulating layer 220, the charge trapping layer 180, and the first barrier layer 170 located on the upper surface of the semiconductor pattern 150, as well as portions of the tunnel insulating layer 220, the charge trapping layer 180, and the first barrier layer 170 located on the upper surface of the first insulating intermediate layer 130, can be removed, and the upper part of the semiconductor pattern 150 can also be partially removed.

[0085] Through an etching process, the tunnel insulating layer 220 can be transformed into a tunnel insulating pattern 225, the charge trapping layer 180 can be transformed into a charge trapping pattern 185, and the first barrier layer 170 can be transformed into a first barrier pattern 175. Therefore, the tunnel insulating pattern 225, the charge trapping pattern 185, and the first barrier pattern 175 can all have a cup shape with the center of their lower surfaces penetrated. The buried pattern structure 210 between the charge trapping pattern 185 and the tunnel insulating pattern 225 can be annular.

[0086] The tunnel insulation pattern 225, the charge trapping pattern 185, and the first blocking pattern 175 can together form a charge storage structure.

[0087] Reference Figure 18 After removing the first spacer 235 to expose the tunnel insulation pattern 225, a trench layer can be formed on the exposed tunnel insulation pattern 225, semiconductor pattern 150 and first insulating intermediate layer 130, and a third buried layer that fully fills the remainder of the trench hole 140 can be formed on the trench layer.

[0088] The channel layer may include, for example, doped or undoped polycrystalline silicon or amorphous silicon. When the channel layer includes amorphous silicon, a laser epitaxial growth (LEG) process or a solid-state epitaxy (SPE) process may be further performed to transform the amorphous silicon into crystalline silicon. The third buried layer may include an oxide, such as silicon oxide.

[0089] By planarizing the third buried layer and the trench layer until the upper surface of the first insulating intermediate layer 130 can be exposed, a third buried pattern 250 can be formed to fill the remainder of the trench hole 140, and the trench layer can be transformed into a trench 245.

[0090] Therefore, the charge storage structure, channel 245, and third buried pattern 250 can be sequentially stacked on the semiconductor pattern 150 within the channel via 140. The charge storage structure can have a cup shape with its lower surface center penetrated, and the third buried pattern 250 can have a cylindrical shape.

[0091] Multiple channels 245 can be formed along each of the second and third directions to form a channel array.

[0092] The upper part of the first structure, including the third buried pattern 250, the channel 245 and the charge storage structure, can be removed to form a trench, and pads 270 can be formed to fill the trench.

[0093] Specifically, after removing the upper portion of the first structure to form a trench using an etch-back process, a pad layer can be formed on the first structure and the first insulating intermediate layer 130 to fill the trench, and the upper portion of the pad layer can be planarized until the upper surface of the first insulating intermediate layer 130 can be exposed to form pads 270. In an example embodiment, the pad layer may include doped polysilicon or amorphous silicon, and when the pad layer includes amorphous silicon, a process for crystallizing the pad layer can be further performed.

[0094] Reference Figure 19 and Figure 20 After the second insulating intermediate layer 280 is formed on the first insulating intermediate layer 130 and the pad 270, a second opening 290 can be formed through the first insulating intermediate layer 130, the second insulating intermediate layer 280, the insulating layer 110 and the sacrificial layer 120 by an etching process using an etching mask to expose the upper surface of the substrate 100.

[0095] In an example embodiment, the second opening 290 may be formed to extend along a second direction, and a plurality of second openings 290 may be formed along the second direction.

[0096] When the second opening 290 is formed, the insulating layer 110 can be transformed into the insulating pattern 115, and the sacrificial layer 120 can be transformed into the sacrificial pattern (not shown).

[0097] The sacrificial pattern exposed by the second opening 290 can be removed to form a gap 300 between the insulating patterns 115 at each level, and a portion of the outer wall of the first blocking pattern 175 and a portion of the sidewall of the semiconductor pattern 150 can be exposed through the gap 300. In an example embodiment, the sacrificial pattern exposed through the second opening 290 can be removed by a wet etching process using an etchant containing phosphoric acid or sulfuric acid.

[0098] Reference Figure 20 A second barrier pattern 310 may be formed on the exposed outer sidewall of the first barrier pattern 175, the exposed sidewall of the semiconductor pattern 150, the inner wall of the gap 300, the surface of the insulating pattern 115, the exposed upper surface of the substrate 100, and the upper surface of the second insulating intermediate layer 280. A gate barrier layer 320 may be formed on the second barrier pattern 310, and a gate conductive layer 330 may be formed on the gate barrier layer 320 to fully fill the remaining portion of the gap 300.

[0099] The second barrier pattern 310 may include a metal oxide, such as aluminum oxide, hafnium oxide, zirconium oxide, etc. The gate conductive layer 330 may include a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc. The gate barrier layer 320 may include a metal nitride, such as titanium nitride, tantalum nitride, etc. Alternatively, the gate barrier layer 320 may also include a first layer containing a metal and a second layer containing a metal nitride.

[0100] Reference Figure 21 The gate conductive layer 330 and the gate barrier layer 320 can be partially removed to form a gate conductive pattern and a gate barrier pattern respectively in the gap 300, and the gate conductive pattern and the gate barrier pattern can be formed together to form a gate electrode. In an example embodiment, the gate conductive layer 330 and the gate barrier layer 320 can be partially removed by a wet etching process.

[0101] In an example embodiment, the gate electrode may extend along a second direction, and multiple gate electrodes may be formed along a third direction. For example, multiple gate electrodes all extending along the second direction may be spaced apart from each other in the third direction through a second opening 290.

[0102] The gate electrode may include first to third gate electrodes 343, 345, and 347 formed sequentially along a first direction. The first gate electrode 343 may serve as a ground select line (GSL), the second gate electrode 345 may serve as a word line, and the third gate electrode 347 may serve as a serial select line (SSL). The first to third gate electrodes 343, 345, and 347 may each be formed in one or more layers. Additionally, one or more dummy word lines may be formed between the first gate electrode 343 and the second gate electrode 345 and / or between the second gate electrode 345 and the third gate electrode 347.

[0103] In an example embodiment, the first gate electrode 343 may be formed at the lowest level of the gate structure (directly above the lowest insulating pattern 115), the third gate electrode 347 may be formed at the highest level of the gate structure (directly below the highest insulating pattern 115) and at a level directly below the highest level, and the second gate electrode 345 may be formed at multiple levels between the first gate electrode 343 and the third gate electrode 347. Therefore, the first gate electrode 343 may be formed horizontally adjacent to the semiconductor pattern 150, and both the second gate electrode 345 and the third gate electrode 347 may be formed horizontally adjacent to the channel 245. For example, the first gate electrode 343 may be formed at the same height or at the same level as the semiconductor pattern 150, and may also be adjacent to or near each other.

[0104] The first gate electrode 343 may include a first gate conductive pattern 333 and a first gate blocking pattern 323 covering the upper and lower surfaces and part of the sidewalls of the first gate conductive pattern 333. The second gate electrode 345 may include a second gate conductive pattern 335 and a second gate blocking pattern 325 covering the upper and lower surfaces and part of the sidewalls of the second gate conductive pattern 335. The third gate electrode 347 may include a third gate conductive pattern 337 and a third gate blocking pattern 327 covering the upper and lower surfaces and part of the sidewalls of the third gate conductive pattern 337.

[0105] Reference Figure 22 After impurities are implanted into the upper portion of the exposed substrate 100 to form impurity region 105, a second spacer layer can be formed on the upper surface of impurity region 105, the sidewalls of the second opening 290, and the upper surface of the second insulating intermediate layer 280. The second spacer layer 280 can be anisotropically etched to form a second spacer 350 on the sidewalls of the second opening 290, thus partially exposing the impurity region 105 on the upper portion of the substrate 100.

[0106] Impurities may include n-type impurities, such as phosphorus and arsenic, and the second spacer layer may include oxides, such as silicon oxide.

[0107] A common source line (CSL) 360 can be formed on the exposed impurity region 105 to fill the remainder of the second opening 290.

[0108] In an example embodiment, after forming a conductive layer on the exposed impurity region 105, the second spacer 350, and the second insulating intermediate layer 280 to fill the second opening 290, the upper portion of the conductive layer can be planarized until the upper surface of the second insulating intermediate layer 280 can be exposed to form CSL 360. The portion of the second barrier pattern 310 located on the upper surface of the second insulating intermediate layer 280 can be removed along with the conductive layer. The conductive layer may include, for example, a metal, a metal nitride, and / or a metal silicide.

[0109] Refer again Figure 1 , Figure 2A and Figure 2B After the third insulating intermediate layer 370 is formed on the second insulating intermediate layer 280, CSL 360, second spacer 350 and second blocking pattern 310, a contact plug 380 can be formed to penetrate the third insulating intermediate layer 370 and the second insulating intermediate layer 280 and contact the upper surface of the pad 270.

[0110] After the fourth insulating intermediate layer 390 is formed on the third insulating intermediate layer 370 and the contact plug 380, a bit line 400 that penetrates the fourth insulating intermediate layer 390 and contacts the upper surface of the contact plug 380 can be formed to complete the manufacturing of the vertical storage device.

[0111] The third insulating intermediate layer 370 and the fourth insulating intermediate layer 390 may include oxides, such as silicon oxide, and the contact plug 380 and bit line 400 may include, for example, metals (e.g., copper, aluminum, tungsten, titanium, tantalum, etc.) and / or metal nitrides (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.).

[0112] In the example embodiment, bit line 400 may extend along a third direction, and multiple bit lines 400 may be formed along a second direction.

[0113] Figure 23 This is a cross-sectional view showing a vertical storage device according to an example embodiment. Except for the shapes of the burial pattern structure 210, the tunnel insulation pattern 225, and the trench 245, the vertical storage device is similar to... Figure 1 , Figure 2A and Figure 2B The vertical storage device described herein. Therefore, the same reference numerals refer to the same elements, and their detailed description is omitted here.

[0114] Reference Figure 23 The vertical storage device may include an insulating pattern 115, gate electrodes 343, 345 and 347, a channel 245, a charge storage structure and a buried pattern structure 210 located on a substrate 100.

[0115] However, the outer sidewall of the buried pattern structure 210 may be concave toward the channel 245, while the inner sidewall of the buried pattern structure 210 may have a vertical sidewall relative to the upper surface of the substrate 100.

[0116] Figures 24 to 26 This is a cross-sectional view illustrating the stages of a method for manufacturing a vertical storage device according to an example embodiment. Figure 24 It is along Figure 1 A cross-sectional view taken from line A-A'. Figures 25 to 26 yes Figure 24 A magnified cross-sectional view of region X in the diagram. The method includes... Figures 3 to 22 as well as Figure 1 , Figure 2A and Figure 2B The processes described herein are essentially the same or similar, so repeated descriptions are omitted here.

[0117] Reference Figure 24 and Figure 25 It can execute with Figures 3 to 10 The process is similar to the one described in the text.

[0118] However, it is not necessary to form a seventh recess 203 and an eighth recess 205 on the second portion of the second buried layer 200 adjacent to each insulating layer 110, which correspond to the fourth recess 193 and the fifth recess 195 on the first buried layer 190, respectively.

[0119] Therefore, the surface of the second buried layer 200 exposed by the channel hole 140 can be a vertical sidewall relative to the upper surface of the substrate 100, and the thickness of the portion of the second buried layer 200 adjacent to each insulating layer 110 can be greater than the thickness of the other portions of the second buried layer 200.

[0120] In an example embodiment, the second buried layer 200 may include a nitride, such as silicon nitride, which has excellent gap-filling properties, and thus can completely fill the fourth recess 193 and the fifth recess 195 on the first buried layer 190. In some cases, to make the surface of the second buried layer 200 exposed by the channel via 140 a sidewall perpendicular to the upper surface of the substrate 100, an additional etching process may be performed.

[0121] Reference Figure 26 It can execute with Figures 11 to 14 The process is similar to the one described in the text.

[0122] Therefore, a buried pattern structure 210 including a first buried pattern 196 and a second buried pattern 206 can be formed on the portion of the charge trapping layer 180 adjacent to each insulating layer 110, and the inner sidewall of the buried pattern structure 210 can be perpendicular to the upper surface of the substrate 100.

[0123] Refer again Figure 23 It can execute with Figures 15 to 22 as well as Figure 1 , Figure 2A and Figure 2B A process similar to that described in the text is used to manufacture vertical storage devices.

[0124] Figure 27 This is a cross-sectional view showing a vertical storage device according to an example embodiment. Except for the shapes of the burial pattern structure 210, the tunnel insulation pattern 225, and the trench 245, the vertical storage device is similar to... Figure 1 , Figure 2A and Figure 2B The vertical storage device described herein. Therefore, the same reference numerals refer to the same elements, and their detailed description is omitted here.

[0125] Reference Figure 27 The vertical storage device may include an insulating pattern 115, gate electrodes 343, 345 and 347, a channel 245, a charge storage structure and a buried pattern structure 210 located on a substrate 100.

[0126] However, with Figure 2A and Figure 2B Unlike the vertical storage device described herein, the outer sidewall of the buried pattern structure 210 may have a concave shape facing the channel 245, and the inner sidewall of the buried pattern structure 210 may have a convex shape facing the channel 245.

[0127] Figures 28 to 33 This is a cross-sectional view illustrating the stages of a method for manufacturing a vertical storage device according to an example embodiment. Figure 28 It is along Figure 1 A cross-sectional view taken from line A-A'. Figures 29 to 33 yes Figure 28 A magnified cross-sectional view of region X in the diagram. The method includes... Figures 3 to 22 as well as Figure 1 , Figure 2A and Figure 2B The process is similar to the one described in the previous section, so its repeated description is omitted here.

[0128] Reference Figure 28 and Figure 29 It can execute with Figures 3 to 10 The process is similar to the one described in the text.

[0129] However, it is not necessary to form a seventh recess 203 and an eighth recess 205 on the second portion of the second buried layer 200 adjacent to each insulating layer 110, which correspond to the fourth recess 193 and the fifth recess 195 on the first buried layer 190, respectively.

[0130] In an example embodiment, the first buried layer 190 and the second buried layer 200 may comprise materials different from each other; that is, they may comprise oxides (e.g., silicon oxide) and nitrides (e.g., silicon nitride), respectively. Furthermore, the first buried layer 190 and the second buried layer 200 may be formed to have different densities, or have a specific gravity greater or less than that of the reference material. Therefore, the first buried layer 190 and the second buried layer 200 can be etched to different thicknesses by a second etching process, as will be referred to later. Figure 41 This will be described.

[0131] Reference Figure 30 It can execute with Figure 11 The process is similar to the one described in the text.

[0132] However, the first oxide layer 202 can be formed by the first oxidation process, but the second buried layer 200 may not be retained on the portion of the first buried layer 190 adjacent to each sacrificial layer 120.

[0133] Reference Figure 31 It can execute with Figure 12 The process is similar to the one described in the text.

[0134] Therefore, the first oxide layer 202 can be selectively removed by the first etching process, and the second buried layer 200 can be formed only on the portion of the first buried layer 190 adjacent to each insulating layer 110.

[0135] Reference Figure 32 It can execute with Figure 13 The process is similar to the one described in the text.

[0136] Therefore, the second buried layer 200 can be completely oxidized by the second oxidation process to form the second oxide layer 204.

[0137] Reference Figure 33 It can execute with Figure 14 The process is similar to the one described in the text.

[0138] Therefore, the first buried layer 190 and the second oxide layer 204 can be removed by a second etching process. However, since the first buried layer 190 and the second oxide layer 204 have different densities or different specific gravities compared to the reference material, a second etching process can be performed to remove the first buried layer 190 and the second oxide layer 204 of different thicknesses.

[0139] In an example embodiment, the surface of the first buried pattern 196 exposed through the channel hole 140 may be perpendicular to the upper surface of the substrate 100 (at least at both ends in a first direction), the surface of the second buried pattern 206 exposed through the channel hole 140 may have a slope that varies relative to the upper surface of the substrate 100, and in this case, the second buried pattern 206 may have a shape that protrudes from the first buried pattern 196 along a third direction.

[0140] In an example embodiment, the burial pattern structure 210, which includes a first burial pattern 196 and a second burial pattern 206, may have a maximum thickness at its central portion in a first direction and a minimum thickness at both ends in the first direction.

[0141] Refer again Figure 27 It can execute with Figures 15 to 22 as well as Figure 1 , Figure 2A and Figure 2B A process similar to that described in the text is used to manufacture vertical storage devices.

[0142] Figures 34 to 37 These are plan and cross-sectional views illustrating a vertical storage device according to an example embodiment. (Figure) Figure 34 It's a floor plan. Figure 35 It is along Figure 34 A cross-sectional view taken from line B-B'. Figure 36 yes Figure 35 A magnified cross-sectional view of region Y in the image. Figure 37 yes Figure 35 An enlarged cross-sectional view of region Z in the diagram.

[0143] Vertical storage devices include those with Figure 1 , Figure 2A and Figure 2B The charge storage structure, buried pattern structure, and channel of the vertical storage device described herein are similar, so their repeated description is omitted here.

[0144] Reference Figure 34 and Figure 35 The vertical memory device may include: a channel connection pattern 735; gate electrodes 760, 770, and 780 located on the channel connection pattern 735; gate electrodes 760, 770, and 780 sequentially stacked to be spaced apart from each other along a first direction and all extending along a second direction; a channel 660 extending along the first direction on a substrate 500, the channel 660 penetrating the gate electrodes 760, 770, and 780 and the channel connection pattern 735; and a CSL 800 extending along the second direction on the substrate 500, the CSL 800 separating the gate electrodes 760, 770, and 780 and the channel connection pattern 735 in a third direction.

[0145] Additionally, the vertical memory device may also include: an impurity region 505 located on the upper part of the substrate 500; a support pattern 540 formed on the substrate 500 to contact the sidewalls of the channel connection pattern 735; a support layer 550 located between the channel connection pattern 735 and the support pattern 540 and the lowermost gate electrode 760 among the gate electrodes 760, 770 and 780; an insulating pattern 565 located between the gate electrodes 760, 770 and 780; a charge storage structure covering the outer sidewalls and lower surface of the channel 660; a third buried pattern 670 filling the space defined by the channel 660; and pads 680 located on the channel 660, the third buried pattern 670 and the charge storage structure, covering the CSL. The second spacer 790 on the sidewall of 800 covers the upper and lower surfaces of the gate electrodes 760, 770 and 780 and the second blocking pattern 750 on part of the sidewall, the first to fourth insulating intermediate layers 580, 690, 810 and 830 are sequentially stacked on the gate electrodes 760, 770 and 780, the contact plug 820 penetrates the second insulating intermediate layer 690 and the third insulating intermediate layer 810 to contact the upper surface of the pad 680, and the bit line 840 penetrates the fourth insulating intermediate layer 830 to contact the upper surface of the contact pad 680.

[0146] Reference Figure 36 and Figure 37 The charge storage structure may include a first blocking pattern 600, a charge trapping pattern 610, and a tunnel insulation pattern 650, and a plurality of buried pattern structures 640 may be formed between the charge trapping pattern 610 and the tunnel insulation pattern 650 of the charge storage structure. The buried pattern structure 640 may include a first buried pattern 620 and a second buried pattern 630.

[0147] A plurality of buried pattern structures 640 may be formed between the trench 660 and each insulating pattern 565 along a first direction. The buried pattern structure 640 may be surrounded by tunnel insulating patterns 650 and charge trapping patterns 610 to contact each tunnel insulating pattern 650 and charge trapping pattern 610. Each buried pattern structure 640 may include an inner sidewall contacting the tunnel insulating pattern 650 and an outer sidewall contacting the charge trapping pattern 610. In an example embodiment, both the inner and outer sidewalls of the buried pattern structure 640 may have a concave shape facing the trench 660.

[0148] Because this example vertical storage device includes a support layer 550 and a channel connection pattern 735, instead of Figure 1 , Figure 2A and Figure 2BThe semiconductor pattern 150 of the vertical memory device described herein allows the charge storage structure and buried pattern structure 640 to be further formed on the sidewall of the insulating pattern 565 between the bottommost gate electrode 760 and the support layer 550.

[0149] In an example embodiment, the first blocking pattern 600, the charge trapping pattern 610, and the tunnel insulation pattern 650 are stacked sequentially around the trench 660. That is, the charge storage structure may have an annular shape, and each buried pattern structure 640 formed between the charge trapping pattern 610 and the tunnel insulation pattern 650 of the charge storage structure may also have an annular shape.

[0150] Figures 38 to 48 This is a cross-sectional view illustrating the various stages of a method for manufacturing a vertical storage device according to an example embodiment. Specifically, Figures 38 to 40 and Figures 43 to 48 It is along Figure 34 A cross-sectional view taken from line B-B'. Figure 41 yes Figure 40 A magnified cross-sectional view of region Y in the image. Figure 42 yes Figure 40 An enlarged cross-sectional view of region Z in the diagram.

[0151] Reference Figure 38 The first to third sacrificial layers 510, 520 and 530 can be stacked sequentially on the substrate 500. The first to third sacrificial layers 510, 520 and 530 can be partially removed to form a support pattern 540 and a support layer 550, which can be formed on the third sacrificial layer 530 and the support pattern 540.

[0152] The first sacrificial layer 510 and the third sacrificial layer 530 may include oxides, such as silicon oxide, and the second sacrificial layer 520 may include nitrides, such as silicon nitride.

[0153] The support pattern 540 can be formed by partially removing the first to third sacrificial layers 510, 520, and 530 to form a first opening and filling the first opening. Therefore, the support pattern 540 can be formed at the same height as the structure including the first to third sacrificial layers 510, 520, and 530, and the sidewalls of the support pattern 540 can contact the sidewalls of the first to third sacrificial layers 510, 520, and 530.

[0154] In an example embodiment, the support pattern 540 and support layer 550 may include a material having etch selectivity relative to each of the first to third sacrificial layers 510, 520, and 530, such as doped or undoped polycrystalline silicon. In one embodiment, the support pattern 540 and support layer 550 may be formed by first depositing amorphous silicon and then performing additional heat treatment processes or crystallization by heat generated in subsequent deposition processes of other layers to form polycrystalline silicon.

[0155] Support pattern 540 can be formed to form the second opening 700 (see reference). Figure 43 The areas of the description overlap. The second opening 700 may extend along the second direction, and multiple second openings 700 may be formed along a third direction. Furthermore, correspondingly, one or more support patterns 540 may extend along the second direction, and multiple support patterns 540 may be formed in a third direction. The insulating layer 560 and the fourth sacrificial layer 570 may be alternately and repeatedly stacked on the support layer 550 to form a mold in the first direction.

[0156] Reference Figure 39 After forming the first insulating intermediate layer 580 on the uppermost insulating layer 560, a set of channel holes 590 can be formed by a dry etching process to penetrate the first to third sacrificial layers 510, 520, and 530. For example, as Figure 39 As shown, both the first channel hole 590 and the second channel hole 590 penetrate the first to third sacrificial layers 510, 520, and 530. For ease of understanding, the example embodiment can be considered as including both the first channel hole 590 and the second channel hole 590.

[0157] Reference Figures 40 to 42 It can execute with Figures 5 to 19 The process is similar to the one described in the text.

[0158] Therefore, a charge storage structure including a first blocking pattern 600, a charge trapping pattern 610, and a tunnel insulating pattern 650, a plurality of insulating pattern structures 640 located between the charge trapping pattern 610 and the tunnel insulating pattern 650, and a channel 660 can be formed to partially fill the channel hole 590. A third buried pattern 670 can be formed to fill the remaining portion of the channel hole 590. Each insulating pattern structure 640 may include a first buried pattern 620 and a second buried pattern 630.

[0159] The upper part of the first structure, including a portion of the third buried pattern 670, a portion of the channel 660, and a portion of the charge storage structure, can be removed to form a trench (not shown), and a pad 680 can be formed to cover the trench (i.e., the removed portion of the third buried pattern 670, the channel 660, and the charge storage structure that was removed to form the trench).

[0160] However, in some example embodiments, it may not be formed in Figures 5 to 19 The semiconductor pattern 150 described herein allows the sequentially formed charge storage structure to cover a portion of the upper surface of the substrate 500.

[0161] In an example embodiment, the charge storage structure and channel 660 may be cup-shaped, the third burial pattern 670 in the inner space of the cup-shaped structure may be columnar, and each insulating pattern structure 640 located between the charge trapping pattern 610 of the charge storage structure and the tunnel insulating pattern 650 may be annular.

[0162] Reference Figure 43 After forming the second insulating intermediate layer 690 on the first insulating intermediate layer 580 and the pad 680, a set of second openings 700 can be formed by a dry etching process to penetrate the first insulating intermediate layer 580, the second insulating intermediate layer 690, and the mold. For example, as Figure 44 As shown, the first opening 700 (left side of the page) and the second opening 700 (right side of the page) penetrate the first insulating intermediate layer 580 and the second insulating intermediate layer 690. For ease of understanding, the example embodiment can be considered to include both the first opening 700 and the second opening 700. In the example embodiment, a dry etching process can be performed until the second set of openings 700 can expose the upper surface of the support layer 550, and a further dry etching process can be performed until the second opening 700 can penetrate the upper part of the support layer 550. When the second set of openings 700 is formed, the insulating layer 560 and the fourth sacrificial layer 570 of the mold can be exposed by the sidewalls of the second opening 700.

[0163] In an example embodiment, the second opening 700 may extend along a second direction, and a plurality of second openings 700 may be formed along a third direction. When the second opening 700 is formed, the insulating layer 560 may be transformed into an insulating pattern 565 extending along the second direction, and the fourth sacrificial layer 570 may be transformed into a fourth sacrificial pattern 575 extending along the second direction.

[0164] Reference Figure 44After the first spacer 710 is formed on the sidewall of the second opening 700, the portion of the support layer 550 exposed through the lower surface of each of the second set of openings 700 below it can be removed, so that the second set of openings extends downward through the support layer 550. Additionally, the portions of the first to third sacrificial layers 510, 520, and 530 below the opening 700 (located on the right side of the page) can be removed, so that the second opening 700 (the opening 700 on the right side of the page) extends downward and exposes the upper surface of the substrate 500. The extension of the second set of openings 700 can thereby form a third set of openings 705, one of which (on the left side of the page) extends into the support pattern 540 (i.e., partially within the upper part of the support pattern 540), and another opening 705 (on the right side of the page) extends into the substrate (i.e., partially within the upper part of the substrate 500).

[0165] In an example embodiment, the first spacer 710 can be formed by forming a first spacer layer covering the inner wall of the second set of openings 700 and the upper surface of the second insulating intermediate layer 690, and then anisotropically etching the first spacer layer. The first spacer 710 may include, for example, doped or undoped polysilicon.

[0166] The third opening 705 (right-hand side) can not only expose the upper surface of the substrate 500, but also penetrate a portion of the upper part of the substrate 500. The third opening 705 (left-hand side) can expose the upper surface of the support pattern 540, and also penetrate a portion of the upper part of the support pattern 540.

[0167] In an example embodiment, when the third set of openings 705 is formed, since the first spacer 710 is formed on the sidewall of the second set of openings 700, the width of the portion formed by the downward extension of the second opening 700 (i.e., the lower part of the third opening 705) can be smaller than the width of the second set of openings 700 (i.e., the width of the upper part of the third opening 705). For example, the width of each uppermost part of each opening 705 in the third set of openings 705 is greater than the width of each lowermost part of each opening 705 in the third set of openings 705.

[0168] Reference Figure 45 The first to third sacrificial layers 510, 520 and 530, which can be exposed by the third opening 705 (right side), can be removed to form the first gap 720.

[0169] In an example embodiment, the second sacrificial layer 520 can be removed by a wet etching process using phosphoric acid (H3PO4), and the first sacrificial layer 510 and the third sacrificial layer 530 can be removed by a wet etching process using hydrofluoric acid (HF).

[0170] When forming the first gap 720, the lower part of the charge storage structure covering the lower part of the outer wall of the channel 660 can be exposed, and the exposed part of the charge storage structure can be further removed to expose the lower part of the outer wall of the channel 660.

[0171] The lower part of the charge storage structure can be removed, for example, by a wet etching process using phosphoric acid (H3PO4) or a wet etching process using hydrofluoric acid (HF). When the lower part of the charge storage structure is removed, the charge storage structure can be understood as being divided into upper and lower parts. That is, the upper part of the charge storage structure can penetrate the mold to cover a portion of the outer wall of the channel 660, and the lower part of the charge storage structure can be formed on the upper surface of the substrate 500 to cover the lower surface of the channel 660.

[0172] exist Figure 45 In an example embodiment, the first gap 720 may include a filler located between the lower surface of the support layer 550 and the upper surface of the substrate 500 and adjacent to the outer wall of the channel 660.

[0173] When the first gap 720 is formed, the support pattern 540 does not need to be removed, so the mold will not collapse. In addition, when the first gap 720 is formed, the lower surface of the mold can be covered by the support layer 550, and the lower part of the mold does not need to be removed.

[0174] Reference Figure 46 A channel connection layer 730 can be formed to fill the first gap 720, and the channel connection layer 730 can also be formed on the sidewalls and lower surface of the third set of openings 705 and on the upper surface of the second insulating intermediate layer 690. Since the channel connection layer 730 is formed to fill the first gap 720, the channels 660 can be connected to each other to form a channel array.

[0175] The portion of the channel connection layer 730 located in the first gap 720 may include an air gap 740.

[0176] The channel interconnect layer 730 may include, for example, polysilicon doped with impurities.

[0177] Reference Figure 47 The channel connection layer 730 can be partially removed so that the channel connection pattern 735 is formed only in the first gap 720.

[0178] In an example embodiment, the channel connection pattern 735 can be formed by performing an etch-back process to remove portions of the channel connection layer 730 located within a set of third openings 705. During the etch-back process, the first spacer 710 (located on the sidewall of the third opening 705) can also be removed.

[0179] The upper portion of the substrate 500 exposed by the third opening 705 can be doped with impurities to form an impurity region 505. In an example embodiment, the impurity region 505 may contact the lower surface of the channel connection pattern 735, so that the impurity region 505 may be electrically connected to the channel connection pattern 735 comprising impurity-doped polysilicon.

[0180] Reference Figure 48 It can execute with Figures 20 to 25 A process similar to that described in the text is used to manufacture vertical storage devices.

[0181] Specifically, after removing each fourth sacrificial pattern 575 to form the second gap, the second barrier pattern 750 can be formed on the exposed outer wall of the first barrier pattern 600, the inner wall of the second gap, the surface of the insulating pattern 565, the surface of the support layer 550, the surface of the channel connection pattern 735, the exposed upper surface of the substrate 500, the upper surface of the support pattern 540, and the sidewall of the second insulating intermediate layer 690, and a gate electrode layer can be formed on the second barrier pattern 750.

[0182] The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked sequentially. The gate conductive layer may include a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc. The gate barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0183] The gate electrode layer can be partially removed to form a gate electrode in each of the second gaps. In an example embodiment, the gate electrode layer can be partially removed by a wet etching process, and the gate electrode formed therefrom can fill some or all of each of the second gaps.

[0184] The gate electrode can extend along the second direction, and multiple gate electrodes can be formed along the third direction. That is, the gate electrodes extending along the second direction can be spaced apart from each other through the third opening 705.

[0185] In an example embodiment, the gate electrodes may be formed in multiple layers spaced apart from each other along a first direction, and the gate electrodes in the multiple layers may form a gate electrode structure. The gate electrode structure may include one or more first gate electrodes 760, a plurality of second gate electrodes 770, and one or more third gate electrodes 780 stacked sequentially. For example, the gate electrode structure may include a first gate electrode 760, a series of second gate electrodes 770 above the first gate electrode 760, and a series of third gate electrodes 780 above the second gate electrodes 770. The number of layers formed by each of the first to third gate electrodes 760, 770, and 780 may vary depending on the number of layers in the fourth sacrificial pattern 575.

[0186] After the second spacer layer is formed on the second barrier pattern 750, the second spacer layer can be anisotropically etched to form the second spacer 790 on the sidewalls of a set of third openings 705, and thus partially expose the upper surface of the second barrier pattern.

[0187] The portion of the second barrier pattern 750 not covered by the second spacer 790 can be etched using the second spacer 790, and the portion of the second barrier pattern 750 located on the upper surface of the second insulating intermediate layer 690 can also be removed. In this case, the substrate 500 (i.e., the upper part of the impurity region 505) and the support pattern 540 can also be partially removed.

[0188] After a conductive layer is formed on substrate 500 (i.e., the upper surface of impurity region 505, the upper surface of support pattern 540, the second spacer 790, and the second insulating intermediate layer 690) to fill the remainder of the third opening 705, the conductive layer may be planarized until the upper surface of the second insulating intermediate layer 690 can be exposed to form a common source line CSL 800. CSL 800 may include a metal, such as tungsten.

[0189] In an example embodiment, CSL 800 may extend along a first direction and may also extend along a second direction. The lower surface of CSL 800 (right-hand side) may be covered by substrate 500 (i.e., impurity region 505), and the lower surface of CSL 800 (left-hand side) may be covered by support pattern 540. Alternatively, CSL 800 may completely penetrate support pattern 540 and may be covered by a portion of substrate 500 located below support pattern 540.

[0190] After forming a third insulating intermediate layer 810 on the second insulating intermediate layer 690, CSL 800, second spacer 790, and second barrier layer 750, a contact plug 820 can be formed to penetrate the second and third insulating intermediate layers 690 and contact the upper surface of the pad 680. For example, as Figure 48 As shown, each of the paired contact plugs 820 contacts a corresponding pad 680. A fourth insulating intermediate layer 830 is formed on the third insulating intermediate layer 810 and the contact plugs 820 (see...). Figure 34 After that, bit lines 840 can be formed that penetrate the fourth insulating intermediate layer 830 and contact the upper surface of the contact plug 820 to complete the manufacturing of the vertical storage device.

[0191] As can be consistent with the previously disclosed example embodiments, buried pattern structures 640 may be formed on various portions of the charge storage structure located between the insulating pattern 565 and the channel 660, and the corresponding portions of the charge trapping pattern 610 located between the insulating pattern 565 and the channel 660 may have a curved shape, thereby reducing lateral charge loss of the charge trapping pattern 610. Additionally, as can be consistent with the previously disclosed example embodiments, portions of the tunnel insulating pattern 650 and the channel 660 horizontally adjacent to the buried pattern structure 640 may have a curved shape; for example, the tunnel insulating pattern 650 and the channel 660 may be curved toward the buried pattern structure 640.

[0192] Furthermore, since the first to third gate electrodes 760, 770, and 780 and the insulating pattern 565, which are alternately and repeatedly stacked on the substrate 500, can be formed to have an overall uneven shape, the outer sidewalls of the charge storage structure that contact the first to third gate electrodes 760, 770, and 780 and the insulating pattern 565 can also be formed to have an overall uneven shape. Therefore, since the charge storage structure can be at least partially arranged between the first to third gate electrodes 760, 770, and 780, interference between the first to third gate electrodes 760, 770, and 780 can be minimized, the coupling rate between the second electrodes 770 used as word lines can be reduced, thereby improving the electrical characteristics of the vertical memory device.

[0193] As described above, although the invention has been described with reference to exemplary embodiments, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A vertical storage device, comprising: A plurality of gate electrodes, the plurality of gate electrodes being spaced apart from each other and stacked sequentially in a vertical direction substantially perpendicular to the upper surface of the substrate, the plurality of gate electrodes including a first gate electrode and a second gate electrode; Multiple insulating patterns are respectively located between the gate electrodes, and the multiple insulating patterns include a first insulating pattern located at a height between the first gate electrode and the second gate electrode; A channel extending in the vertical direction on the substrate, the channel penetrating at least the first gate electrode, the second gate electrode, and the first insulating pattern; A charge storage structure extending along the vertical direction and covering the outer wall of the channel, the charge storage structure comprising tunnel insulating patterns, charge trapping patterns and blocking patterns sequentially stacked from the outer wall of the channel along a horizontal direction substantially parallel to the upper surface of the substrate. as well as Multiple buried pattern structures, including a first buried pattern structure, each buried pattern structure being surrounded by a tunnel insulation pattern and a charge trapping pattern between the trench and a corresponding insulation pattern, each buried pattern structure including an inner sidewall in contact with the tunnel insulation pattern and an outer sidewall furthest from the tunnel insulation pattern in the horizontal direction and in contact with the charge trapping pattern. Wherein, the maximum thickness of the first portion of the charge trapping pattern is less than or equal to the maximum thickness of the second portion of the charge trapping pattern, the first portion has a sidewall perpendicular to the upper surface of the substrate and is located in the horizontal direction between the channel and the first gate electrode, and the second portion has a sidewall perpendicular to the upper surface of the substrate and is located in the horizontal direction between the first buried pattern structure and the first insulating pattern.

2. The vertical storage device according to claim 1, wherein, The thickness of the charge trapping pattern is constant.

3. The vertical storage device according to claim 1, wherein, The inner wall of the first buried pattern structure is concave along the horizontal direction toward the trench.

4. The vertical storage device according to claim 1, wherein, The inner wall of the first buried pattern structure extends along the vertical direction.

5. The vertical storage device according to claim 1, wherein, The inner wall of the first buried pattern structure is convex towards the trench in the horizontal direction.

6. The vertical storage device according to claim 1, wherein, The first buried pattern structure includes a first buried pattern and a second buried pattern that are sequentially stacked from the sidewalls of the charge trapping pattern along the horizontal direction.

7. The vertical storage device according to claim 6, wherein, The first buried pattern includes silicon oxide, and the second buried pattern includes either silicon oxide or silicon oxynitride.

8. The vertical storage device according to claim 1, wherein, The first and second portions of the charge trapping pattern both have a constant thickness in the horizontal direction.

9. The vertical storage device according to claim 8, further comprising: A channel connection pattern is located between the substrate and the second gate electrode, and the channel connection pattern comprises polycrystalline silicon doped with impurities.

10. A vertical storage device, comprising: Support patterns and channel connection patterns located on the substrate; A plurality of gate electrodes are located on the support pattern and the channel connection pattern, the gate electrodes being spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate; Multiple insulating patterns are located between the gate electrodes, the multiple insulating patterns including a first insulating pattern located at a height between two adjacent gate electrodes; A plurality of channels are located on the substrate, each of the channels extending along the vertical direction and penetrating the gate electrode and the insulating pattern; A charge storage structure extending along the vertical direction and covering the outer wall of the channel, the charge storage structure comprising tunnel insulating patterns, charge trapping patterns and blocking patterns sequentially stacked from the outer wall of the channel along a horizontal direction substantially parallel to the upper surface of the substrate. as well as Multiple buried pattern structures, each buried pattern structure being surrounded by the tunnel insulation pattern and the charge trapping pattern between the trench and a corresponding insulation pattern, each buried pattern structure including an inner wall closest to the tunnel insulation pattern in the horizontal direction, an outer wall farthest from the tunnel insulation pattern in the horizontal direction, as well as a lower surface and an upper surface. The inner sidewall is in contact with the tunnel insulation pattern, and the outer sidewall, the lower surface, and the upper surface are in contact with the charge trapping pattern. The plurality of channels are electrically connected to each other through the channel connection pattern, and The first vertical portion of the charge trapping pattern located in the horizontal direction between the channel and the plurality of gate electrodes, and the second vertical portion located in the horizontal direction between the first insulating pattern and the plurality of buried pattern structures, have the same and constant thickness.

11. The vertical storage device according to claim 10, wherein, The tunnel insulation pattern, the blocking pattern, and each burial pattern structure include oxides, and the charge trapping pattern includes nitrides.

12. A method for manufacturing a vertical storage device, comprising: Multiple insulating layers and multiple sacrificial layers are alternately and repeatedly formed on the top of the substrate; A channel hole is formed that penetrates the plurality of insulating layers and the plurality of sacrificial layers, thereby exposing the upper surface of the substrate; The portion of each of the insulating layers exposed through the channel hole is partially removed to form a first recess that extends continuously from the channel hole; A barrier layer, a charge trapping layer, a first burial layer, and a second burial layer are formed on the sidewall of the channel hole and the inner wall of the first recess. A first oxidation process is performed on the surface of the second buried layer, and then the oxidized portion of the second buried layer is removed by a first etching process; A second oxidation process is performed on the remaining portion of the second buried layer, and then a second etching process is used to remove the portion of the second buried layer oxidized by the second oxidation process and a portion of the first buried layer to form a buried pattern; as well as A tunnel insulation layer and a trench layer are formed by sequentially stacking the burial pattern and the charge trapping layer.

13. The method according to claim 12, wherein, Through the first oxidation process, the surface of the first portion of the second buried layer adjacent to each of the sacrificial layers and the surface of the second buried layer adjacent to each of the insulating layers are oxidized.

14. The method of claim 13, wherein after the first etching process, the remaining portion of the second buried layer comprises a third portion adjacent to each of the sacrificial layers and a fourth portion adjacent to each of the insulating layers.

15. The method according to claim 14, wherein, The remaining portion of the second buried layer is completely oxidized by the second oxidation process, and the oxidized portion of the second buried layer oxidized by the second oxidation process is partially removed by the second etching process.

16. The method according to claim 15, wherein, The buried pattern is formed to be adjacent to each of the insulating layers in a horizontal direction that is substantially parallel to the upper surface of the substrate, and is not formed to be adjacent to each of the sacrificial layers in the horizontal direction.

17. The method according to claim 12, wherein, The vertical portion of the second buried layer, which extends substantially perpendicular to the upper surface of the substrate, is conformally formed to have a constant thickness in a horizontal direction that is substantially parallel to the upper surface of the substrate.

18. The method according to claim 12, wherein, The surface of the second buried layer is perpendicular to the upper surface of the substrate.

19. The method according to claim 12, wherein, The second buried layer is formed such that each portion of its surface adjacent to each of the insulating layers has a convex shape in a horizontal direction toward the trench layer, the horizontal direction being substantially parallel to the upper surface of the substrate.

20. The method according to claim 12, wherein, The first buried layer comprises oxides, and the second buried layer comprises nitrides.

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