Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure; a source / drain layer on a portion of the active pattern adjacent to the gate structure, the source / drain layer contacting the channels; and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source / drain layer and comprising silicon germanium.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2019-0056199, entitled "Semiconductor Devices", filed on May 14, 2019 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to semiconductor devices. More specifically, the example embodiments relate to semiconductor devices having vertically stacked channels. Background Technology

[0004] When forming a multi-bridge channel MOSFET (MBCFET) comprising multiple vertically stacked channels in both the PMOS and NMOS regions, the process must be tailored to ensure that the MBCFET exhibits suitable characteristics in both regions. For example, the charge moving in the channel in the PMOS region must have improved mobility, while the channel in the NMOS region must have a long length. Therefore, a process for forming MBCFETs with these characteristics needs to be developed. Summary of the Invention

[0005] According to an example embodiment, a semiconductor device is provided, the semiconductor device comprising: an active pattern located on a substrate and extending in a first direction parallel to an upper surface of the substrate; a gate structure located on the active pattern and extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each channel extending through the gate structure; a source / drain layer located on a portion of the active pattern adjacent to the gate structure, the source / drain layer contacting the channel; and a sacrificial pattern located on the upper surface of each of the opposing edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting the lower portion of the sidewall of the source / drain layer and comprising silicon germanium.

[0006] According to an example embodiment, there is provided a semiconductor device including: first channels on a first region of a substrate including the first region and a second region, the first channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; second channels on the second region of the substrate, the second channels being spaced apart from each other in the vertical direction; a first gate structure on the first region of the substrate, the first gate structure covering at least a portion of a surface of each of the first channels; a second gate structure on the second region of the substrate, the second gate structure covering at least a portion of a surface of each of the second channels; a first source / drain layer on the first region of the substrate, the first source / drain layer contacting the first channels; a second source / drain layer on the second region of the substrate, the second source / drain layer contacting the second channels; and a sacrificial pattern contacting a lower portion of a sidewall of the second source / drain layer, the sacrificial pattern including silicon germanium, wherein a lower surface of the first source / drain layer is a convexly curved surface in the vertical direction, a central portion of a lower surface of the second source / drain layer is flat, and an edge of the lower surface of the second source / drain layer is rounded.

[0007] According to an example embodiment, there is provided a semiconductor device including: an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending in the first direction across the gate structure; a source / drain layer on a portion of the active pattern at each side of the gate structure in opposite walls in the first direction, the source / drain layer contacting the channels; and a sacrificial pattern and a fin spacer structure sequentially stacked in the second direction on a lower portion of each of opposite sidewalls of the source / drain layer in the second direction, the sacrificial pattern and the fin spacer structure including different materials from each other.

[0008] According to an example embodiment, a semiconductor device is provided. The semiconductor device can include a first transistor and a second transistor. The first transistor can include a first active pattern, a first gate structure, first channels, and a first source / drain layer. The first active pattern can be formed on a first region of a substrate including the first region and a second region, and can extend in a first direction parallel to an upper surface of the substrate. The first gate structure can extend in a second direction parallel to the upper surface of the substrate and intersecting the first direction. The first channels can be spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, and each of the first channels can extend partially through the first gate structure. The first source / drain layer can be formed on portions of the first active pattern at each of sides of the first active pattern located opposite sides of the first gate structure in the first direction, and can contact the first channels. The second transistor can include a second active pattern, a second gate structure, second channels, and a second source / drain layer. The second active pattern can be formed on the second region of the substrate, and can extend in the first direction. The second gate structure can be formed on the second active pattern, and can extend in the second direction. The second channels can be spaced apart from each other in the third direction, and each of the second channels can extend partially through the second gate structure. The second source / drain layer can be formed on portions of the second active pattern at each of sides of the second active pattern located opposite sides of the second gate structure in the first direction, and can contact the second channels. An upper surface of the portions of the first active pattern can have a concave curved shape. The portions of the second active pattern can include protrusions protruding upward along the third direction at respective opposite edges of the second active pattern in the second direction. Sacrificial patterns can be formed on each of the protrusions to contact sidewalls of the second source / drain layer.

[0009] According to an example embodiment, a semiconductor device is provided. The semiconductor device can include a first gate structure, first channels, first source / drain layers, a first fin spacer, a second fin spacer, a second gate structure, second channels, second source / drain layers, and a fin spacer structure. The first gate structure can be formed on a first region of a substrate including the first region and a second region. The first channels can be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and each of the first channels can extend through the first gate structure. The first source / drain layers can be formed at each of opposite sides of the first gate structure and contact the first channels. The first fin spacer can contact a portion of a sidewall of the first source / drain layers. The second fin spacer can contact the first fin spacer and a portion of the sidewall and an upper surface of the first source / drain layers. The second gate structure can be formed on the second region of the substrate. The second channels can be spaced apart from each other in the vertical direction, and each of the second channels can extend through the second gate structure. The second source / drain layers can be formed at each of opposite sides of the second gate structure and can contact the second channels. The fin spacer structure can contact a portion of a sidewall of the second source / drain layers. A bottom surface of the first fin spacer can be substantially coplanar with a bottom surface of the fin spacer structure, and an uppermost surface of the first fin spacer can be lower than an uppermost surface of the fin spacer structure.

[0010] According to an example embodiment, a semiconductor device is provided. The semiconductor device can include first channels, second channels, a first gate structure, a second gate structure, a first source / drain layer, and a second source / drain layer. The first channels can be formed on a first region of a substrate including the first region and a second region. The first channels can be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and each of the first channels can extend in a first direction parallel to the upper surface of the substrate. The second channels can be spaced apart from each other in the vertical direction on the second region of the substrate, and each of the second channels can extend in the first direction. The first gate structure can extend in a second direction on the first region of the substrate to cover at least a portion of a surface of each of the first channels. The second direction can be parallel to the upper surface of the substrate and intersect the first direction. The second gate structure can extend in the second direction on the second region of the substrate to cover at least a portion of a surface of each of the second channels. The first source / drain layer can be formed at each of opposite sides of the first gate structure in the first direction and can contact the first channels. The second source / drain layer can be formed at each of opposite sides of the second gate structure in the first direction and can contact the second channels. A third channel, which is an uppermost one of the first channels, can have a length in the first direction that gradually decreases from a top portion toward a bottom portion thereof. Each of fourth channels, which are below the third channel among the first channels, and the second channels can have a length in the first direction that is substantially constant from a top portion toward a bottom portion thereof. BRIEF DESCRIPTION OF DRAWINGS

[0011] The exemplary embodiments will become more fully understood from the detailed description and accompanying drawings, wherein:

[0012] FIG. 1 A plan view of a semiconductor device according to an example embodiment is illustrated;

[0013] FIG. 2 A cross-sectional view taken along line A-A' of FIG. 1 is illustrated;

[0014] FIGS. 3A-3C Cross-sectional views taken along line B-B' and line C-C' of FIG. 1 according to an example embodiment are illustrated;

[0015] FIG. 4 A cross-sectional view taken along line D-D' of FIG. 1 is illustrated;

[0016] FIGS. 5-29top views and cross-sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment are shown;

[0017] FIGS. 30-32 top views and cross-sectional views of a semiconductor device according to an example embodiment are shown; and

[0018] FIGS. 33-35 top views and cross-sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment are shown. DETAILED DESCRIPTION

[0019] FIG. 1 、 FIG. 2 、 FIGS. 3A-3C and FIG. 4 top views and cross-sectional views of a semiconductor device according to an example embodiment are shown. FIG. 1 is a top view, FIG. 2 is a cross-sectional view taken along line A-A’ of FIG. 1 , FIG. 3A includes cross-sections taken along lines B-B’ and C-C’ of FIG. 1 , FIG. 4 is a cross-sectional view taken along line D-D’ of FIG. 1 . FIG. 3B and FIG. 3C are improved embodiments corresponding to the views of FIG. 3A .

[0020] Hereinafter, two directions substantially parallel to the upper surface of the substrate 100 and intersecting each other can be referred to as a first direction and a second direction, respectively, and a direction substantially perpendicular to the upper surface of the substrate 100 can be referred to as a third direction. In example embodiments, the first direction and the second direction can be substantially perpendicular to each other.

[0021] Referring to FIG. 1 , FIG. 2 , FIG. 3A and FIG. 4 , a semiconductor device according to an embodiment can include a first transistor and a second transistor located on a first region I and a second region II of a substrate 100, respectively.

[0022] The substrate 100 can include a semiconductor material (e.g., silicon, germanium, silicon germanium, etc.), or a III-V semiconductor compound (e.g., GaP, GaAs, GaSb, etc.). In some embodiments, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0023] The first region I and the second region II of the substrate 100 can be adjacent to each other or spaced apart from each other. For example, as FIG. 1As shown, the first region I and the second region II of the substrate 100 can be adjacent to each other along the second direction. In an example embodiment, the first region I of the substrate 100 can be a positive channel metal-oxide semiconductor (PMOS) region in which a PMOS transistor can be formed, and the second region II of the substrate 100 can be a negative channel metal-oxide semiconductor (NMOS) region in which an NMOS transistor can be formed.

[0024] The first transistor can be formed on the first active pattern 102 located on the first region I of the substrate 100, and can include a first gate structure 412, a first semiconductor pattern 126, a first source / drain layer 282, a first gate spacer structure 502, and a first fin spacer structure 503.

[0025] The first active pattern 102 can protrude upward from the first region I of the substrate 100 in the third direction, and can also be referred to as a first active fin. In an example embodiment, the first active pattern 102 can extend in the first direction. In the drawing, only one first active pattern 102 is shown, however, embodiments are not limited thereto. Thus, a plurality of first active patterns 102 can be spaced apart from each other in the second direction on the first region I of the substrate 100. The first active pattern 102 can be formed by partially removing an upper portion of the substrate 100, and thus the first active pattern 102 can include a material substantially the same as a material of the substrate 100, for example, a semiconductor material such as silicon.

[0026] The sidewalls of the first active pattern 102 and the upper surface of the first region I of the substrate 100 can be covered with a first liner 142, and a first isolation pattern 152 can be formed on the first liner 142 to surround the sidewalls of the first active pattern 102. FIG. 2 However, an upper portion of each of the opposite sidewalls of the first active pattern 102 in the second direction can not be covered with the first liner 142 and the first isolation pattern 152. The first liner 142 can include nitride, for example, silicon nitride, and the first isolation pattern 152 can include oxide, for example, tonen silazene (TOSZ).

[0027] In an example embodiment, the first active pattern 102 can have a concavely curved upper surface.

[0028] Each of the first semiconductor patterns 126 can extend across the first gate structure 412 in the first direction, and a plurality of first semiconductor patterns 126 can be formed at a plurality of horizontal levels, respectively, to be spaced apart from each other in the third direction from the upper surface of the first active pattern 102. In the drawing, the first semiconductor patterns 126 located at three horizontal levels, respectively, are shown. However, embodiments are not limited thereto.

[0029] The first semiconductor pattern 126 may comprise a material substantially the same as the material of the substrate 100 or the first active pattern 102, such as silicon. In an example embodiment, each first semiconductor pattern 126 may serve as a channel for a first transistor and may therefore be referred to as a first channel.

[0030] In an example embodiment, each sidewall of the uppermost first semiconductor pattern 126 in the first direction may not be substantially perpendicular to the upper surface of the substrate 100, but may be inclined relative to the upper surface of the substrate 100. For example, as FIG. 3A As shown, the uppermost first semiconductor pattern 126 in the stacked first semiconductor patterns 126 may have inclined relative lateral sidewalls to have an inverted trapezoidal cross-section. Therefore, the first length L1 of the uppermost first semiconductor pattern 126 in the first direction can gradually decrease from its top to its bottom. Each lateral sidewall of the other first semiconductor patterns 126 in the first direction may be substantially perpendicular to the upper surface of the substrate 100, so their second length L2 in the first direction may be substantially constant along the third direction. In the example embodiment, the minimum value of the first length L1 may be substantially equal to the second length L2, and the maximum value of the first length L1 may be greater than the second length L2.

[0031] The first gate structure 412 may be formed on the first active pattern 102 and on the portion of the first isolation pattern 152 adjacent to the first active pattern 102 in the second direction, and may surround each first semiconductor pattern 126.

[0032] In the figure, the first gate structure 412 is shown as covering the first semiconductor pattern 126 located on a first active pattern 102; however, the embodiment is not limited thereto. That is, the first gate structure 412 may extend along a second direction on a first region I of the substrate 100 where a first isolation pattern 152 is formed, and may collectively cover the first semiconductor patterns 126 located on a plurality of first active patterns 102 spaced apart from each other in the second direction.

[0033] In the figure, a first gate structure 412 is shown on a first region I of the substrate 100; however, the embodiment is not limited thereto. Therefore, a plurality of first gate structures 412 spaced apart from each other in a first direction can be formed on the first region I of the substrate 100.

[0034] The first gate structure 412 may include a first interface pattern 372, a first gate insulating pattern 382, ​​a first work function control pattern 392, and a first gate electrode 402, which are sequentially stacked from the surface of each first semiconductor pattern 126 or the upper surface of the first active pattern 102.

[0035] The first interface pattern 372 can be formed on the upper surface of the first active pattern 102 and the surface of the first semiconductor pattern 126, and the first gate insulating pattern 382 can be formed on the surface of the first interface pattern 372 and the inner side wall of the first gate spacer structure 502. The first work function control pattern 392 can be formed on the first gate insulating pattern 382, and the first gate electrode 402 can fill the space between the first semiconductor patterns 126 spaced apart from each other in the third direction and the space defined by the inside of the first gate spacer structure 502 on the uppermost first semiconductor pattern 126.

[0036] The first interface pattern 372 can include an oxide, for example, silicon oxide, and the first gate insulating pattern 382 can include a metal oxide having a high k dielectric constant, for example, hafnium oxide, tantalum oxide, zirconium oxide, etc.

[0037] The first work function control pattern 392 can include, for example, titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, tungsten nitricarbide, aluminum oxide, etc. The first gate electrode 402 can include a metal (for example, titanium, aluminum, etc.), a metal alloy, or a nitride or carbide of a metal.

[0038] The first gate structure 412 can include an upper portion and a lower portion. The upper portion of the first gate structure 412 can be formed on the uppermost first semiconductor pattern 126 and can overlap the first semiconductor pattern 126 in the third direction. The lower portion of the first gate structure 412 can be formed between the adjacent first semiconductor patterns 126 and between the first active pattern 102 and the lowermost first semiconductor pattern 126 and can overlap the first semiconductor pattern 126 in the third direction. In addition, the first gate structure 412 can include a portion located on the first isolation pattern 152, that is, the first gate structure 412 can include a lateral portion that does not overlap the first semiconductor pattern 126 in the third direction. The side wall of the upper portion of the first gate structure 412 can be covered by the first gate spacer structure 502.

[0039] The first gate spacer structure 502 can include the first gate spacer 252 covering the side wall of the upper portion of the first gate structure 412 and the second gate spacer 292 located on the outer side wall of the first gate spacer 252. In an example embodiment, the bottom surface of the first gate spacer 252 can be lower than the bottom of the second gate spacer 292. The first gate spacer 252 and the second gate spacer 292 can each include a nitride, for example, silicon oxynitride, silicon oxycarbonitride, etc., and can be merged with each other if they contain the same material.

[0040] The first fin-shaped spacer structure 503 can include a first fin-shaped spacer 253 and a second fin-shaped spacer 293. The first fin-shaped spacer 253 can cover an upper portion of each of the opposing sidewalls (in the second direction) of the portion of the first active pattern 102 not overlapped with the first gate structure 412 and the first gate spacer structure 502 in the third direction. The second fin-shaped spacer 293 can cover the outer sidewall of the first fin-shaped spacer 253.

[0041] The first fin-shaped spacer 253 can cover the upper portion of the sidewall of the first active pattern 102 not covered by the first pad 142 and the first isolation pattern 152, and can contact the lower portion of the sidewall of the first source / drain layer 282.

[0042] The second fin-shaped spacer 293 can not only cover the outer sidewall of the first fin-shaped spacer 253, but also can cover the surface of the upper portion of the first source / drain layer 282, and in addition, can extend in the second direction to cover the portion of the first isolation pattern 152 and the first liner 142 not overlapped with the first gate structure 412 and the first gate spacer structure 502 in the third direction. The second fin-shaped spacer 293 and the second gate spacer 292 can be integrally formed, and for ease of explanation, only the portion of the second gate spacer 292 located on the outer sidewall of the first gate spacer 252 will be referred to as the second gate spacer 292 different from the second fin-shaped spacer 293.

[0043] The first fin-shaped spacer 253 and the second fin-shaped spacer 293 can each include a nitride, for example, silicon oxynitride, silicon carbon oxynitride, etc., and if they include the same material, can be merged with each other. In an example embodiment, the first fin-shaped spacer 253 and the first gate spacer 252 can include substantially the same material, and the second fin-shaped spacer 293 and the second gate spacer 292 can include substantially the same material.

[0044] The first source / drain layer 282 can extend from the upper surface of the first active pattern 102 in the third direction, and can collectively contact each of the opposing sides of the first semiconductor pattern 126 to be connected thereto. The first source / drain layer 282 can contact the lower portion of the outer sidewall of the first gate spacer 252.

[0045] In an example embodiment, the first source / drain layer 282 can include a lower portion 282a and an upper portion 282b located below and above the height of the uppermost surface of the first fin-shaped spacer 253, respectively. The lower portion 282a of the first source / drain layer 282 can have a cross-section in the second direction with a downward convex curved shape (e.g., a shape of a portion of an ellipse or a circle), and the upper portion 282b of the first source / drain layer 282 can have a cross-section in the second direction with a portion of a polygon (e.g., a pentagon or a rectangle). Accordingly, the first source / drain layer 282 can have a lower surface that is not flat but convex downward.

[0046] In an example embodiment, the first source / drain layer 282 can include silicon germanium doped with a p-type impurity, and thus can function as a source / drain of a PMOS transistor.

[0047] As described above, the length of the lower first semiconductor pattern 126 in the first direction can be less than the length of the uppermost first semiconductor pattern 126 in the first direction. Accordingly, the width of the lower portion of the first source / drain layer 282 in the first direction, which contacts all of the first semiconductor patterns 126, can be greater than the width of the upper portion thereof in the first direction.

[0048] The first transistor can include a plurality of first semiconductor patterns 126 stacked in the third direction in the first gate structure 412. Accordingly, the first transistor can be an MBCFET.

[0049] The second transistor can be formed on the second active pattern 104 located on the second region II of the substrate 100, and can include a second gate structure 414, a second semiconductor pattern 128, a second source / drain layer 344, a second gate spacer structure 504, a second fin-shaped spacer structure 505, an inner spacer 330, and a third sacrificial pattern 119.

[0050] The second active pattern 104 can protrude upward from the second region II of the substrate 100 in the third direction, and can also be referred to as a second active fin. In an example embodiment, the second active pattern 104 can extend in the first direction. In the drawings, only one second active pattern 104 is illustrated, however, embodiments are not limited thereto. Accordingly, a plurality of second active patterns 104 can be spaced apart from each other in the second direction on the second region II of the substrate 100. The second active pattern 104 can be formed by partially removing an upper portion of the substrate 100, and thus the second active pattern 104 can include a material substantially the same as that of the substrate 100, for example, a semiconductor material such as silicon. Accordingly, the second active pattern 104 can include the same material as the first active pattern 102.

[0051] The sidewalls of the second active pattern 104 and the upper surface of the second region II of the substrate 100 can be covered with a second pad 144, and a second isolation pattern 154 can be formed on the second pad 144 to enclose the sidewalls of the second active pattern 104. However, the upper portion of each of the opposite sidewalls of the second active pattern 104 in the second direction can not be covered with the second pad 144 and the second isolation pattern 154. The second pad 144 and the second isolation pattern 154 can include substantially the same materials as those of the first pad 142 and the first isolation pattern 152, respectively.

[0052] In an example embodiment, the portions of the second active pattern 104 that do not overlap with the second gate structure 414 and the second gate spacer structure 504 in the third direction can include first protrusions 106 protruding upward from opposite edges thereof in the second direction, respectively, and the upper surface of the portions of the second active pattern 104 located between the first protrusions 106 can be flat FIG. 4 ). For example, as shown in FIG. 1B, the upper surface of the portions of the second active pattern 104 located between the first protrusions 106 can be parallel to the bottom of the substrate 100. FIG. 4

[0053] The inner sidewalls of the first protrusions 106 of the second active pattern 104 can contact the second source / drain layer 344, and the outer sidewalls of the first protrusions 106 of the second active pattern 104 can contact the second fin spacer structure 505. That is, the bottom surface of the first protrusions 106 can be substantially coplanar with the bottom surface of the second source / drain layer 344, and the bottom surface of the second source / drain layer 344 located between the first protrusions 106 adjacent in the second direction can be flat. For example, referring to FIG. 1B, although the first protrusions 106 can be integral with the second active pattern 104 and seamlessly extend from the second active pattern 104, the bottom of the protrusion 106 can be referred to with respect to the imaginary dotted line in FIG. 1A for convenience of description. FIG. 4 FIG. 4

[0054] Each of the second semiconductor patterns 128 can extend across the second gate structure 414 in the first direction, and a plurality of the second semiconductor patterns 128 can be formed at a plurality of horizontal levels, respectively, to be spaced apart from each other in the third direction from the upper surface of the second active pattern 104. In the drawing, the second semiconductor patterns 128 located at three horizontal levels, respectively, are shown. However, embodiments are not limited thereto.

[0055] The second semiconductor patterns 128 can include substantially the same material as that of the first semiconductor patterns 126, and can be formed at the height of the corresponding first semiconductor patterns 126. In an example embodiment, each of the second semiconductor patterns 128 can function as a channel of a second transistor, and thus can be referred to as a second channel. ​​​

[0056] In the example embodiment, each of the opposing sidewalls of the second semiconductor pattern 128 can be substantially perpendicular to the upper surface of the substrate 100. Accordingly, the third length L3 of the second semiconductor pattern 128 in the first direction can be substantially constant along the third direction. In the example embodiment, the third length L3 can be greater than the second length L2, and can also be greater than the maximum value of the first length L1.

[0057] The second gate structure 414 can be formed on the second active pattern 104 and on a portion of the second isolation pattern 154 adjacent to the second active pattern 104 in the second direction, and can enclose each of the second semiconductor patterns 128.

[0058] In the drawing, the second gate structure 414 is illustrated as covering the second semiconductor pattern 128 located on one second active pattern 104. However, the embodiment is not limited thereto. That is, the second gate structure 414 can extend in the second direction on the second region II of the substrate 100 on which the second isolation pattern 154 is formed, and can collectively cover the second semiconductor patterns 128 located on a plurality of second active patterns 104 spaced apart from each other in the second direction.

[0059] In the drawing, one second gate structure 414 is illustrated on the second region II of the substrate 100. However, the embodiment is not limited thereto. Accordingly, a plurality of second gate structures 414 spaced apart from each other in the first direction can be formed on the second region II of the substrate 100.

[0060] The second gate structure 414 can include a second interface pattern 374, a second gate insulating pattern 384, a second work function control pattern 394, and a second gate electrode 404 sequentially stacked from the surface of each of the second semiconductor patterns 128 or the upper surface of the second active pattern 104.

[0061] The second interface pattern 374 can be formed on the upper surface of the second active pattern 104 and the surface of the second semiconductor pattern 128, and the second gate insulating pattern 384 can be formed on the surface of the second interface pattern 374, the inner sidewall of the second gate spacer structure 504, and the inner sidewall of the inner spacer 330. The second work function control pattern 394 can be formed on the second gate insulating pattern 384, and the second gate electrode 404 can fill the spaces between the second semiconductor patterns 128 spaced apart from each other in the third direction and between the inner spacers 330, and the space defined by the inner portion of the second gate spacer structure 504 on the uppermost second semiconductor pattern 128.

[0062] The second interface pattern 374, the second gate insulating pattern 384, the second work function control pattern 394, and the second gate electrode 404 can include substantially the same materials as those of the first interface pattern 372, the first gate insulating pattern 382, the first work function control pattern 392, and the first gate electrode 402, respectively. Alternatively, the second interface pattern 374, the second gate insulating pattern 384, the second work function control pattern 394, and the second gate electrode 404 can include different materials from those of the first interface pattern 372, the first gate insulating pattern 382, the first work function control pattern 392, and the first gate electrode 402, respectively.

[0063] The second gate structure 414 can have a stack structure different from that of the first gate structure 412, and each element of the second gate structure 414 can have a number of layers different from that of the corresponding element of the first gate structure 412. For example, the number of stacked layers of the second work function control pattern 394 and / or the second gate electrode 404 in the second gate structure 414 can be different from that of the first work function control pattern 392 and / or the first gate electrode 402, respectively. Alternatively, the second work function control pattern 394 and / or the second gate electrode 404 in the second gate structure 414 can include different materials from those of the first work function control pattern 392 and the first gate electrode 402 in the first gate structure 412, respectively.

[0064] The second gate structure 414 can include an upper portion and a lower portion. The upper portion of the second gate structure 414 can be formed on the uppermost second semiconductor pattern 128 and can overlap the second semiconductor pattern 128 in the third direction. The lower portion of the second gate structure 414 can be formed between adjacent second semiconductor patterns 128 and between the second active pattern 104 and the lowermost second semiconductor pattern 128, and can overlap the second semiconductor pattern 128 in the third direction. In addition, the second gate structure 414 can include a portion located on the second isolation pattern 154, i.e., a lateral portion not overlapping the second semiconductor pattern 128 in the third direction. The sidewall of the upper portion of the second gate structure 414 can be covered by the second gate spacer structure 504, and the sidewall of the lower portion of the second gate structure 414 can be covered by the inner spacer 330.

[0065] The second gate spacer structure 504 can include a third gate spacer 254 covering a sidewall of an upper portion of the second gate structure 414 and a fourth gate spacer 294 on an outer sidewall of the third gate spacer 254. In an example embodiment, the third gate spacer 254 can have a cross-section of an "L" shape in the first direction. The third gate spacer 254 and the fourth gate spacer 294 can include substantially the same material as the material of the first gate spacer 252 and the second gate spacer 292, respectively, and can be merged if they include the same material.

[0066] The second fin spacer structure 505 can include a third fin spacer 255 and a fourth fin spacer 295. The third fin spacer 255 can cover an upper portion of each of opposite sidewalls of a portion of the second active pattern 104 not overlapping with the second gate structure 414 and the second gate spacer structure 504 in the third direction in the second direction, and the fourth fin spacer 295 can be formed on an outer sidewall of the third fin spacer 255.

[0067] The first fin spacer 255 can cover an upper portion of a sidewall of the second active pattern 104 not covered by the second pad 144 and the second isolation pattern 154, and can contact a lower portion of a sidewall of the second source / drain layer 344.

[0068] The third fin spacer 255 and the fourth fin spacer 295 can include substantially the same material as the material of the first fin spacer 253 and the second fin spacer 293, respectively, and can be merged if they include the same material.

[0069] In an example embodiment, a second height H2 of an uppermost surface of the second fin spacer structure 505 can be greater than a first height H1 of an uppermost surface of the first fin spacer 253. Alternatively, the second height H2 of the uppermost surface of the second fin spacer structure 505 can be substantially equal to the first height H1 of the uppermost surface of the first fin spacer 253. In an example embodiment, a thickness of the second fin spacer structure 505 can be greater than a thickness of the first fin spacer 253.

[0070] The inner spacer 330 can be formed between the second semiconductor patterns 128 adjacent in the third direction, and can cover each of opposite sidewalls of a lower portion of the second gate structure 414 in the first direction. For example, as shown in FIG. 4B, the inner spacer 330 can have a cross-section of a horseshoe shape or a semi-circular shape having a recess on an outer sidewall thereof. In another example, as shown in FIG. 4C, the inner spacer 330 can have a cross-section of a semi-circular shape having a recess on an outer sidewall thereof. FIG. 3A FIG. 3B ​As shown, the inner spacer 330' can have a rounded rectangular cross-section with a recess on its outer sidewall. The inner spacer 330 (or 330') can include a nitride, for example, silicon nitride.

[0071] The second source / drain layer 344 can extend from the upper surface of the second active pattern 104 in the third direction and can collectively contact each of the opposite sides of the second semiconductor pattern 128 to be connected therewith. The second source / drain layer 344 can contact a lower portion of the outer sidewall of the second gate spacer structure 504.

[0072] In an example embodiment, the second source / drain layer 344 can include a lower portion 344a and an upper portion 344b located below and above the height of the uppermost surface of the second fin-shaped spacer structure 505, respectively. The lower portion 344a of the second source / drain layer 344 can have a cross-section having a "U" shape in the second direction, and the upper portion 344b of the second source / drain layer 344 can have a cross-section having various shapes (for example, an ellipse) in the second direction. Accordingly, the second source / drain layer 344 can have a lower surface in which a central portion is flat and each of opposite edges is rounded. In an example embodiment, the second source / drain layer 344 can include silicon doped with n-type impurities or silicon carbide doped with n-type impurities, and thus can function as a source / drain of an NMOS transistor.

[0073] In an example embodiment, the third sacrificial pattern 119 can be formed on the first protrusion 106 of the second active pattern 104. The inner sidewall of the third sacrificial pattern 119 can be covered by the sidewall of the lower portion 344a of the second source / drain layer 344, and the outer sidewall of the third sacrificial pattern 119 can be covered by the second fin-shaped spacer structure 505. In an example embodiment, the bottom surface of the third sacrificial pattern 119 can be higher than the bottom surface of the second source / drain layer 344.

[0074] Due to the formation of the third sacrificial pattern 119, the third sacrificial pattern 119 and the second fin-shaped spacer structure 505 can be sequentially stacked in the second direction on each of the opposite sidewalls of the lower portion 344a of the second source / drain layer 344 in the second direction. The third sacrificial pattern 119 can extend in the first direction in an area not overlapping the second gate structure 414 and the second gate spacer structure 504 in the third direction. In some embodiments, the third sacrificial pattern 119 can partially overlap the second gate spacer structure 504 in the third direction.

[0075] The second transistor can include a plurality of second semiconductor patterns 128 located in the second gate structure 414 stacked in the third direction, and thus can be an MBCFET.

[0076] The semiconductor device can further include a contact plug, a wiring, or the like that can be electrically connected with the first source / drain layer 282 and the second source / drain layer 344 and / or the first gate structure 412 and the second gate structure 414.

[0077] In the semiconductor device, the first source / drain layer 282 of the PMOS transistor can include silicon germanium having a lattice larger than a lattice of the first semiconductor pattern 126 serving as a channel, and can have a relatively large width in the first direction. Thus, the first source / drain layer 282 can exert a stronger compressive stress on the first semiconductor pattern 126, and thereby can increase mobility of charges in the first semiconductor pattern 126.

[0078] Since the first source / drain layer 282 in the first transistor has a relatively large width in the first direction, the lowermost first sacrificial pattern 116 whose width in the first direction is larger than widths of other first sacrificial patterns 116 can not be reserved (see FIG. 6A). In contrast, the lowermost second sacrificial pattern 118 in the second transistor can be reserved as the third sacrificial pattern 119, which will be described later in the method of manufacturing the semiconductor device. FIG. 14A and FIG. 14B ), while the lowermost second sacrificial pattern 118 in the second transistor can be reserved as the third sacrificial pattern 119, which will be described later in the method of manufacturing the semiconductor device.

[0079] For example, as shown in FIG. 2A, the sidewall of the first source / drain layer 282 can have a straight-line shape. In another example, as shown in FIG. 2B, the sidewall of the first source / drain layer 282' can have a curved shape, and thus the volume of the first source / drain layer 282' can be enlarged. However, in this case, not only the uppermost first semiconductor pattern 126 but also other first semiconductor patterns 126 can have sidewalls that do not perpendicularly to the upper surface of the substrate 100 but can have a slope variation. Thus, as further shown in FIG. 2C, a second length L2' of the other first semiconductor patterns 126 in the first direction can not be constant in the third direction. FIG. 3A FIG. 3C FIG. 3C

[0080] FIGS. 5-29 are plan views and sectional views showing stages in the method of manufacturing the semiconductor device according to an example embodiment. FIG. 5 , FIG. 7 , FIG. 10 , FIG. 13 , FIG. 16 , FIG. 19 , FIG. 24 and FIG. 27 are plan views, FIG. 6 , FIG. 8 , FIG. 9 , FIG. 11 , FIG. 12 , FIG. 14A , FIG. 14B ,​​​FIG. 15 FIG. 17 FIG. 18 FIG. 20 FIG. 21 FIG. 22A FIG. 22B FIG. 23A FIG. 23B FIG. 25 FIG. 26 FIG. 28 FIG. 29 are cross-sectional views. FIG. 6 FIGS. 8-9 FIG. 11 FIG. 28 FIG. 12 FIG. 14A FIG. 14B FIG. 17 FIG. 20 FIG. 22A FIG. 22B FIG. 23A FIG. 23B FIG. 25 FIG. 29 FIG. 15 FIG. 18 FIG. 21 FIG. 26 are cross-sectional views taken along line D-D' of the corresponding plan view.

[0081] Referring to FIG. 5 FIG. 6 The sacrificial layers 110 and the semiconductor layers 120 can be alternately stacked on the substrate 100 including a first region I and a second region II. The mask layer 130 can be formed on the uppermost semiconductor layer 120.

[0082] In an example embodiment, the sacrificial layers 110 and the semiconductor layers 120 can be formed by a selective epitaxial growth (SEG) process using an upper portion of the substrate 100 as a seed. In an example embodiment, the sacrificial layers 110 can be formed by an SEG process using a silicon source gas (e.g., dichlorosilane (SiH2Cl2) gas) and a germanium source gas (e.g., germane (GeH4) gas). Accordingly, a single-crystal silicon germanium layer can be formed. In an example embodiment, the semiconductor layers 120 can be formed by an SEG process using a silicon source gas (e.g., disilane (Si2H6) gas), and thus a single-crystal silicon layer can be formed.

[0083] The mask layer 130 can include nitride, e.g., silicon nitride. For example, a pad layer can also be formed between the uppermost semiconductor layer 120 and the mask layer 130.

[0084] Referring to​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​FIG. 7 and FIG. 8 The mask layer 130 can be patterned to form a first mask 132 and a second mask 134 on the first region I and the second region II of the substrate 100, respectively. For example, as shown in FIG. 1B, the first mask 132 and the second mask 134 can have a rectangular shape extending along the first direction to expose a portion of the uppermost semiconductor layer 120. FIG. 7

[0085] As shown in FIG. 1C, the first mask 132 and the second mask 134 can be used as etching masks to etch the semiconductor layer 120, the sacrificial layer 110, and the upper portion of the substrate 100 to form a first trench 103 and a second trench 105 on the first region I and the second region II of the substrate 100, respectively. The first trench 103 and the second trench 105 can expose a portion of the etched substrate 100 defining the first active pattern 102 and the second active pattern 104, respectively. FIG. 8 In detail, the first active pattern 102 can be formed on the first region I of the substrate 100 to extend in the first direction (e.g., along the first mask 132), and a first fin structure including first sacrificial lines 112 and first semiconductor lines 122 alternately and repeatedly stacked with each other can be formed on the first active pattern 102. The first mask 132 can be located on the first fin structure. Hereinafter, the sequentially stacked first active pattern 102, first fin structure, and first mask 132 can be referred to as a first structure.

[0086] FIG. 8 Similarly, the second active pattern 104 can be formed on the second region II of the substrate 100 to extend in the first direction (e.g., along the second mask 134), and a second fin structure including second sacrificial lines 114 and second semiconductor lines 124 alternately and repeatedly stacked with each other can be formed on the second active pattern 104. The second mask 134 can be located on the second fin structure. Hereinafter, the sequentially stacked second active pattern 104, second fin structure, and second mask 134 can be referred to as a second structure.

[0087] In an example embodiment, due to the characteristics of the etching process, the lowermost first sacrificial line 112 among the first sacrificial lines 112 and the lowermost second sacrificial line 114 among the second sacrificial lines 114 can have a sidewall that is not perpendicular but inclined with respect to the upper surface of the substrate 100, unlike the upper portion of the first sacrificial line 112 among the first sacrificial lines 112 and the upper portion of the second sacrificial line 114 among the second sacrificial lines 114. For example, referring to FIG. 1D, the lowermost first sacrificial line 112 among the first sacrificial lines 112 and the lowermost second sacrificial line 114 among the second sacrificial lines 114 can have a sidewall that is not perpendicular but inclined with respect to the upper surface of the substrate 100.

[0088] In an example embodiment, due to the characteristics of the etching process, the lowermost first sacrificial line 112 among the first sacrificial lines 112 and the lowermost second sacrificial line 114 among the second sacrificial lines 114 can have a sidewall that is not perpendicular but inclined with respect to the upper surface of the substrate 100, unlike the upper portion of the first sacrificial line 112 among the first sacrificial lines 112 and the upper portion of the second sacrificial line 114 among the second sacrificial lines 114. For example, referring to FIG. 1D, the lowermost first sacrificial line 112 among the first sacrificial lines 112 and the lowermost second sacrificial line 114 among the second sacrificial lines 114 can have a sidewall that is not perpendicular but inclined with respect to the upper surface of the substrate 100. FIG. 8 ​​Each of the lowermost first sacrificial lines 112 and the lowermost second sacrificial lines 114 can have a width gradually increasing from a top thereof toward a bottom in the second direction, and thus a length of a bottom surface of each of the lowermost first sacrificial lines 112 and the lowermost second sacrificial lines 114 in the second direction can be greater than a length of each of the upper first sacrificial lines 112 and the upper second sacrificial lines 114 in the second direction.

[0089] Referring to FIG. 9 A liner layer can be formed on surfaces of the first and second structures and the upper surface of the substrate 100, and an isolation layer can be formed on the liner layer to fill the first and second trenches 103 and 105 to a height sufficient to be higher than top surfaces of the first and second structures. The liner layer can cover the first sacrificial lines 112 and / or the first semiconductor lines 122 in the first structure and the second sacrificial lines 114 and / or the second semiconductor lines 124 in the second structure so as not to be oxidized. The isolation layer can be planarized until a portion of the liner layer located on the top surfaces of the first and second structures can be exposed. In an example embodiment, the planarization process can include a chemical mechanical polishing (CMP) process.

[0090] An upper portion of the liner layer and the isolation layer can be removed, and the first mask 132 and the second mask 134 can also be removed. Thus, sidewalls of the first and second fin structures can be exposed, and upper sidewalls of the first and second active patterns 102 and 104 can also be exposed.

[0091] As a result, the first and second active patterns 102 and 104, the first and second fin structures, the first and second liners 142 and 144 covering sidewalls of the first and second active patterns 102 and 104, respectively, and an upper surface of the substrate 100, the first isolation pattern 152 filling the first trenches 103 on the first liner 142, and the second isolation pattern 154 filling the second trenches 105 on the second liner 144 can be formed on the first and second regions I and II of the substrate 100, respectively.

[0092] Referring to FIGS. 10-12 A first dummy gate structure 242 can be formed on the first isolation pattern 152 and the first liner 142, and a second dummy gate structure 244 can be formed on the second isolation pattern 154 and the second liner 144 to partially cover the first and second fin structures, respectively.

[0093] Specifically, a dummy gate insulating layer, a dummy gate electrode layer, and a dummy gate mask layer can be sequentially formed on the substrate 100 having the first fin structure and the second fin structure, the first isolation pattern 152 and the second isolation pattern 154, and the first pad 142 and the second pad 144 thereon. A first photoresist pattern extending in the second direction can be formed on the dummy gate mask layer to partially cover the first region I and the second region II of the substrate 100, respectively, and the dummy gate mask layer can be etched using the first photoresist pattern as an etching mask to form a first dummy gate mask 232 and a second dummy gate mask 234 on the first region I and the second region II of the substrate 100, respectively. The dummy gate insulating layer can include an oxide such as silicon oxide, the dummy gate electrode layer can include, for example, polysilicon, and the dummy gate mask layer can include a nitride such as silicon nitride.

[0094] The dummy gate electrode layer and the dummy gate insulating layer can be etched using the first dummy gate mask 232 and the second dummy gate mask 234 as etching masks to form a first dummy gate electrode 222 and a first dummy gate insulating pattern 212 on the first region I of the substrate 100, respectively, and a second dummy gate electrode 224 and a second dummy gate insulating pattern 214 on the second region II of the substrate 100, respectively. The first dummy gate insulating pattern 212, the first dummy gate electrode 222, and the first dummy gate mask 232 sequentially stacked on the first structure and on a portion of the first isolation pattern 152 adjacent to the first structure can form a first dummy gate structure 242. The second dummy gate insulating pattern 214, the second dummy gate electrode 224, and the second dummy gate mask 234 sequentially stacked on the second structure and on a portion of the second isolation pattern 154 adjacent to the second structure can form a second dummy gate structure 244.

[0095] In an example embodiment, the first dummy gate structure 242 can extend in the second direction on the first fin structure and the first isolation pattern 152, and can cover an upper surface of the first fin structure and opposite sidewalls of the first fin structure in the second direction. The first dummy gate structure 242 can further cover an upper sidewall of the first active pattern 102.

[0096] The second dummy gate structure 244 can extend in the second direction on the second fin structure and the second isolation pattern 154, and can cover an upper surface of the second fin structure and opposite sidewalls of the second fin structure in the second direction. The second dummy gate structure 244 can further cover an upper sidewall of the second active pattern 104.

[0097] Referring to FIG. 13 , FIG. 14A and FIG. 15The first spacer layer 250 can be formed on the substrate 100 having the first fin structure and the second fin structure, the first isolation pattern 152 and the second isolation pattern 154, the first pad 142 and the second pad 144, and the first dummy gate structure 242 and the second dummy gate structure 244. The second photoresist pattern 260 covering the second region II of the substrate 100 can be formed on the first spacer layer 250, and a portion of the first spacer layer 250 located on the first region I of the substrate 100 can be etched using the second photoresist pattern 260 as an etching mask. Accordingly, the first gate spacer 252 can be formed on each of opposite sidewalls of the first dummy gate structure 242 in the first direction, and the first fin spacer 253 can be formed on each of opposite sidewalls of the first fin structure in the second direction.

[0098] The first fin structure can be etched using the first dummy gate structure 242 and the first gate spacer 252 as an etching mask to form a first recess 272 exposing an upper surface of the first active pattern 102 of the substrate 100. Accordingly, the first sacrificial line 112 and the first semiconductor line 122 under the first dummy gate structure 242 and the first gate spacer 252 can be transformed into the first sacrificial pattern 116 and the first semiconductor pattern 126, respectively, and the first fin structure extending in the first direction can be divided into a plurality of fin structures spaced apart from each other in the first direction.

[0099] Hereinafter, for convenience of explanation, the first dummy gate structure 242, the first gate spacer 252, and the first fin structure together can be referred to as a third structure. In an example embodiment, the third structure can extend in the second direction, and a plurality of third structures can be spaced apart from each other in the first direction.

[0100] The first recess 272 formed by the etching process can have a volume as large as possible. In an example embodiment, the first recess 272 can have a larger volume than a comparative recess having a vertical sidewall aligned with an outer sidewall of the first gate spacer 252 in the third direction. Accordingly, a sidewall of the first recess 272 can be closer to a central portion of the first dummy gate structure 242 in the first direction than an outer sidewall of the first gate spacer 252, for example, a distance between the sidewall of the first recess 272 and a central vertical axis of the first dummy gate structure 242 along the first direction can be smaller than a distance between the outer sidewall of the first gate spacer 252 and the central vertical axis of the first dummy gate structure 242 along the first direction. FIG. 14A )。

[0101] In an example embodiment, the uppermost first semiconductor pattern 126 can have sidewalls that can not be perpendicular to the upper surface of the substrate but can be inclined. Thus, a first length L1 of the uppermost first semiconductor pattern 126 in the first direction can gradually decrease from its top toward the bottom. The other first semiconductor patterns 126 can have sidewalls that can be substantially perpendicular to the upper surface of the substrate 100, thus, a second length L2 of the other first semiconductor patterns 126 in the first direction can be constant along the third direction. In an example embodiment, a minimum value of the first length L1 can be substantially equal to the second length L2, and a maximum value of the first length L1 can be greater than the second length L2.

[0102] Since the first recess 272 can have a relatively large volume, during the etching process, portions of the first sacrificial lines 112 and the first semiconductor lines 122 located at opposite sides of the first dummy gate structure 242 in the first direction can be completely removed. For example, the lowermost first semiconductor line 122 having a relatively large width in the first direction can be completely removed.

[0103] During the etching process, the first fin spacers 253 can be almost removed. However, portions of the first fin spacers 253 covering upper portions of each of the sidewalls of the first active pattern 102 in the second direction can be remained. The first fin spacers 253 can be used to control a horizontal width of the first source / drain layer 282 (refer to FIGS. 16-18 ), and a height of the uppermost surface of the first fin spacers 253 remained after the etching process can be adjusted so that the first source / drain layer 282 can have a desired width.

[0104] In an example embodiment, the first recess 272 can have a lower surface that can not be flat but can have a downward convex curved shape. The upper surface of the first active pattern 102 can have a concave curved shape corresponding to the shape of the first recess 272.

[0105] In another example, referring to FIG. 14B , the first recess 272 can have a curved shape, thus the volume of the first recess 272 can be maximized. In this case, each of the first semiconductor patterns 126 can have sidewalls that can not be perpendicular but can have a varying slope, thus, the second length L2’ of the lower first semiconductor pattern 126 along the third direction can not be constant.

[0106] Hereinafter, only the first recess 272 having the sidewalls shown in FIG. 14A will be explained.

[0107] Referring to FIGS. 16-18After the second photoresist pattern 260 is removed, a first source / drain layer 282 can be formed on the upper surface of the first active pattern 102 exposed by the first recess 272. In an example embodiment, the first source / drain layer 282 can be formed by an SEG process using the exposed upper surface of the first active pattern 102 and the sidewall of the first semiconductor pattern 126 exposed by the first recess 272 as a seed.

[0108] In an example embodiment, the SEG process can be performed using a silicon source gas (e.g., dichlorosilane (SiH2Cl2) gas) and a germanium source gas (e.g., germane (GeH4) gas) to form a single-crystal silicon germanium (SiGe) layer. The single-crystal silicon germanium layer can be doped with a p-type impurity, and a heat treatment can be performed on the single-crystal silicon germanium layer. The first source / drain layer 282 can serve as a source / drain of a PMOS transistor.

[0109] In an example embodiment, as FIG. 17 illustrated, the first source / drain layer 282 can be formed on each of the opposite sidewalls of the third structure in the first direction, and can contact the sidewall of the first semiconductor pattern 126 and the lower portion of the outer sidewall of the first gate spacer 252. As described above, the first recess 272 can have a relatively large volume, and thus, the first source / drain layer 282 filling the first recess 272 can have a relatively large volume.

[0110] As FIG. 18 illustrated, the first source / drain layer 282 can include a lower portion 282a and an upper portion 282b that are sequentially stacked and connected to each other, and an interface between the lower portion 282a and the upper portion 282b can be located at the level of the uppermost surface of the first fin spacer 253. In an example embodiment, the lower portion 282a of the first source / drain layer 282 can have a cross-section in the second direction that is convexly curved (e.g., a portion of an ellipse or a circle). The upper portion 282b of the first source / drain layer 282 can have a cross-section in the second direction that is a portion of a polygon (e.g., a pentagon or a rectangle).

[0111] Referring to FIGS. 19-21 , a second spacer layer 290 can be formed on the substrate 100 having the third structure, the first source / drain layer 282, the first fin spacer 253, the first isolation pattern 152, and the first spacer layer 250. A third photoresist pattern 300 covering the first region I of the substrate 100 can be formed on the second spacer layer 290, and a portion of the second spacer layer 290 on the second region II of the substrate 100 can be removed by an etching process using the third photoresist pattern 300 as an etching mask.

[0112] Accordingly, a fourth gate spacer 294 can be formed to cover each of opposing sidewalls of the first spacer layer 250 in the first direction located on the second dummy gate structure 244, and a fourth fin spacer 295 can be formed on each of opposing sidewalls of the second fin structure in the second direction. The first spacer layer 250 can be anisotropically etched to form a third gate spacer 254 covering each of opposing sidewalls of the second dummy gate structure 244 in the first direction. A portion of the third gate spacer 254 located under the fourth gate spacer 294 can be preserved, and thus the third gate spacer 254 can have a cross-section of an “L” shape in the first direction. The sequentially stacked third gate spacer 254 and fourth gate spacer 294 can form a second gate spacer structure 504.

[0113] During the anisotropic etching process, a third fin spacer 255 covering each of opposing sidewalls of the second fin structure in the second direction can be formed. The sequentially stacked third fin spacer 255 and fourth fin spacer 295 can form a second fin spacer structure 505.

[0114] The second fin structure can be etched using the second dummy gate structure 244 and the second gate spacer structure 504 as etching masks to form a second recess 304 exposing an upper surface of the second active pattern 104. Accordingly, the second sacrificial lines 114 and the second semiconductor lines 124 located under the second dummy gate structure 244 and the second gate spacer structure 504 can be transformed into second sacrificial patterns 118 and second semiconductor patterns 128, respectively, and the second fin structure extending in the first direction can be divided into a plurality of second fin structures spaced apart from each other in the first direction.

[0115] Hereinafter, the second dummy gate structure 244, the second gate spacer structure 504, and the second fin structure together can be referred to as a fourth structure. In an example embodiment, the fourth structure can extend in the second direction, and a plurality of fourth structures can be spaced apart from each other in the first direction.

[0116] In an example embodiment, the second recess 304 can have a vertical sidewall substantially perpendicular to the upper surface of the substrate 100 and aligned with an outer sidewall of the second gate spacer structure 504 in the third direction. Accordingly, a third length L3 of each of the second semiconductor patterns 128 in the first direction can be constant along the third direction. In an example embodiment, the third length L3 can be greater than the second length L2, and can be greater than a maximum value of the first length L1.

[0117] However, due to the nature of the etching process, the sidewalls of the second recess 304 can not be completely perpendicular to the upper surface of the substrate 100, but rather a portion (e.g., a lower portion) of the sidewalls of the second recess 304 can have an angle with respect to the upper surface of the substrate 100 in a range of, for example, about 80 degrees to 90 degrees. Thus, the length L3 of each second semiconductor pattern 128 (e.g., the lowermost second semiconductor pattern 128) in the first direction can increase near the bottom surface thereof.

[0118] Since the second recess 304 can have vertical sidewalls, even though most of the second sacrificial lines 114 and the second semiconductor lines 124 located at opposite sides of the second dummy gate structure 244 in the first direction are removed during the etching process, the lowermost second sacrificial line 114 having a relatively large width in the first direction can not be completely removed. Most of the second fin spacer structure 505 can be removed during the etching process, however, a portion of the second fin spacer structure 505 covering an upper portion of each of the opposite sidewalls of the second active pattern 104 in the second direction can be preserved. The preserved second fin spacer structure 505 can include a third fin spacer 255 and a fourth fin spacer 295 sequentially stacked. The second fin spacer structure 505 can be used to control the horizontal width of the second source / drain layer 334 (refer to FIGS. 24-26 ), the height of the uppermost surface of the second fin spacer structure 505 preserved after the etching process can be adjusted such that the second source / drain layer 334 can have a desired width.

[0119] In an example embodiment, the second recess 304 can have a lower surface that can be substantially flat except for opposite edges in the second direction, and the corresponding portions of the second active pattern 104 can have an upper surface that can be substantially flat. However, the portions of the second active pattern 104 not overlapping with the second dummy gate structure 244 and the second gate spacer structure 504 in the third direction can have first protrusions 106 protruding from the opposite edges in the second direction, and the upper surface of the portions of the second active pattern 104 located between the first protrusions 106 can be substantially flat.

[0120] In an example embodiment, the second sacrificial line 114 can be preserved on the first protrusion 106 of the second active pattern 104 after the etching process, and the second recess 304 can expose the inner sidewalls of the first protrusion 106 and the inner sidewalls of the second sacrificial line 114. The second fin spacer structure 505 can cover the outer sidewalls of the first protrusion 106 of the second active pattern 104 and the outer sidewalls of the second sacrificial line 114.

[0121] For example, refer to FIG. 22AAfter the third photoresist pattern 300 is removed, each of the side walls of each second sacrificial pattern 118 in the opposite side walls in the first direction exposed by the second recess 304 can be etched to form a third recess 320. In an example embodiment, the third recess 320 can be formed on the second sacrificial pattern 118 by a wet etching process. In an example embodiment, the third recess 320 can have a cross-section in the first direction that can have a semi-circular shape.

[0122] In another example, referring to FIG. 22B , the third recess 320 can have a cross-section in the first direction that can have a rounded rectangular shape in which edges of the side walls facing the second sacrificial pattern 118 are rounded.

[0123] For example, referring to FIG. 23A , an inner spacer 330 can be formed in the third recess 320. In an example embodiment, the inner spacer 330 can be formed by forming a third spacer layer to fill the third recess 320 on the substrate 100 and anisotropically etching the third spacer layer. Accordingly, the inner spacer 330 can cover each of the side walls of each second sacrificial pattern 118 in the opposite side walls in the first direction, and a center portion of the outer side wall of the inner spacer 330 in the third direction can be concave. In an example embodiment, the inner spacer 330 can have a cross-section in the first direction that can have a horseshoe shape or a semi-circular shape in which the outer side wall thereof has a recess.

[0124] In another example, referring to FIG. 23B , the inner spacer 330 can have a cross-section in the first direction that can have a rounded rectangular shape in which the outer side wall thereof has a recess.

[0125] Referring to FIGS. 24-26 , a second source / drain layer 344 can be formed on the upper surface of the second active pattern 104 exposed by the second recess 304. In an example embodiment, the second source / drain layer 344 can be formed by an SEG process using the upper surface of the second active pattern 104 exposed by the second recess 304 and the side wall of the second semiconductor pattern 128 exposed by the second recess 304 as a seed.

[0126] In an example embodiment, the SEG process can be performed using a silicon source gas (e.g., disilane (Si2H6)) to form a single-crystal silicon layer. Alternatively, the SEG process can be performed using a silicon source gas (e.g., disilane (Si2H6)) and a carbon source gas (e.g., SiH3CH3) to form a single-crystal silicon carbide (SiC) layer. The single-crystal silicon layer or the single-crystal silicon carbide layer can be doped with an n-type impurity, and a heat treatment can be performed on the single-crystal silicon layer or the single-crystal silicon carbide layer. The second source / drain layer 344 can serve as a source / drain of an NMOS transistor.

[0127] In an example embodiment, the second source / drain layer 344 can be formed on each of the opposite sidewalls of the fourth structure in the first direction, and can contact the sidewalls of the second semiconductor pattern 128 and the lower portions of the outer sidewalls of the second gate spacer structure 504.

[0128] The second source / drain layer 344 can include a lower portion 344a and an upper portion 344b which are sequentially stacked and connected to each other, and an interface between the lower portion 344a and the upper portion 344b can be located at the level of the uppermost surface of the second fin spacer structure 505. In an example embodiment, the lower portion 344a of the second source / drain layer 344 can have a cross-section having a "U" shape in the second direction. The upper portion 344b of the second source / drain layer 344 can have a cross-section having various shapes (e.g., an oval shape) in the second direction.

[0129] Referring to FIGS. 27-29 An insulating layer 350 can be formed on the second isolation pattern 154 and the second liner 144 to cover the third and fourth structures, the second fin spacer structure 505, the second spacer layer 290, and the first and second source / drain layers 282 and 334, and the insulating layer 350 can be planarized until the upper surfaces of the first dummy gate electrode 222 of the third structure and the second dummy gate electrode 224 of the fourth structure can be exposed. The planarization process can be performed by a CMP process and / or an etch-back process.

[0130] During the planarization process, the first and second dummy gate masks 232 and 234 can also be removed, and the upper portions of the first gate spacer 252, the second spacer layer 290, and the second gate spacer structure 504 can be partially removed.

[0131] The second spacer layer 290, of which the upper portion has been removed, can form a second gate spacer 292 on the outer sidewalls of the first gate spacer 252, and the second spacer layer 290 can also cover the surfaces of the first fin spacer 253 and the first source / drain layer 282, which can be hereinafter referred to as a second fin spacer 293. The second fin spacer 293 can also cover the upper surfaces of the first isolation pattern 152 adjacent to the first source / drain layer 282 in the second direction.

[0132] The first and second gate spacers 252 and 292 which are sequentially stacked on each of the opposite sidewalls of the first dummy gate structure 242 in the first direction can form a first gate spacer structure 502, and the first and second fin spacers 253 and 293 which are sequentially stacked on the upper portions of each of the opposite sidewalls of the first active pattern 102 in the second direction can form a first fin spacer structure 503.

[0133] The exposed first dummy gate electrode 222 and second dummy gate electrode 224 and the first dummy gate insulating pattern 212 and second dummy gate insulating pattern 214 thereunder can be removed to form first and second openings 362 and 364 exposing upper surfaces of the uppermost first semiconductor pattern 126 and the uppermost second semiconductor pattern 128, respectively. The first dummy gate electrode 222 and second dummy gate electrode 224 can be removed by, for example, a wet etching process.

[0134] The first sacrificial pattern 116 can be removed to form a third opening 363 exposing a surface of the first semiconductor pattern 126 and an upper surface of the first active pattern 102, and to form a fourth opening 365 exposing an inner sidewall of the inner spacer 330, a surface of the second semiconductor pattern 126, and an upper surface of the second active pattern 104.

[0135] When the first sacrificial pattern 116 is removed, a portion of the second sacrificial line 114 remaining on the second region II of the substrate 100 and overlapping the fourth structure in the third direction can also be removed. Accordingly, the second sacrificial line 114 extending in the first direction can be divided into a plurality of third sacrificial patterns 119 spaced apart from each other in the first direction.

[0136] Referring again to FIGS. 1-4 The first gate structure 412 can be formed on the first region I of the substrate 100 to fill the first and third openings 362 and 363, and the second gate structure 414 can be formed on the second region II of the substrate 100 to fill the second and fourth openings 364 and 365.

[0137] Specifically, after performing a thermal oxidation process on the upper surfaces of the first and second active patterns 102 and 104 and the surfaces of the first and second semiconductor patterns 126 and 128 exposed by the first to fourth openings 362, 364, 363, and 365 to form first and second interface patterns 372 and 374, a gate insulating layer and a work function control layer can be sequentially formed on the surfaces of the first and second interface patterns 372 and 374, the inner sidewall of the inner spacer 330, the inner sidewalls of the first and second spacer structures 502 and 504, and the upper surface of the insulating layer 350, and a gate electrode layer can be formed to fill the remaining portions of the first to fourth openings 362, 364, 363, and 365.

[0138] The gate insulating layer, the work function control layer, and the gate electrode layer can be formed by, for example, a CVD process, an ALD process, a PVD process, or the like. The first interface pattern 372 and the second interface pattern 374 can also be formed by a CVD process, an ALD process, a PVD process, or the like instead of a thermal oxidation process, in which case each of the first interface pattern 372 and the second interface pattern 374 can also be formed on the inner sidewalls of the inner spacers 330 and the inner sidewalls of the first spacer structure 502 and the second spacer structure 504.

[0139] The gate electrode layer, the work function control layer, and the gate insulating layer can be planarized until the upper surface of the insulating layer 350 can be exposed to form the first gate electrode 402 and the second gate electrode 404, the first work function control pattern 392 and the second work function control pattern 394, and the first gate insulating pattern 382 and the second gate insulating pattern 384, respectively. The first interface pattern 372, the first gate insulating pattern 382, the first work function control pattern 392, and the first gate electrode 402 can form the first gate structure 412, and the second interface pattern 374, the second gate insulating pattern 384, the second work function control pattern 394, and the second gate electrode 404 can form the second gate structure 414.

[0140] A semiconductor device can be manufactured by the above processes. As described above, the first source / drain layer 282 can have a relatively large width in the first direction, and thus the lowermost first sacrificial pattern 116 can not be reserved, and the lowermost second sacrificial pattern 118 can be reserved.

[0141] FIGS. 30-32 is a plan view and cross-sectional views illustrating a semiconductor device according to an example embodiment. FIG. 30 is a plan view, FIG. 31 includes cross-sections taken along FIG. 30 lines B-B' and C-C' of FIG. 32 is a cross-sectional view taken along FIG. 30 line D-D' of FIGS. 1-5 is substantially the same as the semiconductor device of , except for some elements. Accordingly, like reference numerals are used to refer to like elements, and a detailed description thereof will not be repeated here.

[0142] Referring to FIGS. 30-32 , a portion of the first active pattern 102 that does not overlap the first gate structure 412 and the first gate spacer 252 in the third direction can include second protrusions 108 that protrude upward from opposite edges in the second direction, respectively, and a surface of a portion of the second active pattern 104 located between the second protrusions 108 can be flat.

[0143] The inner sidewall of the second protrusion 108 of the first active pattern 102 can contact the first source / drain layer 282, and the outer sidewall of the second protrusion 108 of the first active pattern 102 can contact the first fin spacer 253. That is, the bottom surface of the second protrusion 108 can be substantially coplanar with the lower surface of the first source / drain layer 282, which can be substantially flat between the second protrusions 108 adjacent in the second direction.

[0144] In an example embodiment, the lower portion 282a of the first source / drain layer 282 can have a "U" shaped cross-section.

[0145] In an example embodiment, a fourth sacrificial pattern 117 can be formed on the second protrusion 108 of the first active pattern 102. The inner sidewall of the fourth sacrificial pattern 117 can be covered by the sidewall of the lower portion 282a of the first source / drain layer 282, and the outer sidewall of the fourth sacrificial pattern 117 can be covered by the first fin spacer 253. In an example embodiment, the bottom surface of the fourth sacrificial pattern 117 can be higher than the bottom surface of the first source / drain layer 282.

[0146] The fourth sacrificial pattern 117 can extend in the first direction in an area not overlapping with the first gate structure 412 and the first gate spacer structure 502. In some embodiments, the fourth sacrificial pattern 117 can partially overlap with the first gate spacer structure 502 in the third direction.

[0147] FIGS. 33-35 is a top view and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment. Specifically, FIG. 33 is a top view, FIG. 34 including cross-sections taken along FIG. 33 lines B-B' and C-C' of FIG. 10A, FIG. 35 is a cross-sectional view taken along FIG. 33 line D-D' of FIG. 10A. The method can include substantially the same or similar processes as those shown with reference to FIGS. 5-29 and FIGS. 1-4 and thus a repeated explanation of them is omitted here.

[0148] With reference to FIGS. 33-35 , substantially the same or similar processes as those shown with reference to FIGS. 5-15 may be performed.

[0149] However, the first recess 272 formed by the etching process can have a vertical sidewall that can be substantially perpendicular to the upper surface of the substrate 100 and aligned with the outer sidewall of the first gate spacer 252. Thus, when the first sacrificial lines 112 and the first semiconductor lines 122 located at opposite sides of the first dummy gate structure 242 and the first gate spacer 252 in the first direction are removed, the lowermost first sacrificial line 112 having a relatively large width in the first direction can not be completely removed. For example, the first recess 272 can have a “U”-shaped cross-section.

[0150] The processes substantially the same as or similar to the processes shown in FIGS. 1A to 1C can be performed to complete the fabrication of the semiconductor device. FIGS. 16-29 and FIGS. 1-4 FIGS. 1-4 The processes substantially the same as or similar to the processes shown in FIGS. 1A to 1C can be performed to complete the fabrication of the semiconductor device.

[0151] By way of summary and review, the example embodiments provide a semiconductor device having enhanced characteristics. That is, in the semiconductor device according to the example embodiments, the source / drain layer of the PMOS transistor can have a relatively large lattice and a relatively large volume when compared to the channel of the PMOS transistor. Thus, a relatively strong compressive stress can be applied to the channel to improve the mobility of the charge in the channel. The channel of the NMOS transistor can have a relatively long constant length, and thus the characteristics of the NMOS transistor can have enhanced electrical characteristics.

[0152] Example embodiments have been disclosed herein, although the specific terminology has been used to describe them, they have been used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements of another embodiment unless otherwise specifically indicated. Accordingly, one of ordinary skill in the art will recognize that the various features, characteristics, and / or elements described in connection with a particular embodiment can be used in a variety of other embodiments without departing from the spirit and scope of the present application as set forth in the following claims.

Claims

1. A semiconductor device comprising: an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure; a source / drain layer on a portion of the active pattern adjacent to the gate structure, the source / drain layer contacting the channels; and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source / drain layer and including silicon germanium. The sacrificial pattern extends in the first direction to contact a lower portion of each of opposite sidewalls of the source / drain layer in the second direction.

2. The semiconductor device of claim 1, wherein, The portion of the active pattern adjacent to the gate structure includes a protrusion projecting upward along the third direction at each of the opposite edges in the second direction, the sacrificial pattern being on the protrusion.

3. The semiconductor device of claim 1, wherein, 4. The semiconductor device of claim 1, further comprising a first spacer structure on each of opposite edges of the portion of the active pattern in the second direction, the first spacer structure contacting an outer sidewall of the sacrificial pattern. The first spacer structure contacts a portion of the active pattern and a portion of the source / drain layer.

5. The semiconductor device of claim 4, wherein, The first spacer structure includes a first fin-shaped spacer and a second fin-shaped spacer sequentially stacked.

6. The semiconductor device of claim 4, wherein, The first fin-shaped spacer and the second fin-shaped spacer each include nitride.

7. The semiconductor device of claim 6, wherein, 8. The semiconductor device of claim 1, wherein: the source / drain layer includes a lower portion and an upper portion sequentially stacked to be connected to each other in the third direction, and a cross section of the lower portion of the source / drain layer in the second direction is "U" shaped and a cross section of the upper portion of the source / drain layer in the second direction is elliptical.

9. The semiconductor device of claim 1, further comprising a first gate spacer structure covering each of opposite sidewalls of the gate structure in the first direction. The first gate spacer structure includes a first gate spacer and a second gate spacer sequentially stacked from each of the opposite sidewalls of the gate structure in the first direction, a cross section of the first gate spacer in the first direction being "L" shaped.

10. The semiconductor device of claim 9, wherein, The first gate spacer and the second gate spacer each include nitride.

11. The semiconductor device of claim 10, wherein, Each of the channels includes silicon, the source / drain layer including silicon doped with an n-type impurity or silicon carbide doped with an n-type impurity.

12. The semiconductor device of claim 1, wherein, ​ 13. The semiconductor device of claim 1, further comprising an inner spacer between the channels, the inner spacer contacting the source / drain layer and the gate structure.

14. The semiconductor device of claim 13, wherein, The inner spacer includes nitride.

15. The semiconductor device of claim 1, further comprising: a third fin-shaped spacer on each of opposite edges of the portion of the active pattern in the second direction, the third fin-shaped spacer contacting outer sidewalls of the sacrificial pattern; and a fourth fin-shaped spacer covering the third fin-shaped spacer and the source / drain layer.

16. The semiconductor device of claim 15, wherein, The third fin-shaped spacer and the fourth fin-shaped spacer each include nitride.

17. The semiconductor device of claim 15, wherein: the source / drain layer includes a lower portion and an upper portion stacked in sequence in the third direction to contact each other, and a cross section of the lower portion of the source / drain layer in the second direction is "U” shaped, and a cross section of the upper portion of the source / drain layer in the second direction has a shape of a pentagon or a portion of a rectangle.

18. The semiconductor device of claim 15, wherein, Each of the channels includes silicon, and the source / drain layer includes silicon germanium doped with a p-type impurity.

19. The semiconductor device of claim 15, further comprising a second gate spacer structure covering each of opposite sidewalls of the gate structure in the first direction, the second gate spacer structure including a third gate spacer and a fourth gate spacer, the third gate spacer and the fourth gate spacer stacked in sequence from each of the opposite sidewalls of the gate structure in the first direction, wherein, a height of a bottom surface of the third gate spacer is lower than a height of a bottom surface of the fourth gate spacer.

20. A semiconductor device, comprising: a substrate including a first region and a second region; first channels on the first region of the substrate, the first channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; second channels on the second region of the substrate, the second channels spaced apart from each other in the vertical direction; a first gate structure on the first region of the substrate, the first gate structure covering at least a portion of a surface of each of the first channels; a second gate structure on the second region of the substrate, the second gate structure covering at least a portion of a surface of each of the second channels; a first source / drain layer on the first region of the substrate, the first source / drain layer contacting the first channels; a second source / drain layer on the second region of the substrate, the second source / drain layer contacting the second channels; and ​ a sacrifice pattern contacting a lower portion of a sidewall of the second source / drain layer, the sacrifice pattern including silicon germanium, wherein a lower surface of the first source / drain layer is a convexly curved surface in the vertical direction, a central portion of a lower surface of the second source / drain layer is flat, and an edge of the lower surface of the second source / drain layer is rounded.

21. The semiconductor device of claim 20, wherein, a bottom surface of the sacrifice pattern is higher than the lower surface of the second source / drain layer.

22. The semiconductor device of claim 20, wherein, an upper portion of the first source / drain layer has a shape of a pentagon or a portion of a rectangle in cross section in one direction, and an upper portion of the second source / drain layer has a shape of an ellipse in cross section in the direction.

23. The semiconductor device of claim 20, further comprising: a first fin spacer contacting a lower portion of each of opposing sidewalls of the first source / drain layer in the direction; and a fin spacer structure contacting an outer sidewall of the sacrifice pattern and a lower portion of each of opposing sidewalls of the second source / drain layer in the direction, the fin spacer structure having a thickness greater than a thickness of the first fin spacer.

24. The semiconductor device of claim 23, wherein, an uppermost surface of the fin spacer structure is higher than an uppermost surface of the first fin spacer.

25. A semiconductor device, comprising: an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending in the first direction across the gate structure; source / drain layers on portions of the active pattern at each of opposing sides of the gate structure in the first direction, the source / drain layers contacting the channels; and a sacrifice pattern and a fin spacer structure sequentially stacked in the second direction on a lower portion of each of opposing sidewalls of the source / drain layers in the second direction, the sacrifice pattern and the fin spacer structure including different materials from each other, and the fin spacer structure directly contacting a portion of the source / drain layers and the active pattern.

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