Modification of the ferroelectric properties of hafnium oxide using a hafnium nitride layer

Abstract

A method for forming ferroelectric hafnium oxide (HfO2) in a substrate processing system includes: depositing a HfO2 layer on a substrate; depositing a hafnium nitride (HfN) layer on the HfO2 layer; and annealing the HfO2 layer and the HfN layer to form ferroelectric hafnium HfO2.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 651,454, filed on April 2, 2018. The entire disclosure of the above-referenced application is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to methods for processing substrates, and more particularly to methods for reducing leakage current in hafnium oxide based ferroelectric materials. Background Art

[0004] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the description that could not be determined as prior art at the time the application was filed.

[0005] The discovery of ferroelectric properties in hafnium oxide (HfO2)-based materials has revitalized research into ferroelectric memory (FeRAM). Conventional ferroelectric materials, such as lead zirconate titanate (PZT), do not have sufficient switching windows for thicknesses below 50 nanometers (nm). Therefore, PZT cannot be used in devices with feature sizes below 50nm.

[0006] Due to the high coercive field, HfO2 has a ferroelectric switching hysteresis as low as 6nm thickness. HfO2 is also an ideal candidate for 3D memory structures. HfO2 has been widely used as a gate dielectric in CMOS technology. In these applications, HfO2 is deposited using conformal atomic layer deposition (ALD). Therefore, HfO2 may be suitable for integration into 3D FeRAM using current 3D NAND integration schemes. Summary of the invention

[0007] A method for forming ferroelectric hafnium oxide (HfO2) in a substrate processing system includes: depositing a HfO2 layer on a substrate; depositing a hafnium nitride (HfN) layer on the HfO2 layer; and annealing the HfO2 layer and the HfN layer to form ferroelectric hafnium HfO2.

[0008] In other features, the method further includes depositing a second HfO2 layer on the HfN layer. The method further includes performing oxidation on the HfN layer. Performing the oxidation on the HfN layer includes performing the oxidation using at least one of molecular oxygen and ozone. The method further includes nitriding the HfO2 layer before depositing the HfN layer. Nitriding the HfO2 layer includes generating a plasma using a nitrogen species.

[0009] In other features, the method further includes depositing a top electrode on the HfN layer before the annealing. The top electrode includes a material selected from the group consisting of titanium, tantalum and tungsten. The method also includes depositing a second HfO2 layer on the HfN layer and depositing a top electrode on the HfN layer. The method also includes depositing a bottom electrode on the substrate and depositing the HfO2 layer on the bottom electrode. The HfO2 layer is doped using a dopant substance selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr) and / or lanthanum (La). Annealing the HfO2 layer and the HfN layer includes performing a rapid thermal annealing process at a temperature between 500° C. and 1100° C.

[0010] A system configured to form ferroelectric hafnium oxide (HfO2) on a substrate in a process chamber includes: a gas delivery system configured to supply gas to the process chamber; and a radio frequency (RF) generation system configured to generate plasma in the process chamber. A controller is configured to control the gas delivery system and the RF generation system to: deposit an HfO2 layer on the substrate; deposit a hafnium nitride (HfN) layer on the HfO2 layer; and anneal the HfO2 layer and the HfN layer to form ferroelectric hafnium HfO2.

[0011] In other features, the controller is further configured to deposit a second HfO2 layer on the HfN layer. The controller is further configured to perform oxidation on the HfN layer. Performing the oxidation on the HfN layer includes performing the oxidation using at least one of molecular oxygen and ozone. The controller is further configured to nitridate the HfO2 layer prior to depositing the HfN layer. Nitriding the HfO2 layer includes generating a plasma using a nitrogen species.

[0012] In other features, the controller is further configured to deposit a top electrode on the HfN layer prior to the annealing. The top electrode comprises a material selected from the group consisting of titanium, tantalum and tungsten. The controller is further configured to deposit a second HfO2 layer on the HfN layer and to deposit a top electrode on the HfN layer. The controller is further configured to deposit a bottom electrode on the substrate and to deposit the HfO2 layer on the bottom electrode. The HfO2 layer is doped with a dopant substance selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr) and / or lanthanum (La). Annealing the HfO2 layer and the HfN layer includes performing a rapid thermal annealing process at a temperature between 500 and 1100°C.

[0013] Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings.The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0015] Figure 1 is a functional block diagram of an exemplary substrate processing system for forming a ferroelectric hafnium oxide (HfO2) layer according to the present disclosure;

[0016] FIG. 2A to FIG. 2F is a side cross-sectional view of an exemplary process for forming a device including ferroelectric HfO2;

[0017] FIG. 3A to FIG. 3F is a side cross-sectional view of an exemplary process for forming a ferroelectric HfO2 layer including hafnium nitride (HfN) according to the present disclosure;

[0018] Figure 4A and Figure 4B is a side cross-sectional view of an exemplary device including a HfN layer formed on a HfO2 layer according to the present disclosure;

[0019] Figure 5A and Figure 5B is a side cross-sectional view of an exemplary device including a HfN layer formed between HfO2 layers according to the present disclosure; and

[0020] Figure 6 An example method for forming a ferroelectric HfO2 layer including a HfN layer according to the present disclosure is shown.

[0021] Among the drawings, reference numerals may be repeated to identify similar and / or identical elements. DETAILED DESCRIPTION

[0022] The thermal stability of HfO2 is a barrier to the commercialization of FeRAM applications. Although temperatures of 600-650°C are high enough to crystallize the deposited amorphous HfO2 into a ferroelectric phase, many integration schemes require a thermal budget of at least 1000°C. Higher process temperatures can degrade HfO2-based FeRAM by increasing leakage current and / or shorting the device. Sources of leakage after high-temperature annealing include defects generated at the top electrode / HfO2 interface. Another source of leakage current includes film rupture of HfO2. As HfO2 cleaves, atoms from the top and bottom electrodes (usually TiN) diffuse freely into the HfO2, which ultimately renders the device inoperable. For example, the top electrode acts as a cap during the annealing process to prevent the HfO2 layer from transforming into a thermodynamically stable monoclinic phase. In the monoclinic phase, HfO2 is not ferroelectric.

[0023] In some examples, HfO2 can be doped (i.e., dopants can be added to HfO2). For example, the desired ferroelectricity of HfO2 can be controlled by varying the type and concentration of the dopant. However, certain types and concentrations of dopants may cause undesirable characteristics in the operation of semiconductor devices containing ferroelectric HfO2. For example, increasing the mol% of silicon (Si) in ferroelectric HfO2 (e.g., from 4% to 6%) may cause a "wake-up effect," which may correspond to an increase in the remnant polarization of HfO2. In one example, using zirconium (Zr) instead of Si as a dopant causes an interdependence of polarization and annealing temperature, which increases the sensitivity of the device to process variations and non-uniformities.

[0024] According to the systems and methods of the present disclosure, one or more hafnium nitride (HfN) layers are deposited on the HfO2 layer between alternating HfO2 layers to change the ferroelectric properties of the HfO2 layer. For example, the HfN layer can be deposited using ALD in the same process chamber used to deposit the HfO2 layer.

[0025] Figure 1 An exemplary substrate processing system 100 for depositing and doping a HfO2 layer including one or more HfN layers to form a ferroelectric HfO2 using atomic layer deposition (ALD) according to the present disclosure is shown. Although the deposition and doping of the HfO2 layer and the deposition of the HfN layer are performed in the same processing chamber in this example, separate processing chambers may be used. For example, a transformer coupled plasma (TCP) chamber, a plasma enhanced chemical vapor deposition (PECVD) chamber, a high pressure CVD (HPCVD) chamber, and / or a processing chamber using a remote plasma source may be used to perform one or more deposition or etching steps, as described below.

[0026] The substrate processing system 100 includes a processing chamber 102 that surrounds the other components of the substrate processing system 100 and contains an RF plasma. The substrate processing chamber 102 includes an upper electrode 104 and a substrate support, such as an electrostatic chuck (ESC) 106. During operation, a substrate 108 is disposed on the ESC 106.

[0027] By way of example only, the upper electrode 104 may include a showerhead 109 that introduces and distributes the process gas. The showerhead 109 may include a stem that includes one end connected to the top surface of the process chamber. The base portion is generally cylindrical and extends radially outward from the opposite end of the stem at a position spaced from the top surface of the process chamber. The surface or faceplate of the base portion of the showerhead that faces the substrate includes a plurality of holes that allow the process gas or purge gas to flow through. Alternatively, the upper electrode 104 may include a conductive plate and the process gas may be introduced in another manner.

[0028] The ESC 106 includes a conductive substrate 110 that serves as a lower electrode. The substrate 110 supports a heating plate 112, which may correspond to a ceramic multi-zone heating plate. A thermal resistance layer 114 may be disposed between the heating plate 112 and the substrate 110. The substrate 110 may include one or more coolant channels 116 for flowing a coolant through the substrate 110.

[0029] The RF generation system 120 generates an RF voltage and outputs the RF voltage to one of the upper electrode 104 and the lower electrode (e.g., the substrate 110 of the ESC 106). The other of the upper electrode 104 and the substrate 110 may be DC grounded, AC grounded, or floating. By way of example only, the RF generation system 120 may include an RF voltage generator 122 that generates an RF voltage that is fed to the upper electrode 104 or the substrate 110 by a matching and distribution network 124. In other examples, the plasma may be generated inductively or remotely.

[0030] The gas delivery system 130 includes one or more gas sources 132-1, 132-2, ... and 132-N (collectively referred to as gas sources 132), where N is an integer greater than zero. The gas source provides one or more deposition precursors and mixtures thereof. The gas precursor may include precursor gases for HfO2 layers, HfN layers and / or other layers. The gas source may also supply a purge gas and a gas containing nitrogen substances for plasma nitridation and / or other gas substances for other plasma treatments (e.g., Ar, Ar / H2, NH3, O2, O3, etc.). Vaporized precursors may also be used. The gas source 132 is connected to the manifold via valves 134-1, 134-2, ... and 134-N (collectively referred to as valves 134) and mass flow controllers 136-1, 136-2, ... and 136-N (collectively referred to as mass flow controllers 136). The output of the manifold is supplied to the processing chamber 102. By way of example only, the output of the manifold is supplied to the showerhead 109. In some examples, an optional ozone generator 140 can be provided between the mass flow controller 136 and the manifold. In some examples, the substrate processing system 100 can include a liquid precursor delivery system. The liquid precursor delivery system can be incorporated into the gas delivery system 130 as shown, or can be external to the gas delivery system 130. The liquid precursor delivery system is configured to provide precursors that are liquid and / or solid at room temperature via a bubbler, direct liquid injection, vapor extraction, etc.

[0031] The temperature controller 142 can be connected to a plurality of thermal control elements (TCEs) 144 arranged in the heating plate 112. For example, the TCEs 144 can include, but are not limited to, a respective macro TCE corresponding to each zone in the multi-zone heating plate and / or an array of micro TCEs arranged across multiple zones of the multi-zone heating plate, such as Figure 2A and Figure 2B A temperature controller 142 may be used to control a plurality of heating elements 144 to control the temperature of the ESC 106 and the substrate 108 .

[0032] The temperature controller 142 may communicate with a coolant assembly 146 (eg, including a coolant pump, coolant reservoir, or coolant source) to control coolant flow through the passage 116. The temperature controller 142 operates the coolant assembly 146 to selectively flow coolant through the passage 116 to cool the ESC 106.

[0033] A valve 150 and a pump 152 may be used to evacuate reactants from the process chamber 102. A system controller 160 may be used to control components of the substrate processing system 100. A robot 170 may be used to transport substrates to and from the ESC 106. For example, the robot 170 may transfer substrates between the ESC 106 and a load lock 172. Although the temperature controller 142 is shown as a separate controller, the temperature controller 142 may be implemented within the system controller 160.

[0034] Reference now Figure 2A , 2B 2C, 2D, 2E and 2F show exemplary processes for forming a (HfO2)-based ferroelectric material in device 200. Figure 2A In the present invention, the device 200 includes a substrate (e.g., one or more underlying layers) 204 and an interface layer 208 disposed on the underlying layer 204. For example, the underlying layer 204 includes silicon (Si). In some examples, the interface layer 208 corresponds to a bottom electrode including titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W), but other electrode materials may be used. Other examples include, but are not limited to, platinum (Pt), gold (Au), palladium (Pd), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), etc. In other examples, the interface layer 208 may include silicon dioxide (SiO2) or silicon oxynitride (SiON). In some examples, the interface layer 208 is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In other examples, the interface layer 208 may be formed via thermal oxidation of Si. For example, the interface layer 208 may be formed by thermally oxidizing Si in an oxygen environment with nitrogen species (eg, N2O or N2) to form SiON, plasma nitriding SiO2, and the like.

[0035] like Figure 2BAs shown, a HfO2 layer 212 is deposited on the interface layer 208. In some examples, the thickness of the deposited HfO2 layer 212 is in the range of 2nm to 12nm. In some examples, the HfO2 layer 212 is doped with a dopant substance selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr) and / or lanthanum (La). In some examples, the HfO2 layer 212 is deposited using atomic layer deposition (ALD), but other processes can be used. For example, thermal ALD or plasma enhanced ALD can be used. In some examples, the HfO2 layer 212 is undoped. In other examples, the HfO2 layer 212 is doped to a predetermined doping level, which is from greater than 0mol% to less than or equal to 60mol% of the selected dopant substance. In some examples, the HfO2 layer 212 is doped to a predetermined doping level of 3mol% to 5mol% of the selected dopant substance. The HfO2 layer 212 may be amorphous.

[0036] Plasma treatment of the HfO2 layer 212 may be optionally performed. For example, the HfO2 layer 212 is nitrided by a plasma containing a nitrogen substance. For example, molecular nitrogen (N2) gas may be used. In some examples, nitridation is performed within a predetermined time period in the range of 15s to 60s. In some examples, the RF power may be in the range of 100W to 15kW. In some examples, the plasma power is in the range of 500W to 1200W. In some examples, the RF frequency may be in the range of 1MHz to 15MHz. In some examples, the RF frequency is 2.0MHz and / or 13.56MHz.

[0037] After plasma treatment, Figure 2C As shown, a top electrode 216 is deposited on the HfO2 layer 212. In some examples, the top electrode 216 includes TiN, TaN, or W, but other electrode materials (e.g., Pt, Au, Pd, Al, Mo, Ni, Ti, etc.) can be used. In some examples, the top electrode 216 is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). After depositing the top electrode 216, the device 200 is annealed at a predetermined temperature of 500° C. to 1100° C. In other examples, the annealing temperature is in the range of 800° C. to 1000° C.

[0038] After annealing, Figure 2D , 2E The top electrode 216 is patterned as shown in FIG. 2F. For example, Figure 2D As shown, a mask 220 may be deposited. The mask 220 may include platinum (Pt). Figure 2EAs shown, wet etching or dry etching is used to etch the top electrode 216. In some examples, such as Figure 2F As shown, mask 220 is optionally removed after etching. In other examples, the mask is not removed.

[0039] Reference now Figure 3A , 3B 3C, 3D, 3E and 3F show an exemplary process for forming a (HfO2)-based ferroelectric layer including HfN in device 300 according to the present disclosure. Figure 3A In the embodiment of the present invention, device 300 includes a substrate (e.g., one or more underlying layers) 304 and an interface layer 308 disposed on underlying layer 304. For example, underlying layer 304 includes silicon (Si). In some examples, interface layer 308 corresponds to a bottom electrode including titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W), but other electrode materials may be used. Other examples include, but are not limited to, platinum (Pt), gold (Au), palladium (Pd), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), etc. In other examples, interface layer 308 may include silicon dioxide (SiO2) or silicon oxynitride (SiON). In some examples, interface layer 308 is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0040] like Figure 3B As shown, a HfO2 layer (e.g., a ferroelectric layer) 312 including one or more layers of HfO2 and one or more layers of HfN is deposited on the interface layer 308. The HfO2 layer 312 and the one or more layers of HfN can be deposited using atomic layer deposition (ALD), but other processes can be used. For example, thermal ALD or plasma enhanced ALD can be used. The HfO2 layer 312 can be amorphous. In some examples, the top layer of the HfO2 layer 312 can be a HfN layer. In other examples, the HfN layer can be arranged between adjacent HfO2 layers. In some examples, the thickness of the deposited HfO2 layer 312 including one or more HfN layers is in the range of 2nm to 12nm.

[0041] In some examples, the HfO2 layer 312 is doped with a dopant substance selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr), gd, strontium (Sr), and / or lanthanum (La). For example, the HfO2 layer 312 is doped to a predetermined doping level that is greater than 0 mol% to less than or equal to 60 mol% of the selected dopant substance. In some examples, the HfO2 layer 312 is doped to a predetermined doping level of 3 mol% to 5 mol% of the selected dopant substance. In other examples, the HfO2 layer 312 may be undoped.

[0042] Plasma treatment of the HfO2 layer 312 may be optionally performed. For example, the HfO2 layer 312 is nitrided by a plasma containing a nitrogen substance. For example, molecular nitrogen (N2) gas may be used. In some examples, nitridation is performed within a predetermined time period in the range of 15s to 60s. In some examples, the RF power may be in the range of 100W to 15kW. In some examples, the plasma power is in the range of 500W to 1200W. In some examples, the RF frequency may be in the range of 1MHz to 15MHz. In some examples, the RF frequency is 2.0MHz and / or 13.56MHz. In other examples, the HfO2 layer 312 may be treated with a plasma containing an oxygen substance such as molecular oxygen (O2) or ozone (O3) to modify the properties of HfN.

[0043] After plasma treatment, Figure 3C As shown, a top electrode 316 is deposited on the HfO2 layer 312. In some examples, the top electrode 316 includes TiN, TaN, or W, but other electrode materials (e.g., Pt, Au, Pd, Al, Mo, Ni, Ti, etc.) can be used. In some examples, the top electrode 316 is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). After depositing the top electrode 316, the device 300 is annealed at a predetermined temperature of 500° C. to 1100° C. In other examples, the annealing temperature is in the range of 800° C. to 1000° C.

[0044] After annealing, Figure 3D , 3E The top electrode 216 is patterned as shown in FIG. 3F. For example, Figure 3D As shown, a mask 320 may be deposited. The mask 320 may be patterned using lift-off, shadow masking, or other suitable patterning methods. The mask 320 may include platinum (Pt) or another inert metal. Figure 3E As shown, wet etching or dry etching is used to etch the top electrode 316. In some examples, as shown in FIG. Figure 3F As shown, mask 320 is optionally removed after etching (eg, using a wet etch or a dry etch). In other examples, the mask is not removed.

[0045] Reference now Figure 4A and Figure 4B, an exemplary device 400 formed according to the present disclosure is shown. The device 400 includes a substrate (e.g., one or more underlying layers) 404 and an interface layer 408 disposed on the underlying layer 404. A ferroelectric layer 412 including a HfO2 layer 416 and a HfN layer 420 is formed on the interface layer 408. A top electrode 424 is formed on the ferroelectric layer 412. In some examples, the HfO2 layer 416 is doped (e.g., with Si, Al, Yt, Zr, La, Gd, Sr, etc.). Figure 4A and Figure 4B As shown, the HfN layer 420 is the top layer (ie, upper surface) of the ferroelectric layer 412 .

[0046] The HfO2 layer 416 and the HfN layer 420 can be deposited using an ALD process. The ALD process can correspond to a thermal process using an ammonia (NH3) co-reactant or a plasma process in an NH3, N2, or N2 / H2 gas environment. In some examples (for example, in examples where NH3 is used as a co-reactant), the HfN layer 420 may include residual hydrogen atoms. The residual hydrogen atoms may cause defects during the annealing process, resulting in high leakage current and low thermal stability. Therefore, in some examples, the HfN layer 420 can be treated with a plasma including an oxygen species such as molecular oxygen (O2) or ozone (O3) to reduce the hydrogen content of the HfN layer 420. The oxidation partially oxidizes the HfN layer 420 to reduce the hydrogen content in the HfN layer 420. In this way, the increase in leakage current associated with the HfN layer 420 can be reduced or eliminated. For example, oxidation of the HfN layer can reduce the leakage current by 90% without changing the residual polarization. In Figure 4A In the example shown, no oxidation is performed on the HfN layer 420. Figure 4B In the example shown, oxidation is performed on the HfN layer 420 .

[0047] Reference now Figure 5A and Figure 5B , another exemplary device 500 formed according to the present disclosure is shown. The device 500 includes a substrate (e.g., one or more underlying layers) 504 and an interface layer 508 disposed on the underlying layer 504. A ferroelectric layer 512 including a first HfO2 layer 516, a HfN layer 520, and a second HfO2 layer 524 is formed on the interface layer 508. A top electrode 528 is formed on the ferroelectric layer 512. In some examples, the HfO2 layers 516 and 524 are doped (e.g., with Si, Al, Yt, Zr, La, Gd, Sr, etc.). Figure 5A and Figure 5BAs shown, the HfN layer 420 is disposed between the HfO2 layers 516 and 524. In other examples, multiple HfN layers 420 may be deposited (e.g., alternating with adjacent HfO2 layers). When the HfN layer 420 is deposited between the HfO2 layers 516 and 524, as shown in FIG. Figure 5A and 5B As shown, the remanent polarization increases (e.g., by 25%). Figure 5A In the example shown, no oxidation is performed on the HfN layer 520. Figure 5B In the example shown, oxidation is performed on the HfN layer 520 (e.g., as described above in Figure 4B ).

[0048] Reference now Figure 6 , an exemplary method 600 for forming a ferroelectric HfO2 layer including a HfN layer according to the present disclosure begins at 604. At 608, a substrate is provided. For example, a substrate including one or more underlying layers is arranged on a substrate support in a substrate processing chamber. At 612, an interface layer is deposited on the substrate. The interface layer may include silicon dioxide (SiO2) or silicon oxynitride (SiON), and / or may correspond to a bottom electrode including titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W). The interface layer may be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). At 616, a doped or undoped HfO2 layer is deposited on the interface layer (e.g., using ALD). At 620, a plasma treatment of the HfO2 layer may be optionally performed. For example, the HfO2 layer may be nitrided by a plasma including a nitrogen species.

[0049] At 624, a HfN layer is deposited on the HfO2 layer. For example, the HfN layer can be deposited using atomic layer deposition (ALD). At 628, oxidation is optionally performed on the HfN layer. At 632, the method 600 determines whether to deposit another HfO2 layer. If yes, the method 600 continues to 636. If no, the method 600 continues to 640. At 636, a HfO2 layer is deposited on the HfN layer and optionally treated with plasma. At 644, the method 600 determines whether to deposit another HfN layer. If yes, the method 600 continues to 624. If no, the method 600 continues to 640.

[0050] At 640, a top electrode (e.g., TiN, TaN, or W) is deposited on the HfO2 layer. For example, the top electrode is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). At 648, the substrate, interface layer, HfO2 layer, HfN layer, and top electrode are annealed at a predetermined temperature in the range of 500° C. to 1100° C. (e.g., 800° C. to 1000° C.) to form ferroelectric HfO2. The top electrode may be patterned at 652 (e.g., a mask may be patterned on the top electrode) and etched at 656. Method 600 ends at 660.

[0051] The foregoing description is merely illustrative in nature and is by no means intended to limit the present disclosure, its application or use. The broad teachings of the present disclosure can be implemented in various forms. Therefore, although the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited, because when studying the drawings, the specification and the appended claims, other modifications will become apparent. It should be understood that one or more steps in the method can be performed in different orders (or simultaneously) without changing the principles of the present disclosure. In addition, although each embodiment is described above as having certain features, any one or more of those features described relative to any embodiment of the present disclosure can be implemented in the features of any other embodiment and / or combined with the features of any other embodiment, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and the replacement of one or more embodiments with each other remains within the scope of the present disclosure.

[0052] Various terms are used to describe the spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless the relationship between a first and a second element is explicitly described as "direct," when such a relationship is described in the above disclosure, the relationship can be a direct relationship, in which there are no other intervening elements between the first and second elements, but can also be an indirect relationship, in which there are one or more intervening elements (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B, and C" should be interpreted to mean a logical (A or B or C), using a non-exclusive logical OR, and should not be interpreted to mean "at least one of A, at least one of B, and at least one of C."

[0053] In some implementations, the controller is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or system type, the controller can be programmed to control any process disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0054] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0055] In some implementations, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller for such a purpose may be one or more integrated circuits on a chamber communicating with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0056] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0057] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

Claims

1. A method for forming ferroelectric hafnium oxide (HfO2) for ferroelectric RAM in a substrate processing system, the method comprising: depositing a first HfO2 layer on the substrate; Depositing a HfN layer on the first HfO2 layer; Depositing a second HfO2 layer on the HfN layer, wherein the second HfO2 layer has the same material as the first HfO2 layer; depositing a top electrode on the second HfO2 layer, The first HfO 2 layer, the second HfO 2 layer, and the HfN layer are annealed to form ferroelectric hafnium HfO 2 . The method of claim 1 , further comprising performing oxidation on the HfN layer. 3 . The method of claim 2 , wherein performing the oxidation on the HfN layer comprises performing the oxidation using at least one of molecular oxygen and ozone.

4. The method of claim 1, further comprising nitriding the first HfO2 layer before depositing the HfN layer.

5. The method of claim 4, wherein nitriding the first HfO2 layer comprises generating a plasma using a nitrogen species.

6. The method according to claim 1, wherein: The top electrode includes a material selected from the group consisting of titanium, tantalum, and tungsten.

7. The method of claim 1, further comprising depositing a bottom electrode on the substrate and depositing the first HfO2 layer on the bottom electrode.

8. The method according to claim 1, wherein: The first HfO 2 layer is doped using a dopant species selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr) and / or lanthanum (La).

9. The method according to claim 1, wherein: Annealing the first HfO 2 layer, the second HfO 2 layer, and the HfN layer includes performing a rapid thermal annealing process at a temperature between 500° C. and 1100° C.

10. A system configured to form ferroelectric hafnium oxide (HfO2) for ferroelectric RAM on a substrate in a processing chamber, the system comprising: a gas delivery system configured to supply gas to the process chamber; a radio frequency (RF) generating system configured to generate a plasma within the processing chamber; and a controller configured to control the gas delivery system and the radio frequency generation system to, depositing a first HfO2 layer on the substrate, depositing a HfN layer on the first HfO2 layer, Depositing a second HfO2 layer on the HfN layer, wherein the second HfO2 layer has the same material as the first HfO2 layer; depositing a top electrode on the second HfO2 layer, and The first HfO 2 layer, the second HfO 2 layer, and the HfN layer are annealed to form ferroelectric hafnium HfO 2 .

11. The system according to claim 10, wherein: The controller is also configured to perform oxidation on the HfN layer.

12. The system according to claim 11, wherein: Performing the oxidation on the HfN layer includes performing the oxidation using at least one of molecular oxygen and ozone.

13. The system according to claim 10, wherein: The controller is also configured to nitridate the first HfO 2 layer before depositing the HfN layer.

14. The system of claim 13, wherein nitriding the first HfO2 layer comprises generating a plasma using a nitrogen species.

15. The system according to claim 10, wherein: The top electrode includes a material selected from the group consisting of titanium, tantalum, and tungsten.

16. The system of claim 10, wherein: The controller is also configured to deposit a bottom electrode on the substrate, and deposit the first HfO 2 layer on the bottom electrode.

17. The system according to claim 10, wherein: The first HfO 2 layer is doped with a dopant species selected from the group consisting of silicon (Si), aluminum (Al), yttrium (Y), zirconium (Zr) and / or lanthanum (La).

18. The system of claim 10, wherein annealing the first HfO2 layer, the second HfO2 layer, and the HfN layer comprises performing a rapid thermal annealing process at a temperature between 500 and 1100°C.

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