Semiconductor light emitting element and method for manufacturing the same

Abstract

The present invention provides a semiconductor light-emitting element capable of alleviating multiple peaks in a light-emitting spectrum to form a single peak. The semiconductor light-emitting element according to the present invention is provided with a reflective layer, a first conductive type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light-emitting layer having a light-emitting center wavelength of 1000 to 2200 nm, and a second conductive type cladding layer formed of InGaAsP containing at least In and P in sequence on a substrate, the second conductive type cladding layer being used as a light extraction side, and the surface of the light extraction surface of the second conductive type cladding layer is a rough surface having a surface roughness Ra of 0.03 μm or more and a random concave-convex pattern.

Description

Technical Field

[0001] The present invention relates to a semiconductor light emitting element and a manufacturing method thereof, and in particular to an infrared emitting semiconductor light emitting element. Background Art

[0002] Conventionally, semiconductor light emitting elements that emit infrared light in the infrared region of 750 nm or longer are known. For example, semiconductor light emitting elements that emit infrared light are widely used in applications such as sensors, gas analysis, and surveillance cameras.

[0003] When the emission wavelength of such a semiconductor light-emitting element is set to the near-infrared region of 1000 nm to 2200 nm, an InGaAsP-based III-V semiconductor containing In and P is generally used in the light-emitting layer. Conventionally, when an InGaAsP-based III-V semiconductor layer such as an InP layer is epitaxially grown, an InP substrate is used as a growth substrate in order to lattice match the growth substrate with the InGaAsP-based III-V semiconductor layer containing In and P.

[0004] For example, Patent Document 1 discloses a semiconductor laser with an oscillation wavelength in the 1.3 μm band. The semiconductor laser has a multi-strain quantum well active layer formed on an n-InP substrate, and the multi-strain quantum well active layer has a structure in which InGaAsP strained quantum wells and InGaAsP barrier layers are alternately stacked.

[0005] In addition, Patent Document 2 discloses that an InGaAsP barrier layer and a quantum well layer are provided on an InP substrate, wherein the InGaAsP barrier layer has the same lattice constant as the InP substrate, and the quantum well layer includes InGaAsP having a smaller lattice constant than the InP substrate. 0.3 Ga 0.7 The strain quantum well layer is formed of an As layer and the lattice strain compensation layer is formed of InAs having a larger lattice constant than the InP substrate.

[0006] In the technologies described in Patent Documents 1 and 2, the InP substrate as a growth substrate is directly used as a support substrate for the semiconductor light emitting element. This is because the InP substrate is transparent to light in the near-infrared region and therefore does not hinder light extraction.

[0007] However, in a light-emitting element of a III-V compound semiconductor system containing In and P provided on an InP substrate, the current path is concentrated right below the electrode, and therefore there is a limit to increase in light-emitting output.

[0008] In recent years, as the use of LEDs has become more diverse, semiconductor light-emitting elements that emit long-wavelength light such as infrared light have also been sought to have higher output. Therefore, the present inventors proposed in Patent Document 3 a junction-type semiconductor light-emitting element, which forms a semiconductor stack including an InP-based cladding layer on a growth substrate, then bonds the semiconductor stack to a support substrate and removes the growth substrate.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Laid-Open No. 7-147454

[0012] Patent Document 2: Japanese Patent Application Laid-Open No. 6-237042

[0013] Patent Document 3: Japanese Patent Application Publication No. 2018-6495 Summary of the invention

[0014] Problem that the invention aims to solve

[0015] The present inventors have confirmed that the use of the junction-type semiconductor light-emitting element disclosed in Patent Document 3 can greatly improve the external extraction efficiency. However, the present inventors have also confirmed for the first time that in the luminescence spectrum of the junction-type semiconductor light-emitting element, in addition to the luminescence peak of the luminescence center wavelength with the maximum luminescence intensity, there are also multiple luminescence peaks (hereinafter referred to as "multiple peaks" in this specification). Here, the luminescence peak (hereinafter sometimes abbreviated as "peak") refers to the point where the slope reaches 0 and the maximum value is obtained when the slope of the change of the vertical axis (luminescence intensity) relative to the change of the horizontal axis (wavelength) is taken in the luminescence spectrum. In addition, the above peaks do not include peaks whose relative intensity relative to the luminescence intensity of the luminescence peak at the luminescence center wavelength is less than 0.1.

[0016] It should be noted that in the case of a non-junction type semiconductor light emitting element based on the prior art, there is usually no peak other than the luminescence peak of the luminescence center wavelength in the luminescence spectrum (there is only a luminescence peak of the luminescence center wavelength, hereinafter referred to as a "single peak" in this specification). In a semiconductor light emitting element that emits the above-mentioned multi-peak radiated light, there are luminescence peaks with different wavelengths having a relative intensity of 0.1 or more relative to the luminescence intensity of the luminescence peak of the luminescence center wavelength, so there is a risk of causing a problem when such a semiconductor light emitting element is used for sensor applications, etc.

[0017] Therefore, an object of the present invention is to provide a semiconductor light emitting element and a method for manufacturing the same, which can alleviate multiple peaks in a light emission spectrum of a junction type semiconductor light emitting element having a cladding layer formed of InGaAsP containing at least In and P and make it a single peak.

[0018] Solutions for solving problems

[0019] The inventors of the present invention have conducted in-depth research on ways to solve the above-mentioned problems. It can be considered that when infrared light with a wavelength of 1000 to 2200 nm radiated from the light-emitting layer is incident on the cladding on the light extraction side, when the cladding is InP, since the refractive index of InP is about 3.2 for infrared light, when light is directly extracted from the cladding toward the atmosphere (refractive index 1), most of the light obliquely incident on the interface is reflected and returned to the inner side of the semiconductor layer. On the other hand, in a semiconductor light-emitting element having a reflective layer between the light-emitting layer and the substrate, the infrared light radiated from the light-emitting layer toward the substrate is reflected by the reflective layer, and the reflected light based on the reflection is incident on the cladding on the light extraction side via the light-emitting layer. Here, the total thickness of the semiconductor layer in the semiconductor light-emitting element is about several μm to 15 μm, which falls within the range of the coherence length of infrared light and is prone to interference. It should be noted that the coherence length of light with a central emission wavelength of 1300nm and a half-value width of 100nm is 16.9μm, and the coherence length of light with a central emission wavelength of 1460nm and a half-value width of 100nm is 21.3μm. For this reason, the present inventors considered that multiple peaks may be observed in the emission spectrum because the reflected light at the interface of the cladding on the light extraction side interferes with the reflected light based on the reflective layer. In addition, this phenomenon also occurs when light is extracted from the cladding toward the atmosphere with the help of a protective layer formed by a dielectric having a refractive index less than InP. Therefore, the present inventors thought of roughening the surface of the light extraction surface of the cladding, and found that the multiple peaks could be eliminated by roughening, thereby completing the present invention.

[0020] That is, the gist of the present invention is as follows.

[0021] (1) A semiconductor light emitting element, characterized in that a reflective layer, a first conductivity type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a light emission center wavelength of 1000 to 2200 nm, and a second conductivity type cladding layer formed of InGaAsP containing at least In and P are provided in this order on a substrate, wherein the second conductivity type cladding layer is used as a light extraction side.

[0022] The light extraction surface of the second conductivity type cladding layer is a rough surface having a surface roughness Ra of 0.03 μm or more and a random concavo-convex pattern.

[0023] (2) A semiconductor light emitting element, characterized in that a metal bonding layer, a reflective layer, a first conductive type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a central wavelength of 1000 to 2200 nm, and a second conductive type cladding layer formed of InGaAsP containing at least In and P are sequentially provided on a supporting substrate, wherein the second conductive type cladding layer is used as a light extraction side, and the surface of the light extraction surface of the second conductive type cladding layer is a rough surface having a surface roughness Ra of not less than 0.03 μm and a random concave-convex pattern.

[0024] (3) The semiconductor light emitting element according to (1) or (2) above, wherein the light emission spectrum is a single peak.

[0025] (4) The semiconductor light emitting element according to any one of (1) to (3) above, wherein a skewness Rsk of a surface of the light extraction surface is not less than -1.

[0026] (5) The semiconductor light emitting element according to any one of (1) to (3) above, wherein a protective film is further provided on the light extraction surface.

[0027] (6) The semiconductor light emitting element according to (5), wherein the thickness of the protective film is greater than or equal to 100 nm and less than or equal to 700 nm, and the surface roughness Ra of the surface of the protective film is greater than or equal to 0.02 μm and the skewness Rsk is greater than or equal to −1.

[0028] (7) The semiconductor light emitting element according to (5) or (6) above, wherein the protective film includes at least one selected from the group consisting of silicon oxide, silicon nitride, ITO, and AlN.

[0029] (8) A method for manufacturing a semiconductor light emitting element, characterized in that the method comprises forming a reflective layer, a first conductivity type cladding layer composed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a light emission center wavelength of 1000 to 2200 nm, and a second conductivity type cladding layer composed of InGaAsP containing at least In and P in sequence on a substrate, and using the second conductivity type cladding layer as a light extraction side of the semiconductor light emitting element, the method comprising:

[0030] The roughening treatment step is to roughen the surface of the light extraction surface of the second conductivity type cladding layer after forming the second conductivity type cladding layer, so as to form a rough surface having a surface roughness Ra of 0.03 μm or more and a random concavo-convex pattern.

[0031] (9) The method for manufacturing a semiconductor light emitting element according to (8), wherein in the roughening step, the surface of the light extraction surface is roughened so that a skewness Rsk of the surface becomes greater than or equal to -1.

[0032] (10) A method for manufacturing a semiconductor light emitting element, characterized in that it comprises:

[0033] Semiconductor layer forming step: sequentially forming a III-V compound semiconductor etching stopper layer containing In, Ga and As, a second conductivity type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a light emission center wavelength of 1000 to 2200 nm, and a first conductivity type cladding layer formed of InGaAsP containing at least In and P on a growth substrate;

[0034] A reflection layer forming step: forming a reflection layer on the first conductive type cladding layer for reflecting light emitted by the semiconductor light emitting layer;

[0035] Bonding step: bonding the support substrate to the reflective layer via the metal bonding layer;

[0036] Substrate removal step: removing the aforementioned growth substrate; and

[0037] Roughening step: After the substrate removal step, the surface of the light extraction surface of the second conductivity type cladding layer is roughened to form a rough surface having a surface roughness Ra of 0.03 μm or more and a random concavo-convex pattern.

[0038] (11) The method for manufacturing a semiconductor light emitting element according to (10) above, wherein in the roughening step, the surface of the light extraction surface is roughened so that a skewness Rsk of the surface becomes greater than or equal to -1.

[0039] (12) The method for manufacturing a semiconductor light-emitting element according to (10) or (11) above, further comprising a top surface electrode forming step: in a top surface electrode forming region of the second conductive type cladding layer other than the aforementioned light extraction surface, a second conductive type electrode is formed on the aforementioned second conductive type cladding layer via the aforementioned etching stop layer.

[0040] Effects of the Invention

[0041] According to the present invention, a semiconductor light emitting element having a junction type semiconductor light emitting element including a cladding layer formed of InGaAsP containing at least In and P, capable of reducing multiple peaks in a light emission spectrum to a single peak, and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor light emitting element according to one embodiment of the present invention.

[0043] Figure 2This is a schematic cross-sectional view illustrating a semiconductor light emitting element according to a preferred embodiment of the present invention.

[0044] Figure 3 (A) to (C) are schematic cross-sectional views of a process for producing a semiconductor light emitting device according to one embodiment of the present invention.

[0045] Figure 4 (A)~(C) are continuous Figure 3 A schematic cross-sectional view of a manufacturing process of a semiconductor light emitting element according to one embodiment of the present invention.

[0046] Figure 5 (A) and (B) are continuations of Figure 4 A schematic cross-sectional view of a manufacturing process of a semiconductor light emitting element according to one embodiment of the present invention.

[0047] Figure 6 (A) and (B) are continuations of Figure 5 A schematic cross-sectional view of a manufacturing process of a semiconductor light emitting element according to one embodiment of the present invention.

[0048] Figure 7 It is a schematic cross-sectional view of a semiconductor light emitting element manufactured according to one embodiment of the present invention.

[0049] Figure 8 This is a schematic cross-sectional view for explaining a suitable mode of a dielectric layer and the vicinity of a contact portion of a semiconductor light emitting element according to one embodiment of the present invention.

[0050] Fig. 9 (A) to (D) are schematic cross-sectional views for explaining a suitable mode of a roughening treatment step in a manufacturing process of a semiconductor light emitting element according to one embodiment of the present invention.

[0051] Fig.10 (A) is a top schematic diagram showing the pattern of the ohmic electrode portion in Experimental Example 1, and (B) is a plan schematic diagram showing the pattern of the top surface electrode in Experimental Example 1.

[0052] Fig.11 1 is a schematic plan view of a mask pattern used in Comparative Example 3.

[0053] Fig.12 (A) to (D) are schematic cross-sectional views for explaining the production process of the roughening treatment in Comparative Example 3.

[0054] Fig.13 (A)~(C) are followed by Fig.12 A schematic cross-sectional view illustrating the production process of the roughening treatment in Comparative Example 3.

[0055] Fig.14A This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 1.

[0056] Fig. 14B This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 2.

[0057] Fig. 14C This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 3.

[0058] Fig.14D This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 4.

[0059] Fig.14E This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 5.

[0060] Fig.14F This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 6.

[0061] Figure 14G This is a diagram showing the measurement results of the surface shape of the n-type cladding layer in Example 7.

[0062] Fig.15A This is a diagram showing the measurement results of the surface shape of the n-type cladding layer of Comparative Example 2.

[0063] Fig. 15B 1 is a diagram showing the measurement results of the surface shape of the n-type cladding layer of Comparative Example 3.

[0064] Fig. 15C 1 is a diagram showing the measurement results of the surface shape of the n-type cladding layer of Comparative Example 4.

[0065] Fig.15D 1 is a diagram showing the measurement results of the surface shape of the n-type cladding layer of Comparative Example 5.

[0066] Fig.15E 1 is a diagram showing the measurement results of the surface shape of the n-type cladding layer of Comparative Example 6.

[0067] Fig.15F 1 is a diagram showing the measurement results of the surface shape of the n-type cladding layer of Comparative Example 7.

[0068] Fig.16 3 is a diagram showing the correspondence between the surface roughness Ra and the skewness Rsk in Experimental Example 1.

[0069] Fig.17A This is a diagram showing the emission spectrum of Example 1.

[0070] Fig. 17B This is a diagram showing the emission spectrum of Example 7.

[0071] Fig.18A 3 is a graph showing the emission spectrum of Comparative Example 1.

[0072] Fig.18B 3 is a graph showing the emission spectrum of Comparative Example 2.

[0073] Fig. 18C 3 is a graph showing the emission spectrum of Comparative Example 3.

[0074] Fig.19A 3 is a laser microscope image showing the three-dimensional surface shape of the n-type cladding layer of Example 1.

[0075] Fig.19B 3 is a laser microscope image showing the three-dimensional surface shape of the n-type cladding layer of Comparative Example 2.

[0076] Fig. 20 3 is a graph showing the correlation between the skewness Rsk and the skewness Ssk in Experimental Example 2. DETAILED DESCRIPTION

[0077] Before describing the embodiments of the present invention, the following aspects will be described in advance. First, in the present specification, the case where the composition ratio is not explicitly stated and is abbreviated as "InGaAsP" refers to any compound in which the chemical composition ratio of the group III element (the sum of In and Ga) and the group V element (the sum of As and P) is 1:1, and the ratio of In to Ga as the group III element and the ratio of As to P as the group V element are respectively uncertain. At this time, the case where the group III element does not contain either In or Ga is included, and the case where the group V element does not contain either As or P is included. Among them, in the case of InGaAsP which is clearly stated as "at least containing In and P", it is considered that the group III element contains more than 0% and less than 100% In, and the group V element contains more than 0% and less than 100% P. In addition, the case where it is recorded as "InGaP" means that the above-mentioned "InGaAsP" does not contain As except for the inevitable mixing in the manufacturing process, and the case where it is recorded as "InGaAs" means that the above-mentioned "InGaAsP" does not contain P except for the inevitable mixing in the manufacturing process. Similarly, the case where "InAsP" is recorded means that the above-mentioned "InGaAsP" does not contain Ga except for the inevitable mixing during the production, and the case where "GaAsP" is recorded means that the above-mentioned "InGaAsP" does not contain In except for the inevitable mixing during the production. Furthermore, the case where "InP" is recorded means that the above-mentioned "InGaAsP" does not contain Ga and As except for the inevitable mixing during the production. It should be noted that the composition ratio of each component such as InGaAsP and InGaAs can be measured by photoluminescence measurement and X-ray diffraction measurement. In addition, the "inevitable mixing during the production" mentioned here refers to: in addition to the inevitable mixing in the production equipment using the raw material gas, the diffusion phenomenon of atoms at the interface of each layer accompanied by the crystal growth and the subsequent heat treatment.

[0078] In addition, in this specification, a layer that functions as a p-type layer electrically is referred to as a p-type layer, and a layer that functions as an n-type layer electrically is referred to as an n-type layer. On the other hand, when no specific impurities such as Zn, S, Sn, C, P, Ga, As, Si, Al are actively added and the layer does not function as a p-type or n-type layer electrically, it is referred to as "i-type" or "undoped". Undoped InGaAsP layers may contain unavoidable impurities introduced during the manufacturing process. Specifically, when the carrier density is low (e.g., less than 4×10 16 / cm 3 ) are considered as “undoped” in this specification. In addition, the values ​​of the impurity concentrations such as Zn and Sn are based on SIMS analysis.

[0079] In addition, the thickness of each layer formed can be measured as a whole using an optical interference film thickness meter. Furthermore, the thickness of each layer can be calculated by cross-sectional observation of the growth layer based on an optical interference film thickness meter and a transmission electron microscope. In addition, in the case where the thickness of each layer is small, such as in a superlattice structure, TEM-EDS can be used to measure the thickness. It should be noted that in the cross-sectional view, when a specified layer has an inclined surface, the thickness of the layer uses the maximum height of the flat surface of the layer directly below the layer.

[0080] The surface roughness Ra used in this specification represents the arithmetic mean roughness (μm) in the measured distance. In addition, the skewness Rsk is a value representing the symmetry of the hills and valleys with the average line as the center. When Rsk is zero, it is symmetrical up and down relative to the average line (normal distribution). If it is positive, it means that it is offset to the lower side (valley side) relative to the average line, and if it is negative, it means that it is offset to the upper side (hill side) relative to the average line. The definitions of surface roughness Ra and skewness Rsk are based on ISO4287-1997. Furthermore, the surface roughness Sa used in this specification is a value representing the arithmetic mean roughness (μm) in the same way as the above-mentioned surface roughness Ra, which is based on ISO 25178. Furthermore, the skewness Ssk is a value representing the symmetry of the hills and valleys with the average line as the center in the same way as the above-mentioned skewness Rsk, which is based on ISO 25178. The surface roughness Ra and the skewness Rsk are measured values ​​obtained by a two-dimensional profilometer method based on ISO 4287-1997, whereas the surface roughness Sa and the skewness Ssk are measured values ​​obtained by a three-dimensional surface property method based on ISO 25178.

[0081] In the method for measuring the surface roughness Ra and the skewness Rsk, a stylus-type height difference meter (for example, a contact height difference meter "P-6" manufactured by Tencor) can be used for measurement. The shape of the needle used is set to a stylus tip radius of 2 μm, a stylus pressure of 2 mg, a scanning speed of 2 μm / sec, and a sampling frequency of 50 Hz. The measuring distance (reference length) is set to 200 μm. In addition, in the method for measuring the surface roughness Sa and the skewness Ssk, a non-stylus-type shape analysis laser microscope (VK-X1000 / 1100 manufactured by KEYENCE) can be used for measurement. For the measurement conditions in the embodiment (Experimental Example 2) of this specification, the lens magnification is set to 150 times and the number of pixels is set to 2048×1536.

[0082] In addition, in this specification, "random rough surface" does not include the following situation: in the result of measuring the surface of the light extraction side using the above-mentioned contact height difference meter, a shape with periodic grooves was observed, and the surface roughness Ra of the portion without grooves was less than 0.010μm. It should be noted that the surface shape with a surface roughness Ra of less than 0.010μm of the portion without grooves belongs to the surface shape obtained by etching the surface and forming a recess after periodically forming a mask with holes on the surface of the light extraction side. Even if the surface shape of the light extraction side formed in this way is applied to the light-emitting element, the dispersion of the light reflection angle based on the surface shape is sometimes insufficient, and sometimes the effect of the present invention, that is, the effect of becoming a single peak, cannot be fully obtained.

[0083] (Semiconductor light emitting element 1)

[0084] like Figure 1 As shown in the figure, the semiconductor light emitting element 1 according to one embodiment of the present invention is a semiconductor light emitting element in which a first conductive type cladding layer 3a, a semiconductor light emitting layer 3c, and a second conductive type cladding layer 3b are sequentially provided on a substrate 8, and the second conductive type cladding layer 3b is used as a light extraction side. In addition, the semiconductor light emitting element 1 further includes a reflective layer 6 between the supporting substrate 8 and the first conductive type cladding layer 3a for reflecting light emitted by the semiconductor light emitting layer 3c.

[0085] Furthermore, the first conductivity type cladding layer 3a and the second conductivity type cladding layer 3b are InGaAsP containing at least In and P, and InP is most preferred. In addition, the semiconductor light emitting layer 3c is a light emitting layer that emits light with a central wavelength of 1000 to 2200 nm, and is preferably a layer formed of InGaAsP containing at least In and P. Furthermore, in the semiconductor light emitting element 1, the surface of the light extraction surface of the second conductivity type cladding layer 3b is a rough surface with a surface roughness Ra of more than 0.03 μm and a random concave-convex pattern. It should be noted that in the semiconductor light emitting element 1, the second conductivity type cladding layer 3b can form a top surface electrode including a pad portion 9a and a wiring portion 9b, and can further form a back electrode on the back side of the supporting substrate (the back electrode is not shown).

[0086] In the semiconductor light emitting element 1, the light emitted from the semiconductor light emitting layer 3c is roughly divided into light L1 toward the second conductive type cladding layer 3b and light L2 toward the first conductive type cladding layer 3a. In this embodiment, the surface of the second conductive type cladding layer 3b that emits L1 and L2 to the outside (mainly the atmosphere) is referred to as the "light extraction surface" except for the top surface electrodes 9a and 9b. That is, Figure 1As shown in the figure, the "light extraction surface" in this embodiment refers to: a surface that emits light to the outside in the same surface (top surface) as the surface forming the top surface electrode. It should be noted that light is also extracted from the side of the semiconductor light emitting element 1. However, the light extraction from the side has little effect on the occurrence of multiple peaks, so the side may or may not be roughened. It should be noted that in order to increase the light output, it is preferred to roughen the side as well.

[0087] The "light extraction surface" of the second conductive type cladding layer 3b of the semiconductor light emitting element 1 is a rough surface. The surface roughness Ra of the surface of the light extraction surface is greater than 0.03 μm. In addition, the skewness Rsk is more preferably greater than -1. More preferably, Ra ≥ 0.04 μm and Rsk ≥ -0.5 are provided. Top surface electrodes 9a and 9b are provided on the flat portion of the surface of the second conductive type cladding layer 3b.

[0088] According to the experiments of the inventors, it was experimentally confirmed that if the surface of the light extraction surface is a regular rough surface and the concave-convex pattern is not random, the multi-peaks in the luminescent spectrum cannot be reduced and become a single peak. More specifically, it was confirmed that even if the skewness Rsk is positive, if the depth of the concave-convex is shallow and the surface roughness Ra is less than 0.03μm, it cannot become a single peak. Therefore, the surface roughness Ra is preferably greater than 0.03μm, and in order to become a single peak, it is more preferably greater than 0.04μm. In addition, it is known that even if the surface roughness Ra is greater than 0.03μm, if the skewness Rsk is less than -1 (Rsk<-1) and a large number of flat surfaces or nearly flat parts are formed on the top of the light extraction side, the multi-peaks in the luminescent spectrum cannot be reduced and become a single peak. Therefore, the skewness Rsk is preferably -1 to 0 or positive (ie, Rsk≥-1). More preferably, it is -0.5 to 0.5 (ie, -0.5≤Rsk≤0.5).

[0089] In addition, the inventors' experiments have made it clear that the rough surface shape suitable for improving the output of the light-emitting element is not necessarily the same as the rough surface shape suitable for reducing multiple peaks. The rough surface shape suitable for reducing multiple peaks is the case where the surface roughness Ra is greater than 0.03 μm and the skewness Rsk is greater than -1.0. The rough surface shape that is also effective in reducing multiple peaks and improving light-emitting output is the case where the surface roughness Ra is greater than 0.04 μm and the skewness Rsk is greater than -0.5 and less than 0.5. It should be noted that the upper limit of the surface roughness Ra is at least less than the thickness of the second conductive type cladding to be roughened, for example, 4 μm. There is no particular limitation on the upper limit of the skewness Rsk suitable for reducing multiple peaks, for example, 2. In addition, based on the same reasons as above, the surface roughness Sa of the surface of the light extraction surface is preferably greater than 0.05 μm. Furthermore, the skewness Ssk of the surface of the light extraction surface is preferably greater than -0.5.

[0090] It should be noted that when the conductivity type of the first conductivity type cladding layer 3a is set to n type, the second conductivity type cladding layer 3b is set to p type. Conversely, when the conductivity type of the first conductivity type cladding layer 3a is set to p type, the second conductivity type cladding layer 3b is set to n type.

[0091] Although not shown in the figure, it is also a preferred embodiment to leave the etching stopper layer between the second conductivity type cladding layer 3 b and the top surface electrode including the pad portion 9 a and the wiring portion 9 b .

[0092] In addition, if Figure 2 As shown in FIG. 1 , the semiconductor light emitting element 1 preferably further includes a protective film PF1 on the second conductive type cladding layer 3b in addition to the top surface electrode (pad portion 9a and wiring portion 9b). The protective film PF1 can be made of SiO2, SiN, ITO, AlN, etc., and is particularly preferably formed of SiO2. The protective film PF1 has the effect of suppressing the refractive index difference between the second conductive type cladding layer 3b and the air and improving light extraction.

[0093] Furthermore, although the reason is unclear, it is known that if a protective film is formed after forming the "random rough surface" based on the present invention, the effect of suppressing the output reduction caused by continuous power-on is great. For example, if a protective film is formed on a semiconductor light-emitting element whose luminous output after continuous power-on at 100mA for 1000 hours is 94% relative to the initial luminous output (hereinafter referred to as "luminous output maintenance rate"), the output maintenance rate can be increased to 99-100% (refer to Experimental Example 3 described later). On the other hand, in the case of a rough surface that is not formed and does not meet the conditions of the present invention, the luminous output maintenance rate is 94%. Even if a protective film of the same thickness is formed on them, it is only about 97%.

[0094] The thickness of the protective film PF1 is preferably 100 nm or more, more preferably 215 nm or more. The thickness of the protective film PF1 is preferably 700 nm or less, more preferably 650 nm or less. When the thickness of PF1 is within the above range, light extraction in the wavelength range of 1000 to 2200 nm can be improved.

[0095] When the protective film PF1 is formed, the protective film PF1 is basically covered corresponding to the surface unevenness of the second conductive type cladding 3b that serves as the base. In the case of using a device that precipitates a thin film on the surface such as a plasma CVD method, by covering with the protective film PF1, the unevenness of the protective film PF1 is slightly smoother than the unevenness of the second conductive type cladding 3b. If the surface state including the protective film PF1 is measured, the surface roughness Ra sometimes becomes smaller. Therefore, as the surface roughness including the protective film, it is preferred that the surface roughness Ra is 0.02μm or more (Ra≥0.02μm) and the skewness Rsk is -1 or more (Rsk≥-1).

[0096] It should be noted that if Figure 2 As shown, a protection film PF2 may be provided to protect the side surfaces of the first conductivity type cladding layer 3a, the semiconductor light emitting layer 3c, and the second conductivity type cladding layer 3b. The material of the protection film PF2 may be the same as or different from that of the protection film PF1.

[0097] In addition, you can replace Figure 1 , 2 The substrate 8 of the semiconductor light emitting element 1 shown in the figure is a semiconductor light emitting element of a junction type in which a metal junction layer is provided on the surface of the supporting substrate and the metal junction layer is bonded to the reflective layer.

[0098] Hereinafter, the details of each configuration of the semiconductor light emitting element 1 according to the present invention will be described by sequentially describing each step for manufacturing a junction-type semiconductor light emitting element 100 according to a suitable embodiment of the present invention. It should be noted that the correspondence between each configuration of the semiconductor light emitting element 1 and each configuration of the semiconductor light emitting element 100 is as follows. That is, the first conductive type cladding layer 3a is equivalent to the p-type cladding layer 37, the semiconductor light emitting layer 3c is equivalent to the semiconductor light emitting layer 35, the second conductive type cladding layer 3b is equivalent to the n-type cladding layer 31, the reflective layer 6 is equivalent to the reflective layer 60, and the support substrate 8 is equivalent to the support substrate 80.

[0099] (Method of Manufacturing Semiconductor Light Emitting Element 100)

[0100] The manufacturing method of the semiconductor light emitting element 100 according to one embodiment of the present invention preferably includes the following semiconductor layer forming step, contact layer step, dielectric layer forming step, reflective layer forming step, bonding step, substrate removing step and roughening step, which will be described in detail later.

[0101] First, in the semiconductor layer process, a semiconductor stack 30 ( Figure 3 (A), (B)).

[0102] In the contact portion forming step, first, a contact layer 41 ( Figure 3 Next, an ohmic metal portion 43 is formed on a portion of the contact layer 41, and an exposed region E1 ( Figure 4 (A)). Then, the contact layer 41 in the exposed area E1 is removed until the surface of the semiconductor stack 30 is exposed, thereby forming a contact portion 40 including an ohmic metal portion 43 and a contact layer 41a, and forming an exposed surface E2 ( Figure 4 (B)).

[0103] In the dielectric layer forming step, a dielectric layer 50 ( Figure 4 In the reflection layer forming step, a reflection layer 60 ( Figure 5 In the bonding step, the support substrate 80 having the metal bonding layer 70 on its surface is bonded to the reflective layer 60 with the metal bonding layer 70 interposed therebetween ( Figure 5 Next, in the substrate removal step, the growth substrate 10 ( Figure 6 (A)).

[0104] After that, after masking the region where the top surface electrode is to be formed, a roughening process is performed to form a plurality of concave and convex portions 31C on the surface of the p-type cladding layer 31 ( Figure 6 (B)). Thereafter, a process of forming a top surface electrode on the second conductive type cladding layer is performed. In this way, a semiconductor light emitting element 100 according to a suitable embodiment of the present invention can be manufactured. It should be noted that the formation of the top surface electrode can be performed before the roughening treatment process. In this way, a semiconductor light emitting element 100 according to a suitable embodiment of the present invention can be manufactured ( Figure 7 ). The following describes the details of each process in sequence.

[0105] <Semiconductor Layer Formation Step>

[0106] In the semiconductor layer forming step, a semiconductor stack 30 ( Figure 3 (A), (B)).

[0107] In the semiconductor layer forming process, Figure 3As shown in (A), first, a growth substrate 10 is prepared. Since a p-type cladding layer 37 and an n-type cladding layer 31 are formed in this embodiment, an InP substrate is preferably used as the growth substrate 10. It should be noted that as the InP substrate, a commonly available n-type InP substrate, a high-resistance (also called semi-insulating) InP substrate (for example, an Fe-doped, specific resistance of 1×10 6 Ω·cm or more), or a p-type InP substrate. Hereinafter, for convenience of description, a preferred embodiment using an n-type InP substrate as the growth substrate 10 will be described.

[0108] Next, a III-V compound semiconductor etching stopper layer 20 is formed on the growth substrate 10. As described above, the III-V compound semiconductor etching stopper layer 20 only needs to have etching selectivity with respect to the growth substrate 10. For an InP substrate, for example, InGaAs can be used for the etching stopper layer. In addition, InGaAsP can also be used for the etching stopper layer. The III-V compound semiconductor etching stopper layer 20 can be used when the growth substrate 10 is removed by etching in the substrate removal process. When an n-type InP substrate is used as the growth substrate 10, it is preferred that the III-V compound semiconductor etching stopper layer 20 be set to an n-type so that the conductivity type matches the growth substrate. When InGaAs is used for the III-V compound semiconductor etching stopper layer 20, in order to lattice match the n-type InP substrate with InGaAs, it is preferred that the In composition ratio in the III-group element be set to 0.3 to 0.7, and it is more preferred to use InGaAs having an In composition ratio of 0.5 to 0.6.

[0109] Next, a semiconductor stack 30 is formed on the III-V compound semiconductor etching stopper layer 20, in which an n-type cladding layer 31, a semiconductor light-emitting layer 35, and a p-type cladding layer 37 are sequentially formed. The semiconductor light-emitting layer 35 is sandwiched by the p-type cladding layer 37 and the n-type cladding layer 31, and therefore, it is preferably a layer formed of an InGaAsP-based III-V compound semiconductor containing at least In and P. The semiconductor stack 30 can be made into a double heterogeneous (DH) structure or a multi-quantum well (MQW) structure in which the semiconductor light-emitting layer 35 is sandwiched by the p-type cladding layer 37 and the n-type cladding layer 31. In order to improve the light output by suppressing crystal defects, the semiconductor light-emitting layer 35 is more preferably provided with a multi-quantum well structure. The multi-quantum well structure can be formed by a structure in which the well layer 35W and the barrier layer 35B are alternately repeated, and the well layer 35W can be made of InGaAsP, and preferably the barrier layer 35B is made of InGaAsP or InP having a band gap larger than the well layer 35W. By providing such a semiconductor stack 30, the emission wavelength of the semiconductor light emitting element 100 can be set to a desired wavelength in the near-infrared region. For example, by changing the composition of the InGaAsP series III-V compound, the emission peak wavelength can be set to 1000 to 1650 nm. In the case of an MQW structure, by adjusting the composition difference between the well layer and the barrier layer on the basis of the composition change of the InGaAsP series III-V compound, the well layer can be strained, so that the emission peak wavelength can be set to 1000 to 1900 nm. Furthermore, it is also possible to apply strain to set it to 1000 to 2200 nm. In addition, the component composition of the well layer 35W is shown as In xw Ga 1-xw As yw P 1-yw When , it can be set to 0.5≤xw≤1 and 0.5≤yw≤1, and preferably set to 0.6≤xw≤0.8 and 0.3≤yw≤1.

[0110] The thickness of the semiconductor stack 30 as a whole is not limited, and can be set to, for example, 2 μm to 15 μm. In addition, the thickness of the p-type cladding layer 31 is also not limited, and can be set to, for example, 1 μm to 5 μm. Furthermore, the thickness of the semiconductor light-emitting layer 35 is also not limited, and can be set to, for example, 100 nm to 1000 nm. In addition, the thickness of the n-type cladding layer 31 is also not limited, and can be set to, for example, 0.8 μm to 10 μm. When the semiconductor light-emitting layer 35 has a quantum well structure, the thickness of the well layer 35W can be set to 3 nm to 15 nm, and the thickness of the barrier layer 35B can be set to 5 to 15 nm, and the combined value of the two can be set to 3 to 50.

[0111] In addition, the semiconductor stack 30 preferably has a p-type cap layer 39 formed of InGaAsP containing at least In and P on the p-type cladding layer 37. By providing the p-type cap layer 39, the lattice mismatch can be alleviated. The thickness of the p-type cap layer 39 is not limited and can be set to, for example, 50 to 200 nm. In the following embodiments, for convenience of description, the outermost layer of the semiconductor stack 30 is described as the p-type cap layer 39, but the p-type cap layer 39 is an arbitrary structure, so, for example, the outermost layer of the semiconductor stack 30 can also be set to the p-type cladding layer 37.

[0112] It should be noted that, although not shown in the figure, the semiconductor stack 30 preferably also has an i-type InP spacer between the n-type cladding layer 31 and the semiconductor light-emitting layer 35, and between the semiconductor light-emitting layer 35 and the p-type cladding layer 37. By providing an i-type InP spacer, diffusion of dopants can be prevented. It should be noted that the thickness of the i-type InP spacer is not limited and can be set to, for example, 50 to 400 nm. In addition, the semiconductor stack 30 can further have an n-type InGaAsP layer having a different composition ratio from the III-V compound semiconductor etching stop layer 20 between the n-type cladding layer 31 and the III-V compound semiconductor etching stop layer 20.

[0113] Here, each layer of the semiconductor stack 30 can be formed by epitaxial growth, for example, by a known thin film growth method such as an organic metal vapor phase growth (MOCVD: Metal Organic Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a sputtering method, etc. For example, by using trimethyl indium (TMIn) as an In source, trimethyl gallium (TMGa) as a Ga source, arsine (AsH3) as an As source, and phosphine (PH3) as a P source in a prescribed mixing ratio, and using a carrier gas to make these raw material gases undergo vapor phase growth, an InGaAsP layer can be formed with a desired thickness according to the growth time. It should be noted that other InGaAsP layers to be epitaxially grown, such as the III-V compound semiconductor etching stop layer 20, can also be formed by the same method. When each layer is doped to p-type or n-type, a gas as a doping source can be further used as desired.

[0114] <Contact Portion Forming Step>

[0115] In the contact portion forming step, first, a contact layer 41 ( Figure 3 (C)). For example, Figure 3As shown in (C), a p-type contact layer 41 can be formed on the p-type cap layer 39. The p-type contact layer 41 is a layer that contacts the ohmic metal portion 43 and is sandwiched between the ohmic metal portion 43 and the semiconductor stack 30. It can be any composition as long as the contact resistance between the ohmic metal portion 43 and the semiconductor stack 30 is smaller than that of the semiconductor stack 30. For example, a p-type InGaAs layer can be used. The thickness of the contact layer 41 is not limited, and can be set to, for example, 50nm to 200nm.

[0116] Next, an ohmic metal portion 43 is formed on a portion of the contact layer 41, and an exposed region E1 ( Figure 4 (A)). The ohmic metal part 43 can be formed by dispersing it into an island shape in a prescribed pattern. When a p-type InGaAs layer is used as the p-type contact layer 41, as the ohmic metal part 43, for example, Au, AuZn, AuBe, AuTi, etc. can be used, and their stacked structure is also preferably used. For example, Au / AuZn / Au can be made into the ohmic metal part 43. The thickness (or total thickness) of the ohmic metal part 43 is not limited, and can be set to, for example, 300 to 1300nm, and more preferably 350nm to 800nm.

[0117] Here, for example, an anti-etching pattern is formed on the surface of the contact layer 41, the ohmic metal portion 43 is vapor-deposited, and the anti-etching pattern is peeled off, so that the exposed area E1 can remain on the surface of the contact layer 41. Alternatively, a predetermined metal layer may be formed on the entire surface of the contact layer 41, and a mask may be formed on the metal layer to perform etching, etc., to form the ohmic metal portion 43. In any case, Figure 4 As shown in (A), the ohmic metal portion 43 is formed on a portion of the contact layer 41 , and a surface not in contact with the ohmic metal portion 43 , ie, an exposed region E1 is formed on the surface of the contact layer 41 .

[0118] It should be noted that the shape of the ohmic metal portion 43 may be as follows: Figure 4 Although the ohmic metal portion 43 is trapezoidal in cross-sectional view as shown in (A), this is merely a schematic illustration. The shape of the ohmic metal portion 43 may be rectangular in cross-sectional view or may have curved corners.

[0119] Furthermore, in the contact portion forming step, the contact layer 41 in the exposed region E1 is removed until the surface of the semiconductor stack 30 is exposed, thereby forming a contact portion 40 including an ohmic metal portion 43 and a contact layer 41a, and forming an exposed surface E2 ( Figure 4(B)). That is, the contact layer 41 except for the previously formed ohmic metal portion 43 is etched until the surface of the outermost layer of the semiconductor stack 30, that is, the p-type cap layer 39, is exposed to form the contact layer 41a. For example, a resist mask is formed on the ohmic metal portion 43 and its vicinity (about 2 to 5 μm), and the exposed area E1 of the contact layer 41 is wet-etched using a tartaric acid-hydrogen peroxide system or the like. In addition, wet etching can also be performed using an inorganic acid-hydrogen peroxide system and an organic acid-hydrogen peroxide system etching solution. In addition, when forming the exposed area E1, a mask is formed on the above-mentioned specified metal layer, and etching can be performed continuously when the ohmic metal portion 43 is formed by etching.

[0120] It should be noted that the thickness of the contact portion 40 corresponds to the total thickness of the contact layer 41 ( 41 a ) and the ohmic metal portion 43 , and can be set to 350 nm to 1500 nm, and more preferably 400 nm to 1000 nm.

[0121] <Dielectric Layer Formation Step>

[0122] In the dielectric layer forming step, a dielectric layer 50 ( Figure 4 (C)). Such a dielectric layer 50 can be formed, for example, as follows.

[0123] First, a dielectric layer is formed on the entire surface of the semiconductor stack 30 in such a manner as to cover the semiconductor stack 30 and the contact portion 40. As a film forming method, a known method such as a plasma CVD method and a sputtering method can be applied. Furthermore, when a dielectric on the contact portion is formed on the dielectric layer 50 above the contact portion 40 on the surface of the formed dielectric layer, it is sufficient to form a mask as desired and remove the dielectric on the contact portion by etching or the like. For example, the dielectric on the contact portion can be wet-etched using buffered hydrofluoric acid (BHF) or the like.

[0124] It should be noted that if Figure 8 As shown, it is also preferred to form a dielectric layer 50 on a portion of the exposed surface E2 of the semiconductor stack 30, and to make an exposed portion E3 around the contact portion 40. Such a dielectric layer 50 and the exposed portion E3 can be formed, for example, by the following operation. First, a dielectric layer is formed on the entire surface of the semiconductor stack 30, and a window pattern that completely surrounds the contact portion is formed above the contact portion 40 on the surface of the formed dielectric layer by a resist. At this time, the window pattern preferably has a margin of about 1 to 5 μm relative to the length of the width direction and the length direction of the contact portion. By using the resist pattern formed in this way, the dielectric around the contact portion is removed by etching, thereby forming a dielectric layer 50, and forming an exposed portion E3 around the contact portion 40.

[0125] In order to reliably obtain this shape, the width W of the exposed portion E3 is preferably set to 0.5 μm or more and 5 μm or less, and more preferably set to 1 μm or more and 3.5 μm or less (see Figure 8 ).

[0126] Here, it is also preferred to set the contact area ratio of the dielectric layer 50 and the semiconductor stack 30 to be greater than 80% and less than 95%. This is because: by reducing the area of ​​the contact portion 40 and increasing the area of ​​the dielectric layer 50, light absorption caused by the contact portion can be suppressed. It should be noted that the contact area ratio can be measured in the state of the wafer. When the contact area ratio is reversed from the state of the semiconductor light-emitting element after singulation, the width of the semiconductor layer (the area where the dielectric layer exists) removed during singulation can be assumed to be a single width of 20 to 30 μm (two widths of 40 to 60 μm) for calculation.

[0127] It should be noted that the relationship between the thickness H1 of the dielectric layer 50 formed by the dielectric layer forming step and the thickness H2 of the contact portion 40 is not particularly limited. Figure 8 As shown in FIG. 1 , when the thickness of the dielectric layer 50 is represented by H1 and the thickness of the contact portion is represented by H2, H1 ≥ H2 can be set, and H1>H2 is preferably set. Under this condition, the thickness of the dielectric layer 50 can be set, for example, to 360 nm to 1600 nm, and more preferably to 410 nm to 1100 nm. In addition, it is also preferred that the difference H1-H2 between the thickness H1 of the dielectric layer and the thickness H2 of the contact portion 40 is set to be greater than 10 nm and less than 100 nm.

[0128] In addition, SiO 2 , SiN, ITO, AlN, etc. can be used as the dielectric layer 50 , and it is particularly preferable that the dielectric layer 50 is formed of SiO 2 . This is because SiO 2 can be easily etched by BHF or the like.

[0129] <Reflective Layer Forming Step>

[0130] In the reflection layer forming step, a reflection layer 60 ( Figure 5(A)). It should be noted that, when the exposed portion E3 is formed in the dielectric layer forming process, the reflective layer 60 is also formed on the exposed portion E3. Although DBR, metal reflective layer, photonic crystal, refractive index difference based on local voids, etc. can be used, it is preferred to use a metal reflective layer for the reflective layer 60 because it is easy to manufacture and can be set to a reflectivity appropriate for the radiated light. The metal reflective layer can use Au, Al, Pt, Ti, Ag, etc., but it is particularly preferred to use Au as the main component. At this time, in the composition of the metal reflective layer, it is preferred that Au occupies more than 50% by mass, and it is more preferred that Au is more than 80% by mass. The metal reflective layer may include multiple metal layers, but when it includes a metal layer formed by Au (hereinafter referred to as "Au metal layer"), it is preferred that the thickness of the Au metal layer exceeds 50% of the total thickness of the metal reflective layer. For example, the metal reflective layer may be a single layer consisting only of Au, or the metal reflective layer may include more than two Au metal layers. In order to reliably perform the bonding in the subsequent bonding process, it is preferred that the outermost layer of the metal reflective layer (the surface on the opposite side of the semiconductor stack 30) is made into an Au metal layer. For example, a metal layer can be formed in the order of Al, Au, Pt, and Au on the dielectric layer 50, the exposed portion E3, and the contact portion 40 to form a metal reflective layer. The thickness of one layer of the Au metal layer in the metal reflective layer can be set to, for example, 400nm to 2000nm, and the thickness of the metal layer formed of a metal other than Au can be set to, for example, 5nm to 200nm. The metal reflective layer 60 can be formed by a common method such as evaporation and formed on the dielectric layer 50, the exposed portion E3, and the contact portion 40.

[0131] <Joining process>

[0132] In the bonding step, the support substrate 80 having the metal bonding layer 70 on its surface is bonded to the reflective layer 60 ( Figure 5 (B)). The metal bonding layer 70 may be formed in advance on the surface of the support substrate 80 by sputtering, vapor deposition, or the like. The metal bonding layer 70 and the reflective layer 60 are arranged opposite to each other and bonded together, and then heated and compressed at a temperature of about 250°C to 500°C to bond the two.

[0133] The metal bonding layer 70 bonded to the reflective layer 60 can use metals such as Ti, Pt, and Au; metals (such as Sn) that form a eutectic alloy with gold are preferably stacked. For example, a member obtained by stacking Ti with a thickness of 400nm to 800nm, Pt with a thickness of 5nm to 20nm, and Au with a thickness of 700 to 1200nm in sequence from the surface of the supporting substrate 80 can be used as the metal bonding layer 70. It should be noted that in order to facilitate the bonding of the reflective layer 60 and the metal bonding layer 70, it is preferred that the outermost layer on the metal bonding layer 70 side is set to an Au metal layer, and the metal layer on the metal bonding layer 70 side of the reflective layer 60 is also set to Au, and Au is bonded to each other based on Au-Au diffusion.

[0134] It should be noted that the support substrate 80 can use, for example, a conductive Si substrate. In addition, a conductive GaAs substrate or Ge substrate can also be used. In addition, in addition to the above-mentioned semiconductor substrate, a metal substrate can be used, and a support substrate using a heat-dissipating insulating substrate such as sintered AlN can also be used. Although the thickness of the support substrate 80 will also vary depending on the material used, it can be set to be greater than 100μm and less than 500μm. If it is a Si substrate or a GaAs substrate, it can be operated even if it is set to a thickness of less than 180μm. Considering heat dissipation, brittleness, and cost, a Si substrate is particularly preferred.

[0135] <Substrate Removal Process>

[0136] In the substrate removal step, the growth substrate 10 ( Figure 6 (A)). The growth substrate 10 can be removed by wet etching using, for example, a hydrochloric acid dilution solution, and the III-V compound semiconductor etching stop layer 20 can be set as the end point of the wet etching. It should be noted that when removing the III-V compound semiconductor etching stop layer 20, wet etching can be performed using, for example, a sulfuric acid-hydrogen peroxide-based etching solution.

[0137] <Roughening process>

[0138] In the roughening process, the surface of the light extraction surface of the n-type cladding layer 31 (surface other than the flat surface 31F) is roughened to form a rough surface with a surface roughness Ra of 0.03 μm or more and a random concave-convex pattern, and to form a random concave portion 31C ( Figure 6 (B)). It is preferred to roughen the surface of the light extraction surface in such a way that the skewness Rsk of the surface reaches -1 or more. The roughening process can be performed by sequentially performing masking and roughening of the top surface electrode region. Fig. 9 (A) to (D) of the present invention illustrate the roughening treatment step and the protective film forming step which is suitably performed thereafter.

[0139] <<Mask for Top Electrode Area>>

[0140] First, a masking is performed using a photoresist PR1 or the like on the top surface electrode formation region 31F on the etching stop layer 20 or the second conductive type cladding layer (n-type cladding layer 31) exposed by the substrate removal step. Fig. 9 (A)). As described later, it can be performed simultaneously with the first process for protecting the electrode area when the III-V compound semiconductor etching stop layer 20 in the roughening process is etched to form a pattern. It should be noted that when the top surface electrode is formed before the roughening process, it is sufficient to mask the top surface electrode with a photoresist after the top surface electrode is formed. The top surface electrode can be formed on the second conductive cladding layer (n-type cladding 31). By forming it on the etching stop layer 20, the reliability of the electrode can be improved. Fig. 9 (A) to (D) are schematic diagrams of a method of forming a top surface electrode on the etching stop layer 20 .

[0141] Next, the roughening process can be performed by roughening based on mechanical processing, wet etching, or dry etching alone or in combination. As long as the surface roughness Ra of the concave-convex pattern of the p-type cladding layer 31 is formed to be 0.03 μm or more and the surface is roughened in a random rough surface, preferably in a manner that the skewness Rsk reaches Rsk ≥ -1, any combination may be used.

[0142] An example of a first step to a third step and a protective film forming step preferably performed thereafter, which are included in a suitable form of the roughening treatment step, is shown below. In addition to the following, the roughening treatment may be performed by a different method.

[0143] <<First step (Electrode area protection)>>

[0144] The foregoing Figure 6 (A) corresponds to the state after the growth substrate 10 is removed. Thereafter, in the first step, after the growth substrate 10 is removed, the predetermined portion on the flat region 31F of the n-type cladding layer 31 where the top surface electrode is to be formed or the electrode after the top surface electrode is formed) is protected by a material that can withstand the roughening due to the mechanical processing described later. As a material, any material that is equal to or harder than the hardness of the abrasive in the mechanical processing (i.e., grinding processing) and that is easy to form a film and pattern, for example, SiO2, SiN, TiN, etc. can be selected.

[0145] The patterning may be performed by etching or lift-off using photolithography.

[0146] <<Second step (roughening by machining)>>

[0147] Following the first step, in the second step, grinding is performed on the surface (light extraction surface) other than the portion where the top surface electrode is to be formed. Fig. 9 Such grinding can be performed by attaching the back surface of the wafer to a support plate with wax or the like, and roughly grinding the surface at a predetermined rotation speed using a grinder while flowing a grinding sheet or slurry containing abrasives, thereby producing irregularly shaped irregularities.

[0148] At this time, the etching stop layer 20 may be present at the start of grinding, or may be removed by etching in advance. If the etching stop layer 20 is not removed, the grinding time may be adjusted so that the thickness of the etching stop layer 20 is ground away at a certain level during grinding.

[0149] <<Third step (etching step)>>

[0150] The surface on which the irregularities have been generated in the second step is etched for the purpose of removing surface strain to clean the surface and making the irregularities steeper.

[0151] For etching, for example, a hydrochloric acid-acetic acid system etching solution (hydrochloric acid:acetic acid=1:2) or a commercially available etching solution such as PureEtch F106 manufactured by Hayashi Pure Chemical Industries, Ltd. can be used.

[0152] Based on the concavoconvex amount of the second step, the etching solution or etching conditions (temperature, time, stirring, etc.) in the third step can be arbitrarily combined. Compared with other compound semiconductors, although InP is a material that is more difficult to form concavoconvex by etching, it is sufficient to form concavoconvex by making the surface roughness of the n-type cladding layer 31 reach Ra≥0.03 and Rsk≥-1.

[0153] <Protective Film Formation Step>

[0154] After masking the center of the top electrode with a resist, a protective film PF1 is formed on the entire surface including the concavo-convex surface of the p-type cladding layer 31 ( Fig. 9 (C)). Thereafter, the etching layer is peeled off to expose the top surface electrode ( Fig. 9 (D)).

[0155] As the film forming method, known methods such as plasma CVD method and sputtering method can be applied. In addition, when the top surface electrode has not formed an anti-etching layer in advance, it is sufficient to form a mask after the protective film is formed and remove the protective film on the top surface electrode by etching using buffered hydrofluoric acid (BHF) or the like.

[0156] It should be noted that, although not shown in the figure, the manufacturing method based on the present embodiment preferably further has a grinding step of grinding the thickness of the support substrate 80 to a range of 80 μm or more and less than 200 μm. In the present embodiment, a Si substrate can be used as the support substrate 80. In this case, even if the support substrate 80 is ground to a thickness of less than 200 μm, it will not be damaged. Furthermore, the thickness of the support substrate 80 can be ground to less than 150 μm, or it can be ground to less than 100 μm. Among them, if the thickness of the support substrate 80 is ground to less than 80 μm, even the Si substrate may be damaged, so it is preferred to set the lower limit of the thickness to 80 μm. In addition, if the thickness of the support substrate 80 is greater than 80 μm, the semiconductor light emitting element 100 can be fully processed.

[0157] In addition, in the manufacturing method according to a preferred embodiment of the present invention, Figure 7 As shown in the figure, there may be further a step of forming a top surface electrode 93 on the surface of the semiconductor stack 30 after the semiconductor light emitting element 100 is manufactured. In addition, when the support substrate 80 is conductive, there may be further a step of forming a back surface electrode 91 on the back surface of the support substrate 80. The top surface electrode 93 may include a wiring portion 93a and a pad portion 93b. By performing such a step, a semiconductor light emitting element 100' can be manufactured. The back surface electrode 91 and the top surface electrode 93 can be formed by a known method, such as a sputtering method, an electron beam evaporation method, or a resistance heating method.

[0158] For ease of explanation, this embodiment uses an n-type InP substrate as the growth substrate 10. The n-type and p-type layers formed on the growth substrate 10 are as described above, but it can be naturally understood that the conductivity type of each layer, n-type / p-type, can be reversed.

[0159] Furthermore, if Figure 1 , Figure 2 As shown in the semiconductor light emitting element, the epitaxially formed semiconductor layers 3a, 3b, and 3c may be mesa-etched before cutting.

[0160] It should be noted that in the embodiment of the above-mentioned manufacturing method, the preparation of the junction-type semiconductor light-emitting element 100 is described as a premise, but the present invention is not limited to the junction-type semiconductor light-emitting element. The manufacturing method of the semiconductor light-emitting element based on the present invention can sequentially form a reflective layer, a first conductive type cladding layer formed by InGaAsP containing at least In and P, a semiconductor light-emitting layer with a light emission center wavelength of 1000 to 2200nm, and a second conductive type cladding layer formed by InGaAsP containing at least In and P on a substrate, and after forming the second conductive type cladding layer as the light extraction side, the second conductive type cladding layer is roughened to form a rough surface with a surface roughness Ra of 0.03μm or more and a rough surface with a random concave-convex pattern. In addition, in the aforementioned roughening treatment step, it is preferred to roughen the surface of the aforementioned light extraction surface in such a manner that the skewness Rsk of the surface reaches -1 or more.

[0161] Example

[0162] (Experimental Example 1)

[0163] (Example 1)

[0164] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples at all. Figure 3 to Figure 6 , Fig. 9 The semiconductor light emitting device of Example 1 was manufactured according to the flowchart shown in the figure. The details are as follows.

[0165] First, n-type InP substrate (100) is deposited on the surface by MOCVD. 0.57 Ga 0.43 As etching stop layer (20nm), n-type InP cladding layer (thickness: 3.5μm), i-type InP spacer layer (thickness: 300nm), semiconductor light-emitting layer with quantum well structure with emission wavelength of 1300nm (total 130nm), i-type InP spacer layer (thickness: 300nm), p-type InP cladding layer (thickness: 4.8μm), p-type In 0.8 Ga 0.20 As 0.5 P 0.5 Cap layer (thickness: 50nm), p-type In 0.57 Ga 0.43 As contact layer (thickness: 100 nm). It should be noted that when forming a semiconductor light-emitting layer of a quantum well structure, In 0.73 Ga 0.27 As 0.5 P 0.5 Well layers (thickness: 5 nm) and InP barrier layers (thickness: 8 nm) were alternately stacked 10 layers each.

[0166] like Fig.10 As shown in (A), in p-type In 0.57 Ga 0.43 A p-type ohmic electrode portion (Au / AuZn / Au, total thickness: 530nm) dispersed in an island shape is formed on the As contact layer. When forming this pattern, a resist pattern is formed, and then an ohmic electrode is vapor deposited and formed by peeling off the resist pattern. When the semiconductor layer of the wafer is observed from above using an optical microscope in this state, the contact area ratio between the p-type ohmic electrode portion and the semiconductor layer is 4.5%. It should be noted that Fig.10 The outer dimensions of (A) are 380 μm square.

[0167] Next, the ohmic electrode portion was used as a mask, and the p-type In was removed except for the portion where the ohmic electrode portion was to be formed by wet etching using tartaric acid-hydrogen peroxide system. 0.57 Ga 0.43 As contact layer. Then, a p-type In 0.80 Ga 0.20 As 0.50 P 0.50 A dielectric layer (thickness: 700 nm) made of SiO2 was formed on the entire surface of the cap layer. Next, a window pattern with a width of 3 μm in the width direction and the length direction was formed in the upper region of the p-type ohmic electrode portion by using a resist, and the p-type ohmic electrode portion and the dielectric layer around it were removed by wet etching based on BHF, so that the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 The cap layer is exposed. 0.80 Ga 0.20 As 0.50 P 0.50 The height H1 (700 nm) of the dielectric layer on the cap layer is 70 nm higher than the height H2 (630 nm) of the contact portion including the p-type contact layer (thickness: 130 nm) and the p-type ohmic electrode portion (thickness: 500 nm). It should be noted that when the semiconductor layer of the wafer is viewed from above using an optical microscope in this state, the contact area ratio of the dielectric layer (SiO2) is 90%.

[0168] Next, a metal reflective layer (Al / Au / Pt / Au) is formed on the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 The thickness of each metal layer of the metal reflective layer is 10nm, 650nm, 100nm, and 900nm, respectively.

[0169] On the other hand, a metal bonding layer (Ti / Pt / Au) was formed on a conductive Si substrate (thickness: 300 μm) serving as a support substrate. The thickness of each metal layer of the metal bonding layer was 650 nm, 10 nm, and 900 nm, respectively.

[0170] The metal reflective layer and the metal bonding layer were arranged to face each other and were bonded by heating and compression at 300° C. Next, the InP substrate was wet-etched with a hydrochloric acid dilute solution to remove the InP substrate.

[0171] Next, the surface of the light extraction surface of the n-type InP cladding is roughened. First, a positive photoresist is used to mask the etching stop layer except for the top electrode formation area, and a 50nm SiO2 film is formed by plasma CVD. A 100nm TiN film is formed on the SiO2 film, and the top electrode formation area is protected by the SiO2 film and the TiN film. The photoresist is dissolved, and the SiO2 film and the TiN film are removed by stripping except for the top electrode formation area. Then, while circulating a slurry obtained by mixing aluminum oxide abrasives (#4000 average particle size of 3μm) and a lubricant, the unprotected part of the etching stop layer and the n-type InP cladding is ground using a grinding plate. At this time, the thickness of the etching stop layer is 20nm, and the grinding time is adjusted and ground until the etching stop layer disappears, and the surface of the n-type InP cladding is formed by mechanical processing. Thereafter, the unevenness on the surface of the n-type InP cladding layer was further etched using a hydrochloric acid-acetic acid-based etching solution (hydrochloric acid:acetic acid=1:2).

[0172] Next, the TiN film used for protection in the above-mentioned roughening treatment is removed by a mixed solution of sulfuric acid and hydrogen peroxide solution, and the SiO2 film is removed by BHF. On the etching stop layer in the exposed top surface electrode formation area, an etching pattern is formed, an n-type electrode is evaporated, and the etching pattern is peeled off. Fig.10 As shown in (B), an n-type electrode (Au (thickness: 10nm) / Ge (thickness: 33nm) / Au (thickness: 57nm) / Ni (thickness: 34nm) / Au (thickness: 800nm) / Ti (thickness: 100nm) / Au (thickness: 1000nm)) is formed as the wiring portion of the top surface electrode. Furthermore, a pad portion (Ti (thickness: 150nm) / Pt (thickness: 100nm) / Au (thickness: 2500nm)) is formed on the n-type electrode so that the pattern of the top surface electrode is as shown in (B). Fig.10 It should be noted that Fig.10 (A) Similarly, Fig.10 The outer dimensions of (B) are 380 μm square.

[0173] Finally, the semiconductor layer between each element (width 60 μm) was removed by mesa etching to form a cutting line. In addition, a back electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness 200 nm)) was formed on the back side of the Si substrate, and the chip was singulated by dicing to produce the semiconductor light-emitting element of Example 1. It should be noted that the chip size is 350 μm×350 μm.

[0174] (Example 2, Example 3)

[0175] The semiconductor layer between each element (width 60 μm) was removed by mesa etching in Example 1 to form a cutting line, and then a SiO2 protective film was formed by plasma CVD in a manner that covered the roughened n-type InP cladding layer and the side of the element except for the bonding area (central circular portion) of the top surface electrode, to produce semiconductor light-emitting elements of Examples 2 and 3. Only the formation time of the SiO2 protective film when producing Examples 2 and 3 was adjusted, and as a result, the thickness of the SiO2 protective film in Examples 2 and 3 was 215nm and 645nm, respectively.

[0176] (Examples 4 to 7)

[0177] Semiconductor light emitting devices of Examples 4 to 7 were produced in the same manner as in Example 1 except that the etching time of the hydrochloric acid-acetic acid system in the roughening treatment in Example 1 was changed to control the surface roughness.

[0178] (Comparative Example 1)

[0179] A semiconductor light emitting element of Comparative Example 1 was produced in the same manner as in Example 1 except that the surface of the n-type InP cladding layer was not roughened.

[0180] (Comparative Example 2)

[0181] The semiconductor light emitting element of Comparative Example 2 was manufactured in the same manner as in Example 1 except that the roughening treatment described below was performed. First, when the n-type InP cladding layer was roughened, a positive photoresist PR2 was used to perform patterning. The pattern of the photoresist PR2 was as follows: Fig.11 As shown in the figure, the center points of the concave parts are arranged two-dimensionally into an isosceles triangle lattice. <011> Location and <011> The interval between the center points in the vertical direction was set to 6.6 μm. In addition, the shape of each concave portion was set to a regular hexagon (one side was 2 μm). Next, a tartaric acid-hydrogen peroxide aqueous etching solution was used to etch the n-type In 0.57 Ga 0.43 As etching stop layer for pattern transfer ( Fig.12(A) to (C)). Thereafter, the photoresist PR2 is cleaned and removed ( Fig.12 (D)), another photoresist PR3 is further formed on the top surface of the electrode formation region in the n-type InP cladding layer ( Fig.13 (A)). Then, the n-type InP cladding layer ( Fig.13 (B)), a sulfuric acid-hydrogen peroxide etching solution (sulfuric acid: hydrogen peroxide: water = 3:1:1) was further used to etch the n-type In 0.57 Ga 0.43 The As etch stop layer is wet etched to remove ( Fig.13 As a result, a concavo-convex pattern having crystal orientation dependence is formed.

[0182] (Comparative Example 3)

[0183] A semiconductor light-emitting element is produced by the same operation as in Comparative Example 2, and further a SiO2 protective film (film thickness: 500 nm) is formed to cover the roughened n-type InP cladding and the sides of the element in the same manner as in Example 2 to produce a semiconductor light-emitting element of Comparative Example 3.

[0184] (Comparative Examples 4 to 7)

[0185] Semiconductor light emitting devices of Comparative Examples 4 to 7 were produced in the same manner as in Comparative Example 2, except that the diameter and pitch of the pattern were changed to change the state of the roughened surface in the roughened surface treatment of Comparative Example 2.

[0186] <Measurement of Roughness of Rough Surface>

[0187] The roughened wafer (before dicing) was used, and the rough surface shape of the n-type cladding surface was measured using a contact height difference meter "P-6" manufactured by Tencor. The shape of the needle used was set to: the radius of the stylus tip was 2 μm, the stylus pressure was 2 mg, the scanning speed was 2 μm / sec, and the sampling frequency was 50 Hz. The measurement distance (reference length) was set to 200 μm. The value of the surface roughness Ra and the value of the skewness Rsk were automatically calculated by the height difference meter.

[0188] The data of the height difference meter of Examples 1 to 7 are shown in Figures 14A to 14G The height difference meter data of Comparative Examples 2 to 7, which were roughened using a mask, are shown in FIG. Figures 15A to 15F It should be noted that for Examples 2 and 3 and Comparative Example 3 in which a SiO2 protective film was formed, the surface of the n-type InP cladding layer before the protective film was formed and the surface of the protective film after the protective film was formed were measured. The measurement results of the surface of the n-type InP cladding layer are shown in the figure.

[0189] In Examples 1 to 7, irregular shaped projections and depressions are formed, and the hills and valleys are sharp. In contrast, in Comparative Examples 2 to 7, the spacing between the projections and depressions is uniform due to pattern formation, and the valleys of the depressions are deep. It should be noted that Comparative Example 1 was not subjected to a roughening treatment and is therefore flat. It should be noted that when measuring the data of the height difference meter, the Amplitude parameters (Rp, Rv, Rz, Rc, Rt, Ra, Rq, Rsk, Rku) based on ISO 4287-1997 are automatically calculated. Ra and Rsk are shown in Table 1 below. In addition, a graph showing the corresponding relationship between the surface roughness Ra and the skewness Rsk of Examples 1 to 7 and Comparative Examples 1 to 7 is shown in Fig.16 In addition, referring to the height difference data of Comparative Examples 4, 5, and 7 ( Fig. 15C , D, F), a slightly high peak is observed in the portion where the groove is not formed due to the mask (flat pattern portion), but the surface roughness Ra of the flat pattern portion is 0.004μm. The Ra of the portion where the groove is not formed is less than 0.010μm, and the surface on the light extraction side of the comparative example is evaluated as not being a "random rough surface". The spacing between the flat surfaces is: Comparative Example 2: 6.6μm, Comparative Example 3: 6.6μm, Comparative Example 4: 4.0μm, Comparative Example 5: 4.0μm, Comparative Example 6: 8.0μm, Comparative Example 7: 8.0μm. In addition, no portion where the groove is not formed is observed on the surface of the light extraction side of Examples 1 to 7 as in the comparative examples, and therefore it is evaluated as a "random rough surface".

[0190] [Table 1]

[0191] Table 1

[0192]

[0193] <Evaluation of output and Vf>

[0194] The semiconductor light-emitting elements of Examples 1 to 7 and Comparative Examples 1 to 7 were fixed on the transistor outline headers (TO-18) using silver paste, and the top surface electrodes were bonded using gold wires. Next, the luminous output (Po) and forward voltage (Vf) of Examples 1 to 7 and Comparative Examples 1 to 7 were measured by passing a current of 20 mA respectively. It should be noted that an integrating sphere was used for the measurement of the luminous output (Po). In addition, the forward voltage (Vf) was set to the voltage value of a constant current voltage device (manufactured by ADC: Model 6243)) when 20 mA was passed. The average values ​​of 10 measurements are shown in Table 1.

[0195] <Evaluation of Luminescence Spectrum>

[0196] A current of 20 mA was passed, and a spectrometer manufactured by Otsuka Electronics Co., Ltd. (model: MCPD-9800, light receiving element: InGaAs, wavelength width per 1 channel: 5.5 nm, slit width: 50 μm, wavelength accuracy: ±2 nm) was used. The measurement conditions were set to an exposure time of 1 msec and a cumulative number of 60 times, and the emission spectra of the light emitting elements of Examples 1 to 7 and Comparative Examples 1 to 7 in the wavelength range of 1000 to 1600 nm were measured. It should be noted that the measurement results were not smoothed.

[0197] The measured emission spectrum was evaluated according to the following criteria: It should be noted that the "shoulder" mentioned here refers to a point where the slope of the tangent line on the curve maintains its sign (positive or negative) but the slope of the tangent line changes from large to small or from small to large.

[0198] In the wavelength region with a relative intensity of 0.1 or more when the vertical axis (luminescence intensity) of the luminescence spectrum is represented by a line axis using a relative intensity with the maximum intensity set to 1, the situation in which, in addition to the luminescence peak at the central wavelength where the luminescence intensity reaches the maximum, luminescence peaks (the slope reaches a maximum value of 0) are observed in the luminescence spectrum, resulting in multiple peaks is recorded as ×.

[0199] In the case where no emission peak other than the emission peak of the central wavelength was observed and a single peak was present, a value of ○ was given when a portion called a shoulder was observed.

[0200] The case where a single peak was present and no portion called a shoulder was observed was marked as ◎.

[0201] The emission spectra of Example 1 and Example 7 are shown in FIG. Fig.17A , Fig. 17B The emission spectra of Comparative Examples 1 to 3 are shown in Figures 18A to 18C In addition, the emission center wavelength (λp) was measured. The emission center wavelength (λp) is shown in Table 1.

[0202] From Table 1 and Figures 14A to 14G , Figures 15A to 15F The results show that, as in Examples 1 to 7, if the concavo-convex shape is observed on the light extraction surface of the light emitting element, the luminescent spectrum shows a single peak. It can also be confirmed that if the surface roughness Ra and the skewness Rsk of the concavo-convex shape satisfy Ra ≥ 0.03 μm and Rsk ≥ -1, respectively, a single peak is indeed present. It can also be confirmed that by setting the skewness Rsk to -0.5 ≤ Rsk ≤ 0.5, a single peak is present and the luminescent output is large.

[0203] (Experimental Example 2)

[0204] For Examples 1, 2, 3, 5, 7 and Comparative Examples 1 to 6 prepared in Experimental Example 1, three-dimensional information on the roughness of the rough surface was obtained in the following manner.

[0205] <Measurement of Roughness of Three-Dimensional Rough Surface>

[0206] The rough surface shape of the n-type cladding surface in the roughened wafer (before dicing) was measured using a shape analysis laser microscope (KEYENCE VK-X1000 / 1100). It should be noted that the surface of the protective film after the protective film was formed was measured for Examples 2 and 3 and Comparative Example 3 in which a SiO2 protective film was formed. The lens magnification was set to 150 times and the number of pixels was set to 2048×1536.

[0207] When measuring the data, the parameters of the surface roughness (Sa, Sz, Str, Spc, Sdr, Ssk, etc.) based on ISO 25178 are automatically calculated. The values ​​are shown in Table 2 below. In addition, as a representative example, the three-dimensional images of the surface of the n-type cladding layer in Example 1 and Comparative Example 2 are shown in Table 2. Fig.19A and Fig.19B .like Fig.19A As shown in FIG. 1 , a random rough surface was observed on the surface of the n-type cladding layer of Example 1. On the other hand, on the surface of the n-type cladding layer of Comparative Example 2, a flat pattern portion (Ra of 0.010 μm or less) and a groove portion were arranged in a predetermined pattern, confirming that it was not a random rough surface.

[0208] [Table 2]

[0209] Table 2

[0210]

[0211] The results of studying the correlation between the skewness Rsk and the skewness Ssk based on the measurement results based on the two-dimensional evaluation described in Table 1 and the measurement results based on the three-dimensional evaluation described in Table 2 are shown in the following table. Fig. 20 In view of the Fig. 20 It can be seen from the figure that in order to eliminate multiple peaks, in three-dimensional measurement, it is preferred that the surface roughness Sa is greater than 0.05 μm and the surface skewness Ssk of the light extraction surface is greater than -0.5. In addition, it can be seen that the Sdr value and Po, which represent the size of the development area (surface area), show a tendency to increase relative to the Sdr value and Po.

[0212] (Experimental Example 3)

[0213] Immediately after the semiconductor light emitting elements described in Examples 1 and 3 and Comparative Examples 1 to 3 produced in Experimental Example 1 were produced, the initial light output was measured using an integrating sphere. Thereafter, after the semiconductor light emitting element was continuously energized at 100 mA for 1000 hours at room temperature, the light output was measured using an integrating sphere to determine the light output maintenance rate. The results are shown in Table 3 below. Therefore, it can be confirmed that if a protective film is formed on a random rough surface that meets the conditions of the present invention, the effect of suppressing the decrease in output caused by continuous energization is large.

[0214] [Table 3]

[0215] Table 3

[0216] Presence of protective film Luminous output maintenance rate Remark Example 1 none 94％ Random rough surface Example 3 have 99～100％ Forms a protective film on the random rough surface Comparative Example 1 none 94％ Flat surface Comparative Example 2 none 94％ Regular rough surface Comparative Example 3 have 97％ Forms a protective film on regular rough surfaces

[0217] Industrial Applicability

[0218] According to the present invention, a semiconductor light emitting element having a junction type semiconductor light emitting element including a cladding layer formed of InGaAsP containing at least In and P, capable of reducing multiple peaks in a light emission spectrum to a single peak, and a method for manufacturing the same can be provided.

[0219] Description of Reference Numerals

[0220] 1 Semiconductor light emitting element

[0221] 10 Growth substrate

[0222] 20 III-V compound semiconductor etch stop layer

[0223] 30 Semiconductor stack

[0224] 31 First conductivity type InP cladding

[0225] 35 Semiconductor light emitting layer

[0226] 35W Well Layer

[0227] 35B Barrier layer

[0228] 37 Second conductivity type InP cladding

[0229] 39 Cover layer

[0230] 40 Contact Department

[0231] 41(41a) Contact layer

[0232] 43 Ohm Metal Division

[0233] 50 Dielectric layer

[0234] 60 Metal reflective layer

[0235] 70 Metal bonding layer

[0236] 80 Conductive supporting substrate

[0237] 100, 100' semiconductor light emitting element

[0238] 91 Back electrode

[0239] 93 Top electrode

[0240] E1 Exposed area

[0241] E2 exposed

[0242] E3 exposed part

Claims

1. A semiconductor light emitting element, characterized in that: A reflective layer, a first conductive type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a light emission center wavelength of 1000 to 2200 nm, and a second conductive type cladding layer formed of InGaAsP containing at least In and P are sequentially provided on a substrate, and the second conductive type cladding layer is used as a light extraction side. The surface of the light extraction surface of the second conductivity type cladding layer is a rough surface having a surface roughness Ra of 0.03 μm to 0.142 μm and a random concavo-convex pattern.

2. A semiconductor light emitting element, characterized in that: A metal bonding layer, a reflective layer, a first conductive type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a central wavelength of 1000 to 2200 nm, and a second conductive type cladding layer formed of InGaAsP containing at least In and P are sequentially provided on a supporting substrate. The second conductive type cladding layer is used as a light extraction side, and the surface of the light extraction surface of the second conductive type cladding layer is a rough surface with a surface roughness Ra of not less than 0.03 μm and not more than 0.142 μm and a random concave-convex pattern. The semiconductor light emitting element according to claim 1 , wherein the light emission spectrum is a single peak.

4. The semiconductor light emitting element according to claim 1 or 2, wherein: The skewness Rsk of the surface of the light extraction surface is greater than or equal to -1.

5. The semiconductor light emitting element according to claim 1 or 2, wherein: A protective film is further provided on the light extraction surface.

6. The semiconductor light emitting element according to claim 5, wherein: The thickness of the protective film is greater than or equal to 100 nm and less than or equal to 700 nm. The surface roughness Ra of the surface of the protective film is greater than or equal to 0.02 μm, and the skewness Rsk is greater than or equal to −1.

7. The semiconductor light emitting element according to claim 5, wherein: The protective film includes at least one selected from the group consisting of silicon oxide, silicon nitride, ITO, and AlN.

8. A method for manufacturing a semiconductor light emitting element, characterized in that: The invention relates to a method for manufacturing a semiconductor light emitting element, which comprises forming a reflective layer, a first conductive type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a light emission center wavelength of 1000 to 2200 nm, and a second conductive type cladding layer formed of InGaAsP containing at least In and P in sequence on a substrate, and using the second conductive type cladding layer as a light extraction side. The method comprises: In the roughening treatment step, after forming the second conductive type cladding layer, the surface of the light extraction surface of the second conductive type cladding layer is roughened to form a rough surface having a surface roughness Ra of 0.03 μm to 0.142 μm and a random concavo-convex pattern.

9. The method for manufacturing a semiconductor light emitting element according to claim 8, wherein: In the roughening step, the surface of the light extraction surface is roughened so that the skewness Rsk of the surface becomes greater than or equal to -1.

10. A method for manufacturing a semiconductor light emitting element, characterized in that: It includes: Semiconductor layer forming step: sequentially forming a III-V compound semiconductor etching stopper layer containing In, Ga and As, a second conductivity type cladding layer formed of InGaAsP containing at least In and P, a semiconductor light emitting layer having a light emission center wavelength of 1000 to 2200 nm, and a first conductivity type cladding layer formed of InGaAsP containing at least In and P on a growth substrate; A reflection layer forming step: forming a reflection layer on the first conductive type cladding layer for reflecting light emitted from the semiconductor light emitting layer; A bonding step: bonding the support substrate to the reflective layer via the metal bonding layer; Substrate removal step: removing the growth substrate; as well as Roughening step: After the substrate removal step, the surface of the light extraction surface of the second conductive type cladding layer is roughened to form a rough surface having a surface roughness Ra of 0.03 μm to 0.142 μm and a random concavo-convex pattern.

11. The method for manufacturing a semiconductor light emitting element according to claim 10, wherein: In the roughening step, the surface of the light extraction surface is roughened so that the skewness Rsk of the surface becomes greater than or equal to -1.

12. The method for manufacturing a semiconductor light emitting element according to claim 10 or 11, further comprising: A top surface electrode forming step of forming a second conductivity type electrode on the second conductivity type cladding layer via the etching stopper layer in a top surface electrode forming region of the second conductivity type cladding layer excluding the light extraction surface.

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