Semiconductor device and method for manufacturing the same

Abstract

Methods and semiconductor devices that eliminate the use of additional masks are described herein. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer. Embodiments of the present invention also relate to semiconductor devices and methods of manufacturing the same.

Description

Technical Field

[0001] The technology described in this disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of manufacturing the same. Background Art

[0002] With the exponential growth of the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the process of IC evolution, functional density has generally increased while geometric size has decreased. This proportional reduction process generally provides benefits by improving production efficiency and reducing associated costs. For effective area loss in advanced semiconductor processes, the layout of resistors and capacitors has been considered.

[0003] The semiconductor die in the layout may include analog areas, digital areas, and memory areas. To reduce noise and control the etching rate in large areas, resistors are added to the die. Metal-insulator-metal (MIM) capacitors are formed using thin oxides and metal plates. There may be parasitic capacitance between the bottom metal plate and the bottom substrate. Summary of the invention

[0004] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first interconnect layer; forming a first resistance layer on top of the first interconnect layer; forming a dielectric layer on top of the first resistance layer; and forming a second resistance layer on top of the dielectric layer.

[0005] Another embodiment of the present invention provides a semiconductor device, including: a first interconnect layer; a first resistance layer disposed on top of the first interconnect layer; a dielectric layer disposed on top of the first resistance layer; and a second resistance layer disposed on top of the first resistance layer.

[0006] Yet another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming an interconnection layer; forming a first resistance layer on top of the interconnection layer; forming a dielectric layer on top of the first resistance layer; and forming a second resistance layer on top of the dielectric layer, wherein the first resistance layer, the second resistance layer, the dielectric layer, and the interconnection layer are formed using a single mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1Depicted are cross-sectional views of exemplary semiconductor devices according to various embodiments of the present disclosure.

[0009] Figure 2A Depicted are cross-sectional views of patterned semiconductor devices according to various embodiments of the present disclosure.

[0010] Figure 2B Describes the various embodiments of the present disclosure. Figure 2A A top view of a semiconductor device.

[0011] Figure 2C Describes the various embodiments of the present disclosure. Figure 2A A side profile view of a semiconductor device.

[0012] Figure 3A Depicted are cross-sectional views of example semiconductor devices having through-vias according to various embodiments of the present disclosure.

[0013] Figure 3B Describes the various embodiments of the present disclosure. Figure 3A A top cross-sectional view of a semiconductor device.

[0014] Figure 3C Describes the various embodiments of the present disclosure. Figure 3A A side profile view of a semiconductor device.

[0015] Figure 4A Depicted is a cross section of an example semiconductor device having additional vias formed directly on a metal interconnect layer according to various embodiments of the present disclosure.

[0016] Figure 4B Depicted is a diagram showing metal interconnect deposition within a metal interconnect layer according to various embodiments of the present disclosure. Figure 4A A top view of a semiconductor device.

[0017] Figure 4C Describes the various embodiments of the present disclosure. Figure 4A 4 is a side profile view of a semiconductor device 400.

[0018] Figure 5 Depicted is a cross-sectional view of another example semiconductor device according to various embodiments of the present disclosure.

[0019] Fig. 6A Depicted are cross-sectional views of example semiconductor devices according to various embodiments of the present disclosure.

[0020] Figure 6B Describes the various embodiments of the present disclosure. Fig. 6A A top view of a semiconductor device.

[0021] Figure 7Depicted is a top view of an example semiconductor device with selective via formation according to various embodiments of the present disclosure.

[0022] Figure 8 Depicted is a top view of an example semiconductor device with selective via formation according to various embodiments of the present disclosure.

[0023] Fig. 9 Depicted is a cross-sectional view of another example semiconductor device according to various embodiments of the present disclosure.

[0024] Fig.10 Depicted is a cross-sectional view of another example semiconductor device according to various embodiments of the present disclosure.

[0025] Fig.11 An example flow chart is depicted that illustrates a process for fabricating a semiconductor device according to various embodiments of the present disclosure.

[0026] Fig.12 An example flow chart is depicted that depicts a process for operating a semiconductor device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component refers to forming a first component in direct contact with a second component. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0029] IC development utilizes one or more overlapping layers. Manufacturers develop specific geometries for these ICs to perform specific functions, such as acting as amplifiers, oscillators, timers, microprocessors, or memory. Manufacturing methods typically involve the use of photolithography, deposition, and etching to manufacture semiconductor ICs. Designers consider different goals when optimizing ICs, such as cost, functionality, size, and / or surface area. One expense in manufacturing semiconductor ICs is the number of different photomasks or masks required to pattern or etch semiconductor devices. In back-end-of-line (BEOL) manufacturing, individual electronic devices (such as transistors, capacitors, and / or resistors) are interconnected to interconnect layers. In order to make room for metal interconnects (e.g., vias), many different masks are used to remove portions of the resistive layers that form the electronic devices. The masks mask some of the remaining material while allowing other materials to be removed by patterning the deposited layers. Semiconductor devices typically include front-end, middle-end, and BEOL layers. Semiconductor layouts that form passive devices in the BEOL layers are small-scale, and additional components can be assembled into the formed integrated circuit. Each mask layer adds additional time and cost to the semiconductor manufacturing process, so formation with fewer mask layers is less expensive. Minimizing the number of mask layers required to fabricate the BEOL layers increases efficiency in the manufacturing process.

[0030] For low-cost operation, the IC can utilize passive devices (e.g., resistors and / or capacitors) formed to be electrically coupled to active devices. In some implementations, semiconductor devices form high-density MIM (HDMIM) capacitors between metal interconnects to achieve thinner external capacitors and advanced scaling. Placing capacitors in the BEOL saves space for front-end processes and scaling. HDMIM capacitors can act as charge pools and provide electrical isolation between interconnect layers and electronic components of semiconductor devices. The method of forming HDMIM capacitors in the BEOL layer allows the scaling of semiconductor devices to be reduced while maintaining the capacitor structure. The photolithography process patterns the resistor layer and the capacitor layer to allow space to be left for the through holes between the interconnect layers. During the formation of the HDMIM capacitor, the use of an additional mask layer can be eliminated by forming a structure with a dielectric layer between two resistor layers on top of the interconnect layer. A single mask layer can be used to define the shape of the resistor layer, the dielectric layer, and the interconnect layer.

[0031] Figure 1A cross-sectional view of an exemplary semiconductor device 100 according to various embodiments of the present disclosure is depicted. The semiconductor device 100 may be formed within an IC or as a component of an IC. The semiconductor device 100 includes a metal interconnect layer 101, two resistive layers 103, 107, and a dielectric layer 105. The resistive layer 103 is deposited on the metal interconnect layer 101. The resistive layer 103 is electrically connected to the metal interconnect layer 101. The resistive layer 103 also electrically connects the metal interconnect layer 101 to the dielectric layer 105. The dielectric layer 105 is deposited on top of the resistive layer 103 to electrically connect the resistive layer 103 to the resistive layer 107. The dielectric layer 105 forms a capacitor between the resistive layer 103 and the resistive layer 107. According to some embodiments, the type of capacitor formed by the dielectric layer 105 may be a MIM capacitor or an HDMIM capacitor. The capacitor formed is used to generate an electric potential to stabilize the supply voltage of the active device of the semiconductor device 100 or filter the frequency in an analog system. In a digital system, the capacitor formed may be used as a battery or a voltage pool. The resistive layer 107 is deposited directly on the dielectric layer 105. The resistive layer 107 electrically connects the dielectric layer 105 to other electronic components. The resistive layer 103 and the resistive layer 107 function as resistors, which are used to control the voltage difference between the electronic components of the coupled semiconductor device 100. The semiconductor device 100 allows the resistive layers 103, 107 and the dielectric layer 105 to be deposited simultaneously on the metal interconnect layer 101. After the resistive layers 103, 107 and the dielectric layer 105 are deposited simultaneously, these layers can be patterned simultaneously using any appropriate patterning technique such as photolithography without an additional mask.

[0032] In some embodiments, the resistive layer 103 and / or the resistive layer 107 may be made of one or more of the following materials: W, TiN, TaN, Co, Ru, Ta, TiW, Ta-Si-N, TiZrN, CoTix, Mo, AlC, TiGen, Cr, CrAsC, TiAlC, WNX and / or any material having a resistivity greater than about 5 ohms per centimeter. In an alternative embodiment, the resistive layers 103, 107 are made of a high resistance material to form a thin resistive layer. In an alternative embodiment, the materials of the resistive layers 103, 107 are selected to prevent direct electrical connection between the resistive layers 103 and 107. According to some embodiments, the resistive layer 103 may include a thin film resistor.

[0033] In some embodiments, resistive layer 103 is characterized by a higher resistance than resistive layer 107. The higher resistance in resistive layer 103 may form a resistive characteristic when electrically coupled in parallel with metal interconnect layer 101. For example, resistive layer 103 may be made of a material having a resistivity greater than about 600 ohms per square centimeter.

[0034] In an alternative embodiment, the resistance layer 103 may be made of a metal with a lower resistance than the resistance layer 107 to be electrically connected to the metal interconnect layer 101 to generate a low voltage difference between the metal interconnect layer 101 and the resistance layer 103. For example, the resistance layer 103 may be made of a material with a resistivity between 100 and 300 ohms per square centimeter, and the resistance layer 107 may be made of a material with a resistivity greater than 600 ohms per square centimeter.

[0035] The dielectric layer 105 can be made of any material with a dielectric constant greater than or equal to 1. In some embodiments, the dielectric layer 105 can be made of one or more of CeO2, La2O3, Y2O3, ZrO2, TiO2, Al2O3, a-LaAlO3, HfO2, HfSiO4, La2O3, Nb2O5, Si3N4, SiO2, SrTiO3, Ta2O5, TiO2, Y2O3 and / or ZrO2. Materials with high dielectric constants provide many benefits to semiconductor devices. For example, the dielectric material layer 105 can help stabilize greater voltages by preventing short circuits between the resistive layers 103 and 107. For some semiconductor layouts, the dielectric layer 105 can allow for a reduction in parasitic capacitance between metal interconnect layers.

[0036] Semiconductor device 100 also includes a resistive layer 107. In some embodiments, resistive layer 107 is used to form a MIM capacitor. Resistive layer 107 can be made of a material having a resistance greater than or equal to that of resistive layer 103. The resistance that varies between resistive layers 103 and 107 can increase the voltage difference between the electrically coupled layers. In some embodiments, resistive layer 107 is made of the same material as resistive layer 101. In other embodiments, resistive layer 107 can be a metal having a resistivity greater than about 5 ohms per centimeter, such as W, TiN, TaN, Co, Ru, Ta, TiW, Ta-Si-N, TiZrN, CoTix, Mo, AlC, TiGen, Cr, CrAsC, TiAlC and / or WNX.

[0037] Figure 2A A cross-sectional view of a patterned semiconductor device 200 according to various embodiments of the present disclosure is depicted. Mask layer 209 simultaneously defines resistive layer 203, dielectric layer 205, and resistive layer 207. Mask layer 209 forms space for vias by patterning the underlying layers so that material can be removed. For example, Figure 2B Depicted Figure 2A FIG. 2 is a top view of a semiconductor device 200. Figure 2BAs shown, the first interconnect layer 201 is not completely overlapped by the resistive layer 203, the dielectric layer 205, and the resistive layer 207. The non-overlapping space in the first interconnect layer 201 allows electrical connection to other layers or devices. The design operation of the semiconductor device 200 has the function for some connections to avoid the electrical characteristics of the resistive layer and the dielectric layer while other connections for passive devices are passed through.

[0038] Figure 2C Describes the various embodiments of the present disclosure. Figure 2A 2 is a side profile of a semiconductor device 200. A metal interconnection deposit 202 is formed to avoid direct electrical connection. In some embodiments, the metal interconnection deposit 202 is electrically connected through the resistive layer 201 to form a voltage difference.

[0039] In some embodiments, resistive layer 203 has a higher resistance than resistive layer 207 to achieve reduced current and a larger voltage difference through resistive layer 203. In other embodiments, resistive layer 203 has a lower resistance than resistive layer 207 to allow for a larger voltage difference between electrical connections connected to resistive layer 207 and a lower voltage difference between metal interconnect depositions 202 in metal interconnect layer 201 for low voltage differences.

[0040] Figure 3A A cross-sectional view of an example semiconductor device 300 with a via 311 according to various embodiments of the present disclosure is depicted. The via 311 connects an additional metal interconnect layer 313. An electrical connection is formed between the metal interconnect layer 313 and the metal interconnect layer 301 so that current flows through the resistive layer 303, the dielectric layer 305, and the resistive layer 307. The semiconductor device 300 forms a MIM capacitor between the first interconnect layer 301 and the second interconnect layer 313. The formation of the MIM capacitor is due to the formation of parasitic capacitance across the resistive layer 303 and the resistive layer 307 through the dielectric layer 305. In some embodiments, the resistive layer 303 or the resistive layer 307 is characterized by high resistance to effectively store more charge. In some embodiments, the dielectric layer 305 is characterized by high capacitance to store charge and stabilize the supply voltage of the connected device. The resistive layer 303 and the resistive layer 307 can be thin to allow a low voltage difference between the connected metal interconnect layer 301 and the metal interconnect layer 313 through the resistive layer 303, the dielectric layer 305, and the resistive layer 307.

[0041] Figure 3B Describes various embodiments of the present disclosure Figure 3A300. A first interconnect layer deposit 302 may be formed tangent to a second interconnect layer deposit 313. A mask layer 309 allows for partial removal of the resistive layer 303, the dielectric layer 305, and the resistive layer 307 by photolithography. The semiconductor device 300 is used for BEOL connections, where non-overlapping deposits 302 of the first interconnect layer may be directly connected to the device above via a via. To improve accuracy, a via 311 is formed on the resistive layer 307. The via 311 is smooth to maintain a consistent electrical connection between the resistive layer 307 and the metal interconnect layer 313.

[0042] Figure 3C Describes various embodiments of the present disclosure Figure 3A 300. In some embodiments, via 311 connects a single metal interconnect deposition 314 to resistive layer 307. In some embodiments, resistive layer 307 is made of a material having a higher resistance than resistive layer 303. With the higher resistance, a voltage difference is formed between different depositions in metal interconnect layer 313.

[0043] Figure 4A A cross section of an example semiconductor device 400 having additional vias 411 formed directly on a metal interconnect layer 401 according to various embodiments of the present disclosure is depicted. The semiconductor device 400 is used for BEOL connections, wherein non-overlapping deposits 402 ( Figure 4B 411 is directly connected to the device through the through hole 411. The through hole 411 can be formed directly on the available space patterned by the mask layer 409 of the metal interconnect layer 401. For example, the metal interconnect layer deposition 402 can be directly connected to the metal interconnect layer deposition 414 ( Figure 4B At the same time, the metal interconnect layer deposition 402 (at Figure 4B ) can be connected to the metal interconnect layer deposition 414 through the via 411 through the resistive layer 403, the dielectric layer 405 and the resistive layer 407.

[0044] Figure 4B Describes the various embodiments of the present disclosure. Figure 4A A top view of a semiconductor device 400, Figure 4A Metal interconnect deposits 414 within metal interconnect layer 413 are shown. Figure 4C Describes the various embodiments of the present disclosure. Figure 4A The side profile of the semiconductor device 400 is shown in FIG. The through hole 411 is directly connected to the first interconnect layer 401. Figure 4A and Figure 4B As shown, one or more additional vias may be formed after the via 411 on the resistive layer 407 .

[0045] Figure 5 A cross-sectional view of another example semiconductor device 500 according to multiple embodiments of the present disclosure is depicted. Semiconductor device 500 allows connections between multiple connected metal interconnect layers. For example, metal interconnect layer 501 is connected to metal interconnect layer 513 through via 511, and is again connected to metal interconnect layer 523 through via 511. In some embodiments, the metal interconnect layer can be a single connected deposition. In an alternative embodiment, the metal interconnect layer can be multiple connected and separated depositions (e.g., metal interconnect layer 523). BEOL design can form direct connections between interconnect layers through via 511. In an alternative embodiment, MIM capacitors can be formed between interconnect layers in BEOL. In some embodiments, metal interconnect deposition 525 will not span the length of metal interconnect layer 523. Metal interconnect deposition 514 can be formed above resistive layer 507 or above interconnect layer 501. Resistive layer 503, dielectric layer 505, and resistive layer 507 are formed before forming metal interconnect layer 513 and metal interconnect layer 523. The resistive layer 503, dielectric layer 505 and resistive layer 507 are shaped by a mask layer 509 to allow electrical connection around the resistive layer and the MIM capacitor.

[0046] FIG. 6A to FIG. 6B A diagram of another example semiconductor device 600 is depicted in which metal interconnect layers are deposited in parallel. Fig. 6A Depicted is a cross-sectional view of an example semiconductor device 600 according to various embodiments of the present disclosure. Figure 6B Describes the various embodiments of the present disclosure. Fig. 6A 600. As the current flows through the resistive layer 603 or the resistive layer 607, the semiconductor device 600 forms a resistive characteristic between the metal interconnect layer 601 and the metal interconnect layer 613. The metal interconnect layer 601 and the metal interconnect layer 613 are separated by the MIM capacitor formed across the dielectric layer 605. As the current flows through the MIM capacitor and one of the resistive layers (e.g., the resistive layer 603 or the resistive layer 607), the operation of the semiconductor device 600 is similar to a capacitor and a resistor connected in series. The metal interconnection deposit 619 in the metal interconnection layer 613 is electrically connected to the other metal interconnection deposits 619. The metal interconnection deposit 619 is connected to the metal interconnection layer 613 through the second interconnection layer 613, thereby generating a resistor characteristic. Most of the current flows through the resistive layer with the lowest resistivity level. In an optional embodiment, if the resistivity of the resistive layer 603 and the resistive layer 607 is approximately the same, the current flows approximately evenly through the two resistive layers.

[0047] Figure 7A top view of an example semiconductor device 700 with selective via formation according to multiple embodiments of the present disclosure is depicted. Semiconductor device 700 does not include uniform via formation. For example, via 711 is not formed in region 715. As a result, no current flows between interconnects 701 and 713 at region 715, and the voltage can float. Semiconductor device 700 allows for connection across a length portion of a resistive layer to obtain a higher resistance. In addition, semiconductor device 700 also allows a metal interconnect layer to float between layers connected to active devices to reduce parasitic capacitance. Mask layer 709 shapes the MIM capacitor to form a spatial opening for via 711 formed directly between metal interconnect layer 713 and metal interconnect layer 701.

[0048] Figure 8 A top view of an example semiconductor device 800 with selective via formation according to various embodiments of the present disclosure is depicted. The semiconductor device 800 has regions such as region 815 where no vias are formed between certain deposits in the first interconnect layer 801 and the second interconnect layer 813. For example, no vias may be formed in the region 815 where the mask layer 809 has formed a dielectric layer and a resistive layer, so that the metal interconnect layer 801 and the metal interconnect layer 813 overlap but lack a connecting via 815.

[0049] Fig. 9 A cross-sectional view of another example semiconductor device 900 according to various embodiments of the present disclosure is depicted. The semiconductor device 900 includes a plurality of metal interconnect layers 901, 913, 923, 933 with additional MIM capacitors formed in series between (i) metal interconnect layers 913 and 923 and (ii) metal interconnect layers 901 and 913. The semiconductor device 900 also includes metal interconnect layers extending along different axes that are parallel or perpendicular to other metal interconnect layers. For example, the metal interconnect layer 913 extends parallel to the metal interconnect layer 923 along the y-axis. However, the metal interconnect layer 913 extends perpendicular to the metal interconnect layer 901 along the x-axis. The semiconductor device 900 has two MIM capacitors. A MIM capacitor is formed using a resistive layer 903, a dielectric layer 905, and a resistive layer 907 on the metal interconnect layer 901 and shaped using a mask layer 909. The MIM includes a via 911 connected to the metal interconnect layer 913. The second MIM capacitor is formed on the metal interconnect layer 913 between the metal interconnect layer 913 and the metal interconnect layer 923. The second MIM capacitor includes a resistance layer 917, a dielectric layer 919, and a resistance layer 921. The semiconductor device 900 also includes a metal interconnect layer 933 below the metal interconnect layer 901, and a MIM capacitor is formed between any two metal interconnect layers.

[0050] Fig.10A cross-sectional view of another example semiconductor device 1000 according to various embodiments of the present disclosure is depicted. The semiconductor device 1000 includes a metal interconnect layer 1023 and a metal interconnect layer 1033 below the metal interconnect layer 1001. The semiconductor device 1000 includes a single MIM capacitor formed between the metal interconnect layer 1001 and the metal interconnect layer 1013. The mask layer 1009 shapes the MIM capacitor. The MIM capacitor is formed by the resistive layer 1003, the dielectric layer 1005, and the metal interconnect layer 1007. In some embodiments, for optimal scaling of the semiconductor device 1000, the direction of the metal interconnect layer is switched between adjacent layers.

[0051] Fig.11 An example flow chart 1100 is depicted that depicts a process for fabricating a semiconductor device according to various embodiments of the present disclosure. Fig.11 The process is applicable to many different structures, but for ease of understanding, refer to Figure 1 100. At 1101, a first metal interconnect layer 101 is formed. At 1103, a first resistive layer 103 is formed on top of the first metal interconnect layer 101. The first resistive layer 103 may be formed simultaneously with a dielectric layer 105 and a second resistive layer 107. At 1105, a dielectric layer 105 is formed on top of the first resistive layer 103. At 1007, a second resistive layer 107 is formed on top of the dielectric layer 105. The resistive layer 103, the dielectric layer 105, and the second resistive layer 107 are shaped using a mask 209 lithography to pattern the layers. The patterning process allows additional electrical connections to be added to the semiconductor device 100.

[0052] Fig.12 An example flow chart 1200 is depicted, which depicts a process for operating a semiconductor device according to various embodiments of the present disclosure. At 1201, a HDMIM capacitor formed within a first resistive layer, a dielectric layer, and a second resistive layer is charged. At 1203, the HDMIM capacitor is operated. The first resistive layer, the dielectric layer, and the second resistive layer are simultaneously formed using a single mask layer.

[0053] The formation of various semiconductor devices described herein can eliminate the use of additional masks by requiring only a single mask to shape the resistive layer and the dielectric layer. These semiconductor devices do not require the use of additional mask layers to form HDMIM capacitors. Minimizing the number of mask layers can improve the efficiency of producing semiconductor devices by freeing up resources and / or minimizing overall production costs.

[0054] In one embodiment, a method for manufacturing a semiconductor device includes forming a first interconnect layer, forming a first resistive layer on top of the first interconnect layer, forming a dielectric layer on top of the first resistive layer, and forming a second resistive layer on top of the dielectric layer.

[0055] In another embodiment, a semiconductor device includes a first interconnect layer, a first resistive layer disposed on top of the interconnect layer, a dielectric layer disposed on top of the first resistive layer, and a second resistive layer disposed on top of the first resistive layer.

[0056] In yet another embodiment, a method includes charging a MIM capacitor formed within a first resistive layer, a dielectric layer, and a second resistive layer, and operating the MIM capacitor. The first resistive layer, the dielectric layer, and the second resistive layer are simultaneously formed using a single mask layer.

[0057] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first interconnect layer; forming a first resistance layer on top of the first interconnect layer; forming a dielectric layer on top of the first resistance layer; and forming a second resistance layer on top of the dielectric layer.

[0058] In the above method, the first resistance layer, the dielectric layer, and the first interconnection layer are formed using a mask.

[0059] In the above method, the first resistance layer, the second resistance layer and the dielectric layer are formed simultaneously.

[0060] In the above method, a through hole is additionally formed, the through hole being formed on top of the second resistance layer.

[0061] In the above method, a second interconnection layer located on the top of the through hole is additionally formed.

[0062] In the above method, the first interconnect layer includes manganese.

[0063] In the above method, the first resistance layer includes metal, and the second resistance layer has a resistance greater than that of the first resistance layer.

[0064] In the above method, the first resistance layer has a greater resistance than the second resistance layer, and the second resistance layer includes metal.

[0065] In the above method, at least one of the first resistance layer or the second resistance layer includes a plurality of thin film resistors.

[0066] Another embodiment of the present invention provides a semiconductor device, including: a first interconnect layer; a first resistance layer disposed on top of the first interconnect layer; a dielectric layer disposed on top of the first resistance layer; and a second resistance layer disposed on top of the first resistance layer.

[0067] In the above semiconductor device, the mask layer defines the shapes of the first resistance layer, the dielectric layer, and the second resistance layer.

[0068] In the above semiconductor device, it further includes a through hole formed on top of the second resistance layer or the first interconnection layer.

[0069] In the above semiconductor device, further comprising a second interconnect layer formed on the top of the through hole.

[0070] In the above semiconductor device, the first resistance layer or the second resistance layer includes a plurality of thin film resistors.

[0071] In the above semiconductor device, the first interconnect layer includes manganese.

[0072] In the above semiconductor device, the first resistance layer includes metal, and the second resistance layer has a resistance greater than that of the first resistance layer.

[0073] In the above semiconductor device, the first resistance layer has a resistance greater than that of the second resistance layer, and the second resistance layer includes metal.

[0074] In the above semiconductor device, the resistivity of the first resistance layer is 100 to 300 ohms per square centimeter.

[0075] In the above semiconductor device, the second resistance layer has a resistivity greater than 600 ohms per square centimeter.

[0076] Yet another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming an interconnection layer; forming a first resistance layer on top of the interconnection layer; forming a dielectric layer on top of the first resistance layer; and forming a second resistance layer on top of the dielectric layer, wherein the first resistance layer, the dielectric layer, and the interconnection layer are formed using a single mask.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without deviating from the spirit and scope of the present invention.

[0078] This written description and this application may include terms (such as "on...") that are used for descriptive purposes only and should not be construed as limiting. Embodiments of the devices or articles described herein may be manufactured, used, or shipped in many positions and orientations. For example, unless specifically stated otherwise, the term "on..." as used herein does not necessarily mean that a first layer / structure is directly on and in direct contact with a second layer / structure; one or more third layers / structures may be present between the first layer / structure and the second layer / structure. The term "semiconductor device structure" as used herein may refer to a shallow trench isolation component, a polysilicon gate, a lightly doped drain region, a doped well, a contact, a via, a metal line, or other types of circuit patterns or components formed on a semiconductor substrate.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a plurality of first interconnection layers, each of the first interconnection layers having a length extending in a first direction, and the plurality of first interconnection layers are arranged at intervals in a second direction perpendicular to the first direction; forming a monolithic first resistive layer on top of the plurality of first interconnect layers; forming a dielectric layer on top of the first resistive layer; forming a second resistive layer on top of the dielectric layer; forming a plurality of second interconnect layers, each of the second interconnect layers having a length extending in the second direction and arranged at intervals along the second resistance layer in the first direction; as well as A plurality of vias are formed to interconnect the second interconnect layer and the second resistance layer, each of the vias having a length extending in a third direction perpendicular to the first direction and the second direction.

2. The method according to claim 1, wherein: The first resistance layer, the dielectric layer, and the second resistance layer are formed using a mask.

3. The method according to claim 1, wherein: The first resistance layer, the second resistance layer and the dielectric layer are formed simultaneously.

4. The method according to claim 1, wherein: The dielectric layer forms a capacitor together with the first resistive layer and the resistive layer. The method according to claim 1 , wherein the dielectric layer is made of a material having a dielectric constant greater than or equal to 1. 6 .

6. The method according to claim 1, wherein: The first interconnect layer includes manganese.

7. The method according to claim 1, wherein: The first resistance layer includes metal, and the second resistance layer has a resistance greater than that of the first resistance layer.

8. The method according to claim 1, wherein: The first resistance layer has a greater resistance than the second resistance layer, and the second resistance layer includes metal.

9. The method according to claim 1, wherein: At least one of the first resistive layer or the second resistive layer includes a plurality of thin film resistors.

10. A semiconductor device comprising: A plurality of first interconnect layers having a length extending in a first direction, the plurality of first interconnect layers being arranged at intervals in a second direction perpendicular to the first direction; a first resistance layer disposed on top of the first interconnect layer; a dielectric layer disposed on top of the first resistive layer; a second resistive layer disposed on top of the dielectric layer, a second interconnect layer, located above the second resistance layer, and having a length extending in the second direction; one or more first vias interconnecting the second interconnect layer and the second resistance layer, each first via having a length extending in a third direction perpendicular to the first direction and the second direction; a third interconnect layer, located above the first interconnect layer, and having a length extending in the second direction; as well as One or more second through-holes connect the first interconnection layer and the third interconnection layer, each of the second through-holes has a length extending in the third direction, wherein the number of the second through-holes is different from the number of the first through-holes.

11. The semiconductor device according to claim 10, wherein: The mask layer defines shapes of the first resistance layer, the dielectric layer, and the second resistance layer.

12. The semiconductor device according to claim 10, wherein: The first resistance layer is made of a metal having a lower resistance than that of the second resistance layer.

13. The semiconductor device according to claim 10, wherein the dielectric layer is made of one or more of CeO2, La2O3, Y2O3, ZrO2, TiO2, Al2O3, a-LaAlO3, HfO2, HfSiO4, La2O3, Nb2O5, Si3N4, SiO2, SrTiO3, Ta2O5, TiO2, Y2O3 and / or ZrO2.

14. The semiconductor device according to claim 10, wherein: The first resistance layer or the second resistance layer includes a plurality of thin film resistors.

15. The semiconductor device according to claim 10, wherein The first interconnect layer includes manganese.

16. The semiconductor device according to claim 10, wherein: The first resistance layer includes metal, and the second resistance layer has a resistance greater than that of the first resistance layer.

17. The semiconductor device according to claim 10, wherein: The first resistance layer has a greater resistance than the second resistance layer, and the second resistance layer includes metal.

18. The semiconductor device according to claim 10, wherein: The resistivity of the first resistance layer is 100 to 300 ohms per square centimeter.

19. The semiconductor device according to claim 10, wherein: The second resistive layer has a resistivity greater than 600 ohms per square centimeter.

20. A method for manufacturing a semiconductor device, comprising: forming a plurality of first interconnect layers, each of the first interconnect layers having a length extending in a first direction, and the plurality of first interconnect layers being arranged at intervals in a second direction perpendicular to the first direction; forming a monolithic first resistive layer on top of the plurality of first interconnect layers; forming a dielectric layer on top of the first resistive layer; forming a second resistive layer on top of the dielectric layer, wherein the first resistive layer, the dielectric layer, and the first interconnect layer are formed using a single mask; forming a second interconnect layer having a length extending in the second direction; forming one or more first vias interconnecting the second interconnect layer and the second resistance layer, each of the first vias having a length extending in a third direction perpendicular to the first direction and the second direction; forming a third interconnect layer having a length extending in the second direction; and One or more second vias are formed to interconnect the third interconnection layer with the first interconnection layer, each of the second vias having a length extending in the third direction.

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