A reliable watchdog circuit with time division and control method thereof

Abstract

The present invention discloses a reliable watchdog circuit with time division and a control method thereof. On the one hand, the present invention provides a reliable watchdog circuit with time division, including a processor and a watchdog connected to the processor signal, and also including a synchronous output timer and a timer cycle configuration module; the timer overflow signal output end and the watchdog timeout signal output end of the synchronous output timer are respectively connected to a three-state gate switch signal through a logic gate module to form a monitoring cycle switching control circuit, the synchronous output timer synchronization signal output end is connected to the enable end of the three-state gate switch through a trigger holding circuit, and the output end of the three-state gate switch is respectively connected to the reset end of the trigger holding circuit and the reset end of the watchdog. On the other hand, the present invention provides a reliable watchdog circuit control method with time division. The present invention can effectively enhance the stability of the system circuit, save resources, and improve the flexibility of control.

Description

Technical Field

[0001] The invention belongs to the field of embedded electronic communication, and in particular relates to a reliable watchdog circuit with time division, and also relates to a reliable watchdog circuit control method with time division. Background Art

[0002] In the embedded field, the stability of the processor usually needs to be monitored by peripheral circuits. Most of the practices are to add a watchdog circuit to the peripheral circuit of the processor in the circuit. Therefore, the watchdog timer is a peripheral device often used to detect whether the microprocessor is abnormal. After being set, the watchdog timer monitors the signal from the microprocessor periodically. If the watchdog does not receive the trigger signal from the processor, it is considered that the microprocessor is abnormal in the working software or hardware, and the microprocessor circuit is forced to reset after the timing time is exceeded.

[0003] At present, watchdogs are divided into built-in watchdogs and external circuit hardware watchdogs. Most circuits use external hardware watchdog circuits. External hardware watchdogs need to be fed periodically and need to be controlled by software in a timely manner. The current watchdog circuit has a fixed timing period, generally between a few hundred milliseconds and a few seconds. In embedded systems and multi-task systems where user application tasks have strict real-time requirements, the software needs to feed the dog in a short interval and on time, which is quite difficult; some complex programs also require the ability to flexibly handle the watchdog timing period. Another existing method is to use an additional GPIO port to control the watchdog circuit with an unlock code. Specifically, before the microprocessor runs other real-time programs or when it is powered on, the watchdog output is turned off or the watchdog output signal is blocked. This method not only occupies hardware GPIO resources, but also turns off the watchdog for specific reasons or startup waiting. It cannot be reset and recovered after the software runs away, which is a serious hidden danger. Therefore, the current watchdog circuit control method still needs to be improved in design.

[0004] Even though predecessors have proposed using dual-cycle timers as watchdog timers, the method is to use two timers as the first watchdog cycle and the second watchdog cycle, which requires dual clock signals to the dual timers, or one timer to select two special registers. The timer has no synchronous output signal. In addition, when the first timer is reset and started, switching from the first timer to the second timer also requires the state machine trigger to control the switch to output a reset signal. After that, the first timer cannot continue to work before reset, so it is impossible to realize the cyclic switching of the first watchdog and the second watchdog before reset, so a new design is urgently needed to meet the use needs. Summary of the invention

[0005] The first object of the present invention is to provide a reliable watchdog circuit in time periods, which can effectively enhance the stability of system circuits, save resources, and improve control flexibility.

[0006] A second objective of the present invention is to provide a control method for the above circuit.

[0007] To achieve the first purpose, the present invention provides a reliable watchdog circuit in time periods, including a processor and a watchdog connected to a processor output signal to detect the working state of the processor through a set second cycle, and also including a synchronous output timer connected to the processor signal for detecting and controlling the first cycle set when the processor is started, and a timer period configuration module connected to the synchronous output timer signal for controlling the size of the first cycle; the timer overflow signal output end and the watchdog timeout signal output end of the synchronous output timer are respectively connected to a three-state gate switch signal through a logic gate module to form a monitoring period switching control circuit, the synchronous signal output end of the synchronous output timer is connected to the enable end of the three-state gate switch through a trigger holding circuit, and the output end of the three-state gate switch is respectively connected to the reset end of the trigger holding circuit and the reset end of the watchdog, thereby forming a processor reset control circuit and a first period and second period reset cycle circuit.

[0008] Preferably, the timer period configuration module is a resistor or a capacitor or a register.

[0009] Preferably, the logic gate module is a configurable logic gate.

[0010] To achieve the second objective, the present invention provides a time-division reliable watchdog circuit control method for a circuit, comprising the following processing steps:

[0011] Step 1: The system is powered on, the processor is loaded and started, and the synchronous output timer reads the first cycle of the initialization through the timer cycle configuration module. At the same time, the three-state gate switch is blocked so that the watchdog timeout signal cannot control the processor reset;

[0012] Step 2: After the first cycle time is up, the synchronous output timer sends a synchronous signal to the trigger holding circuit to control the three-state gate switch to turn on so that the processor reset control circuit works;

[0013] Step 3: If the processor starts and sends a dog feeding signal before the first cycle time expires, the watchdog timeout signal is controlled to be cleared, and the synchronous output timer does not generate an overflow signal, and the processor starts working normally; if the processor fails to start and does not send a dog feeding signal before the first cycle time expires, the watchdog timeout signal or the overflow signal of the synchronous output timer controls the watchdog to send a signal to control the processor to reset through the turned-on three-state gate switch, and controls the trigger holding circuit to reset, so that the three-state gate switch is blocked, the processor is restarted, and the synchronous output timer repeats the operations of steps 1 and 2 until the processor starts working normally;

[0014] Step 4: When the processor is started and works normally, if the dog feeding signal sent abnormally exceeds the second cycle, the watchdog sends a timeout signal to control the processor to reset through the turned-on three-state gate switch to control the watchdog to send a signal to control the reset of the processor, and at the same time control the reset of the trigger holding circuit, so that the three-state gate switch is blocked, the processor is restarted, and the synchronous output timer repeats the operations of steps 1 and 2.

[0015] Preferably, the watchdog timeout signal and the overflow signal of the synchronous output timer are sent to the three-state gate switch through a logic gate module.

[0016] Preferably, the first cycle duration is greater than or equal to twice the second cycle duration.

[0017] Preferably, the second cycle duration is less than 1S.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] In the present invention, the design of the logic gate module, the three-state gate switch and the trigger holding circuit enables the processor to be monitored in time periods only through the watchdog super and synchronous output timer, which solves the problem that the system startup time is long and the watchdog cannot effectively monitor, and can effectively enhance the stability of the system circuit, save resources, and improve the flexibility of control. At the same time, in the present invention, the problem that the conventional RC method is unavailable for the RC extension cycle time after the system reset is solved, and the problem that the time cycle cannot be flexibly configured using dual timers is solved, and the watchdog time cycle is switched in the running program. In the present invention, the reset signal output by the three-state gate switch resets the trigger watchdog and generates the reset signal required by the processor. In addition, the three-state switch gate resets the trigger holding circuit, re-enters the reset cycle, and the first cycle and the second cycle are circulated. It is not necessary to re-enter the first cycle of the timer cycle by power failure, which solves the problems of the existing scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural block diagram of the present invention;

[0021] Figure 2 It is a control flow chart in the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0023] like Figure 1As shown, the present invention provides a reliable watchdog circuit in time periods, including a processor 106 and a watchdog 107 connected to the output end of the processor 106 by signal and detecting the working state of the processor 106 through a set second cycle, and also including a synchronous output timer 103 connected to the processor 106 by signal and used for detecting and controlling the first cycle set when the processor 106 is started, and a timer period configuration module 102 connected to the synchronous output timer 103 by signal and used for controlling the size of the first cycle; the timer overflow signal output end of the synchronous output timer 103 and the timeout signal output end of the watchdog 107 are respectively connected to a three-state gate switch 105 by signal through a logic gate module 101 to form a monitoring period switching control circuit, the synchronous signal output end of the synchronous output timer 103 is connected to the enable end of the three-state gate switch 105 through a trigger holding circuit 104, and the output end of the three-state gate switch 105 is respectively connected to the reset end of the trigger holding circuit 104 and the reset end of the watchdog 107, thereby forming a reset control circuit for the processor 106 and a first cycle and a second cycle reset cycle circuit.

[0024] In this embodiment, the timer cycle configuration module 102 is a resistor or a capacitor or a register. The logic gate module 101 is a configurable logic gate, which can be an OR gate. In addition, the logic gate module 101 can use a configurable logic gate, that is, a logic gate with 3 inputs and 1 output. Because the reset signal is generally low-effective, according to the selection of L or gate and the selection of H is an AND gate, the design selection can be made as needed to realize the interchange of the watchdog cycle time from the first cycle to the second cycle. The OR gate state is that the short time cycle second cycle works, when the first cycle> the second cycle, the AND gate state is that the long time cycle first cycle works. The logic gate logic can be controlled by an external signal or a processor. By the processor controlling the selection, the first cycle and the second cycle of the time cycle of the running program can be interchanged. Regardless of the time cycle state, the watchdog monitoring processor can be guaranteed to be effective. Among them, the longer time cycle first cycle is suitable for use in low power consumption and sleep state, so that the product can ensure the stability of the watchdog detection processor in different scenarios.

[0025] like Figure 2 The present invention also provides a reliable watchdog circuit control method in time periods, comprising the following processing steps:

[0026] Step 1: The system is powered on, the processor 106 is loaded and started, and the synchronous output timer 103 reads the first cycle of the initialization through the timer cycle configuration module 102. At the same time, the three-state gate switch 105 is blocked so that the watchdog 107 timeout signal cannot control the processor 106 to reset;

[0027] Step 2: After the first cycle time is up, the synchronous output timer 103 sends a synchronous signal to the trigger holding circuit 104 to control the three-state gate switch 105 to turn on so that the processor 106 resets the control circuit to turn on;

[0028] Step 3: If the processor 106 starts and sends a dog-feeding signal before the first cycle time expires, the timeout signal of the watchdog 107 is cleared, and the synchronous output timer 103 does not generate an overflow signal, and the processor 106 starts working normally; if the processor 106 fails to start and does not send a dog-feeding signal before the first cycle time expires, the watchdog 107 timeout signal or the overflow signal of the synchronous output timer 103 controls the watchdog 107 to send a signal to control the processor 106 to reset through the turned-on three-state gate switch 105, and controls the trigger holding circuit 104 to reset, so that the three-state gate switch 105 is blocked, the processor 106 is restarted, and the synchronous output timer 103 re-performs the operations of steps 1 and 2 until the processor 106 starts working normally;

[0029] Step 4: When the processor 106 is started and works normally, if the abnormally sent dog feeding signal exceeds the second cycle, the watchdog 107 sends a timeout signal to control the watchdog 107 to send a signal to control the processor 106 to reset through the turned-on three-state gate switch 105, and at the same time control the trigger holding circuit 104 to reset, so that the three-state gate switch 105 is blocked, the processor 106 is restarted, and the synchronous output timer 103 re-performs the operations of step 1 and step 2. Thus, the segmented monitoring of the watchdog is formed during work, and the time is the first cycle and the second cycle respectively.

[0030] The timeout signal of the watchdog 107 and the overflow signal of the synchronous output timer 103 are sent to the tri-state gate switch 105 through a logic gate module 101. The first cycle duration is greater than or equal to twice the second cycle duration. The second cycle duration is less than 1S.

[0031] In the present embodiment, during the startup of the processor 106, if the system program runs away or other abnormalities occur, resulting in the dog feeding signal of the processor 6 not being sent to the watchdog 107 and the synchronous output timer 103 before the first cycle arrives, the signal of any one of them causes the processor 106 to reset the system, and the trigger holding circuit 104 is controlled to reset through the three-state gate switch 105, and the trigger holding circuit 104 is reset to the initial state, and the trigger holding circuit 104 is reset using edge triggering. Therefore, in the present invention, the processor is avoided from using GPIO to control the enabling of the watchdog, which not only saves GPIO, but also enhances stability. Whether it is just powered on or in the power-on reset state, if the processor is abnormal or the program runs away, the system must be reset in the first cycle time. Even if there is an accidental reset startup process, the synchronization signal of the synchronous output timer 103 is out of synchronization for DeltaT shortly after the system is reset, resulting in the reset signal of the watchdog 107 can reset the system through the tri-state switch 105. Then, when entering the initial state next time, the synchronization signal of the synchronous output timer 103 needs to wait for at least T1-DeltaT. When the cycle T1 is set to be relatively long, the next synchronization signal of the synchronous output timer 103 will wait for about T1 time before it is triggered, which will not affect the normal startup process. This can effectively improve stability and control flexibility.

[0032] The above are only preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the present invention through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A reliable watchdog circuit control method in time periods, characterized in that: The method relates to a watchdog circuit; the watchdog circuit comprises a processor (106) and a watchdog (107) connected to an output terminal signal of the processor (106) to detect the working state of the processor (106) through a set second cycle, and also comprises a synchronous output timer (103) connected to a signal of the processor (106) for detecting and controlling a first cycle set when the processor (106) is started, and a timer period configuration module (102) connected to a signal of the synchronous output timer (103) for controlling the size of the first cycle; a timer overflow of the synchronous output timer (103) The output signal output end and the watchdog (107) timeout signal output end are respectively connected to a three-state gate switch (105) signal through a logic gate module (101) to form a monitoring cycle switching control circuit, the synchronous output timer (103) synchronous signal output end is connected to the enable end of the three-state gate switch (105) through a trigger holding circuit (104), and the output end of the three-state gate switch (105) is respectively connected to the reset end of the trigger holding circuit (104) and the reset end of the watchdog (107), thereby forming a processor (106) reset control circuit and a first cycle and a second cycle reset cycle circuit; The processing steps include: Step 1: The system is powered on, the processor (106) is loaded and started, the synchronous output timer (103) reads the first cycle of the initialization through the timer cycle configuration module (102), and at the same time, the three-state gate switch (105) is blocked so that the watchdog (107) timeout signal cannot control the processor (106) to reset; Step 2: After the first cycle time expires, the synchronous output timer (103) sends a synchronous signal to the trigger holding circuit (104) to control the three-state gate switch (105) to turn on and make the processor (106) reset the control circuit to turn on; Step 3: If the processor (106) starts and sends a feeding signal before the first cycle time expires, the timeout signal of the watchdog (107) is cleared, and the synchronous output timer (103) does not generate an overflow signal, and the processor (106) starts working normally; if the processor (106) fails to start and does not send a feeding signal before the first cycle time expires, the timeout signal of the watchdog (107) or the overflow signal of the synchronous output timer (103) controls the watchdog (107) to send a signal to control the processor (106) to reset through the turned-on three-state gate switch (105), and controls the trigger holding circuit (104) to reset, so that the three-state gate switch (105) is blocked, the processor (106) is restarted, and the synchronous output timer (103) performs the operations of steps 1 and 2 again until the processor (106) starts working normally; Step 4: When the processor (106) is started and works normally, if the abnormally sent dog feeding signal exceeds the second cycle, the watchdog (107) sends a timeout signal to control the watchdog (107) to send a signal to control the processor (106) to reset through the turned-on three-state gate switch (105), and at the same time controls the trigger holding circuit (104) to reset, so that the three-state gate switch (105) is blocked, the processor (106) is restarted, and the synchronous output timer (103) performs the operations of steps 1 and 2 again.

2. A reliable time-division watchdog circuit control method according to claim 1, characterized in that: The watchdog (107) timeout signal and the synchronous output timer (103) overflow signal are sent to the tri-state gate switch (105) through a logic gate module (101).

3. The reliable time-division watchdog circuit control method according to claim 1, characterized in that: The first cycle duration is greater than or equal to twice the second cycle duration.

4. A reliable time-division watchdog circuit control method according to claim 1 or 3, characterized in that: The second cycle duration is less than 1S.

5. The reliable time-division watchdog circuit control method according to claim 1, characterized in that: The timer period configuration module (102) is a resistor or a capacitor or a register.

6. The reliable time-division watchdog circuit control method according to claim 1, characterized in that: The logic gate module (101) is a configurable logic gate.

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