Ferroelectric Memory, Logic Unit, and Operating Method

Abstract

The present invention relates to a ferroelectric memory, a logic unit, and an operation method. An example provides a storage unit, which includes: a node; a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states. A first transistor includes a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is connected to the node. A selector element includes at least a first terminal and a second terminal, wherein the second terminal is connected to the node.

Description

[0001] Cross - Reference to Related Applications

[0002] This non - provisional application claims the benefit of U.S. Provisional Application No. 62 / 845,464, filed on May 9, 2019, entitled "FERROLECTRIC MEMORY AND LOGIC CELL AND OPERATION METHOD", which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to ferroelectric memory cells, ferroelectric logic cells, ferroelectric logic in memory cells, and ferroelectric weighted units for neuromorphic computing. Background Art

[0004] Many electronic devices and systems have the ability to store and retrieve information in a memory structure. In the von Neumann architecture commonly used in modern electronic devices, information is processed in a central processing unit (CPU), while information is stored in a separate memory. Thus, information must be transferred between the CPU and the memory for processing and storage, creating the so - called von Neumann bottleneck. "Logic in Memory" (LiM) and neuromorphic circuits solve the von Neumann architecture bottleneck by using non - volatile memory (NVM) elements for information processing and implementing logic circuits directly and fine - grained with the storage elements in the processing unit. Many different non - volatile storage devices have been demonstrated in such concepts, including flash memory, resistive RAM (ReRAM), magnetoresistive RAM (MRAM), and phase - change memory (PCM).

[0005] Regarding ferroelectric (FE) structures, non - volatile memory (NVM) elements can be implemented as capacitor - type (e.g., ferroelectric random - access memory (FeRAM), ferroelectric tunnel junction type (FTJ)) and transistor - type (e.g., ferroelectric field - effect transistor (FeFET)) solutions, where information is stored as a certain polarization state of a ferroelectric material layer within the structure. The ferroelectric material used can be hafnium dioxide (HfO2), zirconium dioxide, or a solid solution of two transition - metal oxides. In the case of pure hafnium oxide, the remanent polarization can be improved by incorporating dopant species into the HfO2 layer during deposition.

[0006] Ferroelectric materials are intended to partially or fully replace the gate oxide of a transistor or the dielectric of a capacitor. Switching is caused by applying an electric field via a voltage between the transistor gate and the transistor channel. Specifically, for an n-channel transistor, ferroelectric switching after applying a sufficiently high positive voltage pulse results in a shift of the threshold voltage to a lower or more negative value, while applying a sufficiently high negative voltage pulse results in a shift of the threshold voltage to a higher or more positive value. For a p-channel transistor, ferroelectric switching after applying a sufficiently high positive voltage pulse results in a shift of the threshold voltage to a higher absolute value or more negative value, while applying a sufficiently high negative voltage pulse results in a shift of the threshold voltage to a lower absolute value or more positive value.

[0007] Typically, due to a specific physical storage mechanism, hafnium / zirconium-based memory devices provide fast sensing and programming access times and low power consumption during programming operations. Additionally, since the materials employed in FeFET, FeRAM, and FTJ memory devices have been used as gate oxides or DRAM dielectric materials, these memory devices are easily integrated into high-k metal gate CMOS technology. These and other advantages have contributed to the increasing popularity of hafnium / zirconium-based memory devices for embedded memory as well as for standalone applications employed in devices such as memory cards, USB flash drives, mobile phones, digital cameras, mass storage devices, MP3 players, smart watches, etc.

[0008] Figure 1 is a schematic diagram of a FeFET memory cell according to one example. In a FeFET memory cell, the polarization state of the ferroelectric layer is determined by sensing the threshold voltage of the transistor. In one example, further referring to Figure 2a , this sensing is performed by charging or discharging a bit line connected to the source terminal or drain terminal of the FeFET and sensing the voltage change at the bit line by sensing the current flowing through the FeFET using a suitable sense amplifier (SA) after a certain time. Circuit element T1 represents the FeFET device. In Figure 1 the example shown, the gate (g) of transistor T1 is connected to the word line WL, while the source terminal (s) and drain terminal (d) are connected to the bit line BL and the source line SL, respectively. The body contact (b) of the transistor is connected to the p-well PW terminal, which is shared by many memory transistors in the memory array (not shown). The sensing operation generally determines the threshold voltage or the on-current of the FeFET under specific read conditions. The polarization state of the FeFET is maintained during the read operation. Thus, it is a non-destructive read operation.

[0009] In Figure 2aIn an example FeRAM memory cell. The polarization state of the ferroelectric layer is determined by sensing the displacement current of the ferroelectric capacitor when an electrical switching pulse is applied. According to such an example, such a sensing operation is a destructive read operation because the polarization state must be rewritten into the cell after the read operation.

[0010] Reference Figure 2a , in order to sense the displacement current generated by the polarization reversal during the switching operation, the polarization charge originating from the ferroelectric capacitor C1 is transferred to the bit line (BL) via a selector device T2 (e.g., a CMOS transistor). The voltage change generated at the bit line is determined by a voltage sense amplifier SA connected to the corresponding bit line.

[0011] In addition to the above 1T1C FeFET memory cell, in other examples, additional transistors can be added to the 1T1C ferroelectric memory cell to form a 2T1C ferroelectric memory cell.

[0012] U.S. Patent No. 7,848,131 describes an example configured to prevent read and write interference effects, wherein an additional precharge transistor TP is connected in parallel to the ferroelectric capacitor C1 (see Figure 2b ). The gate of the precharge transistor TP is connected to a precharge control line PCL. The precharge transistor TP is used to precharge the electrical node formed between the selection transistor T2 and the ferroelectric capacitor C1 to a certain potential when T2 is turned off, to prevent read or write interference effects that affect the storage state of C1 during array read / write operations.

[0013] A second example of a 2T1C ferroelectric memory cell for improving the signal-to-noise ratio is described in US 10074422. The selection transistor, bit line, and word line are doubled to connect C1 to complementary bit lines, one for the data read signal BL (data), and one for the reference read signal BL (reference), as Figure 2c schematically described. In this configuration, a differential read operation improves the signal-to-noise ratio to improve the reliability of the data read out by the differential SA.

[0014] When such memory cells are arranged in an array of memory cells, several memory cells are typically connected to a shared BL and thus share a sense amplifier SA. To generate a sufficient voltage signal at the bit line for reliable memory state detection by the SA, the amount of polarized charge stored in each memory cell capacitor must be large enough to induce a sufficient read signal at the bit line. Thus, for highly scaled CMOS technology nodes (i.e., having a half-pitch less than 130 nm or having a half-pitch less than 90 nm and a typical number of 64, 128, or 256 memory cells connected to one bit line), 3D integration of ferroelectric capacitors is typically necessary to achieve the required memory capacitor area without consuming too much silicon area. In one example, when a potential is applied across the two terminals of ferroelectric capacitor C1, the leakage current flowing through ferroelectric capacitor C1 can depend on the polarization state of the ferroelectric capacitor. For example, when the ferroelectric switches to the negative polarization state, thus representing the erased logic state “0”, a relatively lower current will flow through the capacitor when a non-zero voltage is applied across the two terminals of the capacitor, compared to the case when the ferroelectric switches to the positive polarization state, thus representing the programmed logic state “1”, or vice versa. This difference in leakage current exists particularly for the case when a voltage below the coercive voltage of the ferroelectric capacitor is applied across its two terminals. A ferroelectric capacitor exhibiting such electrical behavior is also commonly referred to as a ferroelectric tunnel junction (FTJ).

[0015] Figure 13a is a schematic band diagram generally showing the on-state of a tunnel junction composed of two electrodes (1305, 1330) and a tunnel barrier (1340), which is a two-layer stack including a thin dielectric material (1320) and a ferroelectric material (1310). The Fermi levels E FM1 and E FM2 of the two electrodes (1305, 1330), the valence band E V and the conduction band E B of the tunnel barrier (1340) are plotted. Due to the voltage applied across the two electrodes (1305, 1330) and the polarization of the ferroelectric material layer in the first direction, tunneling from the conduction band of electrode (1330) to the conduction band of electrode (1305) is possible. In Figure 13b the off-state of such a device is shown. The Fermi levels E FM1 and E FM2 of the two electrodes (1305, 1330), the valence band E V and the conduction band E B of the tunnel barrier (1340) are plotted. Due to the same voltage applied across the two electrodes, but the polarization of the ferroelectric material layer in the second direction, tunneling from the valence band of electrode (1330) to the conduction band of electrode (1305) is not possible.

[0016] Typical FTJ stacks feature either very thin ferroelectric material layers, which allow for sufficient tunneling current. In other configurations of the FTJ, a composite stack is employed, where an additional thin dielectric layer serves as the tunneling barrier providing a larger read current, while the ferroelectric material layer is responsible for storing the polarization state.

[0017] Typically, the typical read current density of the FTJ is very low (e.g., typically <1 μA / cm 2 ). Therefore, sufficient FTJ area, low parasitic leakage current at the BL, and a very sensitive SA are required to reliably read the FTJ storage state. For a scalding device with an FTJ area in the range of 100 nm × 100 nm, the low read current may be in the range of <1 nA, which is one of the most critical issues currently hindering the application of FTJ in larger memory arrays.

[0018] Compared with FeRAM and FTJ cells, the advantage of the FeFET storage device is its ease of integration into state-of-the-art CMOS processes. A 3D capacitor structure is not required to provide the current or charge needed for the read operation of the SA. Due to the internal gain of the FeFET device, sufficient charge independent of the gate area can be provided to the BL for sensing the stored polarization state by the SA.

[0019] Due to the degradation of the interfacial silica layer sandwiched between the silicon channel and the ferroelectric high-k hafnium / zirconium oxide layer, the FeFET storage device has lower cycling durability compared with FeRAM capacitor devices. This silica interface is necessary to prevent chemical reactions between the high-k layer and the silicon channel during manufacturing and to maintain sufficient electron mobility in the channel. The relatively high coercive field for polarization reversal of the ferroelectric layer in the range of 1 MV / cm and the relationship between the silica interface (about 3.8 to 7 for a nitride interface) and ferroelectric hafnium oxide (about 30) generate a peak electric field in the range of 10 MV / cm in the interfacial silica layer during the polarization switching operation. This value is close to the breakdown field of the interfacial oxide layer. Therefore, repeated switching of the FeFET device results in wear of the interfacial silica layer, which leads to an increase in the charge trapping effect and a reduction in the measurable storage window.

[0020] To combine the advantages of the high cycling durability of ferroelectric metal-insulator-metal capacitors without an interfacial oxide and thus exhibit improved reliability with a smaller cell size and the lower manufacturing complexity of FeFET devices, the metal-ferroelectric-metal capacitor C1 can be directly connected between the gate electrode of the read transistor T3 and the word line terminal WL, as Figure 3aSchematically shown. In this way, a combined FeFET memory cell that operates in a manner similar to a conventional FeFET memory cell can be realized. In this case, the electrical node n1 is a floating node without a direct ground connection.

[0021] The capacitance divider ratio between the gate capacitor of transistor T3 and the ferroelectric capacitor C1 will determine the potential at node n1 when voltages are applied between the WL terminal and the SL terminal, PW terminal, and BL terminal. For example, for a relatively large capacitor C1 compared to the gate capacitance of T3, a smaller portion of the voltage will drop across capacitor C1, while for a relatively small capacitor C1 compared to the gate capacitance of T3, a larger portion of the voltage will drop across capacitor C1. The capacitance division ratio between C1 and the gate electrode of transistor T3 will determine the effective coercive voltage of the combined FeFET memory cell, where the coercive voltage is defined as the voltage that must be applied to the WL terminal in order to induce a polarization reversal of the ferroelectric capacitor C1.

[0022] To perform a write operation, a positive voltage greater than the effective coercive voltage of the combined FeFET memory cell is applied to the WL terminal of the combined FeFET memory cell ( Figure 3b ), while all other terminals are kept grounded. In this way, the ferroelectric capacitor C1 will switch to the upward polarization state. The resulting polarization current will cause the potential of node n1 to increase.

[0023] In contrast, to perform an erase operation, a negative voltage less than the negative effective coercive voltage of the combined FeFET memory cell is applied to the WL terminal, while all other terminals are kept grounded ( Figure 3b ), or a positive voltage whose absolute value of the voltage is greater than the effective negative coercive voltage of the combined FeFET memory cell is applied simultaneously to the SL terminal, BL terminal, and PW terminal while the WL terminal is kept grounded. In this way, the ferroelectric capacitor C1 will switch to the downward polarization state. The resulting polarization current will cause the potential of node n1 to decrease.

[0024] To perform a read operation, a positive voltage less than the effective coercive voltage of the combined FeFET memory cell is applied to the WL terminal of the combined FeFET memory cell. Additionally, a voltage is applied at the BL terminal. Depending on the polarization charge of capacitor C1 and the corresponding voltage on node n1, the gate terminal of T3 will experience different effective applied gate voltages, and corresponding currents will flow between the SL terminal and the BL terminal. In this way, the polarization state of the ferroelectric capacitor C1 can be determined in a non-destructive manner.

[0025] However, due to the leakage current that may flow through the gate dielectric of transistor T3 and through the ferroelectric capacitor C1, the voltage at node n1 may change over time. For example, refer to Figure 3a, in the case of repeated read operations of the cell, a voltage lower than the coercive voltage of the combined FeFET is applied to the WL terminal, and the electric field generated on the ferroelectric capacitor C1 can induce a leakage current Ileak, which charges the floating node n1. As a result, there is a change in the effective gate potential of T3, thereby generating a changing current flow between the source line and the bit line terminals SL and BL of the combined memory cell, respectively. This charging effect may ultimately lead to the loss of the stored information.

[0026] In addition, even when the potential applied between the WL terminal and the SL / BL / PW terminal of the memory cell is zero, the polarization state of the ferroelectric capacitor C1 may result in a non-zero potential at the node n1, which induces an electric field drop at the gate of the transistor T3 or at the ferroelectric capacitor C1, and this electric field drop can induce a leakage current Ileak that ultimately charges the floating node n1.

[0027] This leakage current that charges / discharges the floating node n1 can change the stored information over time, thus limiting the retention time of the memory cell. That is, the inevitable leakage current that occurs in a real device combined with a floating memory node can prevent the use of such a combined memory cell for non-volatile data storage. Summary of the Invention

[0028] The present disclosure provides examples of integrated circuits for sensing the polarization state of small-scale memory elements having a polarizable material as a storage layer. In an example, by employing a read transistor in addition to a selection transistor within the memory cell to amplify the read signal to be sensed by a sense amplifier (SA), sensing of the polarization state of a small-scale capacitor or a tunnel junction with only a small amount of switching charge or a small read current is provided. In addition, according to an example, the present disclosure provides a solution to the problem of the stored information in the memory cell being changed due to leakage current.

[0029] According to an example implementation described herein, an integrated circuit includes a memory cell having a capacitor, a transistor, and a third circuit element adapted to act as a selector device, which together form a 1T1S1C polarizable memory cell. In one example, the capacitor includes electrodes made of a metal or a semiconductor material or a conductive oxide and a layer of a polarizable material, and may include additional dielectric layers. According to an example of the present disclosure, the capacitor includes a polarizable material, which may be one of a ferroelectric material, an antiferroelectric material, and a relaxor ferroelectric material.

[0030] According to an example of the present disclosure, a memory cell includes: a capacitor having a polarizable material (polarizable capacitor) connected in series to the gate of a transistor; and an additional circuit element in the memory cell that enables direct control of the connection or the potential of a node between one terminal of the polarizable capacitor, the gate of the transistor, and a third circuit element, wherein the third circuit can include one of a transistor, a resistor, and a diode, which enables direct control of the potential of an otherwise floating node (e.g., see Figure 4a node n1).

[0031] According to an example of the present disclosure, the third circuit element can be a second transistor having one of a source and a drain connected to the gate of a first transistor (e.g., see Figure 4a , T3), the first transistor being connected to one electrode of a capacitor (node n1) that includes a polarizable material. In the example, node n1 can be powered via the second transistor by a control circuit such that the potential of node n1 is fixed during a write operation, such that the effective write voltage of the memory cell is in a capacitive voltage division ratio formed by the gate capacitance of the first transistor T3 and the capacitor, such that the effective write voltage is determined only by the coercive voltage of the capacitor. Further, in other examples, prior to a read operation, the potential of n1 can be set to a predefined value that is independent of any cumulative leakage current during a retention time, where the retention time is the time since the last write time. There is no data loss at node n1 due to cumulative leakage current.

[0032] According to an example of the present disclosure, in such a memory cell, the effective coercive voltage of the memory cell is independent of the capacitive voltage divider between the polarizable capacitor and the gate of the read transistor T3. In this way, the size of the polarizable capacitor can vary over a larger range to optimize the cell design for different applications. According to the present invention, increasing the capacitance of C1 or decreasing the gate capacitance of T3 will result in a much larger voltage offset during the polarization reversal of C1 during a read operation, thereby resulting in a much larger memory window of the memory cell without increasing the effective coercive voltage of the memory cell.

[0033] According to some examples of the present disclosure, more than one capacitor including a polarizable material can be connected to node n1 to increase the memory density without reducing the effective coercive voltage of the memory cell. Such a concept allows simultaneous execution of read operations of multiple capacitors including a polarizable material, resulting in a combined readout result of multiple stored information items referred to as "bits". Accordingly, logical operations between multiple stored bits can be performed inside the memory cell.

[0034] According to an example of the present disclosure, impedance matching for non-destructive read operations can be performed by measuring polarization-related leakage current flowing through a polarizable capacitor (e.g., a ferroelectric capacitor) when applying a read voltage less than the coercive voltage of the polarizable capacitor. This concept is also referred to herein as a polarizable tunnel junction (PTJ). Since the capacitance of node n1 is mainly determined by the polarizable capacitor C1 and the small gate capacitance of the read transistor T3 (without any bit lines directly connected to n1), a very small read current can be used to change the electric potential at node n1 during the read operation without switching the polarization of the polarizable capacitor. Additionally, the internal gain from the transconductance of the read transistor T3 of the memory cell can be used to amplify the read signal, enabling a very small polarizable tunnel junction (PTJ) with generally low read current density to perform fast read operations.

[0035] In an example of the present disclosure, the polarizable material of the polarizable capacitor of the polarizable tunnel junction is a ferroelectric material, and the tunnel junction is a ferroelectric tunnel junction (FTJ). According to one example, non-destructive read operations are performed by measuring polarization-related leakage current flowing through the ferroelectric capacitor when applying a read voltage less than the coercive voltage of the ferroelectric capacitor. In another example, the polarizable material of the tunnel junction is an antiferroelectric material or a relaxor-type material, and the tunnel junction is an antiferroelectric tunnel junction (AFTJ) or a relaxor-type tunnel junction (RTJ).

[0036] In the absence of constraints, the polarizable capacitor and the polarizable tunnel junction as described herein can be used as a memory cell or a memory element without the transistors and selector devices as described herein. According to the present disclosure, the polarizable tunnel junction capacitor includes a resonant tunneling barrier between the polarizable material and one electrode of the tunnel junction. In another example of the present disclosure, the polarizable material of the tunnel junction includes an antiferroelectric material or a relaxor-type material, and the tunnel junction includes an antiferroelectric tunnel junction (AFTJ) or a relaxor-type tunnel junction (RTJ). BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic diagram generally showing an example of a known FeFET memory cell.

[0038] Figure 2a is a schematic diagram generally showing an example of a known 1T1C FeRAM memory cell.

[0039] Figure 2b is a schematic diagram showing an example of a known 2T1C FeRAM memory cell.

[0040] Figure 2c is a schematic diagram showing another example of a known 2T1C FeRAM memory cell.

[0041] Figure 3a It is a schematic diagram generally showing an example of a known 1T1C ferroelectric memory cell, where a FeFET is implemented by connecting a ferroelectric capacitor to the gate of a FET.

[0042] Figure 3b It shows Figure 3a an example of the operation of a 1T1C ferroelectric memory cell in a voltage - time graph.

[0043] Figure 4a It is a schematic diagram generally showing an example of a 1T1S1C ferroelectric memory cell according to an example of the present disclosure, where a selector element is implemented as a transistor.

[0044] Figure 4b It is generally showing Figure 4a an example of a memory array composed of a plurality of 1T1S1C ferroelectric memory cells as shown in

[0045] Figure 5a It shows Figure 4a an example of the operation of a 1T1S1C ferroelectric memory cell in a voltage - time graph.

[0046] Figure 5b It shows Figure 4a another example of the operation of a 1T1S1C ferroelectric memory cell in a voltage - time graph.

[0047] Figure 6a It is a schematic diagram generally showing an example of a 1T1S1C ferroelectric memory cell according to an example of the present invention, where both the selector element and the read transistor are connected to a bit line.

[0048] Figure 6b It is a schematic diagram generally showing a 1T1S1C ferroelectric memory cell according to an example of the present disclosure, where the selector element is connected in parallel with the storage capacitor.

[0049] Figure 6c It is generally showing Figure 6a or Figure 6b an example of a memory array composed of a plurality of 1T1S1C ferroelectric memory cells as shown in

[0050] Figure 7 It shows Figure 6a an example of the operation of a T1S1C ferroelectric memory cell in a voltage - time graph.

[0051] Figure 8a It is a schematic diagram generally showing an example of a 1T1S1C ferroelectric memory cell according to an example of the present invention, where the selector element is implemented as a resistor.

[0052] Figure 8b is a schematic diagram generally showing an example of a memory array composed of a plurality of 1T1S1C ferroelectric memory cells as shown in Figure 8a .

[0053] Figure 9 is a voltage - time graph showing an example of the operation of a T1S1C ferroelectric memory cell of Figure 8a .

[0054] Figure 10a is a schematic diagram generally showing an example of a 1T2S2C ferroelectric memory cell according to an example of the present invention, in which two selector devices and two storage capacitors are implemented within one memory cell.

[0055] Figure 10b is a schematic diagram generally showing an example of a memory array composed of a plurality of 2T2S2C ferroelectric memory cells as shown in Figure 10a .

[0056] Figure 11a is a voltage - time graph showing an example of the operation of a 2T2S2C ferroelectric memory cell of Figure 10a .

[0057] Figure 11b is a voltage - time graph showing another example of the operation of a 2T2S2C ferroelectric memory cell of Figure 10a .

[0058] Figure 12 is a schematic diagram generally showing an example of a 1T1S1C ferroelectric memory cell, in which the second terminal of the storage capacitor is connected to a fixed potential.

[0059] Figure 13a is a schematic band diagram generally showing the on - state of a tunnel junction including two electrodes (1305, 1330) and a tunnel barrier (1340) having a two - layer stack including a thin dielectric material (1320) and a ferroelectric material (1310). The valence band E of the tunneling barrier (1340) having a two - layer stack (1310, 1320) is drawn V and the conduction band E B as well as the Fermi levels E FM1 and E FM2 of the two electrodes (1305, 1330) in the on - state.

[0060] Figure 13b is a schematic band diagram generally showing the off - state of a tunnel junction including two electrodes (1310, 1330) and a tunnel barrier (1340) having a two - layer stack including a thin dielectric material (1320) and a ferroelectric material (1310). The valence band E of the tunneling barrier (1340) including the double - layer stack (1310, 1320) is drawnV and the conduction band E B and the Fermi levels E of the two electrodes (1305, 1330) in the off state FM1 and E FM2 .

[0061] Figure 14a is a schematic band diagram showing the on state of a tunnel junction including a tunnel barrier (1410) of two electrodes (1405, 1430) and an antiferroelectric material according to the present disclosure. The valence band E of the tunneling barrier (1410) including the antiferroelectric material is drawn V and the conduction band E B and the Fermi levels E of the two electrodes (1405, 1430) in the on state FM1 and E FM2 .

[0062] Figure 14b is a schematic band diagram showing the off state of a tunnel junction composed of two electrodes (1405, 1430) and a tunnel barrier (1410) including an antiferroelectric material according to the present disclosure. The valence band E of the tunneling barrier (1410) including the antiferroelectric material is drawn V and the conduction band E B and the Fermi levels E of the two electrodes (1405, 1430) in the off state FM1 and E FM2 .

[0063] Figure 15a is a schematic band diagram showing the on state of a tunnel junction composed of two electrodes (1505, 1530) and a resonant tunneling barrier (1540) including a polarizable material (1510), two barriers (1520, 1522) and a dielectric material (1521) or a conductor (not shown) therebetween according to the present disclosure. The valence band E of the tunneling barrier (1540) including the polarizable material (1510), two barriers (1520, 1522) and the dielectric material (1521) is drawn V and the conduction band E B and the Fermi levels E of the two electrodes (1505, 1530) in the on state FM1 and E FM2 .

[0064] Figure 15bSchematic band diagram showing the on-state of a tunnel junction generally composed of two electrodes (1505, 1530) and a resonant tunneling barrier (1540) including a polarizable material (1510), two barriers (1520, 1522), and a dielectric material (1521) or conductor (not shown) therebetween. The valence band E of the tunneling barrier (1540) including the polarizable material (1510), two barriers (1520, 1522), and dielectric material (1521) is drawn V and the conduction band E B as well as the Fermi levels E FM1 and E FM2 of the two electrodes (1505, 1530) in the off-state DETAILED DESCRIPTION

[0065] As described herein, a polarizable memory cell includes: a capacitor having electrodes made of a metal or semiconductor material or a conductive oxide; and a layer of a polarizable material; a transistor; and a third circuit element adapted to act as a selector device, thereby forming a 1T1S1C polarizable memory cell. According to the present disclosure, the layer of polarizable material may be a ferroelectric material, an antiferroelectric material, or a relaxor ferroelectric material

[0066] Figure 4a Schematically depicts a ferroelectric memory cell 100 according to an example of the present disclosure. The memory cell 100 includes a ferroelectric capacitor C1 connected between a plate line terminal PL of the memory cell and the gate of a read transistor T3, wherein this connection forms a circuit node n1. One of the source terminal and the drain terminal of the read transistor T3 is connected to a source line SL terminal of the memory cell, while the other of the source terminal and the drain terminal of the read transistor T3 is connected to a fixed voltage reference, for example connected to a ground terminal, as Figure 4a schematically shown. Note that when the terms source terminal / drain terminal are used herein, if the first terminal of the transistor T3 is the source, then the second terminal of the transistor T3 is the drain, both independent of the gate of the transistor, wherein the gate is the third terminal of the transistor. Similarly, if the first terminal of the transistor is the drain terminal, then the second terminal of the transistor T3 is the source terminal, both independent of the gate of the transistor T3. Thus, the connectivity of the source terminal and the drain terminal of the transistor T3 can be interchanged without loss of functionality

[0067] In addition, one of the source terminal and the drain terminal of a select transistor T4 is connected to the node n1, while the other of the source terminal and the drain terminal of T4 is connected to a BL terminal of the memory cell. The gate of the select transistor T4 is connected to a word line WL terminal of the memory cell. A 1T1S1C memory cell is formed

[0068] In one example, asFigure 4a As shown, a memory array 110 is formed by connecting a plurality of 1T1S1C memory cells 100. In this way, many 1T1S1C memory cells 100 are connected to word lines, bit lines, source lines, and plate lines.

[0069] Figure 5a is a voltage - time graph showing the operation of the 1T1S1C ferroelectric memory cell 100 arranged in the memory array 110 according to one example.

[0070] When the selection transistor T4 is turned on by applying a suitable potential at the WL terminal, the BL is connected to the circuit node n1 via T4. For example, assume that T4 is an NFET device with a threshold voltage of V TH4 = 0.5V. T4 is turned on by applying a voltage to the WL terminal that is at least the threshold voltage of T4 more positive than the applied BL voltage. For example, if the BL voltage is set to 0V, a suitable WL voltage will be 1V to turn on T4. In another example, if the BL voltage is set to 1.5V, a suitable WL voltage will be 2.5V to turn on T4. In another example, assume that T4 is a PFET device. T4 is turned on by applying a voltage to the WL terminal that is at least the threshold voltage of T4 more negative than the applied BL voltage.

[0071] After T4 is turned on, the inversion of the ferroelectric polarization of C1 is performed by applying a positive voltage difference or a negative voltage difference between the PL terminal and the BL terminal of the memory cell, where the potential difference applied between PL and BL is greater than the coercive voltage of the ferroelectric capacitor C1. For example, if the coercive voltage of C1 is V CC1 = 1V, a suitable voltage amplitude applied between PL and BL will be V = 1.5V.

[0072] For example, in the case where a more positive potential is applied to PL compared to BL, the ferroelectric capacitor C1 switches to the negative polarization state, thereby representing the erased logic state "0". In contrast, in the case where a more negative potential is applied to PL compared to BL, the ferroelectric capacitor C1 switches to the positive polarization state, thereby representing the programmed logic state "1".

[0073] For a read operation, in the first step, the node n1 is pre - charged to a specific potential applied to the BL terminal via the selection transistor T4. In one example, for such a pre - charge operation, a suitable potential is applied to the WL terminal to turn on T4 so that the pre - charge potential is transferred from BL to the node n1. For example, if the pre - charge voltage applied to BL is 0.5V and the threshold voltage of T4 is V TH4= 0.5V, a suitable WL voltage is 1.5V to turn on T4. After a certain pre-charge time, T4 is switched back to the off state, for example, by applying another suitable voltage (such as 0V) to the WL terminal. In one example, the pre-charge potential is selected in such a way that the read transistor T3 is partially turned on when the voltage is below or above the threshold voltage of T3, or in another example, the transistor T3 is turned off. For example, if the threshold voltage of T3 is V TH3 = 0.3V, by pre-charging the node n1 to 0.5V, the transistor T3 will turn on and will operate in the linear region with an approximately linear gate voltage to drain current characteristic. In another example, if the threshold voltage of T3 is V TH3 = 0.3V, by pre-charging the node n1 to 0V, the transistor T3 will be turned off and will operate in the sub-threshold region with an exponential gate voltage to drain current characteristic.

[0074] In the second step of the read operation, a voltage pulse is applied to the PL terminal of the memory cell while T4 is turned off. The potential at the node n1 will change according to the capacitive voltage divider formed between the ferroelectric capacitor C1 and the gate capacitance of the read transistor T3. In one example, the amplitude of the voltage pulse at PW is selected in such a way that the potential difference generated between PL and the node n1 exceeds the coercive voltage of the ferroelectric capacitor C1, such that an induced ferroelectric polarization reversal occurs according to the previously stored polarization state of C1.

[0075] For example, in the case where C1 was previously programmed to the positive polarization state to store logic "1", by applying a positive read voltage to the PL terminal, a polarization reversal to the negative polarization state of C1 will occur. This polarization reversal will induce a polarization current that charges the node n1. Therefore, after applying a positive voltage pulse to PL, the potential of the node n1 will remain at a relatively high potential compared to the pre-charge value of the node n1, as shown by the arrow "I" in Figure 5a In contrast, in the case where C1 was previously written to the negative polarization state to store logic "0", after applying a positive read voltage pulse to PL, the potential of the node n1 will remain at approximately the pre-charge value, as shown by the horizontal arrow "II" in Figure 5a In one example, when assuming that the capacitance value of C1 and the capacitance value of the gate of the transistor T3 are similar, the capacitive voltage divider ratio will be approximately 0.5. Further assuming that the coercive voltage V of C1

[0076] = 1V, the pre-charge voltage of the node n1 is 0V, and the quiescent voltage of PL is 0V, then the voltage pulse V CC1 = 1V, the pre-charge voltage of the node n1 is 0V, and the quiescent voltage of PL is 0V, then the voltage pulse V PWA voltage of = 2.2V will generate a voltage of 1.1V at node n1 and a voltage difference of 1.1V between PL and n1, thus exceeding the coercive voltage of C1. Those skilled in the art will understand that the operating conditions of the memory cell can be adjusted by changing the capacitor divider ratio, the pre-charge voltage of n1, the pulse amplitude of PL, etc., so that the operation of the memory cell 100 can be optimized for a large number of different applications and boundary conditions, such as those designed for sense amplifiers that may be connected to SL.

[0077] In one example, in the third step of the read operation, to sense the storage state of the 1T1S1C memory cell, the drain voltage is applied to the read transistor T3 via the SL terminal of the memory cell 100. Therefore, a current will flow between SL and the ground terminal, and this current depends on the potential of n1 after the first two steps of the read operation. Therefore, this current depends on the polarization state of the previously stored ferroelectric capacitor C1. In one example, a sense amplifier connected to SL ( Figure 4a and Figure 4b not shown in) can be used to sense the current flow. For example, in the case where logic "1" has been stored as the positive polarization state of C1, compared with the case where logic "0" has been stored as the negative polarization state of C1, the sense amplifier will sense a relatively larger current at SL.

[0078] In one example, after the read operation, the ferroelectric capacitor C1 is erased to the negative polarization state. Therefore, this read operation is sometimes also called destructive readout. Therefore, the logic data is written back into the memory cell, which can be performed in a similar manner to the above write operation.

[0079] It is known that the leakage current flowing through the ferroelectric capacitor C1 when a potential is applied to the two terminals of the ferroelectric capacitor C1 may depend on the polarization state of the ferroelectric capacitor. For example, in the case where the ferroelectric capacitor switches to the negative polarization state, thus representing the erased logic state "0", compared with the case where the ferroelectric capacitor switches to the positive polarization state, thus representing the programmed logic state "1", when a non-zero voltage is applied to the two terminals of the capacitor, a relatively lower leakage current will flow through the capacitor, or vice versa. This difference in leakage current exists especially when a voltage lower than the coercive voltage of the ferroelectric capacitor is applied to its two terminals. A ferroelectric capacitor exhibiting such electrical behavior is sometimes called a ferroelectric tunnel junction.

[0080] Figure 5b is a voltage-time graph showing the operation of the 1T1S1C ferroelectric memory cell 100 arranged in the memory array 110 according to another example.

[0081] Note that performing the write operation is similar to that regarding Figure 5aThe write operation described in the first example. However, for the read operation, in the first step, node n1 is pre-charged to an appropriate potential applied to the BL terminal via the selection transistor T4. For the pre-charge operation, an appropriate potential is applied to the WL terminal to turn on T4, so that the pre-charge potential is transferred from BL to node n1. After an appropriate pre-charge time, T4 is switched back to the off state, for example, by applying another appropriate voltage (such as 0V) to the WL terminal. In one example, the pre-charge potential is selected in such a way that the read transistor T3 is partially turned on below or above the threshold voltage of T3, or in another example, such that transistor T3 is turned off.

[0082] In the second step of the read operation, a voltage pulse is applied to the PL terminal of the memory cell while T4 is off. Therefore, the potential at node n1 will change according to the capacitive voltage divider formed between the ferroelectric capacitor C1 and the gate capacitance of the read transistor T3. In one example, the amplitude of the voltage pulse at PW is selected such that the potential difference generated between PL and node n1 does not exceed the coercive voltage of the ferroelectric capacitor C1, so that according to the previously stored polarization state of C1, a leakage current will flow through the capacitor, thereby changing the potential at node n1.

[0083] For example, in the case where C1 was previously programmed to the positive polarization state to store logic "1", a relatively large leakage current will flow by applying a positive read voltage to the PL terminal. Therefore, after applying a positive voltage pulse to PL, the potential of n1 will remain at a relatively high potential compared to the pre-charge value, as Figure 5b shown by the arrow "I" in. In contrast, in the case where C1 was previously written to the negative polarization state to store logic "0", after applying a positive read voltage pulse to PL, the potential of n1 will remain at approximately the pre-charge value, as Figure 5b shown by the horizontal arrow "II" in.

[0084] It should be understood that the potential difference between PL and n1 can be positive or negative, thus inducing a positive or negative leakage current flowing through C1. Therefore, according to the potential difference between PL and n1, the potential of n1 will increase or decrease during the read operation. It should also be understood that the potential difference between PL and n1 can be adjusted by the pre-charge operation that defines the potential at n1, or by applying a corresponding voltage to PL during the read operation, or by combining these two measurements.

[0085] According to one example, in order to sense the storage state of the 1T1S1C memory cell, in the third step, the drain voltage can be applied to the read transistor T3 via the SL terminal of the memory cell. In this way, a current will flow between SL and the ground terminal, which depends on the potential of n1 after the first two steps of the read operation and thus on the polarization state of the previously stored ferroelectric capacitor C1. The current flow can be sensed, for example, by a sense amplifier connected to SL. For example, in the case where a logic "1" is stored as the positive polarization state of C1, the sense amplifier can sense a relatively larger current at SL compared to the case where a logic "0" is stored as the negative polarization state of C1.

[0086] In one example, in order to prevent a write operation in an unselected cell, the WL potential of the unselected cell is maintained at a voltage such that the select transistor T4 is turned off during the programming phase. In this way, any programming pulse at BL will not affect the potential of n1 and thus will not cause a polarization inversion of C1. In addition, a programming pulse or an erase pulse at PL will cause a change in the potential at n1, which is determined by a capacitive voltage divider formed between C1 and the gate capacitance of T3. By an appropriate design of this capacitive voltage divider, it can be ensured that the potential on C1 is reduced below the coercive voltage of the ferroelectric capacitor C1. In this way, the programming pulse at BL will not affect the potential of n1 and thus will not cause a polarization inversion of C1.

[0087] It should be understood that Figure 5a and Figure 5b the voltage-time diagrams shown in

[0088] are for illustrative purposes only to illustrate an example of the operating principle of an exemplary ferroelectric memory cell. It should also be understood that additional control signals can be applied to WL, BL, SL, or PL in the memory array to improve the programming or reading conditions and mitigate the read or write interference effects. For example, the potential of n1 of each passive memory cell connected to a BL can be precharged to a potential such that T3 of each passive cell is turned off during the read operation. In this way, an unwanted leakage current flowing through the passive cell to SL is prevented, which would deteriorate the signal-to-noise ratio of the SA.

[0089] It should also be understood that the polarization state of the ferroelectric capacitor C1 can be switched to an intermediate polarization state, where a first portion of the ferroelectric material can be polarized to a positive polarization state, a second portion of the ferroelectric material can be polarized to a negative polarization state, and a third portion of the ferroelectric material can be non-polarized. In this way, depending on the relationship of the positive-polarity, negative-polarity, or non-polarized material, multiple different polarization levels can be programmed into the ferroelectric capacitor C1. In this way, more than two logic values can be stored in the ferroelectric capacitor C1. During the read operation of the ferroelectric memory cell, this intermediate polarization state can be represented as an intermediate voltage level at the node n1 or as an intermediate source line read current level ISL.

[0090] Figure 6a Schematically shows a ferroelectric 1T1S1C memory cell 200 according to an example of the present disclosure. According to such an example, the first source / drain terminal of the read transistor T3 is connected to the BL. Figure 6b Schematically shows a ferroelectric 1T1S1C memory cell 200 according to another example of the present disclosure. According to such an example, the second source / drain terminal of the select transistor T4 is connected to the PL. In Figure 6a and Figure 6b configuration, the SL can be omitted, thereby reducing the wiring complexity of the memory array.

[0091] Figure 6c Generally shows a memory array 210 formed by connecting a plurality of 1T1S1C memory cells 200. In this way, many 1T1S1C memory cells 200 can be connected to word lines, bit lines, and plate lines.

[0092] According to the example, the read and write operations for setting the polarization state of C1 of the 1T1S1C memory cell are implemented in a manner similar to that described in the first example of the memory array 110. However, in order to ensure that no large current flows from the BL through the read transistor T3 during the programming operation, in one example, the BL voltage is selected such that the voltage generated between the source terminal and the drain terminal of the read transistor T3 is close to zero. Figure 6a The read and write operations for setting the polarization state of C1 of the 1T1S1C memory cell are implemented in a manner similar to that described in the first example of the memory array 110. However, in order to ensure that no large current flows from the BL through the read transistor T3 during the programming operation, in one example, the BL voltage is selected such that the voltage generated between the source terminal and the drain terminal of the read transistor T3 is close to zero.

[0093] Figure 7 Is a voltage-time diagram showing an example of the operation of the 1T1S1C ferroelectric memory cell 200 arranged in the memory array 210.

[0094] In one example, the programming operation of the memory cell 200 in the memory cell array 210 is performed by applying a programming pulse with a negative amplitude to the PW terminal instead of applying a programming pulse with a positive amplitude to the BL of the memory cell 200. In this way, the ferroelectric capacitor will be programmed to a positive polarization state, thereby representing the logic state "1", while the BL terminal can be kept at, for example, the ground potential.

[0095] It should be understood that the fixed potential connected to the second source / drain terminal of T3 can be different from the ground potential. Additionally, the BL voltage during the programming operation can also be selected to be different from the ground potential while still ensuring a low current flows through T3 during the programming / erasing operation.

[0096] In another example, during the programming operation of the memory cell 200 in the memory cell array 210, the fixed potential applied to the second source / drain terminal of the read transistor T3 can be selected to be within the range of the coercive voltage of the ferroelectric capacitor C1. In this way, during the write operation, the BL voltage is also set to a voltage similar to the coercive voltage of C1. Then, the negative or positive polarization state of C1 is sensed by applying 0V or twice the coercive voltage of C1 to the PL terminal of the memory cell. In this way, the memory cell is programmed and erased by applying pulses with a positive voltage polarity only to different terminals of the memory cell.

[0097] In another example of the present disclosure, the selection transistor T4 of the combined ferroelectric memory cell is replaced by a two-terminal selector device (such as a diode, resistor, etc.) that may have linear or non-linear current-voltage characteristics, thereby forming a 1T1S1C ferroelectric memory cell. As Figure 8a shown in the example, the first terminal of the resistance device R is connected to the node n1, and the second terminal is connected to the bit line BL, for example. In this way, the potential at the node n1 will be controlled by the BL potential via R during the hold time and can be pre-charged during the read operation.

[0098] In the example, as Figure 8b shown, a memory array 310 is formed by connecting multiple 1T1S1C memory cells 300. In this way, many 1T1S1C memory cells 300 can be connected to the source line, bit line, and plate line.

[0099] Figure 9 is a voltage-time graph showing an example of the operation of the 1T1S1C ferroelectric memory cell 300 arranged in the memory array 310.

[0100] During the write operation, in order to switch the ferroelectric polarization of C1, a positive or negative potential is applied to the PL such that the potential difference between n1 and the PL exceeds the coercive voltage of the ferroelectric capacitor. For example, for a pulse with a duration significantly longer than the RC delay time (where this RC delay is approximately calculated as the product of the resistance R and the capacitance of the floating node C n1 ), the potential at n1 will remain at approximately the BL potential. For such a long pulse, the influence of the capacitive voltage divider formed between C1 and the gate of T3 on the potential at the node n1 is negligible.

[0101] For example, if the capacitance of capacitor C1 is approximately 100 fF and the resistance of R is approximately 1 MΩ, the resulting RC delay time will be in the range of 100 ns. Therefore, when a programming pulse with a duration of, for example, 10 μs and rise and fall times of the pulse edges of, for example, 1 μs is applied, the potential of node n1 will remain at approximately the BL potential.

[0102] During a read operation, in order to switch the ferroelectric polarization of C1, a positive or negative potential is applied to PL such that the potential difference between n1 and PL exceeds the coercive voltage of the ferroelectric capacitor. For example, for a pulse with a duration significantly shorter than the RC delay time (where this RC delay is approximately calculated as the product of the resistance R and the capacitance of the floating node C n1 ), the potential at n1 will be mainly determined by the capacitive voltage divider formed between C1 and the gate of T3. For such short pulses, the influence of the resistance element R on the potential at node n1 is negligible, and the read operation can be performed in a similar manner as described above for Figure 4a the memory cell 100 in

[0103] For example, if the capacitance of capacitor C1 is approximately 100 fF and the resistance of R is approximately 1 MΩ, the resulting RC delay time will be in the range of 100 ns. Therefore, when a read pulse with a duration of, for example, 10 ns and rise and fall times of the pulse edges of, for example, 1 ns is applied to PL, the potential of node n1 will be mainly determined by the capacitive voltage divider formed between C1 and the gate of T3, because for such a short pulse duration, charge compensation via the resistance element R is negligible.

[0104] To prevent programming or erasing operations of unselected cells, for example, the potential at node n1 can be precharged via BL to half or one-third of the amplitude of the programming pulse applied to PL. In this way, the coercive voltage of the ferroelectric capacitor will not be reached, thereby preventing programming or erasing of unselected memory cells.

[0105] It should be understood that in another embodiment of the present invention, the second terminal of the resistance element R can be connected to a terminal other than BL, such as WL or SL, where this terminal can be controlled by a control circuit. In this case, the operation scheme must be adjusted accordingly.

[0106] Figure 10a A ferroelectric 1T1S2C memory cell 400 according to another example of the present disclosure is schematically shown. According to one such example, two ferroelectric capacitors C1 and C2 are connected to node n1 of the memory cell 400 such that the select transistor T4 and the read transistor T3 are shared between the two ferroelectric capacitors C1 and C2. In addition, each ferroelectric capacitor C1 and C2 is connected to a respective plate line PL-A and PL-B.

[0107] By connecting a plurality of 1T1S2C memory cells in the arrangement as Figure 10b shown to form a memory array 410. In this way, many 1T1S2C memory cells 400 will be connected to word lines, bit lines, and plate lines.

[0108] Figure 11a A voltage-time graph showing an example of the operation of the 1T1S2C ferroelectric memory cell 400 arranged in the memory array 410 is shown.

[0109] In one example, the read and write operations of the 1T1S2C memory cell are implemented in a manner similar to that described in the second example of the memory array 210. However, in order to write or read the information of only one ferroelectric capacitor, the write / read signal is applied to only one PL in time, as Figure 11a shown in the example voltage-time graph. For example, when accessing Figure 10a the capacitor C1 of the ferroelectric memory cell 400 in, only PL-A is used during the read / write operation, while PL-B is held at a quiescent potential. Similarly, when accessing Figure 10a the capacitor C2 of the ferroelectric memory cell 400 in, only PL-B is used during the read / write operation, while PL-A is held at a quiescent potential.

[0110] It should be understood that more than two ferroelectric capacitors and more than two plate lines can be used to form a 1T1SxC memory cell, where x represents the number of ferroelectric capacitors. In this way, the memory cell is used to store more than 2 bits of information, while only sharing one select transistor T4 and one read transistor T3 in one memory cell.

[0111] In one example, the read operation of the 1T1SxC memory cell having at least two ferroelectric capacitors can be implemented in a way that simultaneously reads two or more capacitors. According to such an example, logical operations can be performed between the bits stored separately from different capacitors. For the 1T1SxC memory cell having two ferroelectric capacitors C1 and C2, such logical operations between the two bits of the 1T1S2C memory cell will be described as follows.

[0112] In one example, as Figure 11bAs shown, in the first case, logic "0" is written to ferroelectric capacitors C1 and C2. When a read operation is performed simultaneously on both capacitors, the electric potential at node n1 will remain approximately at the pre-charge level V0, which corresponds to the low read current I0 to be sensed at BL. In the second case, logic "1" is written to one of the ferroelectric capacitors, and logic "0" is written to the second ferroelectric capacitor. When a read operation is performed simultaneously on both capacitors, the electric potential at node n1 will increase to the intermediate level V1, which corresponds to the intermediate read current I1 to be sensed at BL. In the third case, logic "1" is written to both ferroelectric capacitors. When a read operation is performed simultaneously on both capacitors, the electric potential at node n1 will increase to the relatively high level V2, which corresponds to the relatively high read current I2 to be sensed at BL. In this way, the sensed current at BL will depend on the two logic states previously written to ferroelectric capacitors C1 and C2.

[0113] In the case where the sense amplifier connected to BL is configured in such a way that only I2 is considered to represent logic "1", a logical AND operation is performed between the logic states programmed for C1 and C2. In another case where the sense amplifier connected to BL is configured in such a way that only I0 is considered to represent logic "0", a logical OR operation is performed between the logic states programmed for C1 and C2.

[0114] It should be understood that a simultaneous read operation of two or more capacitors in a 1T1SxC combined ferroelectric memory cell can be performed based on polarization-dependent leakage current, as discussed for a 1T1S1C combined ferroelectric memory cell. In this case, the leakage current flowing through each ferroelectric capacitor during the read operation will accumulate at node n1, and thus will jointly change the electric potential at node n1. In this way, a logical operation between the logic states stored in each ferroelectric capacitor can be performed.

[0115] In another example of the present disclosure, the second terminal of ferroelectric capacitor C1 can be connected to a fixed electric potential, such as connected to the ground electric potential, as Figure 12As shown schematically. In this configuration, a write operation for switching the polarization state of the ferroelectric capacitor C1 is performed by turning on T4 and applying a positive or negative voltage to the BL, where the voltage exceeds the coercive voltage of the ferroelectric capacitor C1. To read the polarization state of the capacitor C1, as described above, the node n1 is pre-charged via T4 and the BL. After turning off T4, a positive voltage pulse or a negative voltage pulse is applied to both the SL and the BL simultaneously. In this way, the electric potential at the node n1 will be determined by the voltage pulse amplitude applied to both the SL and the BL and the capacitive voltage divider between C1 and the gate of T3. In one example, the amplitude of the voltage pulse is selected such that the electric potential at n1 exceeds the coercive voltage of the ferroelectric capacitor, so as to sense the polarization inversion of C1 according to the stored logic state.

[0116] It should be understood that the present invention is not limited to the different implementations and corresponding operation schemes of the 1T1SxC combined ferroelectric memory cell as described in the above examples. Note that combinations of different implementations are possible and are understood as further embodiments of the present invention.

[0117] According to the present disclosure, a polarizable memory cell includes a small-scale polarizable capacitor having only a small amount of switching charge or a small read current. In one example of the present disclosure, the capacitor is a ferroelectric capacitor (FeCAP) using a ferroelectric material as the storage material. In another example of the present disclosure, the capacitor is an antiferroelectric capacitor (AFeCAP) using an antiferroelectric material or a relaxor material as the storage material. For the AFeCAP, the antiferroelectric material or the relaxor material is sandwiched between two electrodes having different work function values in the capacitor. Therefore, the difference in the work function values between the two electrodes causes a built-in (internal) bias electric field, which shifts the pinched hysteresis loop (PHL) of the antiferroelectric material or the relaxor material. In this way, a part of the P-V hysteresis loop is centered at 0V, enabling the AFeCAP to be used as a binary, non-volatile memory element. The ferroelectric material and the antiferroelectric material used herein refer to materials that are at least partially in a ferroelectric state or an antiferroelectric state and also include oxygen and any one of the group consisting of Hf, Zr, and (Hf, Zr) as a main component.

[0118] According to the present disclosure, a polarizable memory cell includes a small-scale polarizable tunnel junction capacitor having only a small read current. In one example, the polarizable material of the tunnel junction capacitor is a ferroelectric material, and the tunnel junction is a ferroelectric tunnel junction (FTJ). In another example of the present disclosure, the polarizable material of the tunnel junction is an antiferroelectric material or a relaxor material, and the tunnel junction is an antiferroelectric tunnel junction (AFTJ) or a relaxor tunnel junction (RTJ). For an AFTJ or RTJ, the antiferroelectric material or the relaxor material is sandwiched between two electrodes having different work function values in the capacitor. Thus, the difference in work function values between the two electrodes causes a built-in (internal) bias electric field that shifts the pinched hysteresis loop (PHL) of the antiferroelectric material or the relaxor material. In this way, a portion of the P-V hysteresis loop is centered at 0 V, enabling the device to be used as a binary, non-volatile memory element. The ferroelectric material and the antiferroelectric material used herein may refer to materials that are at least partially in a ferroelectric state or an antiferroelectric state and also include oxygen and any one of the group consisting of Hf, Zr, and (Hf, Zr) as a main component.

[0119] In one example, the first electrode of the tunnel junction is platinum (1430), and the second electrode is TiN (1405), as Figure 14a shown. According to such an example, the barrier (1410) of the polarizable tunneling barrier is 2 nm of antiferroelectric zirconia (ZrO2). The band diagram of the tunnel junction capacitor including the polarizable barrier is plotted in Figure 14a . In the on state, electrons can tunnel from platinum (1430) to the second electrode (1405). The valence band E V and the conduction band E B of the tunneling barrier (1410) composed of the antiferroelectric material and the Fermi levels E FM1 and E FM2 of the two electrodes (1405, 1430) are plotted. The band diagram of the off state is plotted in Figure 13b . Since the effective tunneling barrier thickness is too high, tunneling is not possible.

[0120] According to the present disclosure, the polarizable tunnel junction capacitor includes an interface layer between the polarizable material and one of the electrodes of the tunnel junction. The interface layer is a barrier layer. In one example, the interface layer is a low-k high-bandgap material. The low-k material causes a high field drop across the interface layer. The interface layer can further prevent the spontaneous reverse switching of the polarizable material by modulating the energy potential to improve the retention of the device.

[0121] According to the present disclosure, the polarizable material may include a thin intermediate layer to improve the grain size of the polarizable material.

[0122] In another example, a polarizable tunnel junction capacitor includes a resonant tunneling barrier between a polarizable material and an electrode, such as shown in FIGS. 15 and Figure 15b . The resonant tunneling barrier can be thicker compared to the polarizable layer. In one example, the resonant tunneling barrier has a smaller thickness compared to the polarizable layer. In one example, it is advantageous to make the tunneling barrier from multiple individual layers. In one example, the layer has a k value lower than that of the ferroelectric k f (i.e., SiO2 for SiHfO ferroelectric) k ba . The polarization-induced electric field in the barrier layer is approximately k f / k ba times larger than the electric field in the ferroelectric. Since the tunneling probability in a resonant tunneling diode depends not only on the electric field but also on the density of states on both sides, the resonant tunneling barrier can be fabricated in such a way that the current density first increases with the increase of the field for improved reading, but when the applied field for writing is further increased, the current density decreases again.

[0123] In one example, one electrode of the tunnel junction is made of TiN or platinum (1530), and the second electrode is made of TiN (1505), as Figure 15a shown. In such an example, the tunneling barrier consists of a polarizable layer and a resonant tunneling barrier. The two barriers (1520, 1522) of the resonant tunneling barrier are 0.7 nm of silicon dioxide, and between the two barrier materials, a lower bandgap material such as HfO or a conductive material (such as Ti, TiN) with a thickness of to is used. The polarizable material (1510) is 7 nm thick ferroelectric Hf. For the on state, the band diagram of the tunnel junction capacitor including the resonant tunneling barrier is plotted in FIG. 15. The valence band E V and the conduction band E B of the tunneling barrier (1540) composed of the polarizable material (1510), the two barriers (1520, 1522), and the dielectric material (1521), as well as the Fermi levels E FM1 and E FM2 of the two electrodes (1505, 1530) in the on state are plotted. Instead of the dielectric material (1521), a conductive material can be used. In the on state, electrons can tunnel from the first electrode (1530) to the second electrode (1505). Since the tunneling thickness for each barrier is small, the tunneling probability and thus the tunnel current are higher and have improved reliability compared to known tunnel junction capacitors ( Figure 13a and Figure 13b ). The band diagram of the off state is as Figure 13bAs shown. Note that tunneling is not possible because the effective barrier thickness is too high and there is no alignment of the conduction bands of layer (1521) and the first electrode (1530).

[0124] In one example, the electrodes of the polarizable capacitor and the polarizable tunnel junction capacitor can include any one or more suitable conductive metals, including but not limited to TiN, TaN, TaCN, WCN, Ru, Re, RuO, Pt, Ir, IrO, Ti, TiAlN, TaAlN, W, WN, C, Si, Ge, SiGe, and NbCN. The electrodes can be a combination with one or more conductive layers.

[0125] As used herein, the terms "ferroelectric material" and "antiferroelectric material" refer to materials that are at least partially in a ferroelectric state or an antiferroelectric state and include oxygen and any one of the group consisting of Hf, Zr, and (Hf, Zr) as a main component. In one example, the ferroelectric material can include any one of HfO2, ZrO2, any ratio of Hf and Zr combined with oxygen (e.g., ZrxHf1-xO2, where x < 1), and any combination thereof. Additionally, as used herein, the term "main component" refers to any suitable amount of O and any one or combination of Hf, Zr, and (Hf, Zr) per volume content (e.g., unit cell), which is higher compared to other components or further additives introduced into the ferroelectric material oxide layer in any suitable manner.

[0126] In one example, the antiferroelectric material can be a field-induced ferroelectric type layer including ZraXbO2, where X is an element in the periodic table with an ionic radius smaller than Zr, and a > 0, b > 0. Suitable X elements can be one of Hf, Si, Al, Ge in the second group of the periodic table, and a > 0, b > 0. In addition to this combination, the antiferroelectric material layer can also include HfaXbO2, where X is an element in the periodic table with an ionic radius smaller than Hf, and a > 0, b > 0. Suitable elements for this combination can be one of the elements within the second group (Zr, Si, Al, Ge) of the periodic table, where a > 0, b < 0 as above.

[0127] In another example, the antiferroelectric material can be of the field-induced ferroelectric type composed of a pure ZrO2 layer or including a dielectric material based on ZrO2 or HfO2. In another example, the antiferroelectric material can be a relaxor ferroelectric material (e.g., BaTiO3 or PbMg1 / 3Nb2 / 3O3). In another example, the antiferroelectric material can be an antiferroelectric type material such as PbZrO3.

[0128] In one example, the interfacial layer between an electrode and the polarizable material is composed of Al2O3, SiO2, or other dielectrics with a low dielectric constant and a high bandgap.

[0129] In one example, a thin intermediate layer or multiple thin intermediate layers can be used within the polarizable material to reduce the grain size, improve reliability, and reduce the current flowing through the polarizable tunnel junction. Using a ferroelectric or antiferroelectric material including oxygen and any one of the main components in the group consisting of Hf, Zr, and (Hf, Zr) as described herein, the thin intermediate layer can include La2O5, Sc2O3, SrO, or other high bandgap dielectrics comparable to the bandgap of ZrO2 or doped HfO2.

[0130] For example, for a polarizable capacitor, the electrode layer can be deposited on the support structure via any suitable process. Some examples of such forming processes that can be used to form the conductive layer include atomic layer deposition (ALD), metal-organic atomic layer deposition (MOALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or any other suitable deposition technique that facilitates the formation of the conductive layer using one or more suitable conductive materials as described previously herein. The conductive layer can be formed to have a suitable thickness dimension, for example, in the range of about 2 nm to about 5000 nm. In an exemplary embodiment, the thickness range of the conductive layer can be in the range of about 2 nm to about 500 nm or in the range of about 2 nm to about 50 nm.

[0131] In the examples described herein, any one of atomic layer deposition (ALD), metal-organic atomic layer deposition (MOALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE) deposition, sol-gel, or any other suitable deposition technique that facilitates the formation of a layer including the polarizable materials described herein (i.e., oxygen and at least one of Hf and Zr) can be used to form the polarizable material, wherein the growth of each layer can be single crystal or polycrystalline. Any suitable number and type of precursors can be used to introduce elements such as Hf and Zr into the layer using any of the deposition techniques described herein. The dielectric layer and the polarizable layer are formed to have a suitable thickness, for example, in the range of about 2 nm to about 5000 nm. In one example, the thickness range of the two layers can be in the range of about 2 nm to about 500 nm or in the range of about 2 nm to about 50 nm.

[0132] Although specific embodiments have been shown and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present application. This application is intended to cover modifications or variations of the specific examples described herein. Thus, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A memory cell, comprising: A node; A layer stack, comprising: A first electrode; A second electrode connected to the node; A polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states; A first transistor having a source, a drain, and a gate terminal, the gate terminal being connected to the node; and A selector element having at least a first terminal and a second terminal, the second terminal being connected to the node, The first electrode of the layer stack is connected to a plate line, and one of the source and the drain of the first transistor is connected to a reference voltage, The selector element includes a second transistor having a source, a drain, and a gate, wherein one of the source and the drain of the second transistor represents the second terminal of the selector element and is connected to the node, and the gate is connected to a word line, The other of the source and the drain of the first transistor is connected to a selection line, and the other of the source and the drain of the second transistor represents the first terminal of the selector element and is connected to a bit line.

2. The memory cell according to claim 1, wherein the layer stack comprises a ferroelectric material.

3. The memory cell according to claim 1, wherein the reference voltage includes ground.

4. A memory cell, comprising: A node; A layer stack, comprising: A first electrode; A second electrode connected to the node; A polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states; A first transistor having a source, a drain, and a gate terminal, the gate terminal being connected to the node; and A selector element having at least a first terminal and a second terminal, the second terminal being connected to the node, The first electrode of the layer stack is connected to a plate line, and one of the source and the drain of the first transistor is connected to a reference voltage, The selector element includes a second transistor having a source, a drain, and a gate, wherein one of the source and the drain of the second transistor represents the second terminal of the selector element and is connected to the node, and the gate is connected to a word line, The other of the source and the drain of the first transistor is connected to a bit line, and the other of the source and the drain of the second transistor represents the first terminal of the selector element and is connected to the bit line.

5. The memory cell according to claim 4, wherein the layer stack includes a plurality of layer stacks, and the plate line includes a plurality of plate lines, the first electrode of each layer stack is connected to the node, and the second electrode of each layer stack is connected to a different one of the plurality of plate lines.

6. A memory cell, comprising: A node; A layer stack, comprising: A first electrode; A second electrode connected to the node; A polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states; A first transistor having a source, a drain, and a gate terminal, the gate terminal being connected to the node; and A selector element having at least a first terminal and a second terminal, the second terminal being connected to the node, The first electrode of the layer stack is connected to a plate line, and one of the source and the drain of the first transistor is connected to a reference voltage, The selector element includes a second transistor having a source, a drain, and a gate. One of the source and the drain of the second transistor represents the second terminal of the selector element and is connected to the node, and the gate is connected to a word line, The other of the source and the drain of the first transistor is connected to a bit line, and the other of the source and the drain of the second transistor represents the first terminal of the selector element and is connected to the plate line.

7. A memory cell, comprising: A node; A layer stack, comprising: A first electrode; A second electrode connected to the node; A polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states; A first transistor having a source, a drain, and a gate terminal, the gate terminal being connected to the node; and A selector element having at least a first terminal and a second terminal, the second terminal being connected to the node, The first electrode of the layer stack is connected to a plate line, and one of the source and the drain of the first transistor is connected to a reference voltage, The other of the source and the drain of the first transistor is connected to a select line, the selector element includes a two-terminal element having a resistance, and the first terminal of the selector element is connected to a bit line.

8. The memory cell according to claim 7, wherein the selector element includes a resistor.

9. The memory cell according to claim 7, wherein the selector element includes a non-linear element having a non-linear resistance.

10. The memory cell according to claim 9, wherein the selector element includes one of a diode, a threshold switch, and a field-assisted switch.

11. A memory cell, comprising: A node; A layer stack, comprising: A first electrode; A second electrode connected to the node; A polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states; A first transistor having a source, a drain, and a gate terminal, the gate terminal being connected to the node; and A selector element having at least a first terminal and a second terminal, the second terminal being connected to the node, Wherein: The first electrode of the layer stack is connected to a reference voltage; One of the source and the drain of the first transistor is connected to a select line, and the other of the source and the drain of the first transistor is connected to a bit line; and The selector element includes a second transistor having a source, a drain, and a gate. One of the source and the drain of the second transistor represents the second terminal of the selector element and is connected to the node, the other of the source and the drain of the second transistor represents the first terminal of the selector element and is connected to the bit line, and the gate is connected to a word line.

12. A method of operating a memory cell, the memory cell having: a layer stack including a first electrode, a second electrode connected to a node, and a polarizable material layer disposed between the first electrode and the second electrode and having at least two polarization states; A read transistor having a gate terminal connected to the node; and a selector element having a first terminal and a second terminal, wherein the second terminal is connected to the node, the method comprising: setting a polarization state of the polarizable material layer to a polarization state selected from at least two polarization states of a ferroelectric capacitance by applying a voltage between the first electrode of the layer stack and the node such that a voltage across the polarizable material layer of the layer stack is greater than a coercive voltage of the polarizable material layer of the layer stack.

13. The method according to claim 12, the method further comprising: reading the polarization state of the polarizable material layer by applying a voltage pulse to the first electrode of the layer stack such that a voltage on the node generated by a capacitive voltage divider formed by the layer stack and a gate capacitance of the read transistor represents the polarization state.

14. The method according to claim 13, wherein the selector element comprises a selection transistor having a drain terminal or a source terminal representing the second terminal, a drain terminal or a source terminal representing the first terminal and connected to the bit line, and a gate terminal connected to the word line, and wherein, One of the drain terminal and the source terminal of the read transistor is connected to a reference voltage, and the other of the drain terminal and the source terminal of the read transistor is connected to a select line, wherein applying a voltage between the plate line and the bit line when setting the polarization state includes: turning on the select transistor by applying a voltage to the word line that is greater than a threshold of the select transistor by the voltage on the bit line, such that the node is connected to the bit line; and applying a voltage to the plate line and applying a voltage to the bit line such that a voltage across the polarizable material layer of the layer stack is greater than a coercive voltage of the polarizable material layer.

15. The method according to claim 14, wherein, If an amplitude of the plate line voltage is less than an amplitude of the bit line voltage, the polarization state of the polarizable material layer is set to a positive polarization state, and if the amplitude of the plate line voltage is greater than the amplitude of the bit line voltage, the polarization state of the polarizable material layer is set to a negative polarization state.

16. The method according to claim 14, wherein When reading the polarization state, applying the voltage pulse to the plate line includes: applying a voltage to the word line to turn off the select transistor; applying the voltage pulse to the plate line, the amplitude of the voltage pulse being selected to generate a potential difference across the polarizable material layer that exceeds the coercive voltage of the polarizable material layer; and applying a voltage to the sense line to enable a current to flow through the read transistor, the current depending on the potential of the node and indicating the polarization state of the polarizable material layer.

17. The method according to claim 13, wherein the selector element comprises a selection transistor having a drain terminal or a source terminal representing the second terminal, a drain terminal or a source terminal representing the first terminal and connected to the bit line, and a gate terminal connected to the word line, and wherein, One of the drain terminal and the source terminal of the read transistor is connected to a reference voltage, and the other of the drain terminal and the source terminal of the read transistor is connected to a select line, wherein when reading the polarization state, applying the voltage pulse to the plate line includes: applying a voltage to the word line to turn off the select transistor; applying the voltage pulse to the plate line, the amplitude of the voltage pulse being selected to generate a potential difference across the polarizable material layer that does not exceed the coercive voltage of the polarizable material layer, inducing a polarization-related current flowing through the layer stack, the polarization-related current indicating the polarization state of the polarizable material layer; and A voltage is applied to the sense line to enable current to flow through the read transistor, the current depending on the potential of the node and indicating the polarization state of the polarizable material layer.

18. The method according to claim 13, wherein the selector element comprises a selection transistor having a drain terminal or a source terminal representing the second terminal, a drain terminal or a source terminal representing the first terminal and connected to the bit line, and a gate terminal connected to the word line, and wherein, One of the drain terminal and the source terminal of the read transistor is connected to a reference voltage, and the other of the drain terminal and the source terminal of the read transistor is connected to a select line. Before turning off the select transistor, the method includes pre-charging the node by the following steps: Applying a voltage to the word line to turn on the select transistor; and Applying a voltage to the bit line for a selected period of time.

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