Storage and calculation integrated chip and on-chip training method thereof

Abstract

The invention provides a storage and calculation integrated chip which comprises an MAC unit and an auxiliary unit which are arranged in pairs, the MAC unit is used for carrying out multiply-accumulate calculation on weight data and input data, the auxiliary unit is used for carrying out multiply-accumulate calculation on the weight data and auxiliary data, and the auxiliary data are obtained after the input data are disordered; the logic unit is used for respectively performing ReLU activation and pooling operation on the multiply-accumulate calculation results of the MAC unit and the auxiliary unit to obtain an output result; the calculation module is also used for calculating an output difference value matrix and calculating an input difference value matrix if the convolutional layer needs to be trained; the auxiliary unit is also used for carrying out matrix multiplication calculation on the output difference value matrix and the input difference value matrix to obtain a weight updating matrix; and the control unit is used for executing the executable instruction so as to control the data flows of the MAC unit, the auxiliary unit and the logic unit. According to the invention, independent training among the convolution layers can be realized.

Description

Technical Field

[0001] This invention relates to the field of memory design technology, and in particular to an in-memory computing chip and its on-chip training method. Background Technology

[0002] In recent years, with the rapid development of deep learning and the explosive growth of data volume, the depth and complexity of network models have gradually increased, leading to a significant increase in computational demands. Traditional computing architectures face the challenge of handling such massive amounts of data and complex models, and the frequent data transfer between computing and storage resources has become a bottleneck, limiting improvements in computing efficiency and energy utilization. In light of this, in-memory computing chips have demonstrated significant advantages in energy efficiency.

[0003] Currently, in-memory computing chips are widely used in convolutional neural networks (CNNs) to accelerate the training and inference processes of CNN models. However, existing on-chip training methods using gradient descent have the following problems: they cannot achieve independent training between layers; when training a certain convolutional layer, it is necessary to call a large number of weights and outputs from the previous layer and calculate derivatives one after another; the data between layers is closely related, making it difficult to fine-tune a certain convolutional layer. Summary of the Invention

[0004] In view of this, the present invention provides an in-memory computing chip and its on-chip training method, which can realize independent training between each convolutional layer.

[0005] In a first aspect, the present invention provides an in-memory computing chip, comprising: The MAC unit and auxiliary unit are set in pairs, and a pair of MAC units and auxiliary units corresponds to a convolutional layer of the convolutional neural network. The MAC unit is used to store the weight data of the convolutional layer and perform multiplication and accumulation calculation on the weight data and the input data. The auxiliary unit is used to store the weight data of the convolutional layer and perform multiplication and accumulation calculation on the weight data and the auxiliary data. The auxiliary data is obtained by shuffling the input data. The logic unit is configured to perform ReLU activation and pooling operations on the multiplication and accumulation calculation results of the MAC unit and the auxiliary unit, respectively, to obtain a first output result based on the input data and a second output result based on the auxiliary data; it is also configured to calculate the output difference between the first output result and the second output result if a convolutional layer needs to be trained, and to perform thresholding processing on the output difference to obtain an output difference matrix; and to calculate the input difference between the auxiliary data and the input data, and to perform thresholding processing on the input difference to obtain an input difference matrix. The auxiliary unit is also used to store the output difference matrix and perform matrix multiplication on the output difference matrix and the input difference matrix to obtain a weight update matrix, so as to update the weight data stored in the MAC unit and the auxiliary unit. as well as, The control unit is used to execute executable instructions to control the data flow of the MAC unit, auxiliary unit, and logic unit.

[0006] Optionally, the structure of the auxiliary unit is the same as that of the MAC unit. Both the MAC unit and the auxiliary unit include: a memory array, which is composed of memory units in a horizontal array. Each memory unit contains a single transistor and a single resistive switching memory device to form a 1T-1R structure, with bit line or word line voltage as the input terminal. Both the MAC unit and the auxiliary unit include: a 2-to-1 logic circuit, a sensitive amplifier, and a sample-and-hold circuit. The input of the 2-to-1 logic circuit is connected to the output of the memory array, and the output of the 2-to-1 logic circuit is connected to the sensitive amplifier and the sample-and-hold circuit respectively. When verifying and reading weighted data, the branch where the sensitive amplifier is located is selected. When performing multiplication and accumulation calculations, the branch where the sample-and-hold circuit is located is selected.

[0007] Optionally, the in-memory computing chip further includes: A caching unit is used to cache intermediate data, which includes input data of each convolutional layer, auxiliary data, a first output result based on the input data, a second output result based on the auxiliary data, and a weight update matrix.

[0008] Optionally, the in-memory computing chip further includes: A first ADC circuit shared by the plurality of MAC units, the first ADC circuit being used to read the multiply-accumulate calculation result of the MAC unit and to pass the multiply-accumulate calculation result of the MAC unit into the logic unit; A second ADC circuit shared by the multiple auxiliary units is used to read the multiply-accumulate calculation result of the auxiliary unit and pass the multiply-accumulate calculation result of the auxiliary unit into the logic unit.

[0009] Optionally, the logic unit is further configured to, after all convolutional layers have completed inference, calculate the sum of squares of the first output results of all convolutional layers to obtain the maximum value index, wherein the maximum value index is the inference result of the convolutional neural network.

[0010] Optionally, the control unit is one of a microcontroller (MCU), a field-programmable gate array (FPGA), or an RSIC core.

[0011] Optionally, the in-memory computing chip further includes: I / O interface for communication with the host computer.

[0012] Secondly, the present invention provides an on-chip training method for an in-memory computing chip, implemented based on the in-memory computing chip of the first aspect, comprising the following steps: S1: During the initialization phase, weight data is written to the MAC units and auxiliary units of each convolutional layer of the convolutional neural network; S2: Map the input data to the MAC unit of the current convolutional layer, so that the MAC unit performs multiplication and accumulation calculation on the input data and the stored weight data; in parallel, map the auxiliary data to the auxiliary unit of the current convolutional layer, so that the auxiliary unit performs multiplication and accumulation calculation on the auxiliary data and the stored weight data, wherein the auxiliary data is obtained by shuffling the input data; the multiplication and accumulation calculation results of the MAC unit and the auxiliary unit are respectively subjected to ReLU activation and pooling operations in the logic unit to obtain a first output result based on the input data and a second output result based on the auxiliary data; S3: Save the first output result and the second output result; S4: Determine whether the current convolutional layer needs to be trained. If the current convolutional layer needs to be trained, proceed to step S5; otherwise, proceed to step S8. S5: Input the first output result and the second output result into the logic unit, calculate the output difference between the first output result and the second output result within the logic unit, and perform thresholding on the output difference to obtain an output difference matrix; input the auxiliary data and the input data into the logic unit, calculate the input difference between the auxiliary data and the input data within the logic unit, and perform thresholding on the input difference to obtain an input difference matrix; S6: Write the output difference matrix into the auxiliary unit and map the input difference matrix to the auxiliary unit, so that the auxiliary unit performs matrix multiplication on the output difference matrix and the input difference matrix to obtain the weight update matrix; S7: Update the weight data of the MAC unit and the auxiliary unit according to the weight update matrix, and return to S2; S8: If the current convolutional layer does not need to be trained, the inference of the current convolutional layer is determined to be complete, and the first output result is saved as the inference result of the current convolutional layer.

[0013] Optionally, updating the weight data of the MAC unit and the auxiliary unit according to the weight update matrix in step S7 includes: The weight data remains unchanged at the position corresponding to "0" in the weight update matrix, the weight data is written as 1 at the position corresponding to "positive 1" in the weight update matrix, and the weight data is written as 0 at the position corresponding to "negative 1" in the weight update matrix.

[0014] Optionally, the method further includes the following steps: S9: Determine whether all convolutional layers have completed inference. If all convolutional layers have completed inference, proceed to step S10; otherwise, proceed to step S11. S10: Input the first output results of all the convolutional layers into the logic unit, and calculate the sum of squares of the first output results of all the convolutional layers in the logic unit to obtain the maximum value index, which is the inference result of the convolutional neural network; S11: The first output of the current convolutional layer is used as the input data of the MAC unit of the next convolutional layer. The input data is shuffled to obtain auxiliary data, and then the process returns to S2.

[0015] The in-memory computing chip and its on-chip training method provided by this invention incorporate corresponding auxiliary units and auxiliary data. The auxiliary data is obtained by shuffling the input data. During training of a convolutional layer, the auxiliary data channel of that convolutional layer performs forward inference operations simultaneously with the input data channel. The output results obtained from the forward inference operations of the input data and auxiliary data are subtracted, and the difference between the input data and auxiliary data is also subtracted. After thresholding, output difference matrices and input difference matrices are obtained. Then, matrix multiplication of the output difference matrix and input difference matrix is ​​performed to obtain the weight update matrix, which in turn updates the weights. Compared with existing technologies, this invention achieves independent training of individual convolutional layers, meaning that layers do not affect each other during training, and gradient derivative calculations are not required. This avoids frequent access to weight data, reduces training computation, and accelerates the training process. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an in-memory computing chip in one embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the MAC unit and the auxiliary unit in one embodiment of the present invention; Figure 3 This is a flowchart illustrating an on-chip training method for a memory computing chip according to an embodiment of the present invention. Figure 4 This diagram illustrates the accuracy and number of iterations of the training method applied in this embodiment of the invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0020] This invention provides an in-memory computing chip for use in convolutional neural networks, such as... Figure 1 As shown, the in-memory computing chip includes: The MAC (Multiply Accumulate) unit 101 and the auxiliary unit 102 are set in pairs. The pair of MAC units and auxiliary units corresponds to a convolutional layer of the convolutional neural network. The MAC unit 101 is used to store the weight data of the convolutional layer and perform multiply-accumulate calculation on the weight data and the input data. The auxiliary unit 102 is used to store the weight data of the convolutional layer and perform multiply-accumulate calculation on the weight data and the auxiliary data. The auxiliary data is obtained by shuffling the input data. The logic unit 103 is used to perform ReLU activation and pooling operations on the multiplication and accumulation calculation results of the MAC unit and the auxiliary unit respectively to obtain a first output result based on the input data and a second output result based on the auxiliary data; it is also used to calculate the output difference between the first output result and the second output result if it is necessary to train the convolutional layer, and to perform thresholding processing on the output difference to obtain an output difference matrix; and to calculate the input difference between the auxiliary data and the input data, and to perform thresholding processing on the input difference to obtain an input difference matrix. In addition, the auxiliary unit 102 is also used to store the output difference matrix and perform matrix multiplication on the output difference matrix and the input difference matrix to obtain the weight update matrix, so as to update the weight data stored in the MAC unit and the auxiliary unit. as well as, The control unit 104 is used to execute executable instructions to control the data flow of the MAC unit 101, the auxiliary unit 102 and the logic unit 103.

[0021] Furthermore, in one embodiment, the structure of the auxiliary unit 102 is the same as that of the MAC unit 101, such as... Figure 2 As shown, both the MAC unit 101 and the auxiliary unit 102 include a memory array. The memory array is composed of memory cells arranged in a crossbar array. Each memory cell contains a single transistor and a single resistive random access memory device to form a 1T-1R structure. The bit line or word line voltage is used as the input terminal. The memory array can be implemented by any one of MRAM array, ReRAM array, or PCRAM array. It has the characteristic of being non-volatile when power is off and can store weight data for a long time.

[0022] The memory array of MAC unit 101 is used to perform multiplication and accumulation calculations on weight data and input data. The input data is mapped to the word line or bit line of the memory array of MAC unit. The memory array of auxiliary unit 102 is used to perform multiplication and accumulation calculations on weight data and auxiliary data. The auxiliary data is mapped to the word line or bit line of the memory array of auxiliary unit. In addition, the memory array of auxiliary unit 102 is also used to perform matrix multiplication calculations on output difference matrix and input difference matrix to obtain weight update matrix. Both the MAC unit 101 and the auxiliary unit 102 include: a 2-to-1 logic circuit, a sensitive amplifier, and a sample-and-hold circuit. The input of the 2-to-1 logic circuit is connected to the output of the memory array, and the output of the 2-to-1 logic circuit is connected to the sensitive amplifier and the sample-and-hold circuit respectively. When verifying and reading weight data, the branch where the sensitive amplifier is located is selected. When performing multiplication and accumulation calculation, the branch where the sample-and-hold circuit is located is selected.

[0023] It is understandable that the auxiliary unit 102 has two functions: accelerating the multiplication and accumulation calculation of auxiliary data and matrix multiplication calculation of the output difference matrix and the input difference matrix. Generally, the storage array area of ​​the auxiliary unit 102 is twice the storage array area of ​​the MAC unit 101. Half of the storage array of the auxiliary unit 102 is used for accelerating the multiplication and accumulation calculation of auxiliary data, and the other half is used for matrix multiplication calculation of the output difference matrix and the input difference matrix after thresholding.

[0024] Furthermore, in one embodiment, such as Figure 1 As shown, the in-memory computing chip also includes a cache unit 105 for caching intermediate data, which includes input data of each convolutional layer, auxiliary data, a first output result based on the input data, a second output result based on the auxiliary data, and a weight update matrix.

[0025] Furthermore, in one embodiment, such as Figure 1As shown, the in-memory computing chip also includes a first ADC circuit 106 shared by multiple MAC units 101. The first ADC circuit 106 is used to read the multiply-accumulate calculation result of the MAC unit and transmit the multiply-accumulate calculation result of the MAC unit to the logic unit 103. The second ADC circuit 107 is shared by multiple auxiliary units. The second ADC circuit 107 is used to read the multiply-accumulate calculation result of the auxiliary unit and pass the multiply-accumulate calculation result of the auxiliary unit into the logic unit 103.

[0026] The first ADC circuit 106 and the second ADC circuit 107 are multiplexed using a multiplexer for reading analog voltages. Composed of a charge-shared analog-to-digital converter, the ADC can achieve pipelined operation by holding the voltage of the sampling capacitor, reducing the chip footprint and meeting the requirements of pipelined layer-by-layer inference.

[0027] Furthermore, the logic unit 103 is also used to calculate the sum of squares of the first output results of all convolutional layers after all convolutional layers have completed inference, and obtain the maximum value index, which is the inference result of the convolutional neural network.

[0028] Furthermore, the functions of the control unit 104 include: controlling the reading, writing, and calculation of the MAC unit and auxiliary units; reading, decoding, and executing instructions from the host computer; and controlling the enable signals, calculation logic signals, input data buffers, and output data buffers of each unit. The control unit 104 can be composed of a microcontroller (MCU), a field-programmable gate array (FPGA), an RISC core, or other control core units.

[0029] The executable instructions of the control unit 104 include read, write, calculation, and training-related instructions. The training-related instructions include storage instructions, calculation instructions, and address translation instructions. Storage instructions retrieve corresponding data from the cache unit and pass it to the logic unit. After the logic unit performs relevant threshold judgment, ReLU activation, and pooling operations, the data is stored back to the cache unit. Calculation instructions retrieve weight data from the cache unit and write it to the bits of the auxiliary unit. The input data and auxiliary data are mapped to word lines or bit lines on the storage array in the MAC unit and auxiliary unit. Address translation instructions convert the weight update matrix into an address signal and update the weight data of the MAC unit and auxiliary unit according to the address signal.

[0030] Further, refer to Figure 1 The in-memory computing chip also includes an input / output (I / O) interface 108 for communication with a host computer. The I / O interface can be composed of one of the data exchange interfaces such as DMA, SPI, and I2C, and the input and output are both 4-bit to 8-bit integer data.

[0031] It should be noted that the input data is shuffled in the host computer to obtain auxiliary data. The input data and auxiliary data are then input to the MAC unit and the auxiliary unit respectively via the I / O interface.

[0032] Of course, in-memory computing chips also include some conventional units, such as on-chip flash memory for storing executable instructions for the control unit, and a power supply unit to provide power to each unit. These are all standard designs and will not be elaborated upon here.

[0033] The in-memory computing chip provided in this invention incorporates corresponding auxiliary units and auxiliary data. The auxiliary data is obtained by shuffling the input data. During the training of a convolutional layer, the auxiliary data channel of that convolutional layer performs forward inference operations simultaneously with the input data channel. The output results obtained from the forward inference operations of the input data and auxiliary data are subtracted, and the difference between the input data and auxiliary data is also thresholded to obtain the output difference matrix and the input difference matrix. Then, matrix multiplication of the output difference matrix and the input difference matrix is ​​performed to obtain the weight update matrix, which in turn updates the weights. Compared to existing technologies, this achieves independent training of individual convolutional layers, meaning that layers do not affect each other during training, and gradient derivative calculations are not required. This avoids frequent calls to weight data, reduces training computation, and accelerates the training process.

[0034] On the other hand, embodiments of the present invention also provide an on-chip training method for an in-memory computing chip, implemented based on the in-memory computing chip described in the above embodiments, such as... Figure 3 As shown, the on-chip training method includes the following steps: S1: During the initialization phase, weight data is written to the MAC units and auxiliary units of each convolutional layer of the convolutional neural network; S2: Map the input data to the MAC unit of the current convolutional layer, so that the MAC unit performs multiplication and accumulation calculation on the input data and the stored weight data; in parallel, map the auxiliary data to the auxiliary unit of the current convolutional layer, so that the auxiliary unit performs multiplication and accumulation calculation on the auxiliary data and the stored weight data. The auxiliary data is obtained by shuffling the input data; the multiplication and accumulation calculation results of the MAC unit and the auxiliary unit are respectively subjected to ReLU activation and pooling operations in the logic unit to obtain the first output result based on the input data and the second output result based on the auxiliary data. S3: Save the first and second output results; S4: Determine whether the current convolutional layer needs to be trained. If the current convolutional layer needs to be trained, proceed to step S5; otherwise, proceed to step S8. S5: Input the first output result and the second output result into the logic unit, calculate the output difference between the first output result and the second output result within the logic unit, and perform thresholding on the output difference to obtain the output difference matrix; input the auxiliary data and the input data into the logic unit, calculate the input difference between the auxiliary data and the input data within the logic unit, and perform thresholding on the input difference to obtain the input difference matrix; S6: Write the output difference matrix into the auxiliary unit and map the input difference matrix to the auxiliary unit, so that the auxiliary unit performs matrix multiplication on the output difference matrix and the input difference matrix to obtain the weight update matrix; S7: Update the weight data of the MAC unit and the auxiliary unit according to the weight update matrix, and return to S2; S8: If the current convolutional layer does not need to be trained, the inference of the current convolutional layer is determined to be complete, and the first output result is saved as the inference result of the current convolutional layer.

[0035] Taking the training of the nth layer as an example, the structured code is as follows: x n-ass = shuffle(x) n ) h_p n = MAC(x n , w n ) h_p n-ass = MAC(x n-ass , w n ) y n = Pooling [ReLU (h_p n )] y n-ass = Pooling [ReLU (h_p n-ass )] deta_x n = Threshold(x n-ass -x n ) deta_y n = Threshold(y n-ass -y n ) deta_w n = MAC(deta_x n , deta_y n ) Where x n Let x represent the input data of the nth layer. n-ass Represents auxiliary data, h_p nThis represents the result of the multiply-accumulate operation in the MAC unit. MAC stands for multiply-accumulate operation. h_p n-ass y represents the result of the multiplication and accumulation calculation of the auxiliary unit. n This represents the first output result obtained based on the input data, y. n-ass This represents the second output result obtained based on auxiliary data, deta_x n Denotes the input difference matrix, deta_y n This indicates the output difference matrix, deta_w n This represents the weight update matrix, where the subscript ass of each variable indicates the correlation of the auxiliary data, and Threshold represents the thresholding process.

[0036] In step S7, updating the weight data of the MAC unit and the auxiliary unit according to the weight update matrix includes: The weight data remains unchanged at the position corresponding to "0" in the weight update matrix, the weight data is written as 1 at the position corresponding to "positive 1" in the weight update matrix, and the weight data is written as 0 at the position corresponding to "negative 1" in the weight update matrix.

[0037] Training is performed using the training method of this embodiment of the invention, and the training results can be obtained from... Figure 4 The values ​​are derived from the given information. 'GD' represents traditional gradient descent training, and 'SV' represents sign bit update. During training, auxiliary units are used for reference throughout. Figure 4 The results show that the algorithm loses approximately 3.2% accuracy after quantization. After training with 4-bit precision using 1GD-2SV (first layer GD, second and third layers SV), the accuracy is approximately 90% (32-bit floating-point accuracy is approximately 92.2%, 3GD is approximately 89%), and the number of iterations is significantly reduced. This demonstrates that the sign bit update method under this training approach is more beneficial for auxiliary training in this architecture. The above training is all independent training of each convolutional layer, not dependent on data from adjacent convolutional layers, and the accuracy is obtained after inference following training. By updating weights using the above sign bit update method, combined with threshold judgment, the number of iterations can be reduced while maintaining a certain level of accuracy.

[0038] Further, refer to Figure 3 The training method also includes the following steps: S9: Determine whether all convolutional layers have completed inference. If all convolutional layers have completed inference, proceed to step S10; otherwise, proceed to step S11. S10: Pass the first output results of all the convolutional layers into the logic unit, and calculate the sum of squares of the first output results of all the convolutional layers in the logic unit to obtain the maximum value index, which is the inference result of the convolutional neural network. S11: The first output of the current convolutional layer is used as the input data of the MAC unit of the next convolutional layer. The input data is shuffled to obtain auxiliary data, and then the process returns to S2.

[0039] It's important to note that during the inference phase, the sum of the squares of the first outputs of all convolutional layers is used to obtain the maximum value index. This maximum value index represents the inference result of the convolutional neural network, simplifying the process of extracting key information from multi-layer convolutional features. Integrating the first outputs of all convolutional layers into a single maximum value index reduces the dimensionality of the data, resulting in the final output.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory computing chip, characterized in that, The in-memory computing chip includes: The MAC unit and auxiliary unit are set in pairs, and a pair of MAC units and auxiliary units corresponds to a convolutional layer of the convolutional neural network. The MAC unit is used to store the weight data of the convolutional layer and perform multiplication and accumulation calculation on the weight data and the input data. The auxiliary unit is used to store the weight data of the convolutional layer and perform multiplication and accumulation calculation on the weight data and the auxiliary data. The auxiliary data is obtained by shuffling the input data. The logic unit is configured to perform ReLU activation and pooling operations on the multiplication and accumulation calculation results of the MAC unit and the auxiliary unit, respectively, to obtain a first output result based on the input data and a second output result based on the auxiliary data; it is also configured to calculate the output difference between the first output result and the second output result if a convolutional layer needs to be trained, and to perform thresholding processing on the output difference to obtain an output difference matrix; and to calculate the input difference between the auxiliary data and the input data, and to perform thresholding processing on the input difference to obtain an input difference matrix. The auxiliary unit is also used to store the output difference matrix and perform matrix multiplication on the output difference matrix and the input difference matrix to obtain a weight update matrix, so as to update the weight data stored in the MAC unit and the auxiliary unit. as well as, The control unit is used to execute executable instructions to control the data flow of the MAC unit, auxiliary unit, and logic unit.

2. The in-memory computing chip according to claim 1, characterized in that, The structure of the auxiliary unit is the same as that of the MAC unit. Both the MAC unit and the auxiliary unit include: a memory array, which is composed of memory units in a horizontal array. Each memory unit contains a single transistor and a single resistive switching memory device to form a 1T-1R structure, with bit line or word line voltage as the input terminal. Both the MAC unit and the auxiliary unit include: a 2-to-1 logic circuit, a sensitive amplifier, and a sample-and-hold circuit. The input of the 2-to-1 logic circuit is connected to the output of the memory array, and the output of the 2-to-1 logic circuit is connected to the sensitive amplifier and the sample-and-hold circuit respectively. When verifying and reading weighted data, the branch where the sensitive amplifier is located is selected. When performing multiplication and accumulation calculations, the branch where the sample-and-hold circuit is located is selected.

3. The in-memory computing chip according to claim 1, characterized in that, The in-memory computing chip also includes: A caching unit is used to cache intermediate data, which includes input data of each convolutional layer, auxiliary data, a first output result based on the input data, a second output result based on the auxiliary data, and a weight update matrix.

4. The in-memory computing chip according to claim 1, characterized in that, The in-memory computing chip also includes: A first ADC circuit shared by the plurality of MAC units, the first ADC circuit being used to read the multiply-accumulate calculation result of the MAC unit and to pass the multiply-accumulate calculation result of the MAC unit into the logic unit; A second ADC circuit shared by the multiple auxiliary units is used to read the multiply-accumulate calculation result of the auxiliary unit and pass the multiply-accumulate calculation result of the auxiliary unit into the logic unit.

5. The in-memory computing chip according to claim 1, characterized in that, The logic unit is also used to calculate the sum of squares of the first output results of all convolutional layers after all convolutional layers have completed inference, and obtain the maximum value index, which is the inference result of the convolutional neural network.

6. The in-memory computing chip according to claim 1, characterized in that, The control unit is one of the following: microcontroller (MCU), field-programmable gate array (FPGA), or RSIC core.

7. The in-memory computing chip according to claim 1, characterized in that, The in-memory computing chip also includes: I / O interface for communication with the host computer.

8. An on-chip training method for a memory computing chip, implemented based on the memory computing chip as described in claim 1, the method comprising the following steps: S1: During the initialization phase, weight data is written to the MAC units and auxiliary units of each convolutional layer of the convolutional neural network; S2: Map the input data to the MAC unit of the current convolutional layer, so that the MAC unit performs multiplication and accumulation calculation on the input data and the stored weight data; in parallel, map the auxiliary data to the auxiliary unit of the current convolutional layer, so that the auxiliary unit performs multiplication and accumulation calculation on the auxiliary data and the stored weight data, wherein the auxiliary data is obtained by shuffling the input data; The multiply-accumulate calculation results of the MAC unit and the auxiliary unit are subjected to ReLU activation and pooling operations in the logic unit respectively to obtain the first output result based on the input data and the second output result based on the auxiliary data; S3: Save the first output result and the second output result; S4: Determine whether the current convolutional layer needs to be trained. If the current convolutional layer needs to be trained, proceed to step S5; otherwise, proceed to step S8. S5: Input the first output result and the second output result into the logic unit, calculate the output difference between the first output result and the second output result in the logic unit, and perform thresholding on the output difference to obtain the output difference matrix; The auxiliary data and the input data are passed into the logic unit. The input difference between the auxiliary data and the input data is calculated in the logic unit, and the input difference is thresholded to obtain the input difference matrix. S6: Write the output difference matrix into the auxiliary unit and map the input difference matrix to the auxiliary unit, so that the auxiliary unit performs matrix multiplication on the output difference matrix and the input difference matrix to obtain the weight update matrix; S7: Update the weight data of the MAC unit and the auxiliary unit according to the weight update matrix, and return to S2; S8: If the current convolutional layer does not need to be trained, the inference of the current convolutional layer is determined to be complete, and the first output result is saved as the inference result of the current convolutional layer.

9. The method according to claim 8, characterized in that, Step S7, which involves updating the weight data of the MAC unit and the auxiliary unit according to the weight update matrix, includes: The weight data remains unchanged at the position corresponding to "0" in the weight update matrix, the weight data is written as 1 at the position corresponding to "positive 1" in the weight update matrix, and the weight data is written as 0 at the position corresponding to "negative 1" in the weight update matrix.

10. The method according to claim 8, characterized in that, The method further includes the following steps: S9: Determine whether all convolutional layers have completed inference. If all convolutional layers have completed inference, proceed to step S10; otherwise, proceed to step S11. S10: Input the first output results of all the convolutional layers into the logic unit, and calculate the sum of squares of the first output results of all the convolutional layers in the logic unit to obtain the maximum value index, which is the inference result of the convolutional neural network; S11: The first output of the current convolutional layer is used as the input data of the MAC unit of the next convolutional layer. The input data is shuffled to obtain auxiliary data, and then the process returns to S2.

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