Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device may include a semiconductor pattern, a gate structure, a first spacer, a first semiconductor layer, and a second semiconductor layer. The semiconductor pattern may be formed on a substrate and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor pattern. At least a portion of the gate structure may be formed between the semiconductor patterns in the vertical direction. The first spacer may cover opposite side walls of the gate structure, the side walls being opposite to each other in a first direction. The first semiconductor layer may cover the side walls of the semiconductor pattern in the first direction and the surface of the first spacer and the substrate. The first semiconductor layer may have a first impurity concentration. The second semiconductor layer may be formed on the first semiconductor layer and may have a second impurity concentration higher than the first impurity concentration. The semiconductor device may have good characteristics and high reliability.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0061794 filed on May 27, 2019, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Example embodiments relate to semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to semiconductor devices having vertically stacked channels and methods of manufacturing the same. Background Art

[0003] A multi-bridge channel MOSFET (MBCFET) with high integration and high performance has been developed. In a process for forming a multi-bridge channel in an MBCFET, semiconductor materials of source / drain regions formed on both sides of the multi-bridge channel may be partially removed, so defects in the source / drain regions may occur. Summary of the invention

[0004] Example embodiments provide a semiconductor device having excellent characteristics.

[0005] Example embodiments provide a method of manufacturing a semiconductor device having excellent characteristics.

[0006] According to example embodiments, a semiconductor device may include a semiconductor pattern, a gate structure, a first spacer, a first semiconductor layer, and a second semiconductor layer. The semiconductor patterns may be formed on a substrate and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor pattern. At least a portion of the gate structure may be formed between the semiconductor patterns in the vertical direction. The first spacer may cover opposite side walls of the gate structure, the side walls being opposite to each other in a first direction. The first semiconductor layer may cover the side walls of the semiconductor pattern in the first direction and the surface of the first spacer and the substrate. The first semiconductor layer may have a first impurity concentration. The second semiconductor layer may be formed on the first semiconductor layer and may have a second impurity concentration higher than the first impurity concentration.

[0007] According to example embodiments, a semiconductor device may include a stacked structure, a first semiconductor layer, and a second semiconductor layer. The stacked structure may be formed on a substrate. The stacked structure may include a semiconductor pattern, a gate structure, and a first spacer. The semiconductor pattern and the spacer may be exposed at an outer wall of the stacked structure in a first direction parallel to an upper surface of the substrate. The first semiconductor layer may cover the outer wall of the stacked structure in the first direction and may cover the surface of the substrate. The first semiconductor layer may be doped with impurities of a first concentration. The second semiconductor layer may be formed on the first semiconductor layer. The second semiconductor layer may be doped with impurities of a second concentration higher than the first concentration.

[0008] According to example embodiments, a semiconductor device may include a semiconductor pattern, a first spacer, a gate structure, a first semiconductor layer, and a second semiconductor layer. The semiconductor pattern may be formed on a substrate. The semiconductor patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. The first spacer may be formed between the semiconductor patterns in a vertical direction. The first spacer may contact an upper surface and a lower surface of the semiconductor pattern at an edge of the semiconductor pattern. The gate structure may be formed on the substrate to fill a first gap defined by the semiconductor pattern and the first spacer. The first semiconductor layer may cover a sidewall of the semiconductor pattern in a first direction and a surface of the first spacer and the substrate. The second semiconductor layer may be formed on the first semiconductor layer. The second semiconductor layer may have an impurity concentration higher than that of the first semiconductor layer.

[0009] According to an example embodiment, a method for manufacturing a semiconductor device includes: alternately and repeatedly stacking a sacrificial pattern and a semiconductor pattern on a substrate to form a structure. A first spacer may be formed on a sidewall of the sacrificial pattern. A first semiconductor layer may be formed to cover the sidewall of the structure including the sacrificial pattern and the semiconductor pattern and to cover the substrate. A second semiconductor layer may be formed on the first semiconductor layer, and the second semiconductor layer may have an impurity concentration higher than that of the first semiconductor layer. The sacrificial pattern may be removed to form a first gap. A gate structure may be formed to surround a surface of the semiconductor pattern, and the gate structure may at least fill the first gap.

[0010] The semiconductor device according to the example embodiment may include a first semiconductor layer, which covers the sidewalls of the first spacer, the sidewalls of the semiconductor pattern and the surface of the substrate. The semiconductor pattern and the substrate may be used as a channel. The second semiconductor layer may be formed on the first semiconductor layer. The first semiconductor layer may be used as a barrier layer to prevent the etching source from penetrating into the second semiconductor layer. Therefore, the second semiconductor layer used as the source / drain region of the semiconductor device may not be etched, or a hole may not be formed therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A , Figure 1B and Figure 2 is a cross-sectional view showing a semiconductor device according to example embodiments;

[0012] Figure 3 , Figure 4A and Figure 4B is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0013] Figures 5 to 27 are a plan view, a cross-sectional view, and a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0014] Fig.28 and Fig.29 is a cross-sectional view showing a semiconductor device according to example embodiments;

[0015] Fig.30 is a cross-sectional view showing a semiconductor device according to example embodiments;

[0016] Fig.31 and Fig.32 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0017] Fig.33 is a cross-sectional view showing a semiconductor device according to example embodiments;

[0018] Figure 34 to Figure 36 are cross-sectional views showing semiconductor devices according to example embodiments, respectively;

[0019] Fig.37 is a cross-sectional view illustrating a semiconductor device according to example embodiments; and

[0020] Fig.38 is a cross-sectional view illustrating a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, two directions substantially parallel to the upper surface of the substrate and intersecting each other may be referred to as a first direction and a second direction, respectively, and a direction substantially perpendicular to the upper surface of the substrate may be referred to as a vertical direction. In example embodiments, the first direction and the second direction may be substantially perpendicular to each other.

[0022] Figure 1A , Figure 1B and Figure 2 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 3 , Figure 4A and Figure 4B is a cross-sectional view illustrating a semiconductor device according to some example embodiments.

[0023] Figure 1A is a cross-sectional view of a portion of the gate pattern cut along a first direction. Figure 1B is a cross-sectional view of a portion of the gate pattern cut along the second direction. Figure 2 is a cross-sectional view (eg, a top view) taken along line AA' of FIG. 1. That is, Figure 2 is a cross-sectional view of a gate pattern portion between semiconductor patterns in a horizontal direction.

[0024] Reference Figure 1A , Figure 1B and Figure 2A semiconductor device may be formed on a substrate 100 and may include a semiconductor pattern 132a, gate structures 162a and 162b, a first semiconductor layer 150, a second semiconductor layer 152, and a first spacer 144. The semiconductor device may also include an active region 100a, an isolation pattern 110, a second spacer 138, and an insulating layer 154.

[0025] The substrate 100 includes or has a material composition of one or more semiconductor materials, such as silicon, germanium, silicon germanium, or III-V compounds such as GaAs, AlGaAs, InAs, InGaAs, etc. In example embodiments, the silicon substrate may be a (100) substrate, a (110) substrate, or a (111) substrate. Articles having the same material composition as described herein include the same element / compound or element / compound group having the same or substantially the same ratio with each other.

[0026] The active region 100a may protrude from the upper surface of the substrate 100 in a vertical direction and may extend longitudinally in a first direction. An article, layer, or portion of an article or layer described as extending "longitudinally" in a particular direction has a length in the particular direction and a width perpendicular to the direction, wherein the length is greater than the width.

[0027] In addition, a plurality of active regions 100a may be arranged in the second direction. The active region 100a may be formed by partially removing the upper portion of the substrate 100, so the active region 100a may include a material substantially the same as that of the substrate 100, and may have the same material composition as that of the substrate 100. In this case, the active region 100a may be considered as a part of the substrate 100. The terms "same", "equal", "plane" or "coplanar" used herein when referring to orientation, layout, position, shape, size, composition, amount or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, composition, amount or other measurement, but are intended to include, for example, almost the same orientation, layout, position, shape, size, composition, amount or other measurement within an acceptable variation that may occur due to a manufacturing process. The term "substantially (upper)" may be used herein to emphasize this meaning unless otherwise indicated by the context or other statements. For example, an item described as "substantially the same", "substantially equal" or "substantially plane" may be exactly the same, equal or plane, or may be the same, equal or plane within an acceptable variation that may occur, for example, due to a manufacturing process.

[0028] A lower sidewall of the active region 100a may be surrounded by the isolation pattern 110. The isolation pattern 110 may include, for example, an oxide such as silicon oxide, and may be formed of, for example, an oxide such as silicon oxide.

[0029] The semiconductor patterns 132a are spaced apart from each other in the vertical direction and overlap vertically in the vertical direction. In an example embodiment, the bottommost semiconductor pattern 132a is spaced apart from the upper surface of the active area 100a. The semiconductor patterns 132a stacked in the vertical direction can be used as a multi-channel region of a transistor. For example, the stack of semiconductor patterns 132a formed on the active area 100a can form a channel region of a transistor together (the transistor has a plurality of channels corresponding to each individual semiconductor pattern). The semiconductor patterns 132a stacked in the vertical direction can be used as a semiconductor pattern structure. The semiconductor pattern structure can include gaps between the semiconductor patterns 132a in the vertical direction. Each semiconductor pattern 132a can be referred to as a single semiconductor pattern or a single-layer semiconductor pattern, which is different from two or more semiconductor patterns forming a stack, and the stack can be referred to as a stacked semiconductor pattern or a multi-layer semiconductor pattern.

[0030] In example embodiments, the semiconductor pattern structure may be formed on the active region 100a extending in the first direction. A plurality of semiconductor pattern structures may be aligned in each of the first direction and the second direction.

[0031] In example embodiments, the semiconductor pattern 132 a may include and may be silicon. In some example embodiments, the semiconductor pattern 132 a may include and may be a material such as germanium, silicon germanium, InP, GaAs, InGaAs, or the like.

[0032] The gate structures 162a and 162b may be formed on the substrate 100 and may extend longitudinally in the second direction. The first spacer 144 or the second spacer 138 may be formed on sidewalls of the gate structures 162a and 162b.

[0033] The first spacer 144 may be formed at two (e.g., opposite) ends of the gap between the semiconductor patterns 132a stacked in the vertical direction and the gap between the active region 100a and the semiconductor pattern 132a closest to the active region 100a in the first direction. For example, the first spacer 144 may contact the upper and lower surfaces of both ends of the semiconductor pattern 132a stacked in the vertical direction in the first direction, and the first spacer 144 may support the upper and lower surfaces of the semiconductor pattern 132a. Therefore, the first gap (refer to Fig.25 and Fig.26158 in the first spacer 144) may be defined as a space between the semiconductor pattern 132a and the first spacer 144 and a space between the semiconductor pattern 132a, the active region 100a, and the first spacer 144. In addition, the gate structures 162a and 162b may fill the first gap 158. Depending on the context, the "first spacer" 144 may refer to two spacers, each at either end of the first gap 158, or may refer to only one of the spacers.

[0034] The gate structures 162a and 162b may fill the first gaps 158 included in the semiconductor patterns arranged in the second direction, and the gate structures 162a and 162b may cover the front and rear sides of the semiconductor pattern structures in the second direction. In addition, the gate structures 162a and 162b may be formed on the uppermost surface of each semiconductor pattern structure. Therefore, the upper surfaces of the gate structures 162a and 162b may be higher than the uppermost surface of each semiconductor pattern structure.

[0035] Hereinafter, a portion of the gate structure formed in the first gap is referred to as a first gate structure 162 a , and the other portion of the gate structure is referred to as a second gate structure 162 b .

[0036] The second spacer 138 may be formed on the sidewalls of the gate structure 162b formed on the uppermost surface of each semiconductor pattern structure, and on the sidewalls of the gate structure 162b formed between the sidewalls of the semiconductor pattern structure opposite to each other in the second direction. For example, the second spacer 138 may be formed on the sidewalls of the second gate structure 162b opposite to each other in the first direction. Depending on the context, the "second spacer" 138 may refer to two spacers each at either end of the gate structure 162b, or may refer to only one of the spacers.

[0037] The gate structures 162a and 162b may include a gate insulating pattern 160a and a gate pattern 160b. The gate insulating pattern 160a may surround a surface of the gate pattern 160b. In example embodiments, a work function control pattern may be further formed between the gate insulating pattern 160a and the gate pattern 160b.

[0038] The gate insulating pattern 160a may be formed on a surface of each semiconductor pattern 132a and an upper surface of the active region 100a. The gate insulating pattern 160a may contact the first spacer 144 and the second spacer 138. The term "contact" used herein refers to direct connection, for example, touching.

[0039] The gate pattern 160 b may fill the first gap and a space between the semiconductor patterns in the second direction, and the gate pattern 160 b may also be formed on an uppermost surface of the semiconductor pattern structure.

[0040] The gate insulating pattern 160a may include or may be, for example, a metal oxide having a high dielectric constant, such as hafnium oxide, tantalum oxide, zirconium oxide, etc. The work function control pattern (if used) may include or may be, for example, titanium nitride, titanium oxynitride, titanium silicon nitride, titanium silicon oxynitride, titanium aluminum oxynitride, tantalum nitride, tantalum oxynitride, tantalum aluminum oxynitride, tungsten nitride, tungsten carbide nitride, aluminum oxide, etc.

[0041] The gate pattern 160 b may include or may be, for example, a metal such as titanium, aluminum, tungsten, or a metal alloy, a metal nitride, or a metal carbide.

[0042] The first spacer 144 may contact a sidewall of the first gate structure 162a. Therefore, a sidewall profile of the first gate structure 162a may be the same shape as a contact surface between the first spacer 144 and the first gate structure 162a.

[0043] In example embodiments, the outer wall of the first spacer 144 may be parallel to and coplanar with the sidewall of the semiconductor pattern 132a in the vertical direction. Therefore, the sidewall of the first gate structure 162a may be covered by the first spacer 144, and the sidewall of the semiconductor pattern 132a may be exposed by and relative to the first spacer 144.

[0044] In some example embodiments, such as Figure 4A In the semiconductor device shown, the sidewall of the semiconductor pattern 132a may protrude from the outer wall of the first spacer 144a in the first direction. For example, the outer wall of the first spacer 144a may be formed to be recessed inward from the sidewall of the semiconductor pattern 132a in the first direction. Therefore, the sidewall of the first gate structure 162a may be covered by the first spacer 144a, and the upper and lower surfaces of both ends of the semiconductor pattern 132a and the sidewall of the semiconductor pattern 132a are exposed by the first spacer 144a and are exposed relative to the first spacer 144a.

[0045] In some example embodiments, such as Figure 4B In the semiconductor device shown in FIG. 1 , an outer wall of the first spacer 144 may protrude from the semiconductor pattern 132 a in the first direction.

[0046] In example embodiments, the first spacer 144 contacts the sidewalls of the first gate structure 162a and the upper and lower surfaces of the semiconductor pattern 132a at both side edges in the first direction (e.g., at edge portions of the semiconductor pattern 132a). The surface of the first spacer 144 contacting the sidewalls of the first gate structure 162a and the upper and lower surfaces at both side edges of the semiconductor pattern 132a is referred to as the inner surface of the first spacer 144. The inner surface of the first spacer 144 may have a concave rounded shape toward the middle of the first gate structure 162a in the first direction.

[0047] According to the shape of the first spacer 144, the thickness of the semiconductor pattern 132a in the vertical direction may vary according to its position. Specifically, the first thickness T1 of the semiconductor pattern 132a in the vertical direction at the portion in contact with the first spacer 144 may be less than the second thickness T2 of the semiconductor pattern 132a in the vertical direction at the middle portion in the first direction. The middle portion may be a portion of the semiconductor pattern 132a that is not in contact with the first spacer. In example embodiments, the thickness of the semiconductor pattern 132a in the vertical direction at the portion in contact with the first spacer 144 may gradually decrease toward the end of the semiconductor pattern 132a.

[0048] In addition, according to the shape of the first spacer 144, the width of the first gate structure 162a between the semiconductor patterns 132a may vary according to its position. The middle portion of the first gate structure 162a in the vertical direction may have a first width W1 in the first direction. The first width W1 may be smaller than the second width W2 of the upper and lower portions of the first gate structure 162a in the vertical direction in the first direction. In example embodiments, the width of the first gate structure 162a in the first direction may gradually decrease from its upper and lower surfaces toward its middle portion.

[0049] Due to the formation of the first spacer 144 , the width (eg, maximum width) of the first gate structure 162 a in the first direction may be smaller than the width (eg, maximum width) of the semiconductor pattern 132 a in the first direction.

[0050] The stack structure including the gate structures 162a and 162b, the semiconductor pattern 132a, and the first and second spacers 144 and 138 may extend in the second direction. The semiconductor pattern 132a and the first and second spacers 144 and 138 may be exposed at sidewalls of the stack structure in the first direction.

[0051] The first spacer 144 may include or may be a nitride such as silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon oxynitride, etc., and the second spacer 138 may include or may be a nitride such as silicon nitride. The first spacer 144 may have a different material and / or material composition than the second spacer 138. Alternatively, the first spacer 144 and the second spacer 138 may have substantially the same material.

[0052] The first semiconductor layer 150 may contact the sidewalls of the semiconductor pattern 132a and the first spacer 144 and the upper surface of the active area 100a. The first semiconductor layer 150 may have a connected shape and be continuously formed along the sidewalls of the semiconductor pattern 132a and the first spacer 144 and the upper surface of the active area 100a (i.e., to have a continuously connected shape). For example, the first semiconductor layer 150 may be formed along the upper surface of the active area 100a and the sidewalls of the first spacer 144 and the semiconductor pattern 132a adjacent to each other in the first direction. Therefore, the semiconductor pattern 132a may be connected to each other through the first semiconductor layer 150. In addition, the surfaces of the semiconductor pattern 132a and the first spacer 144 may be completely covered by the first semiconductor layer 150.

[0053] In example embodiments, the first semiconductor layer 150 formed on the sidewalls of the semiconductor pattern 132a and the first spacer 144 has a third thickness T3 (e.g., measured in a direction perpendicular to the sidewalls on which the first semiconductor layer 150 is formed, e.g., in the first direction). The first semiconductor layer 150 formed on the upper surface of the active region 100a may have a fourth thickness T4 greater than the third thickness T3 (e.g., measured in a direction perpendicular to the surface on which the first semiconductor layer 150 is formed, e.g., in a vertical direction showing a mark T4).

[0054] The first semiconductor layer 150 may be doped with impurities to have a first impurity concentration.

[0055] In example embodiments, the first semiconductor layer 150 includes silicon doped with n-type impurities. For example, the n-type impurities may include phosphorus (P) or arsenic (As). In this case, the first semiconductor layer 150 may be used as a source / drain extension region of an NMOS transistor.

[0056] In some example embodiments, the first semiconductor layer 150 includes silicon germanium doped with n-type impurities. For example, the p-type impurities may include boron. In this case, the first semiconductor layer 150 may be used as a source / drain extension region of a PMOS transistor.

[0057] In some example embodiments, Figure 3 In the semiconductor device shown, the thickness of the first semiconductor layer 150a formed on the sidewalls of the semiconductor pattern 132a and the first spacer 144 in the first direction is not uniform. For example, the thickness of the first semiconductor layer 150a formed on the semiconductor pattern 132a may be greater than the thickness of the first semiconductor layer 150a formed on the first spacer 144 (e.g., measured perpendicularly to the sidewall surface formed by the sidewalls of the semiconductor pattern 132a and the first spacer 144).

[0058] The second semiconductor layer 152 may be formed on the first semiconductor layer 150. The second semiconductor layer 152 may be doped with impurities to have a second impurity concentration different from, for example, higher than, the first impurity concentration. In example embodiments, the second impurity concentration may be at least ten times the first impurity concentration.

[0059] In example embodiments, the second semiconductor layer 152 may be doped with impurities to have the same conductivity type as that of the impurities of the first semiconductor layer 150. Also, the second semiconductor layer 152 may include the same material (or material group) as that of the first semiconductor layer 150.

[0060] In example embodiments, the second semiconductor layer 152 may fill a space between semiconductor pattern structures spaced apart from each other in the first direction.

[0061] In example embodiments, the second semiconductor layer 152 may include silicon doped with n-type impurities. In this case, the second semiconductor layer 152 may function as a source / drain region of an NMOS transistor.

[0062] In some embodiments, the second semiconductor layer 152 may include silicon germanium doped with p-type impurities. In this case, the second semiconductor layer 152 may be used as a source / drain region of a PMOS transistor.

[0063] As described above, the second semiconductor layer 152 may be doped with impurities to have an impurity concentration higher than that of the first semiconductor layer 150. When an etching source such as an etching gas or an etchant may contact the first semiconductor layer 150 and the second semiconductor layer 152, the second semiconductor layer 152 doped with a high concentration of impurities may be etched faster than the first semiconductor layer 150 doped with a low impurity concentration. Therefore, if the etching gas or the etchant penetrates into the second semiconductor layer 152, the second semiconductor layer 152 may be partially etched to form a hole therein.

[0064] However, as described above, the first semiconductor layer 150 may be formed between the sidewalls of the semiconductor pattern 132a and the first spacer 144 and the upper surface of the active region 100a and the second semiconductor layer 152. Therefore, the second semiconductor layer 152 and the semiconductor pattern 132a may not contact each other, and the second semiconductor layer 152 and the first spacer 144 may not contact each other. For example, the second semiconductor layer 152 may be blocked by the first semiconductor layer 150 having a relatively low etching rate, so that the etching gas or etchant does not penetrate into the second semiconductor layer 152. Therefore, the second semiconductor layer 152 may not be damaged.

[0065] The semiconductor pattern 132 a , the gate structures 162 a and 162 b , and the first and second semiconductor layers 150 and 152 may function as an MBCFET.

[0066] The insulating layer 154 may surround the second spacer 138 and sidewalls of the first and second semiconductor layers 150 and 152. The insulating layer 154 may be formed to fill a space between the gate structures 162a and 162b. The insulating layer 154 may include an oxide such as silicon oxide.

[0067] The semiconductor device may further include contact plugs, wirings, etc. electrically connected to the second semiconductor layer 152 and / or the gate structures 162 a and 162 b .

[0068] As described above, the semiconductor device may include the first semiconductor layer 150, which covers the sidewalls of the semiconductor pattern 132a and the first spacer 144 and the upper surface of the active region 100a. Therefore, the second semiconductor layer 152 may not contact the semiconductor pattern 132a, and the second semiconductor layer 152 may not contact the first spacer 144. Therefore, damage to the second semiconductor layer 152 due to etching gas or etchant may be reduced.

[0069] Figures 5 to 27 are a plan view, a cross-sectional view, and a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0070] Figure 6 , Figure 8 , Fig.11 , Fig.13 and Fig.23 is a plan view, and Fig.16 , Fig.19 , Fig. 22 and Fig.26 1 and 2 are perspective views of a portion of a semiconductor device. Each plan view shows a top portion of the semiconductor device, and each perspective view shows a lower portion of a dummy gate structure.

[0071] Figure 5 , Figure 7 , Fig. 9 and Fig. 27 is along Fig.11 For example, Figure 5 , Figure 7 , Fig. 9 and Fig. 27 is a cross-sectional view of a portion of the gate pattern cut in the second direction. Fig.10 , Fig.12 , Fig.14 , Fig.15 , Fig.17 , Fig.18 , Fig. 20 , Fig.21 , Fig.24 and Fig.25 is along Fig.11 A cross-sectional view taken along line CC'. Fig.10 , Fig.12 , Fig.14 , Fig.15 , Fig.17 , Fig.18 , Fig. 20 , Fig.21 , Fig.24 and Fig.25 is a cross-sectional view of a portion of the gate pattern cut in a first direction.

[0072] Reference Figure 5 and Figure 6 , sacrificial layers 102 and semiconductor layers 104 are alternately and repeatedly stacked on a substrate 100. The uppermost layer may be the semiconductor layer 104.

[0073] The sacrificial layer 102 may include a material having a high etching selectivity with respect to the substrate 100 and the semiconductor layer 104. The sacrificial layer 102 may include a semiconductor material. For example, the semiconductor layer 104 may be a silicon layer, and the sacrificial layer 102 may be silicon germanium.

[0074] In example embodiments, the sacrificial layer 102 and the semiconductor layer 104 are formed by an epitaxial growth process.

[0075] Reference Figure 7 and Figure 8 A hard mask (not shown) extending in the first direction may be formed on the uppermost semiconductor layer 104. The semiconductor layer 104, the sacrificial layer 102, and the upper portion of the substrate 100 may be etched using the hard mask to form the active region 100a and the line structure.

[0076] The active region 100a may be formed on the substrate 100, and the active region 100a may extend in the first direction. A wire structure may be formed on the active region 100a. The wire structure may include sacrificial wires 106 and semiconductor wires 108 alternately and repeatedly stacked on the active region. In example embodiments, a plurality of wire structures are arranged to be spaced apart from each other in the second direction.

[0077] An isolation pattern 110 may be formed on the substrate 100 to cover a portion of a sidewall of the active region 100a. In addition, the hard mask may be removed.

[0078] Reference Figures 9 to 11 , a dummy gate structure 124 and a dummy hard mask 126 extending in the second direction may be formed on the line structure and isolation pattern 110 .

[0079] In an example embodiment, the dummy gate structure 124 may include a dummy gate insulating layer 120 and a dummy gate pattern 122. The dummy gate insulating layer 120 may be an oxide such as silicon oxide, and the dummy gate pattern 122 may be, for example, polysilicon. The dummy hard mask 126 may be, for example, silicon nitride. These dummy patterns are described as dummy patterns because they will be removed later (as described below) and replaced by other patterns that remain in the final product.

[0080] In example embodiments, the dummy gate structure 124 may be formed at a top surface and a sidewall of each line structure in the second direction and in a space between the line structures in the second direction.

[0081] In example embodiments, the plurality of dummy gate structures 124 are spaced apart from one another in the first direction.

[0082] Reference Fig.12 and Fig.13 , a second spacer 138 may be formed on the sidewalls of the dummy gate structure 124 and the dummy hard mask 126 .

[0083] Specifically, a second spacer layer may be formed on the substrate 100 on which the wire structure, the isolation pattern 110, the dummy gate structure 124, and the dummy hard mask 126 are formed. The second spacer layer may be anisotropically etched to form second spacers 138.

[0084] The line structure may be etched using the dummy hard mask 126 , the dummy gate structure 124 , and the second spacer 138 as an etching mask, thereby exposing an upper surface of the active region 100 a .

[0085] Thus, the sacrificial line 106 and the semiconductor line 108 formed under the dummy gate structure 124 and the second spacer 138 may be cut to form a preliminary sacrificial pattern 130 and a preliminary semiconductor pattern 132, respectively. In addition, the first structure 134 including the stacked preliminary sacrificial pattern 130 and the preliminary semiconductor pattern 132 may have a columnar shape. The first structures 134 may be spaced apart from each other in each of the first direction and the second direction.

[0086] The first openings 140 may be formed between the first structures 134 spaced apart from each other in the first direction. Sidewalls of the preliminary sacrificial pattern 130 and the preliminary semiconductor pattern 132 may be exposed through the first openings 140 .

[0087] Reference Fig.14 , both (eg, opposite) sidewalls of the preliminary sacrificial pattern 130 exposed by the first opening 140 may be partially etched to form a first recess 142 .

[0088] During the etching process for forming the first recess 142, upper and lower surfaces at the edge of the preliminary semiconductor pattern 132 may be etched together by an etching source for etching the preliminary sacrificial pattern 130. Thus, a second structure 134a including the sacrificial pattern 130a and the semiconductor pattern 132a may be formed.

[0089] The etching process may include an isotropic etching process. In example embodiments, the etching process may include wet etching or isotropic dry etching.

[0090] When the isotropic etching process is performed, the preliminary sacrificial pattern 130 may be etched by the etchant or etchant gas that continuously flows from the outer wall of the preliminary sacrificial pattern 130. Therefore, the etching amount of the outer wall of the preliminary sacrificial pattern 130 may be large, and the etching amount may decrease toward the inner side of the preliminary sacrificial pattern 130. The inner side of the preliminary sacrificial pattern 130 may be the middle portion of the preliminary sacrificial pattern 130 in the first direction.

[0091] Therefore, the width W1 of the middle portion of the sacrificial pattern 130a in the vertical direction in the first direction may be smaller than the width W2 of the upper and lower sacrificial patterns 130a in the first direction. In example embodiments, the width of the sacrificial pattern 130a in the first direction may gradually decrease from its upper and lower surfaces toward its middle portion.

[0092] During the etching process for forming the first recess, the upper and lower surfaces at the edges of the preliminary semiconductor pattern 132 may be etched together. Therefore, the first thickness T1 of both ends of the semiconductor pattern 132a in the vertical direction may be smaller than the second thickness T2 of the middle portion of the semiconductor pattern 132a in the first direction in the vertical direction.

[0093] In example embodiments, the first recess 142 may have a concave rounded shape toward a middle portion of the sacrificial pattern 130 a in the first direction.

[0094] In example embodiments, due to the formation of the first recess 142, the width of the sacrificial pattern 130a in the first direction (e.g., the average, minimum or maximum width in the first direction) may be smaller than the width of the semiconductor pattern 132a in the first direction (e.g., the corresponding average, minimum or maximum width in the first direction).

[0095] Fig.16 , Fig.19 , Fig. 22 and Fig.26 is a perspective view of a portion below the dummy gate structure.

[0096] Reference Fig.15 and Fig.16 , a first spacer 144 may be formed in each first recess 142 .

[0097] Specifically, a first spacer layer may be conformally formed on the dummy gate structure 124, the dummy hard mask 126, the second spacer 138, the second structure 134a, the active area 100a, and the isolation pattern to fill the first recess 142. The first spacer layer may be anisotropically etched to form the first spacer 144. The first spacer layer may be formed by a deposition process such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. The first spacer 144 may refer to all spacers (e.g., a first spacer group) formed on a specific sidewall during an etching process, or may refer to a single first spacer 144 formed at a specific vertical height to contact a separate sacrificial pattern 130a.

[0098] In example embodiments, the first spacer 144 may be located only in the first recess 142. Therefore, the sacrificial pattern 130a is not exposed by the sidewalls of the second structure 134a in the first direction, and only the semiconductor pattern 132a is exposed at the sidewalls of the second structure 134a.

[0099] In an example embodiment, the outer wall of each first spacer 144 is aligned with the side wall of the semiconductor pattern 132a in the vertical direction (e.g., coplanar). Alternatively, the outer wall of each first spacer 144 may protrude from the side wall of the semiconductor pattern 132a in the first direction. Therefore, the semiconductor pattern 132a may be exposed by the side wall of the second structure 134a in the first direction. When the outer wall of the first spacer 144 protrudes from the side wall of the semiconductor pattern 132a in the first direction, the semiconductor pattern 132a may be manufactured by performing subsequent processes in the same manner. Figure 4B The semiconductor device shown.

[0100] In some example embodiments, Fig.17 As shown, the outer wall of the first spacer 144a may be recessed inward from the side wall of the semiconductor pattern 132a. For example, the side wall of the semiconductor pattern 132a may protrude from the outer wall of the first spacer 144a in the first direction. Therefore, the side wall, the lower surface, and the upper surface of the edge of the semiconductor pattern 132a may be exposed at the side wall of the second structure 134a in the first direction. The first spacer 144a may be formed, and then subsequent processes may be performed in the same manner to form Figure 4A The semiconductor device shown.

[0101] exist Fig.18 and Fig.19 In the embodiment, the first semiconductor layer 150 is formed to cover the semiconductor pattern 132 a , the first spacer 144 , and the active region 100 a exposed by the first opening 140 .

[0102] The first semiconductor layer 150 may be formed through a selective epitaxial growth process (SEG) while being in-situ doped with impurities to have a first impurity concentration.

[0103] In example embodiments, the first semiconductor layer 150 may be formed by performing a first SEG process using the active region 100 a and the surfaces of the semiconductor pattern 132 a exposed by the first opening 140 as seeds.

[0104] For example, in the first SEG process, a semiconductor layer may be grown from the upper surface of the active region 100a and the surface of the semiconductor pattern 132a. In addition, the semiconductor layer grown from the surface of the semiconductor pattern 132a may flow downward in a vertical direction, and an additional layer may be quickly grown from the grown semiconductor layer in a vertical direction. Therefore, the first semiconductor layer 150 may be continuously formed on the surfaces of the semiconductor pattern 132a, the first spacer 144, and the active region 100a exposed by the first opening 140.

[0105] In an exemplary embodiment, when the first spacer 144 has Fig.15 and Fig.16 In the structure shown, the semiconductor layer may grow from the sidewall of the semiconductor pattern 132 a in the first direction, and the semiconductor layer may flow downward in the vertical direction.

[0106] In example embodiments, when the first spacer 144a has Fig.17 In the structure shown, the semiconductor layer grows from the upper and lower surfaces of the sidewalls and edges of the semiconductor pattern 132 a in the first direction, and the semiconductor layer may flow downward in the vertical direction.

[0107] In example embodiments, the first semiconductor layer 150 formed on the sidewalls of the semiconductor pattern 132a and the first spacer 144 may have a third thickness T3 in the first direction. The first semiconductor layer 150 formed on the upper surface of the active region 100a may have a fourth thickness T4 greater than the third thickness T3 in the vertical direction.

[0108] The first SEG process may be performed using a semiconductor source gas and a purge gas at a first pressure and a first temperature. The purge gas may be introduced at a first flow rate.

[0109] In example embodiments, the first pressure may be in a range of about 300 Torr to about 700 Torr. The first temperature may be in a range of about 550° C. and about 750° C. The purge gas may include nitrogen and / or hydrogen. For example, the first flow rate may be in a range of about 10,000 sccm (standard cubic centimeters per minute) to about 30,000 sccm.

[0110] For example, the first SEG process may be performed at a high pressure, thereby increasing the amount of semiconductor source gas remaining in the deposition chamber. Therefore, the first semiconductor layer 150 may grow to merge in the vertical direction, and the first semiconductor layer 150 may easily flow downward in the vertical direction. In addition, as the flow rate of the purge gas increases, the first semiconductor layer 150 may be suppressed from growing upward.

[0111] In example embodiments, the first semiconductor layer 150 may be formed to include silicon doped with n-type impurities. For example, the first SEG process may use a silicon source gas such as disilane (Si 2 H 6 In this case, the first semiconductor layer 150 may be used as a source / drain extension region of the NMOS transistor.

[0112] In some example embodiments, the first semiconductor layer 150 may be formed to include silicon germanium doped with p-type impurities. For example, the first SEG process may use a germanium source gas such as GeH 4 Gas and silicon source gas such as dichlorosilane (SiH 2 Cl 2 In this case, the first semiconductor layer 150 may be used as a source / drain extension region of a PMOS transistor.

[0113] The shape of the first semiconductor layer 150 may vary depending on the process conditions of the first SEG process. Fig. 20 As shown, the thickness of the first semiconductor layer 150a formed on the sidewalls of the semiconductor pattern 132a and the first spacer 144 in the first direction may be non-uniform. For example, the thickness of the first semiconductor layer 150a formed on the semiconductor pattern 132a may be greater than the thickness of the first semiconductor layer 150a formed on the first spacer 144. In this case, the first semiconductor layer 150a may be manufactured in the same manner through subsequent processes. Figure 3 However, even in this case, the maximum thickness of the first semiconductor layer 150a in a direction perpendicular to the sidewall of the second structure 134a (e.g., in the first direction) may be less than the maximum thickness of the first semiconductor layer 150a in a direction perpendicular to the surface of the active layer 100a (e.g., in the vertical direction) where the first semiconductor layer 150a contacts the active layer 100a.

[0114] Reference Figure 21 to Figure 23, a second semiconductor layer 152 may be formed on the first semiconductor layer 150. The second semiconductor layer 152 may be doped with impurities to have a second impurity concentration higher than the first impurity concentration. In example embodiments, the second semiconductor layer 152 may be doped with impurities having the same conductivity type as that of the impurities of the first semiconductor layer 150. In example embodiments, the second semiconductor layer 152 may include the same material and / or material composition as that of the first semiconductor layer 150.

[0115] In example embodiments, the second semiconductor layer 152 fills spaces between the second structures 134 a spaced apart from each other in the first direction.

[0116] The second semiconductor layer 152 may be formed through a second selective epitaxial growth process while being in-situ doped with impurities to have a second impurity concentration.

[0117] In example embodiments, the second SEG process may be performed under process conditions different from those of the first SEG process. For example, the second SEG process may be performed using a semiconductor source gas and a purge gas at a second pressure lower than the first pressure. In addition, the second SEG process may be performed at a second temperature. The purge gas may be introduced at a second flow rate less than the first flow rate.

[0118] In example embodiments, the second pressure may be in the range of about 100 torr to about 300 torr. The second temperature may be in the range of about 550°C and about 750°C. The second temperature may be the same as or different from the first temperature. For example, the second flow rate may be in the range of about 5000 sccm to about 10000 sccm. In this case, the surface of the first semiconductor layer 150 may be used as a seed to grow the second semiconductor layer 152, and the grown semiconductor layer may not flow downward in the vertical direction.

[0119] In some example embodiments, the second SEG process may be performed under the same process conditions as those of the first SEG process except for the doping concentration of the impurities. In this case, the second semiconductor layer 152 may be grown using the surface of the first semiconductor layer 150 as a seed, and the grown semiconductor layer may flow downward in a vertical direction.

[0120] In example embodiments, the second semiconductor layer 152 may be formed to include silicon doped with n-type impurities at a second impurity concentration. In this case, the second semiconductor layer 152 may function as a source / drain region of an NMOS transistor.

[0121] In some example embodiments, the second semiconductor layer 152 may be formed to include silicon germanium doped with p-type impurities at a second impurity concentration. In this case, the second semiconductor layer 152 may function as a source / drain region of a PMOS transistor.

[0122] Reference Fig.24 , an insulating layer 154 may be formed to cover the second structure 134a and the first and second semiconductor layers 150 and 152, and the insulating layer 154 may be planarized until an upper surface of the dummy gate structure 124 is exposed. During the planarization process, the dummy hard mask 126 may be removed together, and an upper portion of the second spacer 138 may be partially removed. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0123] Thereafter, the dummy gate pattern 122 and the dummy gate insulating layer 120 below the dummy gate pattern 122 are removed to form a second opening 156. The inner wall of the second spacer 138 and the sidewall of the second structure 134a in the second direction, the end surface of the first spacer 144 in the second direction, and the upper surface of the active region 100a and the isolation pattern 110 may be exposed through the second opening 156.

[0124] Sidewalls of the semiconductor pattern 132 a and the sacrificial pattern 130 a in the second direction may be exposed through the second openings 156 .

[0125] Reference Figure 25 to Figure 27 , the sacrificial pattern 130a exposed through the second opening 156 is selectively removed to form a first gap 158. The first gap 158 communicates with the second opening 156. Therefore, the first gap 158 and the second opening 156 merge to extend in the second direction.

[0126] The selective removal of the sacrificial pattern 130a may be performed by an isotropic etching process. The isotropic etching process may include a wet etching process or an isotropic dry etching process.

[0127] In the etching process of the sacrificial pattern 130a, an etchant or etching gas may be introduced into the first semiconductor layer 150 along the interface of the first spacer 144. Specifically, the etchant or etching gas may be introduced into the first semiconductor layer 150 through the edge of the semiconductor pattern 132a having the first thickness and the first spacer 144.

[0128] However, the first semiconductor layer 150 may be doped with impurities at a first concentration that is lower than that of the second semiconductor layer 152. Therefore, an etching rate of the first semiconductor layer 150 with respect to an etchant or etching gas may be lower than an etching rate of the second semiconductor layer 152 with respect to an etchant or etching gas. Since the doping concentration of the impurities is low, the first semiconductor layer 150 may not be damaged or etched by the etchant or etching gas.

[0129] In addition, since the first semiconductor layer 150 prevents the etchant or etching gas from being introduced into the second semiconductor layer 152, the second semiconductor layer 152 may not contact the etchant or etching gas. Therefore, the second semiconductor layer 152 may not be damaged or etched by the etchant or etching gas. Therefore, defects such as holes do not occur in the second semiconductor layer 152.

[0130] Reference again Figure 1A , Figure 1B and Figure 2 , gate structures 162 a and 162 b may be formed on the substrate 100 to fill the second opening 156 and the first gap 158 .

[0131] Specifically, an oxide layer (not shown) may be formed on the upper surface of the active region 100a and the surface of the semiconductor pattern 132a exposed by the second opening 156 and the first gap 158. A gate insulating layer may be conformally formed on the oxide layer, the inner walls of the first and second spacers 144 and 138, and the upper surface of the insulating layer 154, and a gate electrode layer may be formed on the gate insulating layer to fill the second opening 156 and the first gap 158. In example embodiments, a work function control layer may be further formed between the gate insulating layer and the gate electrode layer.

[0132] Each of the gate insulating layer, the work function control layer, and the gate electrode layer may be formed by a CVD process, an ALD process, a physical vapor deposition (PVD) process, or the like.

[0133] Thereafter, the gate electrode layer, the work function control layer, and the gate insulating layer may be planarized until a top surface of the insulating layer 154 is exposed to form gate structures 162a and 162b including a gate insulating pattern 160a, a work function control pattern, and a gate pattern 160b.

[0134] As described above, the first semiconductor layer 150 may cover the semiconductor pattern 132a, the first spacer 144, and the active region 100a, and the second semiconductor layer 152 may be formed on the first semiconductor layer 150. Therefore, the second semiconductor layer 152 may not be damaged by an etchant or an etching gas in an etching process for forming the first gap 158. Therefore, the semiconductor device may have high reliability.

[0135] Fig.28 and Fig.29 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0136] Fig.28 is a cross-sectional view of a portion of the gate pattern cut in a first direction, and Fig.29 is a cross-sectional view of a portion of the gate pattern cut in the second direction.

[0137] In addition to using a substrate including a stacked base substrate, an insulating layer, and an upper substrate, the semiconductor device can be used with reference Figure 1A , Figure 1B and Figure 2 The semiconductor devices described are the same or similar.

[0138] Reference Fig.28 and Fig.29 , the active region 100a may be formed by patterning an upper substrate formed on the insulating layer. Therefore, the insulating layer 101 may be disposed below the active region 100a and above the base substrate 100b.

[0139] In some example embodiments, the substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0140] Fig.30 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0141] The semiconductor device may also be included in the reference Figure 1A , Figure 1B and Figure 2 The upper wiring in the semiconductor device is shown.

[0142] Reference Fig.30 A capping pattern 170 may be formed to cover the top of the second gate structure 162b. A second spacer 138 may be formed on the sidewall of the structure including the stacked second gate structure 162b and the capping pattern 170. The capping pattern 170 may be an insulating material, such as silicon nitride or silicon oxynitride.

[0143] The contact plug 172 may pass through the insulating layer filling the space between the second gate structures 162b (see Fig.31 , 154). The contact plug 172 may contact the upper surfaces of the first semiconductor layer 150 and the second semiconductor layer 152. The contact plug 172 may include and may be formed of a metal material. In example embodiments, the contact plug 172 may include a first barrier metal layer 172a and a first metal layer 172b that are stacked.

[0144] In example embodiments, a bottom surface of the contact plug 172 may be lower than a top surface of the uppermost semiconductor pattern 132 a .

[0145] An upper interlayer insulating layer 174 may be formed on the capping pattern 170, the second spacer 138, and the contact plug 172. A conductive pattern 176 may pass through the upper interlayer insulating layer 174. The conductive pattern 176 may contact the contact plug 172.

[0146] The conductive pattern 176 may include and be formed of a metal material. In example embodiments, the conductive pattern 176 may have a second barrier metal layer 176a and a second metal layer 176b stacked.

[0147] In example embodiments, the conductive pattern 176 may have a line shape extending in a certain direction. In some embodiments, the conductive pattern 176 may serve as an upper contact plug.

[0148] As described above, the semiconductor device may further include an upper wiring electrically connected to the source / drain regions of the MBCFET.

[0149] Fig.31 and Fig.32 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0150] You can reference it by executing Figures 5 to 27 The process shown and further performing additional processes to manufacture Fig.30 The semiconductor device shown.

[0151] Reference Fig.31 , first, you can execute the reference Figures 5 to 27 Thereafter, an upper portion of the second gate structure 162 b is partially etched to form a recess defined by upper surfaces of the second gate structure 162 b and the second spacer 138 .

[0152] A capping layer may be formed to fill the recess. The capping layer may be planarized until an upper surface of the insulating layer 154 is exposed to form a capping pattern 170. The capping pattern 170 may be formed on the second gate structure 162b.

[0153] Reference Fig.32 , the insulating layer 154 between the second gate structures 162b may be etched to form a contact hole. The upper surfaces of the first semiconductor layer 150 and the second semiconductor layer 152 may be exposed by the bottom surface of the contact hole. In example embodiments, upper portions of the first semiconductor layer 150 and the second semiconductor layer 152 may be partially etched in the etching process.

[0154] A conductive layer may be formed to fill the contact hole. The conductive layer may be planarized until upper surfaces of the insulating layer 154 and the capping pattern 170 are exposed to form a contact plug 172. The contact plug 172 may contact upper surfaces of the first semiconductor layer 150 and the second semiconductor layer 152 through the insulating layer 154.

[0155] Reference again Fig.30 , an upper interlayer insulating layer 174 may be formed on the capping pattern 170, the second spacer 138, and the contact plug 172. Thereafter, a conductive pattern 176 may be formed on the contact plug 172. The conductive pattern 176 may pass through the upper interlayer insulating layer 174 and may contact the contact plug 172. Thus, a Fig.30 The semiconductor device shown. According to example embodiments, the shape of the first spacer may be variously modified. Hereinafter, example embodiments according to the shape of the first spacer are described.

[0156] Fig.33 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0157] Except that the first spacer has a cubic shape, the semiconductor device can be similar to the reference Figure 1A , Figure 1B and Figure 2 The semiconductor devices shown are the same or similar.

[0158] Reference Fig.33 , the outer wall and the inner wall of the first spacer 145 may have a vertical inclination, respectively. The first spacer 145 may contact the sidewall of the first gate structure 162a and the upper and lower surfaces at the edge of the semiconductor pattern 132a. Therefore, according to the shape of the first spacer 145, the thickness of the semiconductor pattern 132a in the vertical direction may be substantially the same regardless of the position of the semiconductor pattern 132a. In addition, the width of the first gate structure 162a may be substantially the same regardless of the position of the first gate structure 162a.

[0159] Figure 34 to Figure 36 are cross-sectional views illustrating semiconductor devices according to example embodiments, respectively.

[0160] Each semiconductor device may be similar to the reference Figure 1A , Figure 1B and Figure 2 The semiconductor devices shown are the same or similar.

[0161] Reference Fig.34 The outer wall of the first spacer 144 may include a recess at the middle of the outer wall in the vertical direction. The recess may have a concave rounded shape toward the middle of the gate structure in the first direction.

[0162] Reference Fig.35 , the entire outer wall of the first spacer 144 may have a concave rounded shape toward the middle of the gate structure in the first direction. In example embodiments, the curvature of the outer wall of the first spacer 144 may be smaller than the curvature of the inner sidewall of the first spacer 144 .

[0163] In some example embodiments, a thickness of the first spacer in the first direction may be different at each height.

[0164] Reference Fig.36 , the upper and lower surfaces of the first spacer 144 may be flat. In addition, the inner wall of the first spacer 144 may have a rounded shape.

[0165] Fig.37 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0166] In addition to the shapes of the gate structure and the first spacer, Fig.37 The semiconductor device shown in FIG. Figure 1A , Figure 1B and Figure 2 The semiconductor devices shown are the same or similar.

[0167] Reference Fig.37 , a thickness of a middle portion of the first gate structure 162 a in the vertical direction may be greater than a thickness of a middle portion of the semiconductor pattern 132 a in the vertical direction.

[0168] When executing reference Fig.25 and 26 In the process shown, the surface of the semiconductor pattern exposed by the top and bottom of the first gap may be partially etched, thereby increasing the width of the first gap in the vertical direction.

[0169] In example embodiments, a thickness of a middle portion of the first gate structure 162 a in the vertical direction may be greater than a thickness of the first gate structure 162 a in the vertical direction where the first gate structure 162 a contacts the first spacer 144 .

[0170] In example embodiments, a thickness of the first gate structure 162 a in a vertical direction may be greater than a thickness of the first spacer 144 in the vertical direction.

[0171] Fig.38 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0172] The semiconductor device may include an N-type MBCFET formed on a first region of a substrate and a P-type MBCFET formed on a second region of the substrate. The semiconductor device may be a semiconductor chip formed on a die and including an integrated circuit on the die. The integrated circuit includes an N-type MBCFET and a P-type MBCFET.

[0173] Reference Fig.38 , each of the N-type MBCFET and the P-type MBCFET can be compared with the reference Figure 1A and Figure 1B as well as Figure 2 The semiconductor devices shown are the same.

[0174] For example, in an N-type MBCFET, the first semiconductor layer 151a may include or may be silicon doped with n-type impurities. In addition, the second semiconductor layer 153a may include or may be silicon doped with n-type impurities having a higher concentration than that in the first semiconductor layer 151a. For example, the n-type impurities may be or may include phosphorus (P) or arsenic (As).

[0175] In a P-type MBCFET, the first semiconductor layer 151b may include or may be silicon germanium doped with p-type impurities. In addition, the second semiconductor layer 153b may include or may be silicon germanium doped with p-type impurities having a higher concentration than that in the first semiconductor layer 151b. For example, the p-type impurity may be or may include boron.

[0176] As described above, the N-type MBCFET and the P-type MBCFET may include semiconductor layers including different semiconductor materials.

[0177] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present invention. In the claims, means-plus-function clauses are intended to encompass structures described herein that perform the functions described, and include not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as limiting to the specific example embodiments disclosed, and modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims.

[0178] Ordinal numbers such as "first", "second", "third", etc. may be used only as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term mentioned with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

Claims

1. A semiconductor device, include: semiconductor patterns on a substrate, the semiconductor patterns being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and overlapping in the vertical direction; a gate structure on the substrate and the semiconductor pattern, wherein at least a portion of the gate structure is formed between the semiconductor patterns in a vertical direction; a first spacer covering each of opposite sidewalls of the gate structure, the sidewalls being opposite to each other in a first direction; a first semiconductor layer, covering the sidewall of the semiconductor pattern in the first direction and the surface of the first spacer and the substrate, the first semiconductor layer having a first impurity concentration; as well as a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a second impurity concentration higher than the first impurity concentration, wherein at least a portion of the first spacer contacts the upper and lower surfaces of each semiconductor pattern at an edge of the semiconductor pattern, and wherein, for each semiconductor pattern, a first thickness in the vertical direction of an edge portion of the semiconductor pattern in contact with the first spacer is smaller than a second thickness in the vertical direction of a portion of the semiconductor pattern not in contact with the first spacer, The first semiconductor layer formed on the first spacer and on the sidewall of the semiconductor pattern in the first direction has a third thickness, and the first semiconductor layer formed on the surface of the substrate has a fourth thickness greater than the third thickness.

2. The semiconductor device according to claim 1, in, The first spacer contacting the gate structure and the semiconductor pattern has a concave rounded shape toward a middle portion of the gate structure in the first direction.

3. The semiconductor device according to claim 1, in, A maximum width of the gate structure in the first direction is smaller than a maximum width of each semiconductor pattern in the first direction.

4. The semiconductor device according to claim 1, in, The semiconductor patterns spaced apart from each other in a vertical direction serve as semiconductor pattern structures, and a plurality of semiconductor pattern structures are spaced apart from each other in each of the first direction and a second direction perpendicular to the first direction and parallel to an upper surface of the substrate.

5. The semiconductor device according to claim 4, in, The first semiconductor layer has a continuously connected shape to cover the sidewalls of the semiconductor pattern and the first spacer in the semiconductor pattern structure and the substrate, and wherein the second semiconductor layer fills a space between the semiconductor pattern structures adjacent to each other in the first direction.

6. The semiconductor device according to claim 4, in, The gate structure contacts a side surface of the semiconductor pattern included in the semiconductor pattern structure in the second direction, and the gate structure extends in the second direction.

7. The semiconductor device according to claim 1, in, An outer wall of the first spacer is disposed to be aligned with a sidewall of the semiconductor pattern in a vertical direction.

8. The semiconductor device according to claim 1, in, An outer wall of the first spacer is recessed inwardly from a sidewall of the semiconductor pattern in the first direction.

9. The semiconductor device according to claim 1, in, The gate structure is also formed on the uppermost semiconductor pattern, and further includes a second spacer on a sidewall of the gate structure formed on the uppermost semiconductor pattern in the first direction.

10. The semiconductor device according to claim 1, in, The first spacer includes at least one of silicon nitride, silicon carbonitride, silicon boron nitride, and silicon oxynitride.

11. The semiconductor device according to claim 1, in, A top surface of the second semiconductor layer is higher than a top surface of an uppermost semiconductor pattern among the semiconductor patterns, and the second semiconductor layer overlaps the first semiconductor layer in the first direction.

12. The semiconductor device according to claim 1, in, The second semiconductor layer includes the same material as the first semiconductor layer.

13. The semiconductor device according to claim 1, in, A thickness of the first semiconductor layer formed on the semiconductor pattern is greater than a thickness of the first semiconductor layer formed on the first spacer.

14. A semiconductor device, include: A stack structure is formed on a substrate, the stack structure comprising a semiconductor pattern, a gate structure and a first spacer, and the semiconductor pattern and the first spacer are exposed at an outer wall of the stack structure in a first direction parallel to an upper surface of the substrate; a first semiconductor layer, covering an outer wall of the stacked structure in the first direction and covering a surface of the substrate, wherein the first semiconductor layer is doped with impurities of a first concentration; as well as a second semiconductor layer on the first semiconductor layer, the second semiconductor layer being doped with impurities at a second concentration, the second concentration being higher than the first concentration, wherein the first spacer contacts the upper surface and the lower surface of the semiconductor pattern at the edge of the semiconductor pattern, and a first thickness of the semiconductor pattern in a vertical direction at the edge where the semiconductor pattern contacts the first spacer is smaller than a second thickness of a portion of the semiconductor pattern not contacting the first spacer in the vertical direction, The first semiconductor layer formed on the outer wall of the stacked structure in the first direction has a third thickness, and the first semiconductor layer formed on the surface of the substrate has a fourth thickness greater than the third thickness.

15. The semiconductor device according to claim 14, in, The plurality of stacked structures are arranged to be spaced apart from each other in each of the first direction and a second direction perpendicular to the first direction, The first semiconductor layer has a continuously connected shape to cover outer walls of the stacked structures adjacent to each other in the first direction and the surface of the substrate between the stacked structures, and the second semiconductor layer fills the space between the stacked structures adjacent to each other in the first direction.

16. The semiconductor device according to claim 14, in, The first spacer contacting the gate structure and the semiconductor pattern has a concave rounded shape toward a middle portion of the gate structure in the first direction.

17. The semiconductor device according to claim 14, in, The second semiconductor layer includes the same material as the first semiconductor layer.

18. The semiconductor device according to claim 14, in, A thickness of the first semiconductor layer formed on the semiconductor pattern is greater than a thickness of the first semiconductor layer formed on the first spacer.

19. A semiconductor device, include: semiconductor patterns on a substrate, the semiconductor patterns being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a first spacer formed between the semiconductor patterns in a vertical direction, the first spacer contacting upper and lower surfaces of the semiconductor patterns at edges of the semiconductor patterns; a gate structure on the substrate filling a first gap defined by the semiconductor pattern and the first spacer; a first semiconductor layer covering the sidewalls of the semiconductor pattern in a first direction and the surfaces of the first spacer and the substrate; as well as a second semiconductor layer directly on the first semiconductor layer and overlapping the first semiconductor layer in the first direction, the second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer, The first semiconductor layer formed on the first spacer and on the sidewall of the semiconductor pattern in the first direction has a third thickness, and the first semiconductor layer formed on the surface of the substrate has a fourth thickness greater than the third thickness.

20. The semiconductor device according to claim 19, in, The second semiconductor layer includes the same material as the first semiconductor layer.

21. The semiconductor device according to claim 19, in, A thickness of the first semiconductor layer formed on the semiconductor pattern is greater than a thickness of the first semiconductor layer formed on the first spacer.

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