Instruction dispatch method and processor

Abstract

The present disclosure relates to an instruction allocation method and processor, the allocation method comprising: determining the type of instruction based on the attributes of the instruction; sending instructions of the first type to a first issue queue, and sending instructions of the second type to a second issue queue, wherein the first issue queue is an issue queue based on a matrix structure, and the second issue queue is an issue queue based on a scoreboard-content addressable memory (CAM) structure; and executing the instructions in the first issue queue and the second issue queue.

Description

Technical Field

[0001] The present disclosure relates to the field of information processing, and in particular to an instruction distribution method and a processor. Background Art

[0002] Current microprocessors are designed to execute instructions in parallel and out of order. In high-performance processors, instructions are scheduled into an issue queue, where they wait until their operands are ready and the required resources are available. Within the processor's microarchitecture, the issue queue stores instructions awaiting execution and uses logic to monitor operand readiness and select ready instructions for issuance to the execution units. The issue queue is a complex component of the microarchitecture and one of the largest consumers of energy, a primary driver of power density, and a key driver of performance.

[0003] Existing methods for implementing issue queues face the problems of high logic complexity and high power consumption of the issue queues. This application aims to provide an improved issue queue design method that reduces the complexity of the issue queue's issue logic and reduces power consumption by properly allocating instructions. Summary of the Invention

[0004] In view of this, the present disclosure proposes an instruction allocation method, characterized in that the allocation method is applied to a processor, and the allocation method includes: determining the type of instruction according to the attributes of the instruction; sending instructions belonging to the first type to a first issue queue, and sending instructions belonging to the second type to a second issue queue, the first issue queue is a issue queue based on a matrix structure, and the second issue queue is a issue queue based on a scoreboard-content addressable memory CAM structure; and executing instructions in the first issue queue and the second issue queue.

[0005] In one possible implementation, the type of instruction is determined based on the attributes of the instruction, including: judging whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; if it is judged that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the first type; if it is judged that the instruction is not required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the second type.

[0006] In one possible implementation, determining whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle includes: determining whether a source operand of the other instruction depends on a destination operand of the instruction; and in the case where it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the first type includes: in the case where it is determined that the source operand of the other instruction depends on the destination operand of the instruction, determining that the instruction belongs to the first type.

[0007] In a possible implementation, the predetermined period refers to an execution delay from when the instruction is issued until when the instruction is executed.

[0008] In one possible implementation, determining the type of instruction based on the attributes of the instruction includes: determining whether the execution delay of the instruction is fixed or variable; if it is determined that the execution delay of the instruction is fixed, determining that the instruction belongs to the first type; if it is determined that the execution delay of the instruction is variable, determining that the instruction belongs to the second type.

[0009] In a possible implementation, determining whether the execution delay of the instruction is fixed or variable includes determining whether the execution delay of the instruction is fixed or variable according to a unit or an operation code field of the instruction.

[0010] In one possible implementation, the type of instruction is determined based on the attributes of the instruction, including: determining whether the instruction is an important instruction; if the instruction is determined to be an important instruction, determining that the instruction belongs to the first type; if the instruction is determined to be not an important instruction, determining that the instruction belongs to the second type.

[0011] In one possible implementation, the important instructions include earlier instructions stored in the processor, X86 branch instructions in the instruction sequence, and instructions designated as having an importance attribute.

[0012] According to one aspect of the present disclosure, a processor is provided, characterized in that it includes: multiple issue queues, including a first issue queue and a second issue queue, the first issue queue is an issue queue based on a matrix structure, and the second issue queue is an issue queue based on a scoreboard-content addressable memory (CAM) structure; a queue allocation module, configured to determine the type of instruction according to the attributes of the instruction, send instructions of the first type to the first issue queue, and send instructions of the second type to the second issue queue; and multiple execution units, wherein the first issue queue and the second issue queue issue their respective instructions to corresponding execution units among the multiple execution units for execution.

[0013] In one possible implementation, the queue allocation module includes: a first sub-module, configured to determine whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; if it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the first type; if it is determined that the instruction is not required to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the second type.

[0014] In one possible implementation, the queue allocation module includes: a second sub-module, configured to determine whether the execution delay of the instruction is fixed or variable; if it is determined that the execution delay of the instruction is fixed, determining that the instruction belongs to the first type; if it is determined that the execution delay of the instruction is variable, determining that the instruction belongs to the second type.

[0015] In one possible implementation, the queue allocation module includes: a third submodule, configured to determine whether the instruction is an important instruction; if the instruction is determined to be an important instruction, determine that the instruction belongs to the first type; if the instruction is determined to be not an important instruction, determine that the instruction belongs to the second type.

[0016] According to the present disclosure, since all instructions are respectively allocated to a matrix-structured issue queue and a scoreboard-CAM-structured issue queue, compared to an issue queue based on a single structure (using only a matrix-structured issue queue or only a scoreboard-CAM-structured issue queue) or an issue queue based on another structure, the advantages of the matrix structure and the scoreboard-CAM structure enable the utilization of the issue queue to be improved when executing instructions at a high clock rate. According to the present disclosure, the size of the matrix can be reduced, and the number of physical registers can be reduced. Furthermore, the scoreboard-CAM can reduce the number of broadcast destination tags and reduce comparison logic. The present disclosure is conducive to reducing power consumption and improving system performance.

[0017] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0019] Figure 1 A schematic diagram showing a processing method using an issue queue based on a scoreboard-CAM structure.

[0020] Figure 2 A schematic diagram showing a processing method using a matrix-based publishing queue.

[0021] Figure 3 A schematic diagram illustrating the configuration of a publishing queue according to an example embodiment of the present application.

[0022] Figure 4 A flowchart illustrating an instruction dispatching method according to an example embodiment of the present application is shown.

[0023] Figure 5 A block diagram of a processor according to an example embodiment of the present application is shown.

[0024] Figure 6 A block diagram illustrating a processor according to another example embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0026] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0027] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0028] Release queue based on scoreboard-CAM structure

[0029] In current processors, when designing the issue logic of the processor, one of the methods for implementing the issue queue is a method based on a scoreboard-CAM (content addressable memory) structure. Figure 1 A schematic diagram showing a processing method using a release queue based on a scoreboard-CAM structure (sometimes referred to herein as "scoreboard-CAM"). Figure 1As illustrated, the structure holds instruction information and tags. Typically, an instruction accesses the scoreboard to check if it has dependencies on other instructions. Tags used by the CAM are generated. The CAM stores the destination (dest) tag, the source index, and a source tag indicating whether the source is ready. When an instruction is issued, the destination tag of the instruction is broadcast to all instructions held in the "issue queue". The source index of each instruction is then compared with the broadcasted destination tag; if there is a match, the operand is marked as ready. The processor can broadcast and compare multiple tags in parallel. The number of tags is related to the dispatch port. In Figure 1 In the example, N is an integer greater than or equal to 1. Since current microarchitectures support multiple execution units, many results may be generated in a given cycle, resulting in an increasing number of tags. The multiple tag comparisons that must be performed in each cycle make the release logic very complex and consume a lot of power. The characteristic of the release queue based on the scoreboard-CAM structure is that many tag comparisons may be performed, and these tag comparisons must be performed in every cycle. This feature makes the release queue the main place for power density. At the same time, although it is easy to implement a large out-of-order release queue using a release queue based on the scoreboard-CAM structure, it is difficult to implement at high clock rates.

[0030] Release queue based on matrix structure

[0031] In current processors, when designing the processor's issue logic, a matrix-based issue queue (sometimes referred to herein as a "matrix") is another approach to implementing the issue queue. The bit matrix has as many rows as the number of entries in the issue queue and as many columns as the number of physical registers. When the issue logic receives an instruction, this approach clears the bits of all ready physical registers in the instruction line to zero, while keeping the bits of the unready physical registers in the instruction line at 1. When all the bits of the physical registers in the instruction line are 0, it indicates that the instruction is ready. Figure 2 A schematic diagram showing a processing method using a release queue based on a matrix structure. Figure 2As shown, the matrix holds the destination tags and dependency bit vectors of instructions. When an instruction accesses the matrix, the instruction's source index is compared with the destination tag of each entry. If a match occurs, the instruction records the corresponding entry's address. Therefore, each instruction generates a dependency bit vector, indicating which entry's instruction has a dependency relationship. When an instruction is issued, the matrix broadcasts a wakeup bit vector for each entry. The dependency bit vector of each entry performs logic with the wakeup bit vector. If the dependency bit vector is all zero, the instruction is ready and can be issued. The resource consumption of the matrix is related to its size: the dependency bit vector and the wakeup bit vector are proportional to the size of the matrix and quadratically to the number of physical registers. Implementing a large out-of-order issue queue requires a large number of physical registers, which results in a very large matrix size. This also complicates the detection logic because the number of bits checked when checking instruction readiness must be equal to the number of physical registers. Furthermore, the matrix needs to record the status of the instruction, and when an instruction is issued, the corresponding entry cannot usually be released directly. Therefore, the utilization rate of a matrix-based issue queue is low.

[0032] Since it is difficult to implement a large out-of-order release queue at a high clock rate, the present application utilizes the characteristics of a scoreboard-CAM structure-based release queue and a matrix-based release queue, and combines these two structures for implementing release queues to implement a combined large out-of-order release queue.

[0033] As described above, the advantage of a scoreboard-CAM-based issue queue is that the scoreboard can record instruction status, and the CAM can release instructions when they are issued, which can reduce the number of required physical registers and improve issue queue utilization. The advantage of a matrix-based issue queue is that it can operate at a high clock rate, which can increase instruction execution speed. This application combines a scoreboard-CAM-based issue queue with a matrix-based issue queue to leverage their respective advantages while reducing the complexity of the issue queue's issue logic and reducing power consumption.

[0034] Release queue of composite structure

[0035] Figure 3 A schematic diagram illustrating the configuration of an issue queue according to an embodiment of the present disclosure is provided. In a processor, when designing the processor's issue logic, based on the characteristics of an issue queue based on a scoreboard-CAM (content-addressable memory) structure and an issue queue based on a matrix structure, the issue logic configuration is configured to include: classifying instructions based on their attributes; sending some instructions to an issue queue based on a matrix structure, while sending other instructions to an issue queue based on a scoreboard-CAM structure; and having each issue queue send instructions to a corresponding execution unit for execution.

[0036] Figure 4 Flowchart showing the instruction distribution method according to the present application. Figure 4 As shown, in step 401, the type of instruction is determined based on the attributes of the instruction. If the instruction type is determined to be the first type in step 401, the process proceeds to step 402. In step 402, the first type of instruction is sent to an issue queue based on a matrix structure. Then, in step 404, the instructions in the issue queue based on the matrix structure are executed. If the instruction type is determined to be the second type in step 401, the process proceeds to step 403. In step 403, the second type of instruction is sent to an issue queue based on a scoreboard-CAM structure. Then, in step 405, the instructions in the issue queue based on the scoreboard-CAM structure are executed. The process of the instruction dispatch method then ends.

[0037] In one possible implementation, the type of instruction is determined based on the attributes of the instruction, including: judging whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; if it is judged that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the first type; if it is judged that the instruction is not required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the second type.

[0038] Among the instructions to be processed by the processor, some instructions need to wake up other instructions back-to-back within a predetermined cycle. These instructions that need to wake up other instructions back-to-back within a predetermined cycle are assigned to an issue queue based on a matrix structure. This allows the back-to-back wake-up operations to be completed at a higher clock rate. The remaining instructions can be assigned to an issue queue based on a scoreboard-CAM structure.

[0039] In one possible implementation, determining whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle includes: determining whether a source operand of the other instruction depends on a destination operand of the instruction; and in the case where it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the first type includes: in the case where it is determined that the source operand of the other instruction depends on the destination operand of the instruction, determining that the instruction belongs to the first type.

[0040] For example, when the source (src) operand of instruction B depends on the destination (dest) operand of instruction A, instruction A is determined to be of the first type and is assigned to the issue queue based on the matrix structure; instruction B is determined to be of the second type and is assigned to the issue queue based on the scoreboard-CAM structure. Instruction A wakes up instruction B at a certain stage after being issued. "Wake up" here means eliminating the dependency of instruction B on instruction A. After waking up, instruction B becomes a ready instruction and can also be issued through the matrix or scoreboard-CAM. The wake-up stage is determined by the execution delay of instruction A. The predetermined period refers to the execution delay from the time the instruction is issued until the end of its execution.

[0041] The wake-ups are back-to-back, meaning that instruction B will be scheduled immediately after the cycle in which instruction A is scheduled. The reservation station (RS), which consists of two parts: a matrix-based issue queue and a scoreboard-CAM-based issue queue, determines, based on the instruction type, whether a particular instruction needs to wake up another instruction back-to-back within a predetermined cycle of its execution delay. In this case, the reservation station (RS) can determine which instruction needs to wake up other instructions back-to-back during its execution cycle by checking corresponding flags or settings. These other instructions may need to be woken up due to dependencies or may be set to need to be woken up due to design considerations. Thus, instructions determined to need to wake up other instructions back-to-back during their execution cycle are assigned to the matrix-based issue queue, while other instructions are assigned to the scoreboard-CAM-based issue queue.

[0042] When the source (src) of instruction B depends on the destination (dest) of instruction A, before removing the dependency, instruction B is assigned to the issue queue based on the scoreboard-CAM architecture according to the aforementioned determination method. After removing the dependency, instruction B may become independent of other instructions. In this case, the attributes of instruction B are determined. If instruction B needs to wake up other instructions during its execution cycle, instruction B is assigned to the issue queue based on the matrix architecture. If instruction B does not need to wake up other instructions during its execution cycle, instruction B is assigned to the issue queue based on the scoreboard-CAM architecture.

[0043] However, it should be understood that the method of determining whether the instruction needs to wake up another instruction back-to-back in a predetermined cycle is not limited to the method in the above example. The determination can also be made based on system design requirements or the designer's preference for system performance requirements, as long as it can be determined whether the instruction needs to wake up another instruction back-to-back in a predetermined cycle.

[0044] In one possible implementation, determining the type of instruction based on the attributes of the instruction includes: determining whether the execution delay of the instruction is fixed or variable; if it is determined that the execution delay of the instruction is fixed, determining that the instruction belongs to the first type; if it is determined that the execution delay of the instruction is variable, determining that the instruction belongs to the second type.

[0045] Among the instructions processed by the processor, some have a fixed execution delay. These instructions are called "fixed-delay instructions." Fixed-delay instructions can be placed in an issue queue based on a matrix structure, resulting in a simpler structure and faster execution. Variable-delay instructions can be placed in an issue queue based on a scoreboard-CAM structure. The reservation station (RS), consisting of both the matrix and the scoreboard-CAM, determines whether the instruction's execution delay is fixed based on the instruction type. An integer instruction takes 1T (i.e., one clock cycle) to execute; that is, its execution delay is 1T, i.e., one clock cycle. For instructions requiring a (N+1)T (where N is an integer greater than or equal to 1) execution delay greater than 1T, the reservation station (RS) can make the appropriate determination as long as their execution delay is fixed. The reservation station can determine which instructions have a fixed execution delay of 1T or (N+1)T and which do not. Therefore, instructions with a fixed execution delay of 1T or (N+1)T are allocated to the issue queue based on the matrix structure, and other instructions are allocated to the issue queue based on the scoreboard-CAM structure.

[0046] Among the instructions to be executed by the processor, most have fixed execution delays and are assigned to an issue queue based on a matrix structure. Other instructions with variable execution delays, referred to as "variable execution delay instructions," are assigned to an issue queue based on a scoreboard-CAM structure. Examples of variable execution delay instructions include loads that are not in the cache, floating-point divisions, and floating-point square roots. For example, a load instruction that is not in the cache must wait for cache access. For variable execution delay instructions, the execution unit notifies the reservation station (RS) upon completion of execution.

[0047] In a possible implementation, a reservation station (RS) determines whether the execution delay of an instruction is fixed according to a unit and / or an operation code field of the instruction.

[0048] In one possible implementation, instructions with fixed execution delays of 2T (i.e., 2 clock cycles), 3T (i.e., 3 clock cycles), ..., NT (i.e., N clock cycles), etc. (where N is an integer greater than or equal to 1), as long as their execution delays are fixed, can be allocated into the matrix, while the remaining variable execution delay instructions are allocated into the scoreboard-CAM.

[0049] In one possible implementation, the type of instruction is determined based on the attributes of the instruction, including: determining whether the instruction is an important instruction; if the instruction is determined to be an important instruction, determining that the instruction belongs to the first type; if the instruction is determined to be not an important instruction, determining that the instruction belongs to the second type.

[0050] Instructions can be categorized based on their importance. Important instructions can be assigned to a matrix, while the remaining instructions can be assigned to a scoreboard (CAM). In this case, a reservation station (RS) determines instruction attributes to determine which instructions are important. "Important" instructions can be determined by system design requirements or system performance requirements. On the other hand, the determination of "importance" can be subjective to a certain extent, with the designer deciding which instructions are important and marking them as "important" in the instruction attributes. For example, the earliest instruction in a processor may be determined to be an important instruction because it is related to core performance. An X86 branch instruction among the instructions may be determined to be an important instruction because whether or not this branch is predicted miss determines the system performance of the processor. System designers can designate certain instructions as important based on their design preferences. In other words, important instructions include earlier instructions stored in the processor, X86 branch instructions in the instruction sequence, and instructions designated as having importance attributes.

[0051] On the other hand, in a possible implementation, a processor is disclosed, comprising: multiple issue queues, including a first issue queue and a second issue queue, the first issue queue being an issue queue based on a matrix structure, and the second issue queue being an issue queue based on a scoreboard-content addressable memory CAM structure; a queue allocation module, configured to determine the type of instruction based on the attributes of the instruction, send instructions of the first type to the first issue queue, and send instructions of the second type to the second issue queue; and multiple execution units, wherein the first issue queue and the second issue queue issue their respective instructions to corresponding execution units among the multiple execution units for execution.

[0052] In one possible implementation, the queue allocation module includes: a first sub-module, configured to determine whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; if it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the first type; if it is determined that the instruction is not required to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the second type.

[0053] In one possible implementation, the queue allocation module includes: a second sub-module, configured to determine whether the execution delay of the instruction is fixed or variable; if it is determined that the execution delay of the instruction is fixed, determining that the instruction belongs to the first type; if it is determined that the execution delay of the instruction is variable, determining that the instruction belongs to the second type.

[0054] In one possible implementation, the queue allocation module includes: a third submodule, configured to determine whether the instruction is an important instruction; if the instruction is determined to be an important instruction, determine that the instruction belongs to the first type; if the instruction is determined to be not an important instruction, determine that the instruction belongs to the second type.

[0055] Figure 5 A block diagram of a processor according to an example embodiment of the present application is shown. Figure 5 The illustrated processor includes a queue allocation module 501, first to N issue queues 502, and first to N execution units 503, where N is an integer greater than or equal to 1. In one possible implementation, queue allocation module 501 determines the instruction type based on the instruction's attributes, sends instructions of the first type to a first issue queue, and sends instructions of the second type to a second issue queue. The first issue queue is a matrix-based issue queue, and the second issue queue is a scoreboard-content addressable memory (CAM)-based issue queue. Each issue queue 502 is connected to a corresponding execution unit 503, so that instructions in each issue queue 502 can be issued to the corresponding execution unit 503 for execution.

[0056] Figure 6 FIG2 is a block diagram showing a processor according to another example embodiment of the present application. Figure 6 In, with Figure 5 The same reference numerals and examples denote the same contents, and description thereof will not be repeated here. Figure 6 and Figure 5 The difference is that Figure 6 The queue allocation module 501 in FIG. 5 includes an optional first submodule 5011 , a second submodule 5012 and a third submodule 5013 , which are indicated by dotted lines.

[0057] In one possible implementation, the first submodule 5011 is configured to determine whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; if it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the first type; if it is determined that the instruction is not required to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the second type.

[0058] In one possible implementation, the second submodule 5012 is configured to determine whether the execution delay of the instruction is fixed or variable; if it is determined that the execution delay of the instruction is fixed, it is determined that the instruction belongs to the first type; if it is determined that the execution delay of the instruction is variable, it is determined that the instruction belongs to the second type.

[0059] In one possible implementation, the third submodule 5013 is configured to determine whether the instruction is an important instruction; if the instruction is determined to be an important instruction, it is determined that the instruction belongs to the first type; if the instruction is determined to be not an important instruction, it is determined that the instruction belongs to the second type.

[0060] It should be noted that while the criteria for classifying instructions are described using instruction attributes as an example, those skilled in the art will appreciate that the present disclosure is not limited thereto. In fact, users can flexibly set the allocation criteria based on their personal preferences and / or actual application requirements, as long as instructions can be classified and assigned to issuance queues based on different structures.

[0061] As described above, in a processor, when designing its issue logic, a matrix-based issue queue and a scoreboard-CAM-based issue queue can accept different instructions and form a large issue queue. This reduces the size of the matrix and the number of physical registers. According to the present disclosure, all instructions are allocated to the matrix-based issue queue and the scoreboard-CAM-based issue queue, respectively. Therefore, compared to using issue queues based on a single structure (using only a matrix-based issue queue or only a scoreboard-CAM-based issue queue) or other structures, the aforementioned advantages of the matrix and scoreboard-CAM mechanisms improve issue queue utilization when executing instructions at high clock rates. Furthermore, the scoreboard-CAM can broadcast fewer destination tags and reduce comparison logic. The present disclosure helps reduce power consumption and improve system performance.

[0062] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, and conventional procedural programming languages such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0063] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0064] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0065] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0066] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0067] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technical improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for distributing instructions, characterized in that: The allocation method is applied to a processor, and the allocation method includes: Determine the type of instruction based on the attributes of the instruction; Sending instructions of a first type to a first issue queue and sending instructions of a second type to a second issue queue, wherein the first issue queue is an issue queue based on a matrix structure and the second issue queue is an issue queue based on a scoreboard-content addressable memory (CAM) structure; and executing instructions in the first issue queue and the second issue queue, Among them, for the issuance queue based on the scoreboard-CAM structure, when issuing an instruction, the destination tag of the instruction is broadcast to all instructions stored in the issuance queue based on the scoreboard-CAM structure. For the issuance queue based on the matrix structure, when issuing an instruction, a wake-up bit vector is broadcast for each entry in the issuance queue based on the matrix structure.

2. The distribution method according to claim 1, characterized in that Determine the type of instruction based on the attributes of the instruction, including: Determining whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; If it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the first type; If it is determined that the instruction does not need to wake up another instruction back-to-back in a predetermined cycle, it is determined that the instruction belongs to the second type.

3. The distribution method according to claim 2, characterized in that: Determining whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle includes: determining whether a source operand of the other instruction depends on a destination operand of the instruction; In a case where it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determining that the instruction belongs to the first type includes: If it is determined that the source operand of the other instruction is dependent on the destination operand of the instruction, it is determined that the instruction belongs to the first type.

4. The distribution method according to claim 3, characterized in that: The predetermined period refers to the execution delay from when the instruction is issued until the instruction is executed.

5. The distribution method according to claim 1, characterized in that: Determine the type of instruction based on the attributes of the instruction, including: determining whether the execution delay of the instruction is fixed or variable; When it is determined that the execution delay of the instruction is fixed, determining that the instruction belongs to the first type; If it is determined that the execution delay of the instruction is variable, it is determined that the instruction belongs to the second type.

6. The distribution method according to claim 5, characterized in that: Determining whether the execution delay of the instruction is fixed or variable includes: Whether the execution delay of the instruction is fixed or variable is determined according to a unit or an operation code field of the instruction.

7. The distribution method according to claim 1, characterized in that: Determine the type of instruction based on the attributes of the instruction, including: determining whether the instruction is an important instruction; If it is determined that the instruction is an important instruction, determining that the instruction belongs to the first type; If it is determined that the instruction is not an important instruction, it is determined that the instruction belongs to the second type.

8. The distribution method according to claim 7, characterized in that: The important instructions include earlier instructions stored in the processor, X86 branch instructions in the instruction sequence, and instructions designated as having an importance attribute.

9. A processor, characterized in that: include: A plurality of issue queues, including a first issue queue and a second issue queue, wherein the first issue queue is an issue queue based on a matrix structure, and the second issue queue is an issue queue based on a scoreboard-content addressable memory (CAM) structure; a queue allocation module configured to determine the type of instruction according to the attribute of the instruction, send instructions of the first type to the first issue queue, and send instructions of the second type to the second issue queue; as well as Multiple execution units, The first issue queue and the second issue queue issue their respective instructions to corresponding execution units among the plurality of execution units for execution, Among them, for the issuance queue based on the scoreboard-CAM structure, when issuing an instruction, the destination tag of the instruction is broadcast to all instructions stored in the issuance queue based on the scoreboard-CAM structure. For the issuance queue based on the matrix structure, when issuing an instruction, a wake-up bit vector is broadcast for each entry in the issuance queue based on the matrix structure.

10. The processor according to claim 9, wherein: The queue allocation module includes: The first submodule is configured to determine whether the instruction is required to wake up another instruction back-to-back in a predetermined cycle; if it is determined that the instruction is required to wake up another instruction back-to-back in a predetermined cycle, determine that the instruction belongs to the first type; if it is determined that the instruction is not required to wake up another instruction back-to-back in a predetermined cycle, determine that the instruction belongs to the second type.

11. The processor according to claim 9, wherein: The queue allocation module includes: The second submodule is configured to determine whether the execution delay of the instruction is fixed or variable; if it is determined that the execution delay of the instruction is fixed, determine that the instruction belongs to the first type; if it is determined that the execution delay of the instruction is variable, determine that the instruction belongs to the second type.

12. The processor according to claim 9, wherein: The queue allocation module includes: The third submodule is configured to determine whether the instruction is an important instruction; if the instruction is determined to be an important instruction, determine that the instruction belongs to the first type; if the instruction is determined to be not an important instruction, determine that the instruction belongs to the second type.

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