Method of forming integrated circuit devices

Abstract

Methods of forming integrated circuit devices are provided. The methods of embodiments of the invention include receiving a substrate including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins on the third semiconductor layer; forming a trench between two of the fins; depositing a dummy material in the trench; forming a gate structure on a channel region of the fins; forming a source / drain structure on a source / drain region of the fins; bonding the substrate to a handle wafer; removing the first semiconductor layer and the second semiconductor layer to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material contacts the silicon substrate. The trench extends through the third semiconductor layer and has a lower surface on the second semiconductor layer.

Description

Technical Field

[0001] This invention relates to integrated circuit devices, and more particularly to their power rails. Background Technology

[0002] The semiconductor industry has progressed to nanometer technology nodes, aiming for higher device density, higher efficiency, and lower cost. Beyond miniaturizing devices, circuit design seeks new structures to provide better performance. One research direction is three-dimensional design, such as fin field-effect transistors (FETs). A fin field-effect transistor can be envisioned as a planar device extending outwards from the substrate to the gate. An illustrative fin field-effect transistor has thin fins (or fin structures) extending upwards from the substrate. The channel region of the field-effect transistor is formed in the vertical fins, while the gate is located on the channel region of the fin (e.g., covering the channel region). A gate covering the flag increases the contact area between the channel region and the gate, allowing the gate to control the channel from multiple sides. This can be utilized in various ways; in some applications, fin field-effect transistors can reduce short-channel effects, lower leakage current, and increase current. In other words, these three-dimensional devices can be faster, smaller, and more efficient than planar devices.

[0003] To electrically couple fin field-effect transistors (FETs) to other devices, integrated circuits may include interconnect structures with one or more layers of conductive lines for electrically coupling the devices. The overall circuit size and performance may depend on the number and size of the conductive lines and circuit devices, while the space used for the conductive lines is limited. Summary of the Invention

[0004] An embodiment of this disclosure provides a method for forming an integrated circuit device, comprising: receiving a substrate including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, wherein the second semiconductor layer is different from the first semiconductor layer and the third semiconductor layer; forming a plurality of fins on the third semiconductor layer; forming a trench between two fins, wherein the trench extends through the third semiconductor layer and has a lower surface on the second semiconductor layer; depositing dummy material in the trench; forming gate structures on a plurality of channel regions of the fins; forming a plurality of source / drain structures on a plurality of source / drain regions of the fins; bonding the substrate to a carrier wafer; removing the first semiconductor layer and the second semiconductor layer to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material contacts the silicon substrate.

[0005] An embodiment of this disclosure provides a method for forming an integrated circuit device, comprising: receiving a substrate including a first silicon layer, a second silicon layer on the first silicon layer, and a first silicon-germanium layer between the first silicon layer and the second silicon layer; forming a plurality of fins on the second silicon layer; forming a trench between two fins, wherein the trench extends through the second silicon layer and has a lower surface on the first silicon-germanium layer; depositing dummy material in the trench; forming a gate structure on a channel region of the fins; forming a source / drain structure on a source / drain region of the fins; bonding the substrate to a carrier wafer; removing the first silicon layer and the first silicon-germanium layer to expose the dummy material; removing the dummy material in the trench; depositing metal in the trench; and bonding the substrate to a third silicon substrate such that the metal contacts the third silicon substrate.

[0006] An embodiment of the present disclosure provides an integrated circuit device comprising: a substrate including a silicon layer and a silicon-germanium layer thereon; a plurality of fins located on the substrate; and an interconnect conductor located in the silicon layer and extending between two fins. Attached Figure Description

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D ,and Figure 1E This is a flowchart illustrating a method for fabricating an integrated circuit workpiece with embedded conductive lines, according to various embodiments of the present invention.

[0008] Figures 2a to 31a These are perspective and sectional views of the workpiece manufacturing method in various embodiments of the present invention.

[0009] Figures 2b to 31b and Figure 4c These are perspective and sectional views of a method for manufacturing another workpiece in various embodiments of the present invention.

[0010] Figure 32a In various embodiments of the present invention, based on Figures 1A to 1E A cross-sectional view of the power rail structure formed by the method shown.

[0011] Figure 32b In various embodiments of the present invention, based on Figures 1A to 1E A cross-sectional view of another power rail structure formed by the method.

[0012] Explanation of reference numerals in the attached figures:

[0013] A-A': Cross-section

[0014] D1, D2: Penetration depth

[0015] T1, T2: Thickness

[0016] W1, W2, W3: Width

[0017] 100: Method

[0018] 102a,102b,104a,104b,104c,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,146,148,150,152: Steps

[0019] 200,200': Workpiece

[0020] 202: First semiconductor layer

[0021] 204, 204a: Second semiconductor layer

[0022] 204b: Fourth semiconductor layer

[0023] 205,205': base plate

[0024] 206: Third semiconductor layer

[0025] 208a, 208b: Fins

[0026] 210, 212: Hard masking layer on top of the fins

[0027] 214, 215: Dielectric layer

[0028] 216,216',244,252,262,262': Trench

[0029] 216”: Widened groove

[0030] 218: Dummy Materials

[0031] 220: Hard mask layer

[0032] 221: Patterned hard mask

[0033] 222: Patterned photoresist layer

[0034] 224: First dummy fin layer

[0035] 226, 228: Spacers

[0036] 230: Second dummy fin layer

[0037] 232: Cap layer

[0038] 234: Fully Oxide Layer

[0039] 236: Dummy Gate Structure

[0040] 238a, 238b: Extensional structures

[0041] 240: Etching Stop Layer

[0042] 242: Interlayer dielectric layer

[0043] 246,254: Silicides

[0044] 248: First source / drain contact

[0045] 250, 258: Dielectric cap

[0046] 256: Second source / drain contact

[0047] 260: Internal Wiring Structure

[0048] 264,264': Metal layer

[0049] 300: Carrier wafer

[0050] 302, 304, 402, 404: Oxide layer

[0051] 400: Wafer

[0052] 500,500': Complementary Metal-Oxide-Semiconductor Device Detailed Implementation

[0053] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being spaced apart by other additional components rather than in direct contact. Furthermore, various embodiments of the invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0054] In addition, spatial relative terms such as “lower side,” “upper side,” “horizontal,” “vertical,” “above,” “above,” “below,” “below,” “up,” “lower,” “top,” “bottom,” or similar terms (such as “horizontally,” “downward,” “upward,” or similar terms) can be used to simplify the description of the relative relationship between one element and another in a diagram. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the diagram.

[0055] Advances in fabrication methods can reduce the size of transistors and other active devices that make up integrated circuits. As device size shrinks, it can limit the corresponding integrated circuits. In other words, circuit size may depend on the conductive traces in the interconnect structure of electrically coupled circuit devices, rather than the size of the device itself. While the thickness of conductive traces can be reduced to encapsulate more traces within the interconnect, thinner traces have higher resistance, resulting in slower trace speeds and greater loads on the driving devices. Similarly, reducing the space between traces increases the risk of short circuits, noise interference, and capacitive coupling, all of which increase the load on the driving devices. Additional layers of conductive traces can be added to the interconnect structure, but these layers require additional vias, which present associated resistance and interlayer alignment issues. Alignment errors typically occur with each additional interconnect layer, increasing yield risk as the number of layers increases.

[0056] As described below, the technology provided by embodiments of the present invention can provide conductive lines under transistors to alleviate some of the congestion of interconnects. For example, in a fin field-effect transistor circuit, the interconnect lines can be formed under the transistor portion of the fin, or at least partially buried under the transistor portion of the fin. These lines can be used to carry signals between fins, provide power, and / or serve as ground rails. In some examples, buried conductive lines or conductors serve as buried power rails. In some examples, buried power rails can also be considered as super power rails because they are thicker and have lower resistance than the interconnect layer on the transistor (which can be considered as the zeroth metal layer). In these and other examples, the buried interconnect lines can provide additional line sources, which can be used to reduce circuit area, increase circuit density, alleviate line congestion, and / or reduce the line density in the remaining interconnects. Furthermore, since buried power rails or super power rails can be electrically coupled to the zeroth metal layer via multiple contact vias, the density or size of the zeroth metal layer can be reduced to reduce interference and capacitive coupling, and to avoid voltage drops across the zeroth metal layer. It is worth noting that, unless otherwise stated, no embodiment is required to provide a specific advantage.

[0057] Examples include integrated circuits with embedded conductive lines and techniques for forming conductive lines, such as... Figures 1A to 1E , Figures 2a to 32a ,and Figures 2b to 32b As shown. Under this consideration, Figures 1A to 1E This is a flowchart of a method 100 for producing a workpiece 200 or workpiece 200' of an integrated circuit having embedded conductive lines, according to various embodiments of the present invention. Additional steps may be provided before, during, and after method 100, and other embodiments of method 100 may replace or omit some of the steps described. Figure 2a It is a perspective view of workpiece 200, and Figures 3a to 31a In method 100 of various embodiments of the present invention, Figure 2aThe workpiece 200 is shown in a sectional view along section A-A'. Figure 2b It is a perspective view of the workpiece at 200°, and Figures 3b to 31b In method 100 of various embodiments of the present invention, Figure 2b The workpiece 200' is shown in a sectional view along section A-A'. Section A-A' is perpendicular to the fin (e.g., Figure 2a and Figure 2b The extension direction of the fins 208a and 208b in the middle. Figure 32a This is a cross-sectional view of part of workpiece 200 of an integrated circuit. Figure 32b This is a cross-sectional view of workpiece 200' of an integrated circuit. In various figures and embodiments, similar reference numerals are used to identify similar units.

[0058] like Figure 1A Step 102a and Figure 2a As shown, a receiving workpiece 200 is provided. The workpiece 200 includes a substrate 205 on which means are to be formed. In various embodiments, the substrate 205 includes a first semiconductor layer 202, a second semiconductor layer 204 on the first semiconductor layer 202, and a third semiconductor layer 206 on the second semiconductor layer 204. In some embodiments, each of the first semiconductor layer 202, the second semiconductor layer 204, and the third semiconductor layer 206 includes a semiconductor element (single element) such as silicon or germanium in a crystalline structure, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), and / or combinations thereof. In some embodiments, the second semiconductor layer 204 is epitaxially grown on the first semiconductor layer 202, and the third semiconductor layer 206 is epitaxially grown on the second semiconductor layer 204. In some embodiments, the first semiconductor layer 202 and the third semiconductor layer 206 are composed of the same semiconductor material, while the semiconductor material forming the second semiconductor layer 204 is different from the semiconductor materials forming the first semiconductor layer 202 and the third semiconductor layer 206. In one embodiment, the second semiconductor layer 204 is mainly composed of silicon-germanium, and the first semiconductor layer 202 and the third semiconductor layer 206 are mainly composed of silicon. In some examples, the second semiconductor layer 204 is mainly composed of silicon-germanium, wherein the ratio of silicon to germanium is between about 8:2 (80% silicon and 20% germanium) and about 6:4 (60% silicon and 40% germanium), such as about 7:3 (70% silicon and 30% germanium). Since the second semiconductor layer 204 is located under the third semiconductor layer 206, the second semiconductor layer 204 is a semiconductor layer buried under the third semiconductor layer 206. In some embodiments, the thickness of the second semiconductor layer 204 is between about 10 nm and about 50 nm. In some embodiments, the thickness of the second semiconductor layer 204 is 40 nm.

[0059] The composition of the third semiconductor layer 206 may be uniform or may have multiple layers, and some of the third semiconductor layers 206 may be selectively etched to form Figure 2a The fins 208a and 208b are shown in the figure. The layers may have similar or different compositions. In various embodiments, some substrate layers may have inconsistent compositions to induce device stress and thus adjust device performance. In some examples, devices formed on third semiconductor layer 206 extend beyond third semiconductor layer 206. For example, fin field-effect transistors and / or other non-planar devices may be formed on the fins 208a and 208b of the devices located on third semiconductor layer 206. The compositions of fins 208a and 208b may be similar to or different from those of third semiconductor layer 206. For example, in some embodiments, third semiconductor layer 206 may primarily comprise silicon, while fins 208a and 208b comprise one or more layers of primarily germanium or silicon-germanium semiconductors. In some embodiments, third semiconductor layer 206 may primarily comprise silicon, and fins 208a and 208b may also primarily comprise silicon.

[0060] The fins 208a and 208b can be formed by etching portions of the third semiconductor layer 206, depositing multiple layers on the third semiconductor layer 206 and etching the layers, and / or other suitable techniques. For example, the fins 208a and 208b can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography with self-alignment processes, resulting in a pattern spacing smaller than that formed using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on the fins 208a and 208b and one or more hard masking layers on top of the fins (e.g., hard masking layers 210 and 212 on top of the fins). The sacrificial layer is patterned using a photolithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. Next, the sacrificial layer is removed, and the remaining spacers are used to remove the hard mask layers 210 and 212 (located on fins 208a and 208b) on top of the fins not covered by the spacers, in order to pattern the fins 208a and 208b.

[0061] The hard masking layers 210 and 212 on top of the fins can be used to control the etching process defining the fins 208a and 208b, and to protect the fins 208a and 208b in subsequent processes. In summary, the hard masking layers 210 and 212 on top of the fins, and the materials of the fins 208a and 208b, can have different etching selectivity. The hard masking layers 210 and 212 on top of the fins can comprise dielectric materials such as semiconductor oxides, semiconductor nitrides, semiconductor oxide oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbonitrides, and / or metal oxides.

[0062] like Figure 1A Step 104a Figure 3a ,and Figure 4b As shown, the substrate 205 is anisotropically etched to form trenches between fins 208a and 208b until the second semiconductor layer 204 is reached. In some embodiments, a dielectric layer 214 is formed on the third semiconductor layer 206, the fins 208a and 208b, and the hard masking layers 210 and 212 on top of the fins to protect the fins 208a and 208b. In some embodiments, the dielectric layer 214 is compliantly formed on the third semiconductor layer 206, the fins 208a and 208b, and the hard masking layers 210 and 212 on top of the fins, and the formation method can employ any suitable process such as atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma-assisted chemical vapor deposition, and / or other suitable deposition processes. The dielectric layer 214 may comprise a dielectric material such as an oxide of a semiconductor. In some examples, the dielectric layer 214 comprises silicon oxide.

[0063] After forming the dielectric layer 214, a patterned etching mask can be patterned using photolithography, and the third semiconductor layer 206 between the fins 208a and 208b can be etched using the patterned etching mask to form a trench 216 that reaches or terminates at a point in the second semiconductor layer 204. Figure 4a In the illustrated embodiment, trench 216 terminates at the upper surface of the second semiconductor layer 204. Thus, the lower surface of trench 216 lies above or within the second semiconductor layer 204. In other embodiments, trench 216 may extend further into the second semiconductor layer 204, but not through it. Since the second semiconductor layer 204 and the third semiconductor layer 206 are composed of different semiconductor materials, it is possible to detect whether anisotropic etching has penetrated the third semiconductor layer 206. In embodiments where the third semiconductor layer 206 is composed of silicon and the second semiconductor layer 204 is composed of silicon-germanium, the etching tool can detect a small amount of germanium to determine whether the second semiconductor layer 204 has been reached. In other embodiments, whether etching has reached the second semiconductor layer 204 can be determined by detecting changes in the etching rate. In some embodiments, a suitable etching technique, such as dry etching, may be used to achieve the anisotropic etching in step 104a.

[0064] like Figure 1A Step 106 and Figure 5aAs shown, a dielectric layer 215 is deposited on the third semiconductor layer 206, fins 208a and 208b, and trench 216. In some embodiments, the materials and formation methods of dielectric layer 215 and dielectric layer 214 may be similar, and therefore their details are not repeated here. In some embodiments, dielectric layer 215 may include the dielectric layer 214 that was not removed in step 104a. In some embodiments, dielectric layer 215 and dielectric layer 214 have different thicknesses. In these embodiments, dielectric layer 215 is thicker than dielectric layer 214 to protect fins 208a and 208b (see [link to documentation]) when removing dummy material. Figure 8a and Figure 9a ).

[0065] like Figure 1A Step 108 and Figure 6a As shown, dummy material 218 is deposited on dielectric layer 215. In some embodiments, the dummy material 218 is etched back, causing at least a portion of the fins 208a and 208b to protrude from the upper surface of the dummy material 218. In some embodiments, the dummy material 218 may be composed of silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, aluminum oxide, zirconium oxide, or other suitable metal oxides. In one embodiment, the dummy material 218 is composed of aluminum oxide.

[0066] like Figure 1A Step 110 Figure 7a ,and Figure 8a As shown, a patterned hard mask 221 is formed (see...) Figure 8a In some embodiments, a hard mask layer 220 is deposited on a workpiece 200, including deposition on a dielectric layer 215 and a dummy material 218. In some embodiments, a photoresist material is deposited on the hard mask layer 220 using a suitable deposition method such as spin coating. The deposited photoresist material is then exposed to light through a transmissive mask or reflected light from a self-reflective mask. The exposed photoresist material can undergo physical changes that allow a developer to selectively remove the exposed or unexposed photoresist material. In some embodiments, after the developed photoresist material is baked by a post-bake process, a patterned photoresist layer 222 is formed. In subsequent processes, the patterned photoresist layer 222 can be used as an etching mask to etch the hard mask layer 220 and the dielectric layer 215 beneath the hard mask layer 220 to form a patterned hard mask 221. Figure 8aAs shown, the result of step 110 is the removal of portions of the hard mask layer 220 and dielectric layer 215 not covered by the patterned photoresist layer 222, thereby exposing fins 208a and 208b and portions of the hard masks 210 and 212 on top of the fins. In some embodiments, the hard mask layer 220 and dielectric layer 215 are composed of different dielectric materials. In one embodiment, the hard mask layer 220 is composed of carbon-doped silicon oxide or silicon nitride, while the dielectric layer 215 is composed of silicon oxide.

[0067] like Figure 1B Step 112 and Figure 9a As shown, a patterned hard mask 221 is used as an etching mask to etch the workpiece 200 to remove the dummy material 218 and dielectric layer 215 not covered by the patterned hard mask 221. In some embodiments, a suitable etching process is used to etch the dummy material 218 and dielectric layer 215. In some embodiments, dilute hydrofluoric acid is used to etch the dummy material 218 and dielectric layer 215, which tends to etch silicon oxide or metal oxides such as aluminum oxide.

[0068] like Figure 1B Step 114 and Figure 10a As shown, the first dummy fin layer 224 was deposited in Figure 9a In the trench 216 shown. In some embodiments, a first dummy fin layer 224 is deposited on the workpiece 200. In these embodiments, the first dummy fin layer 224 may be deposited compliantly, and the deposition method employs a suitable process such as atomic layer deposition. In some embodiments, the first dummy fin layer 224 may be composed of carbon-doped silicon nitride. After the first dummy fin layer 224 is deposited on the workpiece, the first dummy fin layer 224 outside the trench 216 is removed, such as... Figure 10a As shown. In some embodiments, the first dummy fin layer 224 is composed of dielectric materials such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbonitrides, and / or metal oxides.

[0069] like Figure 1B Step 116 and Figure 11a As shown, spacers (or spacer layers) 226 and 228 are formed on fins 208a and 208b. In some embodiments, spacers 226 and 228 are formed of different dielectric materials.

[0070] like Figure 1B Step 118 and Figure 12aAs shown, the second dummy fin layer 230 is deposited on the workpiece 200, including on the spacer 228. The material and formation method of the second dummy fin layer 230 are similar to those of the first dummy fin layer 224, therefore the details of the second dummy fin layer 230 will not be repeated here.

[0071] like Figure 1B Step 120 and Figure 13a As shown, the second dummy fin layer 230 is etched back. In some embodiments, after the second dummy fin layer 230 is etched back, a capping layer 232 is formed to protect the second dummy fin layer 230.

[0072] like Figure 1C Step 122 and Figure 14a As shown, the workpiece 200 is planarized. Figure 14a In some embodiments shown, the capping layer 232, spacers 226, spacers 228, hard masking layer 212 on top of the fins, dielectric layer 215, hard masking layer 220, and the upper surface of the first dummy fin layer 224 are coplanar. In some embodiments, suitable planarization techniques such as chemical mechanical polishing are used to planarize the workpiece 200.

[0073] like Figure 1C Steps 124 and Figure 15a As shown, spacers 226 and 228, dielectric layer 215, and hard masking layer 220 are selectively etched, causing fins 208a and 208b, as well as dummy fins formed by the first dummy fin layer 224 and the second dummy fin layer 230, to protrude from the upper surfaces of spacers 226 and 228, dielectric layer 215, and hard masking layer 220. In some embodiments, the selective etching in step 124 may employ a suitable etching method such as dry etching.

[0074] like Figure 1C Step 126 and Figure 16a As shown, a full oxide layer 234 may be formed on the workpiece 200, including on fins 208a, fins 208b, and dummy fins formed with the first dummy fin layer 224 and the second dummy fin layer 230. In some examples, the full oxide layer 234 serves as an additional dielectric layer for input / output nodes, and may be removed when other nodes do not require an additional dielectric layer.

[0075] like Figure 1C Step 128 and Figure 17aAs shown, a dummy gate structure 236 is formed in the channel regions of fins 208a and 208b. In some embodiments, the dummy gate structure 236 includes a dummy gate dielectric layer and a dummy gate. In some embodiments, the dummy gate dielectric layer may comprise silicon oxide or other suitable dielectric material, while the dummy gate may comprise polysilicon. In some examples, one or more sidewall spacers or pads may be formed on the dummy gate structure 236.

[0076] like Figure 1C Step 130 and Figure 18a As shown, step 130 removes the hard masking layers 210 and 212 on top of the fins on the source / drain regions of fins 208a and 208b, and also etches back the dummy fins (formed by the first dummy fin layer 224 and not covered by any masking or capping layer) in the source / drain regions of fins 208a and 208b. The result of step 130 is that the fins 208a and 208b in the source / drain regions are exposed. It is worth noting that the dummy gate structure 236 covers the channel regions of fins 208a and 208b containing the hard masking layers 210 and 212 on top of the fins.

[0077] like Figure 1C Step 132 and Figure 19a As shown, epitaxial structures 238a and 238b and an interlayer dielectric layer 242 are formed. In some embodiments, devices with different conductivity profiles are formed on fins 208a and 208b. For example, an n-type fin field-effect transistor can be formed on fin 208a, while a p-type fin field-effect transistor can be formed on fin 208b, and vice versa. Epitaxial structures 238a and 238b can be epitaxially formed to cover fins 208a and 208b, respectively. In some embodiments, the epitaxial structures 238a and 238b can be formed using suitable epitaxial processes, such as vapor phase epitaxy, molecular beam epitaxy, or a combination thereof. In embodiments where an n-type fin field-effect transistor is formed on fin 208a and a p-type fin field-effect transistor is formed on fin 208b, the epitaxial structure 238a may be composed of silicon in situ doped with an n-type dopant such as phosphorus, while the epitaxial structure 238b may be composed of silicon germanium in situ doped with a p-type dopant such as boron. In these embodiments, epitaxial structures 238a and 238b are formed sequentially. For example, when forming epitaxial structure 238a on the source / drain region of fin 208a, the source / drain region of fin 208b may be masked. Similarly, when forming epitaxial structure 238b on the source / drain region of fin 208b, the source / drain region of fin 208a may be masked. Figure 19aIn some embodiments shown, after forming the epitaxial structures 238a and 238b, an etch stop layer 240 may be formed on the source / drain regions of the fins 208a and 208b, including on the epitaxial structures 238a and 238b. The etch stop layer 240 may be composed of doped or undoped silicon nitride, or other suitable dielectric materials. An interlayer dielectric layer 242 may then be deposited on the workpiece 200. In some examples, the interlayer dielectric layer 242 may be composed of silicon oxide, silicon nitride, silicon oxynitride, an oxide of tetraethoxysilane, phosphosilicate glass, borosilicate glass, a low dielectric constant dielectric material, other suitable dielectric materials, or combinations thereof.

[0078] like Figure 1D Step 134 and Figure 20a As shown, trench 244 is formed to expose a portion of the epitaxial structure 238a and the dummy material 218. In some embodiments, a photolithography process is performed to form a patterned mask, and the patterned mask is used to recess the interlayer dielectric layer 242 and form the trench 244. Figure 20a In some embodiments shown, trench 244 exposes a portion of the dummy material 218 between fins 208a and 208b and the epitaxial structure 238a. In some examples, a suitable etching process, such as dry etching, is used to form the recess.

[0079] like Figure 1D Step 136 in Figure 21a ,and Figure 22a As shown, a first source / drain contact 248 is formed on the epitaxial structure 238a and contacts the dummy material 218. In some embodiments, prior to forming the first source / drain contact 248, a silicide 246 may be formed on the epitaxial structure 238a. To form the silicide 246, a metal precursor such as titanium may be deposited on the exposed epitaxial structure 238a and annealed to react between the metal precursor and silicon in the epitaxial structure to form titanium silicide. In these embodiments, after forming the silicide 246, a source / drain contact metal such as tungsten or ruthenium may be deposited in the trench 244 to form the first source / drain contact 248. Furthermore, in these embodiments, the first source / drain contact 248 is electrically coupled to the silicide 246 and physically contacts the dummy material 218. In some embodiments, planarization processes such as chemical mechanical polishing can be performed after depositing the source / drain contact metal to remove excess source / drain contact metal on the interlayer dielectric layer 242. In some examples, a dielectric cap 250 can be formed on the first source / drain contact 248 to protect its integrity. In some embodiments, the dielectric cap 250 can be formed using a self-aligned process, and therefore can be referred to as a self-aligned dielectric cap 250.

[0080] like Figure 1D Step 138 Figure 23a ,and Figure 24a As shown, a trench 252 is formed to expose the epitaxial structure 238b, and a second source / drain contact 256 is formed in the trench 252 on the epitaxial structure 238b. The formation process of the second source / drain contact 256 is similar to that of the first source / drain contact 248. The method for forming the trench 252 to expose the epitaxial structure 238b employs photolithography. Figure 23a As shown, trench 252 differs from trench 244 in that trench 252 does not expose the dummy material 218. In some embodiments, after forming trench 252, a metal precursor such as nickel or cobalt may be deposited on the exposed epitaxial structure 238b, and annealing may be performed to allow the silicon in the epitaxial structure 238b to react with the metal precursor to form silicide 254. In these embodiments, after forming silicide 254, source / drain contact metal such as tungsten or ruthenium may be deposited in trench 252 to form a second source / drain contact 256. Furthermore, in these embodiments, the second source / drain contact 256 is electrically coupled to silicide 254. In some embodiments, after depositing the source / drain contact metal, a planarization process such as chemical mechanical polishing may be performed to remove excess source / drain contact metal on the interlayer dielectric layer 242. In some examples, a dielectric cap 258 may be formed on the second source / drain contact 256 to protect the integrity of the second source / drain contact 256.

[0081] In some examples, the dummy gate structure 236 can be replaced by a gate replacement process. In the gate replacement process, the interlayer dielectric layer 242 and any hard masking layer on the dummy gate structure 236 are removed to form an opening and expose the upper surface of the dummy gate structure 236. An etching process is then performed through the opening to remove the dummy gate structure 236. A high-dielectric-constant gate dielectric layer is then formed in the channel regions of the fins 208a and 208b. For example, the high-dielectric-constant gate dielectric layer may comprise hafnium oxide, hafnium silicon oxide, hafnium oxysilicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof. In some embodiments, to enhance the bonding between the high-dielectric-constant gate dielectric layer and the fins 208a and 208b, an interface layer may be formed in the channel region between the high-dielectric-constant gate dielectric layers. The interface layer may include silicon oxide. After forming the gate dielectric layer, gate metal may be deposited in the opening to form the gate of the gate structure. In some examples, one or more work function layers may be formed on the gate to adjust the work function, and one or more dielectric layers may be formed on the gate to protect the gate.

[0082] In some embodiments, an interconnect structure 260 may be formed on the workpiece 200 before the remaining steps of step 140 and after the formation of the first source / drain contact 248 and the second source / drain contact 256. The interconnect structure 260 may include multiple dielectric layers and metal conductive layers.

[0083] like Figure 1D Step 140 and Figure 25a As shown, the workpiece 200 is flipped and bonded to the carrier wafer 300. In some embodiments, a dielectric layer-to-dielectric layer bonding method is used to bond the workpiece 200 to the carrier wafer 300. In these embodiments, an oxide layer 304 is formed on the first source / drain contact 248 and the second source / drain contact 256 (or interconnect structure 260), and another oxide layer 302 is formed on the carrier wafer 300. After forming oxide layers 302 and 304, the workpiece 200 can be flipped along the oxide layer 304 and placed on the carrier wafer 300 so that the oxide layer 302 contacts the oxide layer 304. Annealing is performed to bond the oxide layers 302 and 304, thereby bonding the workpiece 200 to the carrier wafer 300.

[0084] like Figure 1D Step 142 and Figure 26a As shown, the workpiece 200 is thinned from the first semiconductor layer 202 until the second semiconductor layer 204 is exposed or reached. In some embodiments, planarization techniques such as chemical mechanical polishing are used to remove the first semiconductor layer 202 to thin the workpiece 200. In these embodiments, the compositional differences and resistance differences to the planarization process between the first semiconductor layer 202 and the second semiconductor layer 204 can be used to monitor the progress of the planarization process and control the planarization of the workpiece 200.

[0085] like Figure 1E Step 144 and Figure 27a As shown, the second semiconductor layer 204 is removed to expose the dummy material 218. In some embodiments, the removal method of the second semiconductor layer 204 may employ a suitable planarization technique such as chemical mechanical polishing. Figure 27a As shown, after planarizing the workpiece 200 in step 144, the dummy material 218 in the third semiconductor layer 206 can be exposed.

[0086] like Figure 1E Step 146 and Figure 28a As shown, dummy material 218 is removed. In some embodiments, the dummy material 218 exposed in step 144 is removed to form trench 262, and the removal method may be a suitable etching technique. For example, dilute hydrofluoric acid may be used to etch the exposed dummy material 218.

[0087] like Figure 1E Step 148 and Figure 29a As shown, metal is deposited on workpiece 200 to form metal layer 264. In some embodiments, the metal material deposited on workpiece 200 includes deposition within and on trench 262. In these embodiments, excess metal outside trench 262 can be removed by suitable planarization techniques such as chemical mechanical polishing. The metal forming metal layer 264 may include copper, tungsten, ruthenium, nickel, cobalt, combinations thereof, or other suitable metals. Since the first source / drain contact 248 is in physical contact with the dummy material 218 after the removal of dummy material 218 and the formation of metal layer 264, the first source / drain contact 248 is electrically coupled to metal layer 264. In some embodiments, interconnect layers (such as a zeroth metal layer) on fins 208a and 208b are electrically coupled to a plurality of source / drain contacts (such as the first source / drain contact 248) and electrically coupled to metal layer 264 via a plurality of source / drain contacts distributed throughout the entire length / width of workpiece 200. In this way, Figure 29a The metal layer 264 shown may be part of an embedded power rail or super power rail, which can provide an additional conductive path to the zero metal layer and reduce the voltage drop caused by the zero metal layer.

[0088] like Figure 1E Step 150 and Figure 30a As shown, the workpiece 200 is flipped and bonded to the wafer 400. In some embodiments, an oxide layer 404 is formed on the metal layer 264 of the workpiece 200, and another oxide layer 402 is formed on the wafer 400. In these embodiments, the oxide layers 402 and 404 are annealed to bond the workpiece 200 to the wafer 400. In some embodiments, the wafer 400 may be a silicon wafer.

[0089] like Figure 1E Step 152 and Figure 31a As shown, the carrier wafer 300 is removed from workpiece 200. In some embodiments, planarization techniques such as chemical mechanical polishing are used to remove the carrier wafer 300 from workpiece 200. Additional processes may be performed to fabricate an integrated circuit on workpiece 200. For example, additional metal interconnect structures may be formed on workpiece 200.

[0090] In some examples, Figure 31a The workpiece 200 may include a complementary metal-oxide-semiconductor device 500, and Figure 32a This shows an enlarged view of a complementary metal-oxide-semiconductor (CMOS) device 500. The CMOS device 500 includes n-type fin field-effect transistors, such as those formed on fin 208a, and p-type fin field-effect transistors, such as those formed on fin 208b. Figure 32aAs shown, the complementary metal-oxide-semiconductor device 500 includes a metal layer 264. In some embodiments, the portion of the metal layer 264 in the complementary metal-oxide-semiconductor device 500 along section A-A' includes a thickness T1, a width W1, and a penetration depth D1 through the third semiconductor layer 206 between the first source / drain junction 248 and the oxide layer 402. In some embodiments, the thickness T1 is between about 40 nm and about 100 nm, the width W1 is between about 15 nm and about 25 nm, and the penetration depth D1 is between about 10 nm and about 50 nm.

[0091] Compared with existing integrated circuit structures and methods, Figures 1A to 1E The integrated circuit structure and method 100 on the workpiece 200 shown offer several advantages. The metal layer 264 located between and beneath the fins 208a and 208b can serve as part of a buried power rail or super power rail, providing additional conductive paths to the interconnect structures on the fins 208a and 208b, thereby reducing the resistivity of the metal interconnects without occupying area. In fact, because the metal layer 264 provides additional interconnects, a smaller interconnect structure can be formed on the fins 208a and 208b, maintaining the same or providing better interconnect resistivity. By employing dummy material 218 as a placeholder for the metal layer 264 in method 100, the metal layer 264 can undergo fewer thermal cycles and has fewer spikes (which could degrade the conductivity quality in the metal layer 264). Furthermore, employing a second semiconductor layer 204 in the substrate allows for better control over the depth to which the metal layer 264 extends into the substrate 205.

[0092] In other embodiments or, as appropriate, such as Figure 2b As shown, the substrate 205' of workpiece 200' is different. Figure 2a The substrate 205 and the workpiece 200' are used in method 100 to generate a low-resistivity supercharger rail. It is worth noting that, for the sake of simplifying the drawings and description of the embodiments, similar reference numerals are used to identify similar units.

[0093] like Figure 1A Step 102b Figure 2b ,and Figure 3bAs shown, a receiving workpiece 200' is provided. Workpiece 200' includes a substrate 205' on which means will be formed. In various embodiments, substrate 205' includes a first semiconductor layer 202, a second semiconductor layer 204a on the first semiconductor layer 202, a third semiconductor layer 206 on the second semiconductor layer 204a, and a fourth semiconductor layer 204b on the third semiconductor layer 206. In some embodiments, each of the first semiconductor layer 202, the second semiconductor layer 204a, the third semiconductor layer 206, and the fourth semiconductor layer 204b includes a semiconductor element (single element) such as silicon or germanium in a crystalline structure, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), and / or a combination thereof. In some embodiments, a second semiconductor layer 204a is epitaxially grown on a first semiconductor layer 202, a third semiconductor layer 206 is epitaxially grown on a second semiconductor layer 204a, and a fourth semiconductor layer 204b is epitaxially grown on a third semiconductor layer 206. In some embodiments, the first semiconductor layer 202 and the third semiconductor layer 206 are composed of the same semiconductor material, while the semiconductor materials forming the second semiconductor layer 204a and the fourth semiconductor layer 204b are different from the semiconductor materials forming the first semiconductor layer 202 and the third semiconductor layer 206. In one embodiment, the second semiconductor layer 204a and the fourth semiconductor layer 204b are mainly composed of silicon and germanium, and the first semiconductor layer 202 and the third semiconductor layer 206 are mainly composed of silicon. In some examples, the second semiconductor layer 204a and the fourth semiconductor layer 204b are primarily composed of silicon and germanium, wherein the silicon to germanium ratio is between approximately 8:2 (80% silicon and 20% germanium) and approximately 6:4 (60% silicon and 40% germanium), such as approximately 7:3 (70% silicon and 30% germanium). Since the second semiconductor layer 204a is located beneath the third semiconductor layer 206, the second semiconductor layer 204a is a semiconductor layer buried beneath the third semiconductor layer 206. In some embodiments, the thickness of the second semiconductor layer 204a is between approximately 10 nm and approximately 50 nm, such as 40 nm.

[0094] The fourth semiconductor layer 204b can have various layered structures, and some of the fourth semiconductor layer 204b can be selectively etched to form Figure 2bThe fins 208a and 208b are layered. The layers may have similar or different compositions. In various embodiments, some substrate layers may have inconsistent compositions to induce device stress and thus adjust device performance. In some examples, devices formed on a fourth semiconductor layer 204b extend beyond the fourth semiconductor layer 204b. For example, fin field-effect transistors and / or other non-planar devices may be formed on the fins 208a and 208b of the devices located on the fourth semiconductor layer 204b. The compositions of the fins 208a and 208b may be similar to or different from those of the fourth semiconductor layer 204b. For example, in some embodiments, the fourth semiconductor layer 204b may primarily comprise silicon germanium, while the fins 208a and 208b may primarily comprise one or more layers of silicon. In some embodiments, the fourth semiconductor layer 204b may primarily comprise silicon germanium, and the fins 208a and 208b may also primarily comprise silicon germanium.

[0095] The fins 208a and 208b can be formed by depositing multiple layers on the fourth semiconductor layer 204b and etching these layers using other suitable techniques. For example, the fins 208a and 208b can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, resulting in a pattern spacing smaller than that formed using a single direct photolithography process. For example, some embodiments form a sacrificial layer on the fourth semiconductor layer 204b and multiple layers on top of one or more hard masking layers (such as hard masking layers 210 and 212 on top of the fins). The sacrificial layer is patterned using a photolithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. Next, the sacrificial layer is removed, and the remaining spacers are used to remove the hard mask layers 210 and 212 (located on fins 208a and 208b) on top of the fins not covered by the spacers, in order to pattern the fins 208a and 208b.

[0096] The hard masking layers 210 and 212 on top of the fins can be used to control the etching process defining the fins 208a and 208b, and to protect the fins 208a and 208b in subsequent processes. In summary, the hard masking layers 210 and 212 on top of the fins, and the materials of the fins 208a and 208b, can have different etching selectivity. The hard masking layers 210 and 212 on top of the fins can comprise dielectric materials such as semiconductor oxides, semiconductor nitrides, semiconductor oxide oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbonitrides, and / or metal oxides.

[0097] In some embodiments, a dielectric layer 214 is formed on the fourth semiconductor layer 204b, the fins 208a and 208b, and the hard masking layers 210 and 212 on top of the fins to protect the fins 208a and 208b, such as Figure 4b As shown. In some embodiments, a dielectric layer 214 is compliantly formed on the fourth semiconductor layer 204b, fins 208a and 208b, and hard mask layers 210 and 212 on top of the fins, and the formation method may employ any suitable process such as atomic layer deposition, plasma-assisted atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma-assisted chemical vapor deposition, and / or other suitable deposition processes. The dielectric layer 214 may comprise a dielectric material such as an oxide of a semiconductor. In some examples, the dielectric layer 214 comprises silicon oxide.

[0098] like Figure 1A Step 104b and Figure 4b As shown, anisotropic etching of substrate 205' forms trench 216' between fins 208a and 208b and through the fourth semiconductor layer 204b and dielectric layer 214, exposing the third semiconductor layer 206 in the trench 216' between fins 208a and 208b. In some embodiments, after forming dielectric layer 214, photolithography can be used to pattern an etch mask, and the patterned etch mask can be used to etch the fourth semiconductor layer 204b between fins 208a and 208b to form trench 216', which reaches or terminates somewhere in the third semiconductor layer 206. In some embodiments, anisotropic etching techniques such as dry etching can be used to perform step 104b to form trench 216'. Figure 4b In some embodiments shown, trench 216' extends into but does not extend through the third semiconductor layer 206. In other embodiments, trench 216' terminates at or near the interface between the fourth semiconductor layer 204b and the third semiconductor layer 206. The lower surface of trench 216' lies above or within the third semiconductor layer 206.

[0099] like Figure 1A Step 104c and Figure 4c As shown, the third semiconductor layer 206 is selectively etched isotropically via trench 216' to form a widened trench 216" in the third semiconductor layer 206. In some embodiments, a selective etching process can be used to selectively and isotropically etch the third semiconductor layer 206 between the second semiconductor layer 204a and the fourth semiconductor layer 204b, and to laterally etch the third semiconductor layer 206 between the second semiconductor layer 204a and the fourth semiconductor layer 204b. This selective etching process can be a wet etching using an alkaline solution such as ammonia.

[0100] exist Figure 4cIn the illustrated embodiment, the widened trench 216” terminates at or near the upper surface of the second semiconductor layer 204a. In other embodiments, the widened trench 216” may extend into the second semiconductor layer 204a but not through it. The semiconductor materials constituting the second semiconductor layer 204a and the fourth semiconductor layer 204b are different from the semiconductor materials constituting the third semiconductor layer 206, therefore the second semiconductor layer 204a and the fourth semiconductor layer 204b can serve as etch stop layers or etch barrier layers, allowing lateral etching in the third semiconductor layer 206 to form the widened trench 216.

[0101] like Figure 1A Step 106 and Figure 5b As shown, a dielectric layer 215 is deposited on the third semiconductor layer 206, fins 208a and 208b, and the sidewalls of the widened trench 216. In some embodiments, the materials and formation methods of dielectric layer 215 and dielectric layer 214 may be similar, and therefore their details are not repeated here. In some embodiments, dielectric layer 215 may include dielectric layer 214 that was not removed in steps 104b and 104c. In some embodiments, dielectric layer 215 and dielectric layer 214 have different thicknesses. In these embodiments, dielectric layer 215 is thicker than dielectric layer 214 to protect fins 208a and 208b (see [link to original text]) when removing dummy material. Figure 8b and Figure 9b ).

[0102] like Figure 1A Step 108 and Figure 6b As shown, dummy material 218 is deposited on dielectric layer 215, including deposition into widened trenches 216". In some embodiments, dummy material 218 is etched back, causing at least a portion of fins 208a and 208b to protrude from the upper surface of dummy material 218. In some embodiments, dummy material 218 may be composed of silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride oxycarbonate, aluminum oxide, zirconium oxide, or other suitable metal oxides. In one embodiment, dummy material 218 is composed of aluminum oxide.

[0103] like Figure 1A Step 110 Figure 7b ,and Figure 8b As shown, a patterned hard mask 221 is formed (see...) Figure 8bIn some embodiments, a hard mask layer 220 is deposited on a workpiece 200', including deposition on a dielectric layer 215 and a dummy material 218. In some embodiments, a photoresist material is deposited on the hard mask layer 220 using a suitable deposition method such as spin coating. The deposited photoresist material is then exposed to light through a transmissive mask or reflected light from a self-reflective mask. The exposed photoresist material can undergo physical changes that allow a developer to selectively remove the exposed or unexposed photoresist material. In some embodiments, after the developed photoresist material is baked by a post-bake process, a patterned photoresist layer 222 is formed. In subsequent processes, the patterned photoresist layer 222 can be used as an etching mask to etch the hard mask layer 220 and the dielectric layer 215 beneath the hard mask layer 220 to form a patterned hard mask 221. Figure 8b As shown, the result of step 110 is the removal of the patterned hard mask 221 not covered by the patterned photoresist layer 222, exposing fins 208a and 208b and a portion of the hard masks 210 and 212 on top of the fins. In some embodiments, the hard mask layer 220 and the dielectric layer 215 are composed of different dielectric materials. In one embodiment, the hard mask layer 220 is composed of carbon-doped silicon oxide or silicon nitride, while the dielectric layer 215 is composed of silicon oxide.

[0104] like Figure 1B Step 112 and Figure 9b As shown, a patterned hard mask 221 is used as an etching mask to etch the workpiece 200' to remove the dummy material 218 and dielectric layer 215 not covered by the patterned hard mask 221. In some embodiments, a suitable etching process is used to etch the dummy material 218 and dielectric layer 215. In some embodiments, dilute hydrofluoric acid is used to etch the dummy material 218 and dielectric layer 215, which tends to etch silicon oxide or metal oxides such as aluminum oxide.

[0105] like Figure 1B Step 114 and Figure 10b As shown, the first dummy fin layer 224 was deposited in Figure 9b In the trench shown. In some embodiments, a first dummy fin layer 224 is deposited on the workpiece 200'. In these embodiments, the first dummy fin layer 224 can be deposited compliantly, and the deposition method employs a suitable process such as atomic layer deposition. In some embodiments, the first dummy fin layer 224 may be composed of carbon-doped silicon nitride. After depositing the first dummy fin layer 224 on the workpiece 200', the first dummy fin layer 224 outside the trench is removed, such as... Figure 10bAs shown. In some embodiments, the first dummy fin layer 224 is composed of dielectric materials such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbonitrides, and / or metal oxides.

[0106] like Figure 1B Step 116 and Figure 11b As shown, spacers (or spacer layers) 226 and 228 are formed on fins 208a and 208b. In some embodiments, spacers 226 and 228 are formed of different dielectric materials.

[0107] like Figure 1B Step 118 and Figure 12b As shown, the second dummy fin layer 230 is deposited on the workpiece 200', including deposition on the spacer 228. The material and formation method of the second dummy fin layer 230 are similar to those of the first dummy fin layer 224, therefore the details of the second dummy fin layer 230 will not be repeated here.

[0108] like Figure 1B Step 120 and Figure 13b As shown, the second dummy fin layer 230 is etched back. In some embodiments, after the second dummy fin layer 230 is etched back, a capping layer 232 is formed to protect the second dummy fin layer 230.

[0109] like Figure 1C Step 122 and Figure 14b As shown, the workpiece 200' is planarized. Figure 14b In some embodiments shown, the capping layer 232, spacers 226, spacers 228, hard masking layer 212 on top of the fins, dielectric layer 215, hard masking layer 220, and the upper surface of the first dummy fin layer 224 are coplanar. In some embodiments, suitable planarization techniques such as chemical mechanical polishing are used to planarize the workpiece 200'.

[0110] like Figure 1C Steps 124 and Figure 15b As shown, spacers 226 and 228, dielectric layer 215, and hard masking layer 220 are selectively etched, causing fins 208a and 208b, as well as dummy fins formed by the first dummy fin layer 224 and the second dummy fin layer 230, to protrude from the upper surfaces of spacers 226 and 228, dielectric layer 215, and hard masking layer 220. In some embodiments, the selective etching in step 124 may employ a suitable etching method such as dry etching.

[0111] like Figure 1C Step 126 and Figure 16bAs shown, a full oxide layer 234 may be formed on workpiece 200', including on fins 208a, fins 208b, and dummy fins formed with the first dummy fin layer 224 and the second dummy fin layer 230. In some examples, the full oxide layer 234 serves as an additional dielectric layer for input / output nodes, and may be removed when other nodes do not require an additional dielectric layer.

[0112] like Figure 1C Step 128 and Figure 17b As shown, a dummy gate structure 236 is formed in the channel regions of fins 208a and 208b. In some embodiments, the dummy gate structure 236 includes a dummy gate dielectric layer and a dummy gate. In some embodiments, the dummy gate dielectric layer may comprise silicon oxide or other suitable dielectric material, while the dummy gate may comprise polysilicon. In some examples, one or more sidewall spacers or pads may be formed on the dummy gate structure 236.

[0113] like Figure 1C Step 130 and Figure 18b As shown, step 130 removes the hard masking layers 210 and 212 on top of the fins on the source / drain regions of fins 208a and 208b, and also etches back the dummy fins (formed by the first dummy fin layer 224 and not covered by any masking or capping layer) in the source / drain regions of fins 208a and 208b. The result of step 130 is that the fins 208a and 208b in the source / drain regions are exposed. It is worth noting that the dummy gate structure 236 covers the channel regions of fins 208a and 208b containing the hard masking layers 210 and 212 on top of the fins.

[0114] like Figure 1C Step 132 and Figure 19bAs shown, epitaxial structures 238a and 238b and an interlayer dielectric layer 242 are formed. In some embodiments, devices with different conductivity profiles are formed on fins 208a and 208b. For example, an n-type fin field-effect transistor can be formed on fin 208a, while a p-type fin field-effect transistor can be formed on fin 208b, and vice versa. Epitaxial structures 238a and 238b can be epitaxially formed to cover fins 208a and 208b, respectively. In some embodiments, the epitaxial structures 238a and 238b can be formed using suitable epitaxial processes, such as vapor phase epitaxy, molecular beam epitaxy, or a combination thereof. In embodiments where an n-type fin field-effect transistor is formed on fin 208a and a p-type fin field-effect transistor is formed on fin 208b, the epitaxial structure 238a may be composed of silicon in situ doped with an n-type dopant such as phosphorus, while the epitaxial structure 238b may be composed of silicon germanium in situ doped with a p-type dopant such as boron. In these embodiments, epitaxial structures 238a and 238b are formed sequentially. For example, when forming epitaxial structure 238a on the source / drain region of fin 208a, the source / drain region of fin 208b may be masked. Similarly, when forming epitaxial structure 238b on the source / drain region of fin 208b, the source / drain region of fin 208a may be masked. Figure 19b In some embodiments shown, after forming the epitaxial structures 238a and 238b, an etch stop layer 240 may be formed on the source / drain regions of the fins 208a and 208b, including on the epitaxial structures 238a and 238b. The etch stop layer 240 may be composed of doped or undoped silicon nitride, or other suitable dielectric materials. An interlayer dielectric layer 242 may then be deposited on the workpiece 200'. In some examples, the interlayer dielectric layer 242 may be composed of silicon oxide, silicon nitride, silicon oxynitride, an oxide of tetraethoxysilane, phosphosilicate glass, borosilicate glass, a low dielectric constant dielectric material, other suitable dielectric materials, or combinations thereof.

[0115] like Figure 1D Step 134 and Figure 20b As shown, trench 244 is formed to expose a portion of the dummy material 218 in the epitaxial structure 238a and the widened trench 216". In some embodiments, a photolithography process is performed to form a patterned mask, and the patterned mask is used to recess the interlayer dielectric layer 242 and form the trench 244. Figure 20b In some embodiments shown, trench 244 exposes a portion of the dummy material 218 between fins 208a and 208b and the epitaxial structure 238a. In some examples, a suitable etching process, such as dry etching, is used to form the recess.

[0116] like Figure 1D Step 136 in Figure 21b ,and Figure 22b As shown, a first source / drain contact 248 is formed on the epitaxial structure 238a and contacts the dummy material 218. In some embodiments, prior to forming the first source / drain contact 248, a silicide 246 may be formed on the epitaxial structure 238a. To form the silicide 246, a metal precursor such as titanium may be deposited on the exposed epitaxial structure 238a and annealed to react between the metal precursor and silicon in the epitaxial structure to form titanium silicide. In these embodiments, after forming the silicide 246, a source / drain contact metal such as tungsten or ruthenium may be deposited in the trench 244 to form the first source / drain contact 248. Furthermore, in these embodiments, the first source / drain contact 248 is electrically coupled to the silicide 246 and physically contacts the dummy material 218. In some embodiments, planarization processes such as chemical mechanical polishing can be performed after depositing the source / drain contact metal to remove excess source / drain contact metal on the interlayer dielectric layer 242. In some examples, a dielectric cap 250 can be formed on the first source / drain contact 248 to protect its integrity. In some embodiments, the dielectric cap 250 can be formed using a self-aligned process, and therefore can be referred to as a self-aligned dielectric cap 250.

[0117] like Figure 1D Step 138 Figure 23b ,and Figure 24b As shown, a trench 252 is formed to expose the epitaxial structure 238b, and a second source / drain contact 256 is formed in the trench 252 on the epitaxial structure 238b. The formation process of the second source / drain contact 256 is similar to that of the first source / drain contact 248. The method for forming the trench 252 to expose the epitaxial structure 238b employs photolithography. Figure 23b As shown, trench 252 differs from trench 244 in that trench 252 does not expose the dummy material 218. In some embodiments, after forming trench 252, a metal precursor such as nickel or cobalt may be deposited on the exposed epitaxial structure 238b, and annealing may be performed to allow the silicon in the epitaxial structure 238b to react with the metal precursor to form silicide 254. In these embodiments, after forming silicide 254, source / drain contact metal such as tungsten or ruthenium may be deposited in trench 252 to form a second source / drain contact 256. Furthermore, in these embodiments, the second source / drain contact 256 is electrically coupled to silicide 254. In some embodiments, after depositing the source / drain contact metal, a planarization process such as chemical mechanical polishing may be performed to remove excess source / drain contact metal on the interlayer dielectric layer 242. In some examples, a dielectric cap 258 may be formed on the second source / drain contact 256 to protect the integrity of the second source / drain contact 256.

[0118] In some examples, the dummy gate structure 236 can be replaced by a gate replacement process. In the gate replacement process, the interlayer dielectric layer 242 and any hard masking layer on the dummy gate structure 236 are removed to form an opening and expose the upper surface of the dummy gate structure 236. An etching process is then performed through the opening to remove the dummy gate structure 236. A high-dielectric-constant gate dielectric layer is then formed in the channel regions of the fins 208a and 208b. For example, the high-dielectric-constant gate dielectric layer may comprise hafnium oxide, hafnium silicon oxide, hafnium oxysilicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof. In some embodiments, to enhance the bonding between the high-dielectric-constant gate dielectric layer and the fins 208a and 208b, an interface layer may be formed in the channel region between the high-dielectric-constant gate dielectric layers. The interface layer may include silicon oxide. After forming the gate dielectric layer, gate metal may be deposited in the opening to form the gate of the gate structure. In some examples, one or more work function layers may be formed on the gate to adjust the work function, and one or more dielectric layers may be formed on the gate to protect the gate.

[0119] In some embodiments, an interconnect structure 260 may be formed on the workpiece 200' before the remaining steps of step 140 and after the formation of the first source / drain contact 248 and the second source / drain contact 256. The interconnect structure 260 may include multiple dielectric layers and metal conductive layers.

[0120] like Figure 1D Step 140 and Figure 25b As shown, the workpiece 200' is flipped and bonded to the carrier wafer 300. In some embodiments, a dielectric layer-to-dielectric layer bonding method is used to bond the workpiece 200' to the carrier wafer 300. In these embodiments, an oxide layer 304 is formed on the first source / drain contact 248 and the second source / drain contact 256 (or interconnect structure 260), and another oxide layer 302 is formed on the carrier wafer 300. After forming oxide layers 302 and 304, the workpiece 200' can be flipped along the oxide layer 304 and placed on the carrier wafer 300 so that the oxide layer 302 contacts the oxide layer 304. Annealing is performed to bond the oxide layers 302 and 304, thereby bonding the workpiece 200' to the carrier wafer 300.

[0121] like Figure 1D Step 142 and Figure 26bAs shown, the workpiece 200' is thinned from the first semiconductor layer 202 until the second semiconductor layer 204a is exposed or reached. In some embodiments, planarization techniques such as chemical mechanical polishing are used to remove the first semiconductor layer 202 to thin the workpiece 200'. In these embodiments, the compositional differences and resistance differences to the planarization process between the first semiconductor layer 202 and the second semiconductor layer 204a can be used to monitor the progress of the planarization process and control the planarization of the workpiece 200'.

[0122] like Figure 1E Step 144 and Figure 27b As shown, a portion of the second semiconductor layer 204a and the third semiconductor layer 206 is removed to expose the dummy material 218 in the widened trench 216". In some embodiments, the removal of the second semiconductor layer 204a may employ a suitable planarization technique such as chemical mechanical polishing. Figure 27b As shown, after planarizing the workpiece 200' in step 144, the dummy material 218 in the third semiconductor layer 206 can be exposed. Furthermore, in Figure 27b In one embodiment, step 144 also removes a portion of the third semiconductor layer 206 and the dummy material 218.

[0123] like Figure 1E Step 146 and Figure 28b As shown, dummy material 218 is removed. In some embodiments, the dummy material 218 exposed in step 144 is removed to form trench 262', and the removal method may be a suitable etching technique. For example, dilute hydrofluoric acid may be used to etch the exposed dummy material 218.

[0124] like Figure 1E Step 148 and Figure 29b As shown, metal is deposited on workpiece 200' to form metal layer 264'. In some embodiments, the metal material deposited on workpiece 200' includes deposition within and on trench 262'. In these embodiments, excess metal outside trench 262' can be removed by suitable planarization techniques such as chemical mechanical polishing. The metal forming metal layer 264' may include copper, tungsten, ruthenium, nickel, cobalt, combinations thereof, or other suitable metals. Since the first source / drain contact 248 is in physical contact with the dummy material 218 after the removal of dummy material 218 and the formation of metal layer 264', the first source / drain contact 248 is electrically coupled to metal layer 264'. In some embodiments, the interconnect layers (such as the zeroth metal layer) on the fins 208a and 208b are electrically coupled to a plurality of source / drain contacts (such as the first source / drain contacts 248), and electrically coupled to the metal layer 264' via a plurality of source / drain contacts distributed along the entire length / width of the workpiece 200'. In this way, Figure 29bThe metal layer 264' shown may be part of an embedded power rail or super power rail, which can provide an additional conductive path to the zero metal layer and reduce the voltage drop caused by the zero metal layer.

[0125] like Figure 1E Step 150 and Figure 30b As shown, the workpiece 200' is flipped and bonded to the wafer 400. In some embodiments, an oxide layer 404 is formed on the metal layer 264' of the workpiece 200', and another oxide layer 402 is formed on the wafer 400. In these embodiments, the oxide layers 402 and 404 are annealed to bond the workpiece 200' to the wafer 400. In some embodiments, the wafer 400 may be a silicon wafer.

[0126] like Figure 1E Step 152 and Figure 31b As shown, the carrier wafer 300 is removed from workpiece 200'. In some embodiments, planarization techniques such as chemical mechanical polishing are used to remove the carrier wafer 300 from workpiece 200'. Additional processes may be performed to fabricate an integrated circuit on workpiece 200'. For example, additional metal interconnect structures may be formed on workpiece 200'.

[0127] In some examples, Figure 31b The workpiece 200' may include a complementary metal-oxide-semiconductor device 500', and Figure 32b This shows an enlarged view of a complementary metal-oxide-semiconductor (CMOS) device 500'. The CMOS device 500' includes n-type fin field-effect transistors, such as those formed on fin 208a, and p-type fin field-effect transistors, such as those formed on fin 208b. Figure 32b As shown, the complementary metal-oxide-semiconductor device 500' includes a metal layer 264'. In some embodiments, the portion of the metal layer 264' in the complementary metal-oxide-semiconductor device 500' along section A-A' includes a thickness T2 between the first source / drain junction 248 and the oxide layer 402, a minimum width W2, a maximum width W3, and a penetration depth D2 through the third semiconductor layer 206. In some embodiments, the thickness T2 is between about 40 nm and about 100 nm, the width W2 is between about 15 nm and about 25 nm, the width W3 is between about 40 nm and about 60 nm, and the penetration depth D2 is between about 10 nm and about 50 nm. In some examples, the width W3 is greater than the width W2, and the width W3 may be between about 1.6 times and about 4 times the width W2.

[0128] Compared with existing integrated circuit structures and methods, Figures 1A to 1EThe integrated circuit structure and method 100 on the workpiece 200' shown offer several advantages. The metal layer 264' located between and beneath the fins 208a and 208b can serve as part of a buried power rail or super power rail, providing additional conductive paths to the interconnect structures on the fins 208a and 208b to reduce the resistivity of the metal interconnects without occupying area. In fact, because the widened metal layer 264' provides additional conductors, a smaller interconnect structure can be formed on the fins 208a and 208b, maintaining the same or providing better interconnect resistivity. By employing dummy material 218 as a placeholder for the metal layer 264' in method 100, the metal layer 264' can undergo fewer thermal cycles and has fewer spikes (which could degrade the conductivity quality of the metal layer 264'). Furthermore, the second semiconductor layer 204a and the fourth semiconductor layer 204b serve as an etch stop layer and an etch barrier layer, respectively, which can form a widened trench 216” and thus widen the metal layer 264’ to further reduce resistivity.

[0129] In summary, an integrated circuit having buried interconnect conductors and a method for forming the same are provided herein. In some embodiments, the method includes: receiving a substrate including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, wherein the second semiconductor layer is different from the first and third semiconductor layers; forming a plurality of fins on the third semiconductor layer; forming a trench between two fins, wherein the trench extends through the third semiconductor layer and has a lower surface on the second semiconductor layer; depositing dummy material in the trench; forming gate structures on a plurality of channel regions of the fins; forming a plurality of source / drain structures on a plurality of source / drain regions of the fins; bonding the substrate to a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material from the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material contacts the silicon substrate.

[0130] In some embodiments, the first and third semiconductor layers are composed of silicon, while the second semiconductor layer is composed of silicon-germanium. In some embodiments, the trench forming step includes selectively etching the third semiconductor layer while substantially not etching the second semiconductor layer. In some embodiments, the substrate further includes a fourth semiconductor layer on the third semiconductor layer, and the fourth semiconductor layer is different from the third semiconductor layer. In some examples, the trench forming step includes: forming an opening between two fins and through the fourth semiconductor layer; and selectively etching the third semiconductor layer through the opening while substantially not etching the second and fourth semiconductor layers. In some embodiments, the selective etching step of the third semiconductor layer includes isotropic etching of the third semiconductor layer. In some embodiments, the dummy material includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, aluminum oxide, or other metal oxides. In some embodiments, the conductive material includes copper, tungsten, nickel, cobalt, ruthenium, or combinations thereof.

[0131] In other embodiments, the method includes receiving a substrate including a first silicon layer, a second silicon layer on the first silicon layer, and a first silicon-germanium layer between the first and second silicon layers; forming a plurality of fins on the second silicon layer; forming a trench between two fins, wherein the trench extends through the second silicon layer and has a lower surface on the first silicon-germanium layer; depositing dummy material in the trench; forming a gate structure on a channel region of the fins; forming a source / drain structure on a source / drain region of the fins; bonding the substrate to a carrier wafer; removing the first silicon layer and the first silicon-germanium layer to expose the dummy material; removing the dummy material in the trench; depositing metal in the trench; and bonding the substrate to a third silicon substrate such that the metal contacts the third silicon substrate.

[0132] In some embodiments, the trench forming step includes selectively etching the second silicon layer without substantially etching the first silicon-germanium layer. In some embodiments, the substrate further includes a second silicon-germanium layer on the second silicon layer. In some examples, the trench forming step includes forming an opening through the second silicon-germanium layer; and selectively etching the second silicon layer through the opening without substantially etching the first and second silicon-germanium layers. In some embodiments, the selective etching step of the second silicon layer includes isotropic etching of the second silicon layer under the two fins. In some examples, the dummy material includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, aluminum oxide, or other metal oxides. In some embodiments, the method further includes forming source / drain contacts, wherein the source / drain contacts contact the dummy material. In some embodiments, the removal of the first silicon layer and the first silicon-germanium layer includes: removing the first silicon layer using a first etching process; and removing the first silicon-germanium layer using a second etching process, wherein the first etching process is different from the second etching process.

[0133] In other embodiments, the integrated circuit device includes: a substrate including a silicon layer and a silicon-germanium layer on the silicon layer; a plurality of fins located on the substrate; and an interconnect conductor located in the silicon layer and extending between two of the fins. In some embodiments, the integrated circuit device may further include: a source / drain structure located on one of the fins; and a source / drain contact electrically connected to the source / drain structure. The source / drain contact is electrically connected to the interconnect conductor. In some embodiments, the interconnect conductor extends from between the two fins through the silicon-germanium layer into the silicon layer. In these embodiments, a portion of the interconnect conductor in the silicon layer extends laterally beneath the silicon-germanium layer and the two fins.

[0134] It is worth noting that the embodiments described herein can be used to design and / or fabricate any kind of integrated circuit or part thereof, which may include any of a variety of devices and / or components, such as static random access memory and / or logic circuits, passive components (such as resistors, capacitors, and inductors), active components (such as p-channel field-effect transistors, n-channel field-effect transistors, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistor devices, fully wound gate devices, Ω-gate devices, or Π-gate devices), as well as strained semiconductor devices, semiconductor-on-insulator devices, partially depleted semiconductor-on-insulator devices, fully depleted semiconductor-on-insulator devices, other memory cells, or other devices known in the art. Those skilled in the art will understand that the embodiments of the present invention are advantageous for other semiconductor devices and / or circuits (including their design and fabrication methods).

[0135] The features of the above embodiments are beneficial for those skilled in the art to understand the embodiments of the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the concept and scope of the present invention.

Claims

1. A method for forming an integrated circuit device, comprising: A substrate is received, comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, wherein the second semiconductor layer is different from the first semiconductor layer and the third semiconductor layer. Multiple fins are formed on the third semiconductor layer; A trench is formed between the two plurality of fins, wherein the trench extends through the third semiconductor layer and has a lower surface on the second semiconductor layer; Deposit a dummy material into the trench; A gate structure is formed on the multiple channel regions of the plurality of fins; Multiple source / drain structures are formed on the multiple source / drain regions of the multiple fins; The substrate is bonded to a carrier wafer; Remove the first semiconductor layer and the second semiconductor layer to expose the dummy material; Remove the dummy material from the trench; A conductive material is deposited in the trench; as well as The substrate is bonded to a silicon substrate so that the conductive material contacts the silicon substrate.

2. The method for forming an integrated circuit device as claimed in claim 1, wherein the first semiconductor layer and the third semiconductor layer are composed of silicon, and the second semiconductor layer is composed of silicon-germanium.

3. The method of forming an integrated circuit device as claimed in claim 1, wherein the step of forming the trench includes selectively etching the third semiconductor layer while substantially not etching the second semiconductor layer.

4. The method for forming an integrated circuit device as claimed in claim 1, wherein the substrate further includes a fourth semiconductor layer located on the third semiconductor layer, and the fourth semiconductor layer is different from the third semiconductor layer.

5. The method for forming an integrated circuit device as claimed in claim 4, wherein the step of forming the trench includes: An opening is formed between the two fins and extends through the fourth semiconductor layer; as well as The third semiconductor layer is selectively etched through the opening, while the second and fourth semiconductor layers are not substantially etched.

6. The method for forming an integrated circuit device as claimed in claim 5, wherein the step of selectively etching the third semiconductor layer includes isotropic etching of the third semiconductor layer.

7. The method for forming an integrated circuit device as claimed in claim 1, wherein the dummy material includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, aluminum oxide, or other metal oxides.

8. The method of forming an integrated circuit device as claimed in claim 1, wherein the conductive material comprises copper, tungsten, nickel, cobalt, ruthenium, or a combination thereof.

9. A method for forming an integrated circuit device, comprising: A substrate is received, comprising a first silicon layer, a second silicon layer on the first silicon layer, and a first silicon-germanium layer between the first silicon layer and the second silicon layer; Multiple fins are formed on the second silicon layer; A trench is formed between the two fins, wherein the trench extends through the second silicon layer and has a lower surface on the first silicon-germanium layer; Deposit a dummy material into the trench; A gate structure is formed on the channel region of the fin; Multiple source / drain structures are formed on the source / drain regions of the fin; The substrate is bonded to a carrier wafer; Remove the first silicon layer and the first silicon-germanium layer to expose the dummy material; Remove the dummy material from the trench; A metal is deposited in the trench; as well as The substrate is bonded to a third silicon substrate such that the metal contacts the third silicon substrate.

10. The method of forming an integrated circuit device as claimed in claim 9, wherein the step of forming the trench includes selectively etching the second silicon layer while substantially not etching the first silicon-germanium layer.

11. The method of forming an integrated circuit device as claimed in claim 9, wherein the substrate further includes a second silicon-germanium layer located on the second silicon layer.

12. The method of forming an integrated circuit device as claimed in claim 11, wherein the step of forming the trench includes: An opening is formed through the second silicon-germanium layer; as well as The second silicon layer is selectively etched through the opening, while the first silicon-germanium layer and the second silicon-germanium layer are not substantially etched.

13. The method of forming an integrated circuit device as claimed in claim 12, wherein the step of selectively etching the second silicon layer includes isotropic etching of the second silicon layer under the two said fins.

14. The method of forming an integrated circuit device as claimed in claim 9, wherein the dummy material includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, aluminum oxide, or other metal oxides.

15. The method of forming an integrated circuit device as claimed in claim 9, further comprising forming a source / drain contact, wherein the source / drain contact contacts the dummy material.

16. The method for forming an integrated circuit device as claimed in claim 9, wherein the step of removing the first silicon layer and the first silicon-germanium layer comprises: The first silicon layer is removed using a first etching process; as well as The first silicon-germanium layer is removed using a second etching process, and the first etching process is different from the second etching process.

17. A method for forming an integrated circuit device, comprising: Receive a substrate, which includes a first silicon layer, a first silicon-germanium layer on the first silicon layer, a second silicon layer on the first silicon-germanium layer, and a second silicon-germanium layer on the second silicon layer; Multiple fin-like structures are formed on the second silicon-germanium layer; A trench is formed between the two fins, wherein the trench extends through the second silicon-germanium layer and has a lower surface on the second silicon layer; The second silicon layer is selectively etched anisotropically to widen the trench into a wider trench; Deposit a dummy material in the widened trench; A dummy gate structure is formed on the channel region of the fin; Multiple source / drain structures are formed on the source / drain regions of the fin; A source / drain contact is formed to contact the dummy material in the widened trench; The substrate is bonded to a carrier wafer; Remove the first silicon layer and the first silicon-germanium layer to expose the dummy material; Selectively remove the dummy material in the widened trench to expose the source / drain contact; as well as A metal is deposited in the widened trench.

18. The method of forming an integrated circuit device as claimed in claim 17, wherein the dummy material includes silicon oxide, silicon nitride, silicon carbonitride, silicon nitride, aluminum oxide, or zirconium oxide.

19. The method of forming an integrated circuit device as claimed in claim 17, further comprising: After the dummy material is deposited, a first dummy fin is formed on the trench; as well as A second dummy fin is formed, such that each fin is located between the first dummy fin and the second dummy fin.

20. The method of forming an integrated circuit device as described in claim 19, The first dummy fin includes a dielectric layer; The second dummy fin includes the dielectric layer and a capping layer on the dielectric layer.

21. An integrated circuit device, comprising: A substrate comprising a silicon layer and a silicon-germanium layer thereon; Multiple fins are located on the substrate; An internal interconnect conductor is located in the silicon layer and extends between the two fins; A source / drain structure is located on one of the fins; as well as A source / drain contact is electrically connected to this source / drain structure. The source / drain contact is electrically connected to the internal interconnect conductor and has an interface with the internal interconnect conductor.

22. The integrated circuit device of claim 21, wherein the interconnect conductor extends from between the two fins through the silicon-germanium layer into the silicon layer.

23. The integrated circuit device of claim 22, wherein a portion of the interconnect conductor in the silicon layer extends laterally beneath the silicon-germanium layer and the two fins.

24. The integrated circuit device of claim 22, wherein the interconnect conductor is separated from the two fins by a dielectric layer.

25. The integrated circuit device of claim 24, wherein the interconnect conductor and the silicon-germanium layer are separated from the silicon layer by the dielectric layer.

26. The integrated circuit device of claim 24, wherein the source / drain contact directly contacts the dielectric layer.

27. An integrated circuit device, comprising: A first fin, a second fin, and a third fin are located on a silicon layer; An internal interconnect conductor is located between the first fin and the second fin, and extends through the silicon layer; A dummy fin is located between the second fin and the third fin; A first source / drain structure is located on the first fin; and A first source / drain contact is electrically connected to the first source / drain structure. The first source / drain contact is electrically connected to the internal interconnect conductor and has an interface with the internal interconnect conductor.

28. The integrated circuit device as claimed in claim 27, The first fin, the second fin, and the third fin comprise silicon. The dummy fin includes semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor carbonitrides, semiconductor carbonitrides, semiconductor carbonitrides, or metal nitrides.

29. The integrated circuit device of claim 27, wherein the interconnect conductor extends through the silicon layer.

30. The integrated circuit device of claim 29, wherein the interconnect conductor is separated from the first fin, the second fin, and the third fin by a dielectric layer.

31. The integrated circuit device of claim 30, wherein the dielectric layer comprises silicon oxide.

32. The integrated circuit device of claim 27, further comprising: A silicide layer is located on the first source / drain structure. The first source / drain junction is located on the silicide layer. The first source / drain contact extends between the first fin and the second fin to contact the internal interconnect conductor.

33. The integrated circuit device of claim 32, wherein the first source / drain contact is separated from the second fin by a dielectric layer, and the dielectric layer extends into the silicon layer.

34. The integrated circuit device of claim 27, further comprising: A second source / drain structure is located on the second fin; as well as A third source / drain structure is located on the third fin. The second source / drain structure is separated from the third source / drain structure by the dummy fin.

35. The integrated circuit device of claim 27, wherein the dummy fin is separated from the second fin, the silicon layer, and the third fin by at least one spacer layer.

36. An integrated circuit device, comprising: One silicon layer; A silicon-germanium layer is located on the silicon layer; A first fin, a second fin, and a third fin are located on the silicon-germanium layer; An internal interconnect conductor is located between the first fin and the second fin, and extends through the silicon-germanium layer; A dummy fin is located between the second fin and the third fin; A source / drain structure is located on one of the fins; as well as A source / drain contact is electrically connected to this source / drain structure. The source / drain contact is electrically connected to the internal interconnect conductor and has an interface with the internal interconnect conductor.

37. The integrated circuit device of claim 36, wherein the interconnect conductor further extends through the silicon layer.

38. The integrated circuit device of claim 36, wherein the interconnect conductor is separated from the first fin, the second fin, the silicon layer, and the silicon-germanium layer by a dielectric layer.

39. The integrated circuit device as claimed in claim 36, The first fin, the second fin, and the third fin extend longitudinally along a first direction; The interconnect conductor has a first width in the silicon layer and a second width in the silicon-germanium layer along a second direction, and the second direction is perpendicular to the first direction. The first width is greater than the second width.

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