Semiconductor device having a top die positioned to reduce die cracking

Abstract

The present invention is entitled "Semiconductor device with top die positioned to reduce die cracking". The present invention discloses a semiconductor device comprising a die stack including a plurality of dies aligned with each other relative to an axis and a top die offset along the axis to prevent die cracking.

Description

Background Art

[0001] Strong growth in demand for portable consumer electronic devices has driven the need for high-capacity storage devices. Non-volatile semiconductor storage devices, such as flash memory cards, have been widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, as well as their high reliability and large capacity, make such storage devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, and cellular phones.

[0002] Although many different packaging configurations are known, flash memory semiconductor products can generally be manufactured as a system-in-package (SIP) or a multi-chip module (MCM), in which multiple semiconductor dies are mounted and interconnected to the upper surface of a substrate. The substrate can generally include a rigid dielectric base having a conductive layer etched on one or both sides. Solder balls are generally mounted on contact pads formed on the lower surface of the substrate to allow the substrate to be soldered to a host device, such as a printed circuit board. Once mounted, signals can be transmitted between the semiconductor dies in the package and the host device via the substrate.

[0003] There is a need to provide greater storage capacity in a smaller overall form factor semiconductor package. One way to do this is to reduce the thickness of the semiconductor die within the package without losing or even gaining storage capacity. One disadvantage of reducing the thickness of the semiconductor die is that they become more fragile and prone to cracking, for example, when subjected to the packaging process. Of all the dies in the package, the top die is usually the most susceptible to cracking. This is because there are no other dies on it to provide structural support. It is also because the top die has the shortest heating time for joining the die to the stack. For example, the bottom die is heated not only when it is added, but also when each subsequent die is added. No more dies are added after the top die, so it only undergoes a single heating process related to its attachment. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a flow chart for forming a semiconductor device according to an embodiment of the present technology.

[0005] Figure 2 is a top view of a semiconductor wafer including a semiconductor die according to an embodiment of the present technology.

[0006] Figure 3 is a top view of a semiconductor die according to an embodiment of the present technology.

[0007] Figure 4 is an edge view of a semiconductor die according to an embodiment of the present technology.

[0008] Figure 5 is a top view of a group of stacked semiconductor dies in accordance with an embodiment of the present technology.

[0009] Figure 6 According to the embodiment of the present invention Figure 5 A front view of the group of semiconductor dies.

[0010] Figure 7 is a top view of a set of stacked and wire-bonded semiconductor dies in accordance with an embodiment of the present technology.

[0011] Figure 8 According to the embodiment of the present invention Figure 7 A front view of a group of stacked and wire-bonded semiconductor dies.

[0012] Fig. 9 According to the embodiment of the present invention Figure 7 A side view of a group of stacked and wire-bonded semiconductor dies.

[0013] Fig.10 According to the embodiment of the present invention Figure 7 A perspective view of a group of stacked and wire-bonded semiconductor dies.

[0014] Fig.11 is a top view of a set of stacked and wire-bonded semiconductor dies in accordance with an embodiment of the present technology.

[0015] Fig.12 According to the embodiment of the present invention Fig.11 A front view of a group of stacked and wire-bonded semiconductor dies.

[0016] Fig.13 According to the embodiment of the present invention Fig.11 A side view of a group of stacked and wire-bonded semiconductor dies.

[0017] Fig.14 According to the embodiment of the present invention Fig.11 A graph of bonding times for different semiconductor dies in a die stack is shown.

[0018] Fig.15 is a top view of a set of stacked and wire-bonded semiconductor dies in accordance with an embodiment of the present technology.

[0019] Fig.16 According to the embodiment of the present invention Fig.11 A front view of a group of stacked and wire-bonded semiconductor dies.

[0020] Fig.17According to the embodiment of the present invention Fig.11 A side view of a group of stacked and wire-bonded semiconductor dies.

[0021] Fig.18 is a side view of a complete semiconductor device according to an embodiment of the present technology.

[0022] Fig.19 is a front view of an alternative embodiment of the present technology. DETAILED DESCRIPTION

[0023] The technology of the present invention will now be described with reference to the accompanying drawings, which relate to a semiconductor device including a top die in an embodiment, which is offset to prevent die cracking. It should be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure will be thorough and complete, and the present invention will be fully communicated to those skilled in the art. In fact, the present invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are all included in the scope and essence of the present invention as defined by the appended claims. In addition, in the following specific embodiments of the present invention, many specific details are given in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention can be implemented without such specific details.

[0024] The terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal", and forms thereof, as used herein, are used herein by way of example only and for exemplary purposes, and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "approximately" mean that a specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ±2.5% of a given dimension.

[0025] Now refer to Figure 1 Flowchart and Figures 2 to 18 In step 200, the semiconductor wafer 100 can be processed into Figure 2 A plurality of semiconductor dies 102 are shown. Semiconductor wafer 100 may begin as an ingot of wafer material, which may be single crystal silicon grown according to a Czochralski (CZ) or floating zone (FZ) process. However, in other embodiments, wafer 100 may be formed from other materials and by other processes.

[0026] The semiconductor wafer 100 can be cut from the ingot and formed on a first major planar surface 104 and a second major planar surface 105 ( Figure 4 ) to provide a smooth surface. The first major surface 104 may undergo various processing steps to separate the wafer 100 into respective semiconductor dies 102. Specifically, in step 200, the semiconductor dies 102 may be processed in an embodiment to form integrated circuits and internal electrical connections in a dielectric substrate. The top surface of the semiconductor die may include a polyimide (PI) / passivation layer 110 and a die bond pad 106 ( Figure 3 ). Figure 2 The number of semiconductor dies 102 shown on the wafer 100 is for illustrative purposes, and the wafer 100 may include more semiconductor dies 102 than shown in alternative embodiments.

[0027] As is well known, the scribe lines 112 may be defined between rows and columns of semiconductor dies 102 on the wafer 100. Figure 2 1 and 10. Although shown and labeled in dashed lines, horizontal and vertical scribe lines are provided around each semiconductor die in the wafer 100. These scribe lines 112 are free of integrated circuits and PI / passivation layer 110, and are provided as areas where the wafer can be cut, for example, by a blade or laser. In an embodiment, the scribe lines 112 can be 70 microns wide, but in other embodiments, the scribe lines 112 can be wider or narrower. In step 202, after the wafer 100 is processed to form the integrated circuits, a die attach film (DAF) layer 114 ( Figure 4 ).

[0028] In step 204, the semiconductor wafer 100 may be cut along the scribe lines 112 to separate the semiconductor dies 102 from the wafer 100. Figure 3 and Figure 4 1 and 10. In an embodiment, a laser can be used to cut the wafer 100, which provides a highly accurate and controlled cutting force for wafers with narrow kerf widths. As a result, the cut semiconductor dies 102 each include a border around its four edges, including a portion (e.g., half) of the width of the scribe line 112. As described above, these borders, marked as 118 in the figure, do not have any integrated circuits and do not have the PI / passivation layer 110.

[0029] In an embodiment, border 118 may have a width w of 35 microns, but in other embodiments, the width may be smaller or larger. In an embodiment, border 118 may have the same width around all four edges of semiconductor die 102, but in other embodiments, the border may have unequal widths around one or more edges. Figure 4 As can be seen in FIG. 1 , PI / passivation layer 110 may extend over border 118 formed around the periphery of semiconductor die 102. Thus, semiconductor die 102 includes an inner portion having a thickness t1 and an outer border having a thickness t2 that is less than t1. In an embodiment, the thickness t1 of the inner portion of die 102 (including DAF layer 114) may be 43.4 microns, and the thickness t2 of the border portion around die 102 may be 37 microns. These thicknesses are shown by way of example only and may vary in additional embodiments.

[0030] In addition to insulation and protection, the PI / passivation layer 110 provides additional strength to the semiconductor die 102 along an axis perpendicular to the major surfaces 104, 105. Therefore, the semiconductor die 102 is stronger and has a greater resistance to shear and bending forces along a cross section through the die 102 including the PI / passivation layer 110 than a cross section through the boundary 118.

[0031] In step 208, after dicing, the plurality of semiconductor dies 102 may be mounted on a substrate such as Figure 5 and Figure 6 The substrate 120 is shown. Figure 5 and Figure 6 A top view and a front view, respectively, of a portion of a semiconductor device 150 are shown, the semiconductor device including some of the dies in a die stack 122. As described below, additional dies 102 are added to the stack 122. Figure 5 and Figure 6 In the die stack 122 shown, the dies are stacked in a stepped offset configuration in the y-direction so that a row of die bond pads 106 on a first die 102 is uncovered and exposed by a second die 102 mounted thereon. The dies 102 in the stack 122 can be aligned with each other relative to the x-axis. The dies 102 can be formed by the DAF layer 114 ( Figures 5 to 19 1 and 12 are attached to the substrate 120 and to each other. Figure 6 As can be seen in FIG. 1 , the thickness of the PI / passivation layer 110 provides space between boundaries 118 of adjacent dies 102 in the stack 122 .

[0032] Figure 7 , Figure 8 , Fig. 9 and Fig.10A top view, a front view, a side view, and a perspective view of a portion of a semiconductor device 150 including a complete die stack 122 are shown, respectively. Figures 7 to 10 In the die stack 122 shown, the topmost die 102a has been added to the stack. As in the lower die 102 in the stack 122, the die 102a is stepped in an offset configuration in the y direction. According to aspects of the technology, the die 102a is also offset in the x direction. The die 102a can be offset along the x-axis so that the edge 126 ( Figure 7 , Figure 8 and Fig.10 ) is located above the PI / passivation layer 110 of the next lower die 102. In an embodiment, the top die 102a can be offset by 6.4 microns along the x-axis, but in other embodiments, it can be offset by more or less. In addition, although the edge 126 is shown as being directly mounted above the PI / passivation layer 110 of the next lower die 102, it should be understood that the offset along the x-axis can be increased so that the edge 126 of the die 102a is spaced inwardly from the edge of the PI / passivation layer 110 of the next lower die.

[0033] The semiconductor die 102 may be any of a variety of semiconductor dies, including, for example, a memory die, such as a 2D NAND flash memory or a 3D BiCS (bit cost scaling), V-NAND or other 3D flash memory. However, other types of semiconductor dies may be used, including, for example, RAM, such as SDRAM, DDR SDRAM, LPDDR, and GDDR. Additionally, in step 208, a controller die, such as an ASIC (not shown), may also be mounted on the substrate or on top of the stack 122.

[0034] Passive components (not shown) may be mounted on substrate 120 in step 210, either before or after mounting the semiconductor die on substrate 120. Passive components may include, for example, resistors, capacitors, and / or inductors.

[0035] Once the dies 102 (including die 102a) are mounted in stack 122, the dies 102 may be electrically interconnected to each other and to substrate 120 at step 214. In one embodiment, the electrical interconnects may be, for example, Figures 7 to 10 Wire bonds 128 are shown. Wire bonds may be formed in a known wire bonding process using a wire bonding capillary (not shown) that connects corresponding die bond pads 106 in different dies 102 to each other and to contact pads 130 ( Figure 7 and Fig.10 The wire bonds may extend straight up the die stack 122 and then extend diagonally between the topmost die 102a and the next lower die.

[0036] Wire bonds 128 may be, for example, wedge bonds formed on ball bonds deposited on bond pads 106 and contact pads 130, but other types of wire bonds are possible in other embodiments. Furthermore, it is contemplated that in addition to wire bonds, electrical interconnects may be formed by through silicon vias (TSVs) formed down through the different dies 102 in stack 122 and in contact with a pattern of contact pads on substrate 120.

[0037] Although Figures 7 to 10 Four semiconductor dies are shown in stack 122, but it should be understood that in other embodiments, stack 122 may include various numbers of memory dies, including, for example, 2, 8, 16, 32, and 64 memory dies. Other numbers of dies between 2 and 64 and greater than 64 are possible. Figures 11 to 13 A top view, front view, and side view of another such embodiment including eight semiconductor dies are shown. As described above, all dies in the die stack 122 are offset along the y-axis in a stepped configuration. All dies in the die stack 122 are aligned with each other relative to the x-axis except for the topmost die 102a. As described above, the topmost die 102a is offset along the x-axis so that the edge 126 of the die 102a is aligned above the PI / passivation layer 110 of the next lower die.

[0038] As described in the Background section, given the thin profile of modern semiconductor dies, these semiconductor dies are fragile and prone to cracking during manufacturing. For example, given the height of the PI / passivation layer, the semiconductor die is unsupported around its edges in the border region. When subjected to stress, such as during the packaging process, the die may crack at these edges. This is most likely at the top semiconductor die because this die experiences the least amount of curing time. Fig.14 As shown in the graph of , each die in the eight-die stack experiences 1 second of direct bonding. However, the dies that are bonded early (i.e., those lower in the stack 122) also experience indirect bonding time. For example, the first (bottom-most) die experiences 1 second of direct bonding time, and then each additional die added to the die stack adds an additional 1 second of indirect bonding time. Each die in the stack 122, except the top-most die, experiences this additional indirect bonding time. Therefore, the top-most die 102a has the weakest bond to the stack and may bend and / or break when subjected to stress.

[0039] The present invention solves this problem by offsetting the top die 102a along the x-axis. Thus, the outer edge 126 of the die 102a is fully supported on the die below it (i.e., on the PI / passivation layer 110 of the die below it). The opposite edge-edge 134 ( Fig.12 ) still overhangs the empty space. However, the portion of die 102a overhanging the empty space at edge 134 also includes PI / passivation layer 110. Thus, the portion of die 102a extending beyond the PI / passivation layer 110 of the next lower die has a greater thickness at the overhang (i.e., the thickness of boundary 118 plus the thickness of PI / passivation layer 110). This relatively greater thickness at the overhang area at edge 134 (compared to the lower die) provides greater strength and resistance to shear stresses than the lower die in the stack.

[0040] Figures 15 to 17 A top view, a front view, and a side view of another embodiment of a stack 122 including eight dies are shown, respectively. Fig.17 As can be seen in FIG. 1 , rather than each die being offset in the same direction along the y-axis, the dies are stacked so as to be folded in half upon themselves. This embodiment may have a smaller footprint on the substrate in the xy plane. In this embodiment, wire bonds 128 may be connected to two rows of contact pads on substrate 120 at opposite edges of substrate 120, such as Fig.17 All of the dies may be aligned with one another along the x-axis except for the uppermost die 102a, which may be offset along the x-axis as described above.

[0041] Reference again Figure 1 After the semiconductor dies 102 are mounted in the stack 122 and electrically interconnected, the semiconductor dies 102 may be encapsulated in a molding compound 140 in step 216, such as Fig.18 As shown. The molding compound 140 may include, for example, solid epoxy resins, phenolic resins, fused silica, crystalline silica, carbon black, and / or metal hydroxides. Other molding compounds from other manufacturers are contemplated. The molding compound may be applied by various known processes, including by compression molding, FFT (no flow thin) molding, transfer molding, or injection molding techniques.

[0042] During the manufacturing process, the substrate 120 can be maintained as a panel of many substrates to achieve economies of scale in the manufacturing process. After the packaging step, the individual semiconductor devices 150 can be cut (separated) from each other in step 220 to form Fig.18 The complete semiconductor device shown in FIG. 1 is a semiconductor device of FIG. 150. Depending on the application of the semiconductor device 150, a pattern of solder balls 148 may be applied to the bottom surface of the substrate 120, such as Fig.18As shown. For example, these solder balls can be applied before step 208 of mounting the die on the substrate. Then, the semiconductor device 150 can be mounted on a host device (not shown) by soldering the solder balls 148 on the contact pads of the host device. Thereafter, communication between the semiconductor device 150 and the host device can be completed through the semiconductor die 102.

[0043] In the above embodiment, the uppermost die 102a is strengthened to prevent cracking by offsetting the die so that one edge is directly supported on the next lower die and the opposite edge has a relatively greater thickness where it overhangs the next lower die. It should be understood that dies other than the uppermost die may also be offset along the x-axis to increase strength for these dies. Fig.19 An example is shown in which the top three dies (die 102a, die 102b, and die 102c) are each offset not only from one another along the y-axis, but also along the x-axis in the manner described above with respect to die 102a. Fig.19 In the illustrated embodiment, die 102a, die 102b, and die 102c are offset in alternating directions along the x-axis. In other embodiments, die 102a, die 102b, and die 102c can each be offset in the same direction along the x-axis. It should be understood that in other embodiments, the top two dies or more than the top three dies can be offset from each other along the x-axis.

[0044] In summary, an example of the technology of the present invention relates to a semiconductor device comprising: a plurality of semiconductor dies, each of the plurality of semiconductor dies comprising: an inner portion having a first thickness, and an outer portion having a second thickness less than the first thickness along opposite first and second edges; wherein the plurality of semiconductor dies are stacked on top of each other in a stack such that a group of semiconductor dies at the bottom of the stack are aligned with each other relative to a first axis, and at least the topmost die is offset along the first axis relative to the next lower die, the offset positioning the outer portion of the topmost die at the first edge above the inner portion of the next lower die.

[0045] In another example, the technology of the present invention relates to a semiconductor device, including: a plurality of n semiconductor dies, each of the plurality of semiconductor dies including: an inner portion having a first thickness, and an outer portion having a second thickness less than the first thickness along opposite first and second edges; wherein the plurality of n semiconductor dies are stacked on top of each other in a stack, and are configured to increase the strength and crack resistance of the topmost semiconductor die by aligning a group of n-1 semiconductor dies at the bottom of the stack with each other relative to a first axis, and offsetting the topmost die along the first axis relative to the next lower die, the offset positioning the outer portion of the topmost die at the first edge above the inner portion of the next lower die.

[0046] In another example, the technology of the present invention relates to a semiconductor device, including: a plurality of n semiconductor dies, each of the plurality of semiconductor dies including: an inner portion having a first thickness, and an outer portion having a second thickness less than the first thickness along opposite first and second edges; wherein the plurality of n semiconductor dies are stacked on top of each other; and a device for increasing the strength and crack resistance of the topmost semiconductor die by aligning a group of n-1 semiconductor dies at the bottom of the stack with each other relative to a first axis, and offsetting the topmost die along the first axis relative to the next lower die, the offset positioning the outer portion of the topmost die at the first edge above the inner portion of the next lower die.

[0047] The above specific embodiments of the present invention have been proposed for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. Based on the above teachings, many modifications and variations are possible. The described embodiments are selected to best illustrate the principles of the present invention and its practical application, so that other technical personnel in the field can best use the present invention with various modifications suitable for the specific purpose contemplated in various embodiments. The scope of the present invention is intended to be limited by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of semiconductor dies, each of the plurality of semiconductor dies comprising: an inner portion having a first thickness, and an outer portion along opposing first and second edges having a second thickness less than the first thickness; wherein the plurality of semiconductor dies are stacked on top of each other in a stack such that a group of semiconductor dies at a bottom of the stack are aligned with each other relative to a first axis and at least an uppermost die is offset relative to a next lower die along the first axis; wherein the number of dies in the stack is n, and the number of dies aligned with each other relative to the first axis in the die group at the bottom of the stack is n-1; wherein the plurality of semiconductor dies in the stack are offset from one another in a stepped configuration along a second axis orthogonal to the first axis such that a die bond pad on each semiconductor die of the plurality of semiconductor dies is uncovered and exposed by a semiconductor die mounted thereon; wherein the offset positions an outer portion of the uppermost die sheet at the first edge above an inner portion of the next lower die sheet; and Wherein the thickness difference between the inner portion and the outer portion is that the inner portion includes a polyimide / passivation layer extending above a surface of the outer portion. 2 . The semiconductor device of claim 1 , wherein the inner portion of the uppermost die at the second edge overhangs the outer portion of the next lower die. 3 . The semiconductor device according to claim 1 , wherein the outer portion is a portion of a scribe line where the plurality of semiconductor dies are cut from the wafer. 4 . The semiconductor device of claim 1 , wherein the plurality of semiconductor dies in the stack are offset from each other in the stepped configuration in the same direction along the second axis.

5. The semiconductor device of claim 1 , wherein some of the plurality of semiconductor dies in the stack are offset from each other in the stepped configuration along the second axis in a first direction, and wherein some of the plurality of semiconductor dies in the stack are offset from each other in the stepped configuration along the second axis in a second direction opposite to the first direction. 6 . The semiconductor device of claim 1 , further comprising wire bonds extending in a second direction between corresponding die bond pads on the plurality of semiconductor dies in the stack.

7. The semiconductor device according to claim 1, wherein the plurality of semiconductor dies are memory dies. 8 . The semiconductor device of claim 7 , wherein the plurality of memory dies are one of 2D NAND flash memory or 3D bit cost scaling flash memory.

9. A semiconductor device comprising: n semiconductor dies, each of the n semiconductor dies comprising: an inner portion having a first thickness, and an outer portion along opposing first and second edges having a second thickness less than the first thickness; wherein the n semiconductor dies are stacked on top of each other in a stack and are configured to increase the strength and crack resistance of an uppermost semiconductor die by aligning a group of n-1 semiconductor dies at a bottom of the stack with each other relative to a first axis and offsetting an uppermost die relative to a next lower die along the first axis by an amount that positions an outer portion of the uppermost die at the first edge above an inner portion of the next lower die; wherein the n semiconductor dies in the stack are offset from each other in a stepped configuration along a second axis orthogonal to the first axis such that a die bond pad on each of the n semiconductor dies is uncovered and exposed by a semiconductor die mounted thereon; and Wherein the thickness difference between the inner portion and the outer portion is that the inner portion includes a polyimide / passivation layer extending above a surface of the outer portion.

10. The semiconductor device of claim 9, wherein the inner portion of the uppermost die at the second edge overhangs the outer portion of the next lower die.

11. The semiconductor device according to claim 9, wherein the outer portion is a portion of a scribe line where the n semiconductor dies are cut from the wafer. 12 . The semiconductor device of claim 9 , wherein the n semiconductor dies in the stack are offset from each other in the stepped configuration in the same direction along the second axis.

13. A semiconductor device according to claim 9, wherein some of the n semiconductor dies in the stack are offset from each other in the stepped configuration along the second axis in a first direction, and wherein some of the n semiconductor dies in the stack are offset from each other in the stepped configuration along the second axis in a second direction opposite to the first direction. 14 . The semiconductor device of claim 9 , further comprising wire bonds extending in a second direction between corresponding die bond pads on the n semiconductor dies in the stack.

15. A semiconductor device comprising: n semiconductor dies, each of the n semiconductor dies comprising: an inner portion having a first thickness, and an outer portion along opposing first and second edges having a second thickness less than the first thickness; wherein the n semiconductor dies are stacked on top of each other; means for increasing the strength and crack resistance of an uppermost semiconductor die by aligning a group of n-1 semiconductor dies at a bottom of the stack with respect to a first axis and offsetting the uppermost die relative to a next lower die along the first axis by an amount that positions an outer portion of the uppermost die at the first edge above an inner portion of the next lower die; The n semiconductor dies in the stack are offset from each other in a stepped configuration along a second axis orthogonal to the first axis such that a die bond pad on each of the n semiconductor dies is uncovered and exposed by a semiconductor die mounted thereon; and Wherein the thickness difference between the inner portion and the outer portion is that the inner portion includes a polyimide / passivation layer extending above a surface of the outer portion.

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