Semiconductor device

Abstract

A semiconductor device is provided, including: a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper portion of the air spacer.

Description

[0001] Korean Patent Application No. 10-2019-0063657, entitled "Semiconductor Device and Method for Fabricating the Same", filed on May 30, 2019 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0003] As semiconductor devices become increasingly highly integrated, individual circuit patterns can be further miniaturized to accommodate more semiconductor devices within the same area. Summary of the Invention

[0004] An embodiment can be implemented by providing a semiconductor device comprising: a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering the upper portion of the air spacer.

[0005] An embodiment can be implemented by providing a semiconductor device comprising: a substrate including an active region; a bit line structure located on the substrate and intersecting the active region; an air spacer extending along the sidewall of the bit line structure; and a quantum dot pattern covering the upper portion of the air spacer.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: a substrate; a first conductive pattern on the substrate; an air spacer extending along a sidewall of the first conductive pattern; a cover pattern on the first conductive pattern, the cover pattern including a trench open to the upper portion of the air spacer; and a quantum dot pattern filling at least a portion of the trench.

[0007] An embodiment can be implemented by providing a semiconductor device comprising: a substrate including an active region; a bit line structure intersecting the active region; an air spacer extending along a sidewall of the bit line structure; a plurality of bonding pads located on the bit line structure and connected to the active region; a trench open to the upper portion of the air spacer and separating each of the bonding pads; and a quantum dot pattern filling at least a portion of the trench.

[0008] An embodiment can be implemented by providing a method for manufacturing a semiconductor device, the method comprising the steps of: forming a first conductive pattern on a substrate and forming a second conductive pattern on the substrate, such that the first conductive pattern and the second conductive pattern are spaced apart; forming an air spacer between the first conductive pattern and the second conductive pattern; and forming a quantum dot pattern such that the quantum dot pattern covers the upper part of the air spacer. Attached Figure Description

[0009] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0010] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0011] Figure 2 It shows Figure 1 A magnified view of region S.

[0012] Figure 3 A layout diagram of a semiconductor device according to some embodiments is shown.

[0013] Figure 4 It shows along Figure 3 A sectional view taken by line A-A'.

[0014] Figures 5 to 8 It shows Figure 4 Various magnified views of region R.

[0015] Figure 9 It shows along Figure 3 The sectional view taken by line B-B'.

[0016] Figure 10 It shows along Figure 3 A sectional view taken by line C-C'.

[0017] Figures 11 to 13 The stages of a method for manufacturing a semiconductor device according to some embodiments are shown.

[0018] Figures 14 to 24 The stages of a method for manufacturing a semiconductor device according to some embodiments are shown. Detailed Implementation

[0019] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments is shown. Figure 2 Show Figure 1 A magnified view of region S.

[0020] Reference Figure 1 and Figure 2According to some embodiments, a semiconductor device may include a substrate 10, a plurality of conductive patterns 20, an air spacer 40, a quantum dot pattern QD, and a filling insulating film 50.

[0021] In embodiments, substrate 10 may have a structure including, for example, a base substrate and an epitaxial layer stack. Substrate 10 may also be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, or an SOI (semiconductor on insulator) substrate. As an example, substrate 10 described below is a silicon substrate.

[0022] Multiple conductive patterns 20 may be located on the substrate 10. In one embodiment, the multiple conductive patterns 20 may be in contact with the substrate 10 (e.g., in direct contact). In another embodiment, the multiple conductive patterns 20 may be located in or on an insulating film on the substrate 10, and may not be in direct contact with the substrate 10.

[0023] Air spacers 40 may be located between two adjacent conductive patterns 20. For example, multiple conductive patterns 20 may be electrically separated from each other by air spacers 40 (e.g., electrically separated from each other in the first direction X). In embodiments, air spacers 40 may be composed of air or gaps.

[0024] In one embodiment, the air spacer 40 can simply expose the side surface of the corresponding conductive pattern 20. In another embodiment, an insulating film (or spacer) can be located between the air spacer 40 and the corresponding conductive pattern 20.

[0025] The quantum dot pattern QD may be located on the air spacer 40. The quantum dot pattern QD may cover the upper part of the air spacer 40 (e.g., the end or side of the air spacer 40 away from the substrate 10 in the third direction Z). For example, the quantum dot pattern QD may define the upper end of the air spacer 40. For example, the quantum dot pattern QD may close or block the open upper end of the air spacer 40.

[0026] In one embodiment, the cover pattern 30 may be located on the conductive pattern 20. In another embodiment, the cover pattern 30 may include a trench T that exposes the upper end of the air spacer 40 (e.g., the trench T may be open to or in fluid communication with the air spacer 40). The quantum dot pattern QD may fill at least a portion of the trench T. For example, as... Figure 1 and Figure 2 As shown, the quantum dot pattern QD can fill the lower portion of the trench T (e.g., the portion of the trench T near the substrate 10 in the third direction Z). This can be advantageous for covering the upper end of the air spacer 40 exposed to the trench T with the quantum dot pattern QD.

[0027] A quantum dot pattern (QD) can include multiple quantum dots. A quantum dot can refer to an ultrafine semiconductor particle having a size of several nanometers. In embodiments, a quantum dot pattern (QD) can include, for example, silicon oxide quantum dots, silicon nitride quantum dots, polycrystalline silicon quantum dots, silicon-germanium quantum dots, or combinations thereof. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0028] In some embodiments, the quantum dot pattern (QD) may include, for example, spherical quantum dots. In some embodiments, the quantum dot pattern (QD) may include, for example, multiple quantum dots having the same size as each other. In some embodiments, the quantum dot pattern (QD) may include, for example, quantum dots in forms other than spherical, and / or may include multiple quantum dots with different sizes.

[0029] In one embodiment, the size of the quantum dot pattern QD can be larger than the width of the air spacer 40. In another embodiment, such as... Figure 2 As shown, when the quantum dot pattern QD is spherical, the diameter W1 of the quantum dot pattern QD measured in the first direction X can be larger than the width W2 of the air spacer 40 measured in the first direction X.

[0030] The insulating filler 50 can be located on the quantum dot pattern QD. The insulating filler 50 can cover the quantum dot pattern QD. In an embodiment, such as... Figure 2 As shown, the filling insulating film 50 can partially fill the space between the multiple quantum dots of the quantum dot pattern QD (e.g., fill only some spaces). In an embodiment, the filling insulating film 50 can fill all the space between the multiple quantum dots of the quantum dot pattern QD, or it can leave the space between the multiple quantum dots unfilled.

[0031] In an embodiment, the insulating film 50 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbide (SiCN), silicon oxycarbide (SiOCN), or combinations thereof.

[0032] In one implementation, air spacers 40 may be included between the conductive patterns 20 to facilitate minimizing parasitic capacitance. In the process of covering the upper end of the air spacers 40, if the quantum dot pattern QD is omitted, the insulating filler 50 may penetrate into the air spacers 40, potentially narrowing their width. This could lead to a deterioration in the operating characteristics of the semiconductor device including the air spacers 40.

[0033] Semiconductor devices according to some embodiments can help minimize or completely prevent the penetration of the filling insulating film 50 (or any other undesirable element or material) into the air spacer 40 by including a quantum dot pattern QD covering or additionally sealing the upper end of the air spacer 40. For example, a semiconductor device can be provided in which parasitic capacitance between conductive patterns 20 is minimized and operating characteristics are improved. For example, undesirable narrowing of the air spacer 40 can be reduced and / or prevented by including a quantum dot pattern QD that blocks or seals the open upper end of the air spacer 40.

[0034] Figure 3 A layout diagram of a semiconductor device according to some embodiments is shown. Figure 4 It shows along Figure 3 A sectional view taken by line A-A'. Figures 5 to 8 It shows Figure 4 Various magnified views of region R. Figure 9 It shows along Figure 3 The sectional view taken by line B-B'. Figure 10 It shows along Figure 3 The cross-sectional view taken along line C-C'. For ease of description, the description may be brief or omitted. Figure 1 and Figure 2 The repeated part of the description.

[0035] Reference Figures 3 to 9 According to some embodiments, a semiconductor device may include a substrate 110, an element separation film 120, an insulating pattern 130, a bit line structure 140, a direct contact DC, a spacer structure 150, a quantum dot pattern QD, a filling insulating film 180, a contact structure CS, a word line structure 160, and a capacitor 190.

[0036] Substrate 110 can be with Figure 1 The substrate 10 corresponds to this. The substrate 110 may include an active region AR. As the design specifications of semiconductor devices decrease, the active region AR can be formed in the form of diagonal stripes. For example, as... Figure 3 As shown, in a plane in which the first direction X and the second direction Y extend, the active region AR can be formed in the form of a strip extending in any direction other than the first direction X and the second direction Y.

[0037] The active region AR can be in the form of multiple strips extending in directions parallel to each other. In an implementation, the center of one active region AR can be adjacent to the end portion of another active region AR.

[0038] The active region AR may include impurities and can be used as both a source and a drain region. In one embodiment, the center of the active region AR can be connected to the bit line structure 140 via a direct contact DC, and both ends of the active region AR can be connected to the capacitor 190 via a contact structure CS.

[0039] The element separation membrane 120 can define multiple active regions AR. In an embodiment, such as Figure 4 , Figure 9 and Figure 10 As shown, the sidewalls of the element separation membrane 120 may have a slope, but this is only a process feature and the sidewalls may not have a slope.

[0040] In an embodiment, the component separation membrane 120 may include, for example, an oxide membrane, a nitride membrane, or a combination thereof. The component separation membrane 120 may be a single-layer membrane made of one type of insulating material, or it may be a multilayer membrane made of a combination of various types of insulating materials.

[0041] Insulating pattern 130 may be located on substrate 110 and component separation membrane 120. Insulating pattern 130 may extend along the upper surface of substrate 110 and upper surface of component separation membrane 120 in areas where direct contacts DC and buried contacts BC are not formed.

[0042] In an embodiment, the insulating pattern 130 may be a single-layer film or, as shown, a multilayer film comprising a first insulating film 131, a second insulating film 132, and a third insulating film 133. The first insulating film 131 may include, for example, silicon oxide. The second insulating film 132 may include a material having etch selectivity relative to the first insulating film 131. For example, the second insulating film 132 may include silicon nitride. The third insulating film 133 may include a material having a dielectric constant smaller than that of the second insulating film 132. For example, the third insulating film 133 may include silicon oxide.

[0043] In an embodiment, the width of the third insulating film 133 may be substantially the same as the width of the bit line structure 140 (e.g., the width along the first direction X). In this specification, the term "same" means not only identical things, but also minor differences that may occur due to process allowances, etc.

[0044] Bit line structure 140 may be located on substrate 110, element separation film 120, and insulating pattern 130. Bit line structure 140 may extend longitudinally along a second direction Y across active region AR and word line structure 160. For example, bit line structure 140 may obliquely intersect active region AR and perpendicularly intersect word line structure 160. Multiple bit line structures 140 may extend parallel to each other. In embodiments, multiple bit line structures 140 may be spaced apart from each other with equal spacing.

[0045] Bit line structure 140 may include first conductive patterns 141, 142 and 143 and a first cap pattern 144 sequentially stacked on substrate 110.

[0046] The first conductive patterns 141, 142, and 143 can be connected with Figure 1 Some of the multiple conductive patterns 20 correspond to each other. For example, the first conductive patterns 141, 142 and 143 may be spaced apart from other conductive patterns (e.g., the second conductive patterns BC and LP) by air spacers 150A.

[0047] In embodiments, the first conductive patterns 141, 142, and 143 may be single-layer films, or they may be multilayer films including a first conductive film 141, a second conductive film 142, and a third conductive film 143, as shown. The first conductive film 141, the second conductive film 142, and the third conductive film 143 may include, for example, polycrystalline silicon, TiN, TiSiN, tungsten, tungsten silicide, or combinations thereof. In embodiments, the first conductive film 141 may include, for example, polycrystalline silicon, the second conductive film 142 may include, for example, TiSiN, and the third conductive film 143 may include, for example, tungsten.

[0048] The first cover pattern 144 may be located on the first conductive patterns 141, 142, and 143. In an embodiment, the first cover pattern 144 may include, for example, silicon nitride.

[0049] A direct contact DC can penetrate the insulating pattern 130 to connect the active region AR of the substrate 110 to the bit line structure 140. For example, the substrate 110 may include a first trench T1 in the active region AR. The first trench T1 can penetrate the insulating pattern 130 to expose a portion of the active region AR. The direct contact DC can be located in the first trench T1 to connect the active region AR of the substrate 110 to the first conductive patterns 141, 142, and 143.

[0050] In the implementation method, such as Figure 3 As shown, the first trench T1 can expose the center of the active region AR. For example, the direct contact DC can be connected to the center of the active region AR. A portion of the first trench T1 can be superimposed on a portion of the element separation membrane 120. For example, the first trench T1 can expose not only a portion of the substrate 110 but also a portion of the element separation membrane 120.

[0051] The direct contact DC may include a conductive material. For example, the first conductive patterns 141, 142, and 143 of the bit line structure 140 may be electrically connected to the active region AR of the substrate 110. The active region AR of the substrate 110 connected to the direct contact DC can be used as a source region and a drain region.

[0052] In one embodiment, the direct contact DC may include the same material as the first conductive film 141. In another embodiment, the direct contact DC may include polycrystalline silicon. In yet another embodiment, depending on the manufacturing process, the direct contact DC may include a material different from the material of the first conductive film 141.

[0053] The spacer structure 150 may extend along the sidewall of the bit line structure 140. For example, the spacer structure 150 may extend longitudinally in the second direction Y.

[0054] In one embodiment, a portion of the spacer structure 150 may be located within the first trench T1. For example, as... Figure 4 As shown, the lower portion of the spacer structure 150 may extend along the sidewall of the direct contact DC. The lower portion of the direct contact DC may fill a portion of the first trench T1, and the lower portion of the spacer structure 150 may fill another portion of the first trench T1. The spacer structure 150 may be located on the insulating pattern 130 in the area of ​​the bit line structure 140 where the direct contact DC is not formed.

[0055] The spacer structure 150 may include an air spacer 150A. The air spacer 150A can be connected with... Figure 1 The air spacer 40 corresponds to this. For example, the air spacer 150A may be located between two adjacent conductive patterns (e.g., first conductive patterns 141, 142, and 143 and second conductive patterns BC and LP). The air spacer 150A may have a dielectric constant smaller than that of silicon oxide, which can more effectively reduce the parasitic capacitance of the semiconductor device according to some embodiments.

[0056] In one embodiment, the spacer structure 150 may be a multilayer film composed of a combination of various types of insulating materials. In another embodiment, the spacer structure 150 may include a first spacer 151, a second spacer 152, and a third spacer 153.

[0057] The first spacer 151 may extend along a sidewall of the bit line structure 140. In an embodiment, the first spacer 151 may be located between the air spacer 150A and the bit line structure 140. For example, the first spacer 151 may define a side surface of the air spacer 150A. In an embodiment, such as Figure 4 As shown, the first spacer 151 can completely cover the sidewall of the bit line structure 140. In an embodiment, the first spacer 151 can only cover a portion of the sidewall of the bit line structure 140.

[0058] In one embodiment, a portion of the first spacer 151 may be located in the first groove T1. For example, the lower portion of the first spacer 151 may extend along the sidewall of the direct contact member DC and the contour of the first groove T1.

[0059] The second spacer 152 may be located on the first spacer 151. In an embodiment, the second spacer 152 may be located below the air spacer 150A (e.g., it may be located between the air spacer 150A and the substrate 110 in a third direction Z). For example, the second spacer 152 may define the bottom surface of the air spacer 150A.

[0060] In one embodiment, the second spacer 152 may fill the first trench T1. For example, the second spacer 152 may fill the area of ​​the first trench T1 remaining after the direct contact DC and the first spacer 151 have been filled.

[0061] The third spacer 153 may extend along the sidewall of the bit line structure 140. The third spacer 153 may be spaced apart from the first spacer 151 by an air spacer 150A. For example, the third spacer 153 may define the other side surface of the air spacer 150A.

[0062] In one embodiment, the third spacer 153 may extend along the sidewall of the contact structure CS. For example, the third spacer 153 may be located between the air spacer 150A and the contact structure CS.

[0063] The first to third spacers 151, 152, and 153 may include an insulating material. In embodiments, the first to third spacers 151, 152, and 153 may each independently include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), silicon oxycarbide nitride (SiOCN), or combinations thereof. The first to third spacers 151, 152, and 153 may include the same material as each other, or they may include different materials as each other.

[0064] In this embodiment, the first to third spacers 151, 152, and 153 may comprise materials resistant to wet etching processes. For example, the first to third spacers 151, 152, and 153 may comprise materials resistant to wet etching processes using hydrogen fluoride (or hydrofluoric acid, HF) or phosphoric acid (H3PO4). For ease of description, the first to third spacers 151, 152, and 153 will be described below as comprising silicon nitride.

[0065] In some embodiments, at least one of the first to third spacers 151, 152 and 153 may be omitted. For example, spacer structure 150 may include only air spacer 150A.

[0066] The quantum dot pattern QD can be located on the air spacer 150A. The quantum dot pattern QD can be with... Figure 1 The quantum dot pattern QD corresponds to this. For example, the quantum dot pattern QD can cover the upper end of the air spacer 150A. For example, the quantum dot pattern QD can define the upper surface or side surface of the air spacer 150A.

[0067] In an implementation, the size of the quantum dot pattern QD (e.g., the size of the quantum dots in the quantum dot pattern QD) can be larger than the width of the air spacer 150A. For example, as Figure 5 As shown, when the quantum dot is spherical, the diameter W1 of the quantum dot can be larger than the width W2 of the air spacer 150A.

[0068] In this embodiment, the width W2 of the air spacer 150A can be, for example, less than about 5 nm. In such a case, the size of the quantum dot can be 5 nm or larger.

[0069] The insulating filler 180 can be located on the quantum dot pattern QD. The insulating filler 180 can be coupled with... Figure 1 The filling insulating film 50 corresponds to this. For example, the filling insulating film 180 can cover the quantum dot pattern QD.

[0070] In one embodiment, the filled insulating film 180 can be formed, for example, by low-pressure chemical vapor deposition (LPCVD).

[0071] Reference Figure 6 The semiconductor device according to some embodiments may also include a cover insulating film 182.

[0072] The cover insulating film 182 may be located between the quantum dot pattern QD and the fill insulating film 180. In an embodiment, the cover insulating film 182 may extend along or cover the outer peripheral surface of the quantum dot pattern QD (e.g., on the surface of the outermost quantum dot of the quantum dot pattern QD).

[0073] In an embodiment, the insulating film 182 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbide (SiCN), silicon oxycarbide (SiOCN), or combinations thereof.

[0074] In one embodiment, the step coverage of the cover insulating film 182 may be superior to or greater than the step coverage of the fill insulating film 180. In another embodiment, the cover insulating film 182 may include silicon carbide (SiCN), and the fill insulating film 180 may include silicon nitride (SiN).

[0075] In one embodiment, the cover insulating film 182 can be formed, for example, by plasma-enhanced chemical vapor deposition (PECVD).

[0076] Reference Figure 7 In a semiconductor device according to some embodiments, the cover insulating film 182 may be a multilayer film.

[0077] For example, the cover insulating film 182 may include a first cover film 182a and a second cover film 182b sequentially stacked on the quantum dot pattern QD. In an embodiment, the first cover film 182a may extend along the outer peripheral surface of the quantum dot pattern QD, and the second cover film 182b may extend between the first cover film 182a and the fill insulating film 180.

[0078] In one embodiment, the step coverage of the first cover film 182a may be superior to or greater than the step coverage of the second cover film 182b. In another embodiment, the first cover film 182a and the second cover film 182b may comprise silicon carbide (SiCN), and the carbon (C) content of the first cover film 182a may be higher than the carbon (C) content of the second cover film 182b.

[0079] Reference Figure 8 In a semiconductor device according to some embodiments, a portion of the cover insulating film 182 may be located in the air spacer 150A.

[0080] For example, a portion of the cover insulating film 182 may further extend along the first spacer 151 and / or the third spacer 153.

[0081] In this embodiment, the thickness W3 of the cover insulating film 182 extending along the outer peripheral surface of the quantum dot pattern QD can be greater than the thickness W4 of the cover insulating film 182 in the air spacer 150A. This is likely because the quantum dot pattern QD covers the air spacer 150A. For example, during the process of forming the cover insulating film 182, the portion of the cover insulating film 182 that enters the air spacer 150A can be blocked by the quantum dot pattern QD.

[0082] Refer again Figure 4 The contact structure CS can be located on the substrate 110 and the element separation film 120. The contact structure CS can penetrate the insulating pattern 130 to connect the active region AR of the substrate 110 and the capacitor 190.

[0083] In one embodiment, the contact structure CS may be located on the sidewall of the bit line structure 140. The contact structure CS may be spaced apart from the bit line structure 140 (e.g., along the first direction X) by a spacer structure 150. For example, the spacer structure 150 may electrically insulate the bit line structure 140 from the contact structure CS.

[0084] The contact structure CS may include a second conductive pattern BC and LP. The second conductive pattern BC and LP may be coupled with... Figure 1Some of the multiple conductive patterns 20 correspond to each other. For example, the second conductive patterns BC and LP may be spaced apart from other conductive patterns (e.g., the first conductive patterns 141, 142, and 143) by air spacers 150A. The second conductive patterns BC and LP may include, for example, buried contacts BC and landing pads LP sequentially stacked on the substrate 110.

[0085] The buried contact element BC can be located on the substrate 110 among multiple bit line structures 140. For example, as Figure 3 As shown, the buried contact BC can be inserted into the region defined by the word line structure 160 and the bit line structure 140. In an embodiment, the buried contact BC can form a plurality of spaced-apart regions. In an embodiment, the upper surface of the buried contact BC can be lower than the upper surface of the bit line structure 140 (e.g., closer to the substrate 110 in the third direction Z than the upper surface of the bit line structure 140). For example, the distance from the substrate 110 to the upper surface of the buried contact BC in the third direction Z can be smaller than the distance from the substrate 110 to the upper surface of the bit line structure 140 in the third direction Z.

[0086] The buried contact BC can penetrate the insulating pattern 130 to connect the active region AR of the substrate 110 and the bonding pad LP. For example, the substrate 110 may include a second trench T2 in the active region AR. The second trench T2 can penetrate the insulating pattern 130 to expose a portion of the active region AR. The buried contact BC can be located in the second trench T2 to connect the active region AR of the substrate 110 to the bonding pad LP.

[0087] In an implementation, the second trench T2 can expose both ends of the active region AR. For example, as... Figure 3 As shown, the buried contact BC can be connected to both ends of the active region AR. A portion of the second trench T2 can be superimposed on a portion of the element separation membrane 120. For example, the second trench T2 can expose not only a portion of the substrate 110 but also a portion of the element separation membrane 120.

[0088] The buried contact BC may include a conductive material. For example, the buried contact BC may be electrically connected to the active region AR of the substrate 110. The active region AR of the substrate 110 connected to the buried contact BC may serve as both a source and a drain region. In some embodiments, the buried contact BC may include, for example, polysilicon.

[0089] The bonding pad LP may be located on the buried contact BC. For example, the bonding pad LP may be attached to the upper surface of the buried contact BC. In an embodiment, the upper surface of the bonding pad LP may be higher than the upper surface of the bit line structure 140 (e.g., farther from the substrate 110 in the third direction Z than the upper surface of the bit line structure 140). For example, the distance from the substrate 110 to the upper surface of the bonding pad LP in the third direction Z may be greater than the distance from the substrate 110 to the upper surface of the bit line structure 140 in the third direction Z. For example, the bonding pad LP may cover a portion of the upper surface of the bit line structure 140.

[0090] The bonding pad LP can form multiple spaced-apart regions. In an implementation, such as... Figure 3 As shown, each bonding pad LP can be, for example, circular. In an implementation, as... Figure 3 As shown, multiple bonding pads LP can be arranged, for example, in a honeycomb structure.

[0091] Multiple bonding pads LP can be individually connected to the buried contact BC that forms multiple separated areas. For example, the respective bonding pads LP can be separated by a third trench T3.

[0092] The bonding pad LP may include a conductive material. For example, capacitor 190 may be electrically connected to the active region AR of substrate 110. In embodiments, the bonding pad LP may include, for example, tungsten (W).

[0093] In one embodiment, a portion of the third trench T3 may expose a portion of the bit line structure 140. For example, the third trench T3 may extend from the upper surface of the bonding pad LP to the lower portion of the upper surface of the bit line structure 140. For example, multiple bonding pads LP may be separated from each other by the bit line structure 140 and the third trench T3. In one embodiment, the bottom surface of the third trench T3 may be higher than the bottom surface of the first cover pattern 144. For example, the third trench T3 may expose a portion of the first cover pattern 144.

[0094] The third groove T3 can be with Figure 1 The groove T corresponds to this. For example, the third groove T3 can expose a portion of the upper end of the air spacer 150A. In an embodiment, the third groove T3 can expose the upper surface of the first spacer 151 and the upper surface of the third spacer 153.

[0095] In one embodiment, the quantum dot pattern QD can fill at least a portion of the third trench T3. For example, the quantum dot pattern QD can fill the lower portion of the third trench T3. For example, the quantum dot pattern QD can cover the upper end of the air spacer 150A exposed by the third trench T3. Figure 4 As shown, the quantum dot pattern QD can be located between the first cover pattern 144 and the bonding pad LP. In an embodiment, as... Figure 9 and Figure 10 As shown, the quantum dot pattern QD can surround the periphery of the bonding pad LP.

[0096] In an embodiment, the uppermost portion of the quantum dot pattern QD (e.g., the portion of the quantum dot pattern QD furthest from the substrate 110) can be higher than the upper surface of the bit line structure 140 (e.g., the surface of the bit line structure 140 facing away from the substrate 110 in the third direction Z) (e.g., farther from the substrate 110 in the third direction Z than the upper surface of the bit line structure 140). For example, the distance from the substrate 110 to the uppermost portion of the quantum dot pattern QD in the third direction Z can be greater than the distance from the substrate 110 to the upper surface of the bit line structure 140 in the third direction Z. For example, as... Figure 9 and Figure 10 As shown, the height H1 from the bottom surface of the third trench T3 to the uppermost part of the quantum dot pattern QD in the third direction Z can be greater than the height H2 from the bottom surface of the third trench T3 to the upper surface of the line structure 140 in the third direction Z. For example, as Figure 10 As shown, the quantum dot pattern QD can also cover the side surface of the upper end of the air spacer 150A.

[0097] In one embodiment, the filling insulating film 180 may fill another portion of the third trench T3. For example, multiple bonding pads LP may be separated from each other by the bit line structure 140 and the filling insulating film 180. In one embodiment, the upper surface of the filling insulating film 180 may be higher than the upper surface of the bonding pads LP. In one embodiment, the filling insulating film 180 may expose at least a portion of the upper surface of the bonding pads LP.

[0098] Word line structure 160 may extend longitudinally along a first direction X, spanning the active region AR and bit line structure 140. For example, word line structure 160 may obliquely intersect the active region AR and perpendicularly intersect the bit line structure 140. Multiple word line structures 160 may extend parallel to each other. In an embodiment, multiple word line structures 160 may be spaced apart from each other with equal spacing.

[0099] The word line structure 160 may include a gate dielectric film 161, third conductive patterns 162 and 163, and a second cover pattern 164.

[0100] In an embodiment, the third conductive patterns 162 and 163 may be a single-layer film, or as shown, a multilayer film including a fourth conductive film 162 and a fifth conductive film 163. In an embodiment, the fourth conductive film 162 and the fifth conductive film 163 may respectively comprise, for example, metal, polycrystalline silicon, or combinations thereof.

[0101] The gate dielectric film 161 may be located between the third conductive patterns 162 and 163 and the substrate 110. The gate dielectric film 161 may comprise, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. Examples of high-k materials may include hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0102] The second cover pattern 164 may be located on the third conductive patterns 162 and 163. In an embodiment, the second cover pattern 164 may include, for example, silicon nitride.

[0103] In the implementation method, such as Figure 9 and Figure 10 As shown, the word line structure 160 can be buried in the substrate 110. For example, the substrate 110 can include a fourth trench T4 extending in the first direction X. The gate dielectric film 161 can extend along the contour of the fourth trench T4. Third conductive patterns 162 and 163 can fill a portion of the fourth trench T4 on the gate dielectric film 161, and a second capping pattern 164 can fill another portion of the fourth trench T4.

[0104] Capacitor 190 may be located on the filling insulating film 180 and the bonding pad LP. Capacitor 190 may be connected to the portion of the upper surface of the bonding pad LP that is exposed by the filling insulating film 180. As a result, capacitor 190 may be electrically connected to the source and drain regions connected to the buried contact BC. For example, capacitor 190 may store charge in a semiconductor memory device, etc.

[0105] For example, capacitor 190 may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. The capacitor dielectric film 192 may be located between the lower electrode 191 and the upper electrode 193. Capacitor 190 may use the potential difference generated between the lower electrode 191 and the upper electrode 193 to store charge in the capacitor dielectric film 192.

[0106] In one embodiment, the lower electrode 191 and the upper electrode 193 may comprise, for example, doped polysilicon, metal, or metal nitride. In another embodiment, the capacitor dielectric film 192 may comprise, for example, silicon oxide or a high-k material.

[0107] With the increasing integration of semiconductor devices, the impact of parasitic capacitance and leakage current may gradually increase. For example, as the spacing between bit line structures in DRAM (Dynamic Random Access Memory) becomes narrower, the parasitic capacitance between bit line structures and between bit line structures and contact structures may increase.

[0108] To minimize parasitic capacitance, an air spacer can be formed between the bit line structure and the contact structure. In a process where the cover extends along the sidewall of the bit line structure above the air spacer, the cover insulating film may penetrate into the air spacer, potentially narrowing its width. This can lead to deterioration of the operating characteristics of the semiconductor device that includes the air spacer.

[0109] According to some embodiments, a semiconductor device may use a quantum dot pattern QD covering the upper end of the air spacer 150A to help minimize the penetration of the cover insulating film 182 and / or the fill insulating film 180 into the air spacer 150A. For example, a semiconductor device can be provided in which parasitic capacitances between one bit line structure 140 and another bit line structure 140, and between the bit line structure 140 and the contact structure CS, are minimized, and operating characteristics are improved.

[0110] In the following text, reference will be made to Figures 1 to 24 Methods for manufacturing semiconductor devices according to some embodiments are described.

[0111] Figures 11 to 13 The stages in a method for manufacturing a semiconductor device according to some embodiments are illustrated. For ease of description, the above descriptions may be brief or omitted. Figures 1 to 10 The repeated part of the description.

[0112] Reference Figure 11 Multiple conductive patterns 20 and multiple cover patterns 30 can be formed on the substrate 10.

[0113] For example, a conductive film and an insulating film can be sequentially formed on the substrate 10. Subsequently, the conductive film and the insulating film can be patterned to form a plurality of conductive patterns 20 spaced apart from each other and a plurality of cap patterns 30 spaced apart from each other.

[0114] Additionally, air spacers 40 can be formed to separate the plurality of conductive patterns 20 from each other. For example, the air spacers 40 can be located between two adjacent conductive patterns 20.

[0115] Reference Figure 12 Grooves T can be formed in the cover pattern 30.

[0116] The groove T can be formed to expose the upper part or upper end of the air spacer 40. For example, the portion of the cover pattern 30 adjacent to the air spacer 40 can be etched to form the groove T.

[0117] Reference Figure 13 This can form quantum dot patterns (QD) that fill at least a portion of the trench T.

[0118] The quantum dot pattern QD can cover the upper end of the air spacer 40. In an embodiment, the size of the quantum dot pattern QD can be larger than the width of the air spacer 40. For example, the quantum dot pattern QD can cover the upper end of the air spacer 40 without filling it.

[0119] A quantum dot pattern (QD) may include multiple quantum dots. In embodiments, the quantum dot pattern (QD) may include, for example, silicon oxide quantum dots, silicon nitride quantum dots, polycrystalline silicon quantum dots, silicon-germanium quantum dots, or combinations thereof.

[0120] In embodiments, quantum dot patterns (QDs) can be formed, for example, by coating methods. For instance, quantum dots can be dispersed in a polymer, and the dispersed quantum dots in the polymer can be subjected to spin coating, screen printing, etc. For example, multiple quantum dots filling trenches T can be formed. In embodiments, quantum dots can be formed by coating a quantum dot colloid via self-assembly, for example, using dip coating or the Langmuir-Blodgett method, or by forming quantum dot nuclei using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0121] Subsequently, an etch-back process can be performed on the quantum dots. For example, a quantum dot pattern QD can be formed that fills at least a portion of the trench T.

[0122] Figures 14 to 24 The stages in a method for manufacturing a semiconductor device according to some embodiments are illustrated. For ease of description, the above descriptions may be brief or omitted. Figures 1 to 13 The repeated part of the description. Figures 14 to 24 It shows along Figure 3 A sectional view taken by line A-A'.

[0123] Reference Figure 14 A first insulating film to a third insulating film 131, 132 and 133, a first conductive film to a third conductive film 141, 142 and 143, a direct contact DC and a first cover pattern 144 can be formed on the substrate 110 and the component separation film 120.

[0124] For example, a first insulating film to a third insulating film 131, 132, and 133, and a first conductive film 141 may be sequentially formed on the substrate 110 and the element separation film 120. Subsequently, a first trench T1 (exposing a portion of the active region AR) may be formed in the substrate 110. In this embodiment, the first trench T1 may expose the center of the active region AR. A direct contact DC may then be formed to fill the first trench T1. Subsequently, a second conductive film 142 and a third conductive film 143, and a first cap pattern 144 may be formed on the first conductive film 141 and the direct contact DC.

[0125] Reference Figure 15 The first conductive film to the third conductive films 141, 142 and 143, the direct contact DC and the first cover pattern 144 can be patterned.

[0126] For example, a bit line structure 140 can be formed that extends longitudinally along the second direction Y across the active region AR and the word line structure 160. In an embodiment, the width of the bit line structure 140 and the width of the direct contact DC can be smaller than the width of the first trench T1 (e.g., along the first direction X). For example, the patterned direct contact DC may not completely fill the first trench T1.

[0127] In one embodiment, the third insulating film 133 may also be patterned. The third insulating film 133 may be patterned to have the same width as the bit line structure 140 (e.g., along the first direction X).

[0128] Reference Figure 16 , can Figure 15 A first spacer 151 and a second spacer 152 are formed on the product.

[0129] In one embodiment, the first spacer 151 may be formed conformally. As a result, the first spacer 151 may extend along the contour of the sidewalls and top surface of the bit line structure 140, the sidewalls of the direct contact DC, the top surface of the second insulating film 132, and the first trench T1.

[0130] A second spacer 152 can be formed on the first spacer 151. In an embodiment, the second spacer 152 can fill the unfilled area of ​​the first trench T1 after the direct contact DC and the first spacer 151 have been filled. For example, a first spacer film can be formed on the first spacer 151. Subsequently, the first spacer 151 can be used as an etch stop film to etch a portion of the first spacer film. For example, a second spacer 152 can be formed to fill the first trench T1.

[0131] Reference Figure 17 Sacrificial spacers 154 and third spacers 153 may be formed on the sidewalls of bit line structure 140 (e.g., sacrificial spacers 154 and third spacers 153 are formed to form an initial spacer structure).

[0132] Sacrificial spacer 154 and third spacer 153 may extend along the sidewall of bit line structure 140. For example, a second spacer film and a third spacer film may be formed sequentially stacked on the first spacer 151 and the second spacer 152. Subsequently, the first spacer 151 and the second spacer 152 may be used as etch stop films to etch a portion of the second spacer film and a portion of the third spacer film. For example, sacrificial spacer 154 and third spacer 153 may be formed on the first spacer 151 and the second spacer 152.

[0133] In one embodiment, the sacrificial spacer 154 may include a material that is etch-selective for the materials of the first to third spacers 151, 152, and 153. For example, the first to third spacers 151, 152, and 153 may include silicon nitride, and the sacrificial spacer 154 may include silicon oxide.

[0134] Reference Figure 18 A second trench T2 is formed in the substrate 110.

[0135] The second trench T2 can penetrate the insulating pattern 130 to expose a portion of the active region AR. For example, the insulating pattern 130 located between bit line structures 140 can be etched to form the second trench T2. In an embodiment, the second trench T2 can expose both ends of the active region AR.

[0136] Reference Figure 19 The contact structure CS can be formed in the second groove T2.

[0137] For example, it can be Figure 18 A polycrystalline silicon film is formed on the product. Next, an etching process can be performed so that the upper surface of the polycrystalline silicon film becomes lower than the upper surface of the initial spacer structure (e.g., first spacer 151, second spacer 152, third spacer 153, and sacrificial spacer 154) (e.g., closer to the substrate 110 in the third direction Z). For example, buried contacts BC can be formed, which form multiple separating regions.

[0138] Next, a bonding pad LP can be formed on the buried contact BC. In an embodiment, the upper surface of the bonding pad LP may be higher than the upper surface of the initial spacer structure (e.g., farther from the substrate 110 in the third direction Z than the upper surface of the initial spacer structure). In an embodiment, the bonding pad LP may include, for example, tungsten (W).

[0139] Reference Figure 20 A third groove T3 can be formed in the bonding pad LP.

[0140] For example, the bonding pad LP can be patterned using a third groove T3. The bonding pad LP can be formed to create multiple partitioned regions. In one embodiment, the third groove T3 can be formed such that the multiple bonding pads LP can be arranged in a honeycomb structure.

[0141] In one embodiment, the third trench T3 may be formed to overlap with the bit line structure 140 and the initial spacer structure. For example, the upper portion of the sacrificial spacer 154 may be exposed by the third trench T3.

[0142] Reference Figure 21 The sacrificial spacer 154 can be removed to form an air spacer 150A.

[0143] For example, after the third trench T3 is formed, a wet etching process can be performed. In an embodiment, the wet etching process may use, for example, hydrogen fluoride (HF) or phosphoric acid (H3PO4). For example, the sacrificial spacer 154 exposed by the third trench T3 can be removed, and an air spacer 150A defined by the first spacer to the third spacers 151, 152 and 153 can be formed.

[0144] Reference Figure 22 This allows the quantum dot pattern QD to fill at least a portion of the third trench T3.

[0145] The quantum dot pattern QD can cover the upper end of the air spacer 150A. In an embodiment, the size of the quantum dot pattern QD can be larger than the width of the air spacer 150A. For example, the quantum dot pattern QD can cover the upper part of the air spacer 150A, for example, blocking the opening at the upper end of the air spacer 150A without filling the air spacer 150A.

[0146] The formation of quantum dot patterns can be combined with the above-mentioned methods. Figure 13 The formation of the quantum dot patterns described is similar, and a detailed description of their repetition will not be provided.

[0147] Reference Figure 23 A filling insulating film 180 can be formed on a quantum dot pattern (QD).

[0148] The filling insulating film 180 can cover the quantum dot pattern QD. In embodiments, the filling insulating film 180 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), silicon oxycarbide nitride (SiOCN), or combinations thereof.

[0149] In one embodiment, the filled insulating film 180 can be formed, for example, by low-pressure chemical vapor deposition (LPCVD).

[0150] Reference Figure 24 The filling insulating film 180 can be patterned to expose a portion of the upper surface of the bonding pad LP.

[0151] Subsequently, referring to Figure 4 A capacitor 190 can be formed on the filling insulating film 180 and the bonding pad LP. For example, the capacitor 190 can be attached to the portion of the upper surface of the bonding pad LP that is exposed by the filling insulating film 180.

[0152] Through summarization and review, it is evident that with the increasing integration of semiconductor devices, the impact of parasitic capacitance and leakage current may gradually increase. Parasitic capacitance and leakage current can degrade the operating characteristics of semiconductor devices.

[0153] One or more embodiments may provide a semiconductor device including an air spacer.

[0154] One or more embodiments may provide a semiconductor device that minimizes parasitic capacitance and leakage current.

[0155] One or more embodiments may provide a semiconductor device with improved operating characteristics.

[0156] One or more embodiments may provide a method for manufacturing a semiconductor device with improved operating characteristics.

[0157] Example embodiments have been disclosed herein. Although specific terminology has been used, the terminology will be used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device comprising: a substrate; a first conductive pattern on the substrate; a second conductive pattern on the substrate and spaced apart from the first conductive pattern; an air spacer between the first conductive pattern and the second conductive pattern; and a quantum dot pattern covering an upper portion of the air spacer, wherein a size of the quantum dot pattern is larger than a width of the air spacer.

2. The semiconductor device as claimed in claim 1, wherein: the quantum dot pattern includes a plurality of quantum dots, and a size of the quantum dots is larger than the width of the air spacer.

3. The semiconductor device as claimed in claim 1, further comprising a cap pattern on the first conductive pattern and the second conductive pattern, the cap pattern including a trench open to the upper portion of the air spacer, the quantum dot pattern filling at least a portion of the trench. wherein 4. The semiconductor device as claimed in claim 1, further comprising a fill insulating film covering the quantum dot pattern.

5. The semiconductor device as claimed in claim 4, further comprising a cap insulating film between the quantum dot pattern and the fill insulating film, a step coverage of the cap insulating film being larger than a step coverage of the fill insulating film. wherein 6. The semiconductor device as claimed in claim 5, wherein: the cap insulating film includes silicon carbon nitride, and the fill insulating film includes silicon nitride.

7. The semiconductor device as claimed in claim 5, wherein: the cap insulating film includes: a first cap film directly on a peripheral surface of the quantum dot pattern; and a second cap film between the first cap film and the fill insulating film, and a step coverage of the first cap film is larger than a step coverage of the second cap film.

8. The semiconductor device as claimed in claim 1, further comprising: a first spacer between the first conductive pattern and the air spacer; and a second spacer between the second conductive pattern and the air spacer. the quantum dot pattern includes silicon oxide quantum dots, silicon nitride quantum dots, polysilicon quantum dots, silicon germanium quantum dots, or a combination thereof.

10. A semiconductor device comprising:

9. The semiconductor device as claimed in claim 1, wherein, a substrate including an active region; a bit line structure on the substrate and crossing the active region; an air spacer extending along a sidewall of the bit line structure; and a quantum dot pattern covering an upper portion of the air spacer, wherein a size of the quantum dot pattern is larger than a width of the air spacer. the width of the air spacer is less than 5 nm. an uppermost portion of the quantum dot pattern is higher than an upper surface of the bit line structure.

13. The semiconductor device as claimed in claim 10, further comprising a contact structure connected to the active region and spaced apart from the bit line structure by an air spacer between the contact structure and the bit line structure.

11. The semiconductor device as claimed in claim 10, wherein, 14. The semiconductor device as claimed in claim 13, wherein:

12. The semiconductor device as claimed in claim 10, wherein, the contact structure includes a buried contact and a bond pad sequentially stacked on the active region, an upper surface of the buried contact is lower than the upper surface of the bit line structure, and an upper surface of the bond pad is higher than the upper surface of the bit line structure.

15. The semiconductor device as claimed in claim 13, further comprising a capacitor on the contact structure, ​ ​ ​ wherein The capacitor includes a lower electrode connected to an upper surface of the contact structure, an upper electrode on the lower electrode, and a capacitor dielectric film between the lower electrode and the upper electrode.

16. The semiconductor device of claim 10, further comprising a direct contact connecting the active region to the bit line structure. wherein: the substrate includes a trench in the active region, and the direct contact is in the trench.

17. The semiconductor device of claim 16, further comprising: a contact structure connected to the active region and spaced apart from the bit line structure by an air spacer between the contact structure and the bit line structure; a first spacer extending along sidewalls of the bit line structure, sidewalls of the direct contact, and sidewalls of the trench; a second spacer on the first spacer and filling the trench; and a third spacer extending along sidewalls of the contact structure, wherein the quantum dot pattern, the first spacer, the second spacer, and the third spacer define the air spacer.

18. A semiconductor device, comprising: a substrate; a first conductive pattern on the substrate; an air spacer extending along sidewalls of the first conductive pattern; a cap pattern on the first conductive pattern, the cap pattern including a trench open to an upper portion of the air spacer; and a quantum dot pattern filling at least a portion of the trench, wherein a size of the quantum dot pattern is larger than a width of the air spacer.

19. The semiconductor device of claim 18, further comprising a second conductive pattern on the substrate and spaced apart from the first conductive pattern by an air spacer between the first conductive pattern and the second conductive pattern.

20. The semiconductor device of claim 18, further comprising a fill insulating film on the quantum dot pattern and filling a remaining portion of the trench. ​ ​

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