Three-dimensional semiconductor storage devices

Abstract

A three-dimensional semiconductor memory device is provided. The three-dimensional semiconductor memory device includes a stacked structure including a gate electrode on a substrate. The three-dimensional semiconductor memory device includes a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure arranged sequentially in a zigzag shape along a first direction, penetrating the stacked structure. Furthermore, the three-dimensional semiconductor memory device includes a first first line extending in the first direction. The first first line perpendicularly overlaps the second and fourth vertical structures. The centers of the second and fourth vertical structures are spaced apart from the first first line by the same distance. The first vertical structure is spaced apart from the first first line by a first distance. The third vertical structure is spaced apart from the first first line by a second distance.

Description

Technical Field

[0001] The present invention relates to semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices. Background Technology

[0002] Semiconductor devices have become highly integrated to meet customer demands for high performance and low manufacturing costs. Because the integration level of semiconductor devices can be a significant factor in determining product price, there is an increasing need for high integration. The integration level of a typical two-dimensional or planar semiconductor device is primarily determined by the area occupied by a single memory cell, making it highly susceptible to the technological level used to form intricate patterns. However, the extremely expensive process equipment used to increase pattern precision sets a practical limit to increasing the integration level of two-dimensional or planar semiconductor devices.

[0003] To overcome these limitations, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. However, for the mass production of three-dimensional semiconductor memory devices, it is desirable to develop new process technologies that can provide a lower per-unit manufacturing cost than two-dimensional semiconductor devices while maintaining or exceeding their reliability levels. Summary of the Invention

[0004] Some exemplary embodiments of the present invention provide semiconductor memory devices with improved reliability.

[0005] The purpose of this invention is not limited to the above-mentioned contents, and those skilled in the art will clearly understand from the following description other purposes not mentioned above.

[0006] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include a stacked structure on a substrate and including a plurality of gate electrodes on the substrate. The three-dimensional semiconductor memory device may include a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure arranged sequentially in a zigzag shape along a first direction, penetrating the stacked structure. Furthermore, the three-dimensional semiconductor memory device may include a first first line extending in the first direction. The first first line may vertically overlap the second and fourth vertical structures. The centers of the second and fourth vertical structures may be spaced apart from the first first line by the same distance. The first vertical structure may be spaced apart from the first first line by a first distance. The third vertical structure may be spaced apart from the first first line by a second distance. The first distance may be greater than the second distance.

[0007] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include a stacked structure comprising a plurality of gate electrodes sequentially stacked on a substrate. The three-dimensional semiconductor memory device may include a first vertical structure, a second vertical structure, a third vertical structure, a fourth vertical structure, and a fifth vertical structure arranged in a zigzag shape along a first direction, penetrating the stacked structure. Furthermore, the three-dimensional semiconductor memory device may include a plurality of bit lines extending on the stacked structure in the first direction. A first minimum distance between the first vertical structure and the second vertical structure may be greater than a second minimum distance between the second vertical structure and the third vertical structure.

[0008] According to some exemplary embodiments conceived in this invention, a three-dimensional semiconductor memory device may include a stacked structure on a substrate, including a first string of select lines and a second string of select lines spaced apart in a first direction on the substrate. The three-dimensional semiconductor memory device may include a plurality of first vertical structures and a plurality of second vertical structures penetrating the first and second string of select lines. The first vertical structures may be spaced apart from the second vertical structures in the first direction. The three-dimensional semiconductor memory device may include a plurality of third vertical structures penetrating the first and second string of select lines. The third vertical structures may be spaced apart from lines passing through the centers of the first and second vertical structures at a first distance. Furthermore, the three-dimensional semiconductor memory device may include a first first line extending across the stacked structure. The first first line may connect one of the plurality of third vertical structures penetrating the first string of select lines to one of the plurality of second vertical structures penetrating the second string of select lines. Attached Figure Description

[0009] Figure 1 A simplified circuit diagram of a cell array of a three-dimensional semiconductor memory device, illustrating some exemplary embodiments of a concept according to the present invention, is shown.

[0010] Figure 2 A top view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention.

[0011] Figure 3 The display shows Figure 2 A magnified view of part A.

[0012] Figure 4 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0013] Figure 5 The display shows Figure 4 A magnified view of part B.

[0014] Figure 6 The display shows Figure 3 An enlarged top view of the vertical structure.

[0015] Figure 7 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0016] Figure 8 The display shows Figure 2 A magnified view of part A.

[0017] Figure 9 The display shows Figure 8 An enlarged top view of the vertical structure.

[0018] Figure 10 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0019] Figure 11 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0020] Figure 12 A top view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention.

[0021] Figure 13 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 12 The sectional view taken from line II-II'.

[0022] Figure 14 A cross-sectional view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention.

[0023] Figures 15A to 15C The diagram illustrates a method for manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the concept of the present invention. Figure 3 A sectional view taken by line I-I'. Detailed Implementation

[0024] Figure 1 A simplified circuit diagram of a cell array of a three-dimensional semiconductor memory device, illustrating some exemplary embodiments of the concept according to the present invention, is shown.

[0025] Reference Figure 1A three-dimensional semiconductor memory device may include a common source line CSL, multiple bit lines BL0 to BL2, and multiple cell strings CSTRs between the common source line CSL and the bit lines BL0 to BL2.

[0026] Bit lines BL0 to BL2 can be arranged in two dimensions, and multiple cell strings CSTRs can be connected in parallel to each of the bit lines BL0 to BL2. Therefore, cell strings CSTRs can be arranged in two dimensions on the common source line CSL or on the substrate.

[0027] Each cell string CSTR may include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to one of the bit lines BL0 to BL2, and a plurality of memory cell transistors MCTs disposed between the ground select transistor GST and the string select transistor SST. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCTs may be connected in series. In addition, the ground select line GSL, a plurality of word lines WL0, WL1, WL2, and WL3, and a plurality of string select lines SSL0, SSL1, and SSL2 may be used as the gate electrode of the ground select transistor GST, the gate electrode of the memory cell transistor MCT, and the gate electrode of the string select transistor SST, respectively, and these lines GSL, WL0 to WL3, and SSL0 to SSL2 are disposed between the common source line CSL and the bit lines BL0 to BL2.

[0028] Figure 2 A top view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention.

[0029] Reference Figure 2 Multiple stacked structures ST can be set on substrate 100 ( Figure 4 The stacked structure ST can be spaced apart in the first direction X. The substrate 100 can be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The substrate 100 can include a cell array region CAR and a pad region PR. The stacked structure ST can extend from the cell array region CAR of the substrate 100 toward the pad region PR along a second direction Y intersecting the first direction X. The stacked structure ST has ends forming a stepped structure STS on the pad region PR of the substrate 100. The stacked structure ST can include a plurality of gate electrodes 120a, 120b, 120c_1, and 120c_2, all of which have their ends disposed on the pad region PR of the substrate 100. The gate electrodes 120a, 120b, 120c_1, and 120c_2 can have their lengths in the second direction Y that decrease with increasing distance from the substrate 100. Therefore, the ends of the gate electrodes 120a, 120b, 120c_1 and 120c_2 can be exposed on the pad region PR of the substrate 100.

[0030] The contact plug CP can be disposed on the stepped structure STS on the pad region PR of the stacked structure ST. For example, the contact plug CP can be disposed at the ends corresponding to the gate electrodes 120a, 120b, 120c_1 and 120c_.

[0031] Figure 3 The display shows Figure 2 A magnified view of part A. Figure 4 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'. Figure 5 The display shows Figure 4 A magnified view of part B. Figure 6 The display shows Figure 3 An enlarged top view of the vertical structure.

[0032] Reference Figure 3 and Figure 4 Each of the stacked structure ST may include gate electrodes 120a, 120b, 120c_1, and 120c_2, a buffer dielectric layer 101, and a dielectric pattern 110. Gate electrodes 120a, 120b, 120c_1, and 120c_2 may include a ground-select gate electrode 120a, a unit gate electrode 120b, and string-select gate electrodes 120c_1 and 120c_2. The ground-select gate electrode 120a may be the lowermost gate electrode among gate electrodes 120a, 120b, 120c_1, and 120c_2, and each of the string-select gate electrodes 120c_1 and 120c_2 may be the uppermost gate electrode among gate electrodes 120a, 120b, 120c_1, and 120c_2. The unit gate electrode 120b may be located between the ground-select gate electrode 120a and the string-select gate electrodes 120c_1 and 120c_2. The string selection gate electrodes 120c_1 and 120c_2 may include a first string selection gate electrode 120c_1 and a second string selection gate electrode 120c_2. The first string selection gate electrode 120c_1 and the second string selection gate electrode 120c_2 may be spaced apart in a first direction X on the uppermost unit gate electrode 120b. The first string selection gate electrode 120c_1 and the second string selection gate electrode 120c_2 may be electrically / physically separated from each other. The ground selection gate electrode 120a may correspond to... Figure 1 The ground selection line GSL discussed in the text, the unit gate electrode 120b can correspond to Figure 1 The word lines WL0 to WL3 discussed in the text, the first string selection gate electrode 120c_1 and the second string selection gate electrode 120c_2 can correspond to Figure 1The series select lines SSL0 to SSL2 are discussed in the text. The gate electrodes 120a, 120b, 120c_1, and 120c_2 may include semiconductor materials (e.g., polycrystalline silicon), metallic materials (e.g., tungsten), and / or metal nitride materials (e.g., titanium nitride, tantalum nitride, or tungsten nitride).

[0033] A buffer dielectric layer 101 may be disposed between the substrate 100 and the ground select gate electrode 120a. The buffer dielectric layer 101 may include, for example, a silicon oxide layer or a thermal oxide layer. A dielectric pattern 110 may be disposed between gate electrodes 120a, 120b, 120c_1, and 120c_2 that are adjacent to each other in a third direction Z perpendicular to the top surface of the substrate 100. The uppermost dielectric pattern in the dielectric pattern 110 may be disposed on the first string of select gate electrodes 120c_1 and the second string of select gate electrodes 120c_2. The dielectric pattern 110 may include, for example, a silicon oxide layer.

[0034] A separator pattern SEP can be disposed on the upper part of the stacked structure ST between the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2. The separator pattern SEP can extend in a second direction Y between the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2. The separator pattern SEP can penetrate the uppermost dielectric pattern 110 and can be disposed on the top surface of the dielectric pattern 110 between the uppermost cell gate electrode 120b and the string select gate electrodes 120c_1 and 120c_2. The separator pattern SEP may include, for example, a silicon oxide layer.

[0035] Multiple vertical structures VS can penetrate the stacked structure ST. For example, the vertical structures VS can penetrate the unit gate electrode 120b, the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2, and the dielectric pattern 110. The vertical structures VS can be arranged in a zigzag shape along the first direction X. Each of the vertical structures VS may include a charge storage structure SL, a vertical channel VC, a gap filling layer 130, and a pad P. The vertical channel VC may have a hollow tube shape, a cylindrical shape, or a cup shape. The vertical channel VC may include a single layer or multiple layers. The vertical channel VC may include one or more of, for example, a monocrystalline silicon layer, a polycrystalline silicon layer, an organic semiconductor layer, and a carbon nanostructure.

[0036] The charge storage structure SL can surround the vertical channel VC. (See reference...) Figure 5The charge storage structure SL may include a tunnel dielectric layer TL, a charge storage layer TBL, and a barrier dielectric layer BKL. The barrier dielectric layer BKL may be disposed between the vertical channel VC and the unit gate electrode 120b, and between the vertical channel VC and the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2, extending in the Z-direction. The barrier dielectric layer BKL may include, for example, a silicon oxide layer or a high-k dielectric layer (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The tunnel dielectric layer TL may be disposed between the barrier dielectric layer BKL and the vertical channel VC, extending in the Z-direction. The tunnel dielectric layer TL may include, for example, a silicon oxide layer or a silicon nitride layer or a high-k dielectric layer (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage layer TBL may be disposed between the barrier dielectric layer BKL and the tunnel dielectric layer TL, extending in the Z-direction. The charge storage layer (TBL) may include, for example, a silicon nitride layer.

[0037] An interstitial filling layer 130 may be disposed within the internal space surrounded by the vertical channel VC. The interstitial filling layer 130 may include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxide nitride layer. A pad P may be disposed on the upper portion of each of the vertical channel VC, the charge storage structure SL, and the interstitial filling layer 130. The pad P may comprise a conductive material or a semiconductor material, said semiconductor material being doped with impurities whose conductivity type differs from that of the vertical channel VC. A semiconductor pillar SP may be disposed between the vertical channel VC and the substrate 100. The semiconductor pillar SP may be disposed on the substrate.

[0038] The following section will primarily describe the planar layout of the vertical structures (or the first to fifth vertical structures).

[0039] Reference Figure 3 and Figure 6In some embodiments, the vertical structure VS may include a first vertical structure VS1, a second vertical structure VS2, a third vertical structure VS3, a fourth vertical structure VS4, and a fifth vertical structure VS5. The first vertical structures VS1 through VS5 may penetrate the stacked structure ST. The first vertical structures VS1 through VS5 are located on the top surface of the substrate 100 and may penetrate to select the gate electrode 120a. The semiconductor pillars SP and the vertical channel VC may be in contact with each other. The semiconductor pillars SP may be intrinsic semiconductors or semiconductors having the same conductivity type as the substrate 100. The five vertical structures VS5 may be arranged sequentially in a zigzag pattern along the first direction X. The first vertical structure VS1 may be arranged in the second direction Y. The second vertical structure VS2 may be arranged in the second direction Y. The third vertical structure VS3 may be arranged in the second direction Y. The fourth vertical structure VS4 may be arranged in the second direction Y. The fifth vertical structure VS5 may be arranged in the second direction Y.

[0040] The second vertical structure VS2 and the fourth vertical structure VS4, spaced apart in the first direction X, can be vertically overlapped and electrically connected to the first line BL1 of the fourth vertical structure VS4. The second vertical structure VS2 and the fourth vertical structure VS4 can have their centers G spaced apart from the first line BL1 by the same distance L0. The first vertical structure VS1 can be spaced apart from the first line BL1 by a first distance L1 in the second direction Y. The third vertical structure VS3 can be spaced apart from the first line BL1 by a second distance L2 in the second direction Y. The fifth vertical structure VS5 can be spaced apart from the first line BL1 by a first distance L1 in the second direction Y. The first distance L1 can be different from the second distance L2. For example, the first distance L1 can be greater than the second distance L2. The first vertical structure VS1 and the fifth vertical structure VS5, penetrating the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2, can be positioned facing each other in the first direction X. For example, each of the first vertical structures VS1 and the fifth vertical structure VS5 adjacent in the first direction X may have its center G set on the first reference line RL1, and each of the third vertical structures VS3 may have its center G spaced apart from the first reference line RL1.

[0041] The first minimum (i.e., shortest) distance D1 between adjacent second vertical structures VS2 and third vertical structures VS3 can be less than the second minimum distance D2 between adjacent first vertical structures VS1 and second vertical structures VS2. The third minimum distance D3 between adjacent third vertical structures VS3 and fourth vertical structures VS4 can be less than the fourth minimum distance D4 between adjacent fourth vertical structures VS4 and fifth vertical structures VS5. The first minimum distance D1 can be substantially the same as the third minimum distance D3 (i.e., substantially equal), and the second minimum distance D2 can be substantially the same as the fourth minimum distance D4.

[0042] In some embodiments, adjacent first vertical structures VS1, second vertical structures VS2, and third vertical structures VS3 can be arranged in a triangular shape or an inverted triangular shape. For example, adjacent first vertical structures VS1, second vertical structures VS2, and third vertical structures VS3 can be configured as (i.e., can be collectively defined) an scalene triangle shape or an inverted scalene triangle shape. Adjacent third vertical structures VS3, fourth vertical structures VS4, and fifth vertical structures VS5 can be arranged in a triangular shape or an inverted triangular shape. For example, adjacent third vertical structures VS3, fourth vertical structures VS4, and fifth vertical structures VS5 can be configured as an scalene triangle shape or an inverted scalene triangle shape. Adjacent second vertical structures VS2, third vertical structures VS3, and fourth vertical structures VS4 can be arranged in a triangular shape or an inverted triangular shape. For example, adjacent second vertical structures VS2, third vertical structures VS3, and fourth vertical structures VS4 can be configured as an isosceles triangle shape or an inverted isosceles triangle shape.

[0043] The dummy vertical structure (DVS) can penetrate the separator pattern (SEP) and the stacked structure (ST). The dummy vertical structure (DVS) can be arranged (e.g., aligned) along the separator pattern (SEP) in the second direction Y. The dummy vertical structure (DVS) can be disposed between the fourth vertical structure (VS4) penetrating the first string select gate electrode 120c_1 and the second vertical structure (VS2) penetrating the second string select gate electrode 120c_2. The dummy vertical structure (DVS) can have the same stacked structure as the stacked structure of the layers included in each of the vertical structures (VS). For example, each of the dummy vertical structure (DVS) can include a dummy vertical channel, a dummy charge storage structure surrounding the dummy vertical channel, a dummy gap filling layer in the internal space surrounded by the dummy vertical channel, and a dummy pad. Furthermore, dummy semiconductor pillars can be disposed between the dummy vertical structure and the substrate 100.

[0044] Return to reference Figure 4The first interlayer dielectric layer ILD1 can be disposed on the stacked structure ST. The first interlayer dielectric layer ILD1 can cover the top surface of the uppermost dielectric pattern 110 and the top surface of the separator pattern SEP. The first interlayer dielectric layer ILD1 may include, for example, a silicon oxide layer.

[0045] A common source region (CSR) can be disposed in the substrate 100 between the stacked structures ST. The common source region CSR can extend in the second direction Y. The common source region CSR can have a different conductivity type than that of the substrate 100. A common source contact structure (CSP) can be disposed on the substrate 100 between the stacked structures ST. The common source contact structure CSP can penetrate the first interlayer dielectric layer ILD1. The common source contact structure CSP can be electrically connected to the common source region CSR. The common source contact structure CSP can include a spacer 171 and a common source contact plug 173. The spacer 171 can surround the sidewall of the common source contact plug 173.

[0046] A horizontal dielectric layer PL can be disposed between the charge storage structure SL and the unit gate electrode 120b, between the charge storage structure SL and the first string selection gate electrode 120c_1 and the second string selection gate electrode 120c_2, and between the ground selection gate electrode 120a and the semiconductor pillar SP, extending to the top and bottom surfaces of the gate electrodes 120a, 120b, 120c_1, and 120c_2. The horizontal dielectric layer PL can extend between the uppermost dielectric pattern 110 and the common source contact structure CSP, and between the first interlayer dielectric layer ILD1 and the common source contact structure CSP. The horizontal dielectric layer PL can include, for example, a silicon oxide layer (e.g., SiO2) or a high-k dielectric layer (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

[0047] A gate dielectric layer 150 may be disposed between a semiconductor pillar SP and a horizontal dielectric layer PL covering the side surface of the ground selection gate electrode 120a. The gate dielectric layer 150 may have side surfaces that are convexly curved in opposite directions. The gate dielectric layer 150 may include, for example, a thermal oxide layer. A second interlayer dielectric layer ILD2 may be disposed on top of the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may cover the top surface of the first interlayer dielectric layer ILD1 and the top surface of the common source contact structure CSP. The second interlayer dielectric layer ILD2 may include, for example, a silicon oxide layer.

[0048] The cell contact plug CCP can be disposed on the pad P. The cell contact plug CCP can penetrate the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2, and can contact the pad P. The cell contact plug CCP can be electrically connected to the vertical channel VC. (See reference...) Figure 3The unit contact plug CCP can be arranged in a zigzag shape along the first direction X. The unit contact plug CCP may not extend beyond the sidewalls of the first vertical structure VS1 to the fifth vertical structure VS5 (i.e., it does not extend beyond the sidewalls of the first vertical structure VS1 to the fifth vertical structure VS5). For example, the unit contact plug CCP may be disposed on the corresponding vertical structure in the first vertical structure VS1 to the fifth vertical structure VS5, but may not be precisely vertically aligned with the central axis of the corresponding vertical structure.

[0049] Reference Figure 3 The unit contact plug CCP may not be located at the center of the first vertical structure VS1 to the fifth vertical structure VS5. For example, the unit contact plug CCP may be located closer to the sidewall of the first vertical structure VS1 to the fifth vertical structure VS5. For example, the unit contact plug CCP on the first vertical structure VS1 and the second vertical structure VS2 may be located further away from the center of the first vertical structure VS1 and the second vertical structure VS2 in the second direction Y. The unit contact plug CCP on the third vertical structure VS3 to the fifth vertical structure VS5 may be located further away from the center of the third vertical structure VS3 to the fifth vertical structure VS5 in the fourth direction Y' opposite to the second direction Y. The unit contact plug CCP may include a metallic material (e.g., tungsten, copper, or aluminum).

[0050] Refer to together Figure 3 and Figure 4 The second interlayer dielectric layer ILD2 may be provided with a first bit line BL1, a second bit line BL2, a third bit line BL3, a fourth bit line BL4, and a fifth bit line BL5. The first bit lines BL1 to BL5 may extend in a first direction X, traversing (i.e., extending) the stacked structure ST and the common source contact structure CSP. In some embodiments, when viewed in a top view, the stacked structure ST may have its side surfaces SS parallel to the second direction Y and perpendicular to the top surface of the substrate 100. The side surfaces SS of the stacked structure ST parallel to the second direction Y may contact the common source contact structure CSP. The first bit lines BL1 to BL5 may have their sidewalls SW traversing (i.e., extending) the side surfaces SS of the stacked structure ST and forming a first angle θ1 with the side surfaces SS of the stacked structure ST. The first angle θ1 may be, for example, a right angle.

[0051] The first bit line BL1 to the fifth bit line BL5 can be arranged sequentially in the second direction Y. The first bit line BL1 can contact the cell contact plug CCP disposed on the fourth vertical structure VS4 penetrating the first string select gate electrode 120c_1, and also contact the cell contact plug CCP disposed on the fourth vertical structure VS4 penetrating the second string select gate electrode 120c_2. For example, the first bit line BL1 can be electrically connected to the vertical channel VC of the fourth vertical structure VS4 penetrating the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2. The second bit line BL2 can contact the cell contact plug CCP disposed on the second vertical structure VS2 penetrating the first string select gate electrode 120c_1, and also contact the cell contact plug CCP disposed on the second vertical structure VS2 penetrating the second string select gate electrode 120c_2. For example, the second bit line BL2 can be electrically connected to the vertical channel VC of the second vertical structure VS2 penetrating the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2.

[0052] The third bit line BL3 can contact the cell contact plug CCP disposed on the third vertical structure VS3 that penetrates the first string of select gate electrodes 120c_1, and can also contact the cell contact plug CCP disposed on the third vertical structure VS3 that penetrates the second string of select gate electrodes 120c_2. For example, the third bit line BL3 can be electrically connected to the vertical channel VC of the third vertical structure VS3 that penetrates the first string of select gate electrodes 120c_1 and the second string of select gate electrodes 120c_2. The fourth bit line BL4 can contact the cell contact plug CCP disposed on the fifth vertical structure VS5 that penetrates the first string of select gate electrodes 120c_1, and can also contact the cell contact plug CCP disposed on the fifth vertical structure VS5 that penetrates the second string of select gate electrodes 120c_2. For example, the fourth bit line BL4 can be electrically connected to the vertical channel VC of the fifth vertical structure VS5 that penetrates the first string of select gate electrodes 120c_1 and the second string of select gate electrodes 120c_2. The fifth bit line BL5 can contact the cell contact plug CCP disposed on the first vertical structure VS1 that penetrates the first string of select gate electrodes 120c_1, and can also contact the cell contact plug CCP disposed on the first vertical structure VS1 that penetrates the second string of select gate electrodes 120c_2. For example, the fifth bit line BL5 can be electrically connected to the vertical channel VC of the first vertical structure VS1 that penetrates the first string of select gate electrodes 120c_1 and the second string of select gate electrodes 120c_2.

[0053] According to some exemplary embodiments of the present invention, the third vertical structure VS3 may not be linearly arranged with the first vertical structure VS1 and the fifth vertical structure VS5 (i.e., it may not be collinear with the first vertical structure VS1 and the fifth vertical structure VS5), and the center G of the third vertical structure VS3 may be arranged to be spaced apart in the fourth direction Y' from the first reference line RL1 passing through the center G of the first vertical structure VS1 and the center G of the fifth vertical structure VS5. Therefore, adjacent first bit lines BL1 to fifth bit lines BL5 can have electrical connections with the first vertical structures VS1 to fifth vertical structures VS5 penetrating the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2 without electrical short circuits between them, thereby allowing the first vertical structures VS1 to fifth vertical structures VS5 penetrating the first string select gate electrode 120c_1 to correspond to the first vertical structures VS1 to fifth vertical structures VS5 penetrating the second string select gate electrode 120c_2.

[0054] Figure 7 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0055] Reference Figure 7 The vertical channel VC and charge storage structure SL can be in direct contact with the substrate 100. For example, the device may not include the above references. Figure 4 The semiconductor pillar SP discussed does not include the above references. Figure 4 The gate dielectric layer 150 is discussed.

[0056] Figure 8 The display shows Figure 2 A magnified view of part A. Figure 9 The display shows Figure 8 An enlarged top view of the vertical structure. The following will mainly describe the planar layout of the vertical structure (or the first to fifth vertical structures).

[0057] Reference Figure 8 and Figure 9 The first vertical structure VS1 can be separated from the second reference line RL2, which passes through the center G of the second vertical structure VS2 and the center G of the fourth vertical structure VS4, by a first distance L1 in the second direction Y. The third vertical structure VS3 can be separated from the second reference line RL2, which passes through the center G of the second vertical structure VS2 and the center G of the fourth vertical structure VS4, by a second distance L1 in the second direction Y. The first distance L1 can be substantially the same as the second distance L2.

[0058] The first minimum distance D1 between adjacent second vertical structures VS2 and third vertical structures VS3 can be substantially the same as the second minimum distance D2 between adjacent first vertical structures VS1 and second vertical structures VS2. The third minimum distance D3 between adjacent third vertical structures VS3 and fourth vertical structures VS4 can be substantially the same as the fourth minimum distance D4 between adjacent fourth vertical structures VS4 and fifth vertical structures VS5. The first minimum distance D1 can be substantially the same as the third minimum distance D3, and the second minimum distance D2 can be substantially the same as the fourth minimum distance D4.

[0059] In some embodiments, adjacent first vertical structures VS1, second vertical structures VS2, and third vertical structures VS3 can be arranged in a triangular shape or an inverted triangular shape. For example, adjacent first vertical structures VS1, second vertical structures VS2, and third vertical structures VS3 can be configured as an isosceles triangle or an inverted isosceles triangle. Adjacent third vertical structures VS3, fourth vertical structures VS4, and fifth vertical structures VS5 can be arranged in a triangular shape or an inverted triangular shape. For example, adjacent third vertical structures VS3, fourth vertical structures VS4, and fifth vertical structures VS5 can be configured as an isosceles triangle or an inverted isosceles triangle. Adjacent second vertical structures VS2, third vertical structures VS3, and fourth vertical structures VS4 can be arranged in a triangular shape or an inverted triangular shape. For example, adjacent second vertical structures VS2, third vertical structures VS3, and fourth vertical structures VS4 can be configured as an isosceles triangle or an inverted isosceles triangle.

[0060] Return to reference Figure 8 The first bit line BL1 to the fifth bit line BL5 can be arranged sequentially in the second direction Y. The first bit line BL1 can contact the cell contact plug CCP on the second vertical structure VS2 that penetrates the first string select gate electrode 120c_1, and can also contact the cell contact plug CCP on the fifth vertical structure VS5 that penetrates the second string select gate electrode 120c_2. The second bit line BL2 can contact the cell contact plug CCP on the fourth vertical structure VS4 that penetrates the first string select gate electrode 120c_1, and can also contact the cell contact plug CCP on the second vertical structure VS2 that penetrates the second string select gate electrode 120c_2.

[0061] The third bit line BL3 can contact the cell contact plug CCP on the first vertical structure VS1 that penetrates the first string select gate electrode 120c_1, and can also contact the cell contact plug CCP on the fourth vertical structure VS4 that penetrates the second string select gate electrode 120c_2. The fourth bit line BL4 can contact the cell contact plug CCP on the third vertical structure VS3 that penetrates the first string select gate electrode 120c_1, and can also contact the cell contact plug CCP on the first vertical structure VS1 that penetrates the second string select gate electrode 120c_2. The fifth bit line BL5 can contact the cell contact plug CCP on the fifth vertical structure VS5 that penetrates the first string select gate electrode 120c_1, and can also contact the cell contact plug CCP on the third vertical structure VS3 that penetrates the second string select gate electrode 120c_2.

[0062] When viewed from above, the side surface SS of the stacked structure ST, which is parallel to the second direction Y, may be perpendicular to the top surface of the substrate 100. The first line BL1 to the fifth line BL5 may have their sidewalls SW that travel across (i.e., extend) the side surface SS of the stacked structure ST and form a second angle θ2 with the side surface SS of the stacked structure ST. The second angle θ2 may be, for example, an acute angle or an obtuse angle.

[0063] According to some exemplary embodiments of the present invention, when viewed in a top view, the first bit line BL1 to the fifth bit line BL5 may be tilted relative to the first direction X. Therefore, adjacent first bit lines BL1 to the fifth bit lines BL5 may have electrical connections with the first vertical structures VS1 to the fifth vertical structures VS5 penetrating the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2 without an electrical short circuit between them, thereby allowing the first vertical structures VS1 to the fifth vertical structures VS5 penetrating the first string select gate electrode 120c_1 to correspond to the first vertical structures VS1 to the fifth vertical structures VS5 penetrating the second string select gate electrode 120c_2.

[0064] Figure 10 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0065] Reference Figure 10Each of the stacked structures ST can include a lower stacked structure LST and an upper stacked structure UST. The upper stacked structure UST can be disposed on the lower stacked structure LST. For example, the ground select gate electrode 120a can correspond to the bottommost gate electrode of the lower stacked structure LST, the string select gate electrodes 120c_1 and 120c_2 can each correspond to the topmost gate electrode of the upper stacked structure UST, and the unit gate electrode 120b can correspond to the gate electrode between the bottommost gate electrode of the lower stacked structure LST and the topmost gate electrode of the upper stacked structure UST.

[0066] A vertical structure VS can penetrate both the lower stack structure LST and the upper stack structure UST. Each vertical structure VS can include a lower vertical structure LVS and an upper vertical structure UVS. The lower vertical structure LVS can penetrate the lower stack structure LST, and the upper vertical structure UVS can penetrate the upper stack structure UST. For example, the upper vertical structure UVS can be disposed on the lower vertical structure LVS. The upper vertical structure UVS and the lower vertical structure LVS can be electrically connected to each other.

[0067] The lower vertical structure LVS may include a vertical channel VC', a charge storage structure SL', an interstitial filling layer 130, and a pad P. The upper vertical structure UVS may include a vertical channel VC', a charge storage structure SL', an interstitial filling layer 130', and a pad P'. A semiconductor pillar SP may be disposed between the lower vertical structure LVS and the substrate 100, and may penetrate to select the gate electrode 120a. The lower portion of the vertical channel VC' of the upper vertical structure UVS and the lower portion of the charge storage structure SL' of the upper vertical structure UVS may contact the pad P of the lower vertical structure LVS. The lower portion of the upper vertical structure UVS may be disposed on / in the pad P of the lower vertical structure LVS.

[0068] In some implementations, such as Figure 10 As shown, the lower vertical structure LVS and the upper vertical structure UVS can have their sidewalls perpendicular to the top surface of the substrate 100. In another embodiment, the lower vertical structure LVS and the upper vertical structure UVS can have their sidewalls inclined relative to the top surface of the substrate 100. The lower vertical structure LVS can have a lower width smaller than its upper width. The upper vertical structure UVS can have a lower width smaller than its upper width. The upper width of the lower vertical structure LVS can be greater than the lower width of the upper vertical structure UVS. Each of the lower vertical structure LVS and the upper vertical structure UVS can have a tapered shape.

[0069] Figure 11 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 3 A sectional view taken by line I-I'.

[0070] Reference Figure 11 Each of the vertical structures VS can include a lower vertical structure portion LVSP and an upper vertical structure portion UVSP. The lower vertical structure portion LVSP can penetrate the lower stack structure LST, and the upper vertical structure portion UVSP can penetrate the upper stack structure UST. The lower vertical structure portion LVSP and the upper vertical structure portion UVSP can be integrally connected into a single body. For example, the vertical channel VC of the lower vertical structure portion LVSP can be integrally connected to the vertical channel VC of the upper vertical structure portion UVSP, and the charge storage structure SL of the lower vertical structure portion LVSP can be integrally connected to the charge storage structure SL of the upper vertical structure portion UVSP. The gap filling layer 130 of the lower vertical structure portion LVSP can be integrally connected to the gap filling layer 130 of the upper vertical structure portion UVSP. The pad P of the vertical structure VS can be disposed on the upper portion of the upper vertical structure portion UVSP. (No reference is required.) Figure 10 Semiconductor pillar SP under discussion.

[0071] In some embodiments, the lower vertical structure portion LVSP may have sidewalls inclined relative to the top surface of the substrate 100, and the upper vertical structure portion UVSP may have sidewalls inclined relative to the top surface of the substrate 100. For example, the sidewalls of the lower vertical structure portion LVSP may not be aligned with the sidewalls of the upper vertical structure portion UVSP. The lower vertical structure portion LVSP may have a lower width smaller than the upper width of the lower vertical structure portion LVSP. The upper vertical structure portion UVSP may have a lower width smaller than the upper width of the upper vertical structure portion UVSP. The upper width of the lower vertical structure portion LVSP may be greater than the lower width of the upper vertical structure portion UVSP. In another embodiment, the lower vertical structure portion LVSP may have sidewalls perpendicular to the top surface of the substrate 100, and the upper vertical structure portion UVSP may have sidewalls perpendicular to the top surface of the substrate 100.

[0072] Figure 12 A top view is shown illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention. Figure 13 The diagram illustrates some exemplary embodiments of a three-dimensional semiconductor memory device according to the concept of the present invention. Figure 12 The sectional view taken from line II-II'.

[0073] Reference Figure 12 and Figure 13The stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2. The first stacked structure ST1 and the second stacked structure ST2 may be spaced apart from each other in a first direction X. Each of the first stacked structure ST1 and the second stacked structure ST2 may include a buffer dielectric layer 101, a dielectric pattern 110, and gate electrodes 120a, 120b, 120c_1, and 120c_2.

[0074] The lower substrate 200 may be disposed below the substrate 100. The lower substrate 200 may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The device isolation layer 201 may be disposed in the lower substrate 200. The device isolation layer 201 may include a dielectric material (e.g., a silicon oxide layer). The device isolation layer 201 may define the active region of the lower substrate 200.

[0075] A peripheral circuit structure (PES) can be disposed between a lower substrate 200 and a substrate 100. The PES may include a lower interlayer dielectric layer 203, transistors (TRs), a path 215, and a lower interconnect 217. The lower interlayer dielectric layer 203 may be disposed between the lower substrate 200 and the substrate 100. The lower interlayer dielectric layer 203 may include, for example, a silicon oxide layer or a silicon nitride layer. Each transistor (TR) may include a source / drain region 210, a peripheral circuit gate dielectric layer 211, and a peripheral circuit gate electrode 213. The peripheral circuit gate electrode 213 may be disposed within the lower interlayer dielectric layer 203. The peripheral circuit gate electrode 213 may be disposed on each of the active regions of the lower substrate 200. The peripheral circuit gate dielectric layer 211 may be disposed between the peripheral circuit gate electrode 213 and the lower substrate 200. The source / drain region 210 may be disposed in the active regions of the lower substrate 200 located on opposite sides of the peripheral circuit gate electrode 213. The lower connection line 217 can be disposed in the lower interlayer dielectric layer 203. The path 215 can be disposed between the lower connection line 217 and the source / drain region 210, and can electrically connect the lower connection line 217 and the source / drain region 210.

[0076] The through-dielectric pattern TVS can penetrate the first stacked structure ST1 and the second stacked structure ST2, and also penetrate the substrate 100. The through-dielectric pattern TVS can be disposed adjacent to the pad region PR of the substrate 100. For example, the through-dielectric pattern TVS can be disposed between the vertical structure VS of the nearest (i.e., closest) pad region PR and the contact plug CP that penetrates the first string select gate electrode 120c_1 and the second string select gate electrode 120c_2. The through-dielectric pattern TVS can be disposed on the top surface of the lower interlayer dielectric layer 203. The through-dielectric pattern TVS may include, for example, a silicon oxide layer.

[0077] The peripheral circuit contact plug (PCP) can be disposed within the through-dielectric pattern TVS. For example, the PCP can penetrate the through-dielectric pattern TVS, the first interlayer dielectric layer ILD1, and the second interlayer dielectric layer ILD2. The PCP can be electrically connected to the transistor TR via the lower connection line 217 and the path 215. The upper connection line 180 can be disposed on the second interlayer dielectric layer ILD2. The upper connection line 180 can be electrically connected to the PCP.

[0078] Figure 14 Cross-sectional views of three-dimensional semiconductor memory devices illustrating some exemplary embodiments of the concept according to the present invention are shown. For the sake of brevity, descriptions of repeated parts will be omitted.

[0079] Reference Figure 14 A separator structure SES can separate the gate electrode 120 in the first direction X. The uppermost gate electrode 120 may include a series select line SSL and a ground select line GSL separated in the first direction X by the separator structure SES. A plurality of vias CH can be provided to penetrate the gate electrode 120, the dielectric pattern 110, and the buffer dielectric layer 101. The substrate 100 may have a recessed region RSR therein, the recessed region RSR being spatially connected to a pair of vias CH spaced apart in the first direction X. For example, one via CH penetrating the series select line SSL may be spatially connected to another via CH adjacent to said one via CH and penetrating the ground select line GSL. A vertical structure VS may be provided in the vias CH.

[0080] The vertical structure VS may include a charge storage structure SL and a vertical channel VC sequentially provided in a channel via CH. The vertical structure VS may have one end that penetrates the string select line SSL and has therein sequentially provided a first contact 20, an auxiliary connection line 30, and a second contact 40 for connecting the vertical structure VS to the bit line BL. The vertical structure VS may have an opposite end that penetrates the ground select line GSL and is connected to the common source line CSL via another first contact 20.

[0081] Figures 15A to 15C The diagram illustrates a method for manufacturing a three-dimensional semiconductor memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 A sectional view taken by line I-I'.

[0082] Reference Figure 15A The molded structure MS can be formed on the substrate 100. The substrate 100 can be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate.

[0083] The molded structure MS may include a buffer dielectric layer 101 on a substrate 100, and may also include a sacrificial layer 102 and a dielectric layer 104 alternately and repeatedly stacked on the buffer dielectric layer 101. The sacrificial layer 102 may include a material having an etch selectivity different from that of the dielectric layer 104. For example, the sacrificial layer 102 may include a silicon nitride layer or a silicon oxide nitride layer, and the dielectric layer 104 may include a silicon oxide layer.

[0084] The uppermost sacrificial layer 102 and the uppermost dielectric layer 104 can be patterned to form a separation trench 105 in the molded structure MS. The separation trench 105 can divide a single uppermost sacrificial layer 102 into multiple portions in the first direction X, and can also divide a single uppermost dielectric layer 104 into multiple portions in the first direction X. The separation trench 105 can be formed by performing an anisotropic etching process (e.g., dry etching). A separation pattern SEP can be formed in the separation trench 105. The separation pattern SEP can be formed by forming a dielectric layer in the separation trench 105 and then performing a planarization process on the dielectric layer. The separation pattern SEP can extend in a second direction Y intersecting the first direction X. The separation pattern SEP may include, for example, a silicon oxide layer.

[0085] The molded structure MS can be etched to form channel holes CH that expose the substrate 100. For example, a mask pattern can be formed on the uppermost dielectric layer 104, and then an anisotropic etching process, in which the mask pattern is used as an etching mask, can be performed to anisotropically etch the molded structure MS. The anisotropic etching process can be performed to form each channel hole CH having the same width along its height from the substrate 100. Alternatively, the anisotropic etching process can be performed to form each channel hole CH having a variable width along its height from the substrate 100. For example, the channel holes CH may have their sidewalls inclined relative to the substrate 100. An over-etching action can be performed such that the substrate 100 can be etched to have a recessed top surface. When viewed in top view, each channel hole CH may have a circular, elliptical, or polygonal shape.

[0086] Semiconductor pillars (SPs) can be formed in channel vias (CHs). Selective epitaxial growth can be performed to grow semiconductor pillars (SPs) from a substrate 100, with the portion of the substrate 100 exposed to the channel vias (CHs) serving as a seed. Semiconductor pillars (SPs) can comprise a material having the same conductivity type as the substrate 100, such as an intrinsic semiconductor or a p-type conductive semiconductor.

[0087] A charge storage structure SL can be formed on the sidewalls of a channel hole CH. The charge storage structure SL can cover the sidewalls of the channel hole CH and partially cover the top surface of the semiconductor pillar SP exposed to the channel hole CH. For example, the formation of the charge storage structure SL may include: forming first, second, and third dielectric layers sequentially covering the inner walls of the channel hole CH; and performing a dry etching process to remove portions of the first to third dielectric layers, thereby partially exposing the top surface of the semiconductor pillar SP.

[0088] Also refer to Figure 5 Each of the charge storage structures SL may include a barrier dielectric layer BKL, a charge storage layer TBL, and a tunnel dielectric layer TL sequentially formed on the sidewalls of the channel hole CH. The barrier dielectric layer BKL may include, for example, a silicon oxide layer or a high-k dielectric layer (e.g., Al2O3 or HfO2); the charge storage layer TBL may include, for example, a silicon nitride layer; and the tunnel dielectric layer TL may include, for example, a silicon oxide nitride layer or a silicon oxide layer or a high-k dielectric layer (e.g., Al2O3 or HfO2).

[0089] A vertical channel (VC) can be formed in a channel hole (CH) in which a charge storage structure (SL) is formed. The VC can conformally cover the inner wall of the tunnel dielectric layer (TL) and the top surface of the semiconductor pillar (SP) exposed by the charge storage structure (SL). The VC can include, for example, a semiconductor material. For instance, the VC can be one of a single-crystal silicon layer, a polycrystalline silicon layer, an organic semiconductor layer, and a carbon nanostructure.

[0090] An interstitial filling layer 130 can be formed within the interior of a channel hole CH surrounded by a vertical channel VC. The interstitial filling layer 130 can completely fill the channel hole CH. Spin-on glass (SOG) technology can be used to form the interstitial filling layer 130. The interstitial filling layer 130 may include a dielectric material, such as one of a silicon oxide layer and a silicon nitride layer. Prior to the formation of the interstitial filling layer 130, a hydrogen annealing process can be performed to anneal the vertical channel VC in a gas atmosphere comprising hydrogen or deuterium. The hydrogen annealing process can repair crystal defects present in the vertical channel VC.

[0091] The pad P can be formed on the upper portion of the vertical channel VC, the upper portion of the charge storage structure SL, and the upper portion of the gap filling layer 130. The pad P can be formed by etching the upper portion of the charge storage structure SL, the upper portion of the vertical channel VC, and the upper portion of the gap filling layer 130 to form a recessed region; then filling the recessed region with a conductive material. Alternatively, the pad P can be formed by doping the upper portion of the vertical channel VC with an impurity of a different conductivity type than that of the vertical channel VC.

[0092] Reference Figure 15BThe molded structure MS can undergo an anisotropic etching process to form trenches T. Trench T can be formed by: forming a first interlayer dielectric layer ILD1 covering the top surface of the molded structure MS; and performing an anisotropic etching process in which the first interlayer dielectric layer ILD1 serves as an etching mask to anisotropically etch the molded structure MS until the top surface of the substrate 100 is exposed. Trench T can be formed to extend in a second direction Y. Then, trench T can be formed to have a linear or rectangular shape extending in the second direction Y. The formation of trench T can be achieved by forming a plurality of stacked structures ST on the substrate 100 that are spaced apart from each other in the first direction X.

[0093] Each of the stacked structures ST may include a buffer dielectric layer 101, and may also include a sacrificial pattern SC and a dielectric pattern 110 stacked sequentially and alternately on the buffer dielectric layer 101. Trench T may expose the sidewalls of the stacked structure ST.

[0094] Reference Figure 15C The sacrificial pattern SC exposed to the trench T can be removed to form a recessed region RR between dielectric patterns 110 spaced apart along the third direction Z. The recessed region RR can be formed by performing a wet etching process and / or an isotropic dry etching process to remove the sacrificial pattern SC. Because the sacrificial pattern SC comprises a material that is etch-selective relative to the dielectric pattern 110, the dielectric pattern 110 may not be removed when the sacrificial pattern SC is removed. Furthermore, the spacer pattern SEP may not be removed when the sacrificial pattern SC is removed. For example, when the sacrificial pattern SC comprises a silicon nitride layer, and when the dielectric pattern 110 and the spacer pattern SEP comprise silicon oxide layers, the etching process can be performed using an etchant comprising phosphoric acid.

[0095] The recessed region RR can extend horizontally from the trench T into the gap between the dielectric patterns 110. The recessed region RR can expose the top and bottom surfaces of the dielectric pattern 110, and can also partially expose the outer walls of the charge storage structure SL. Gate dielectric layer 150 ( Figure 4 ) can be used in semiconductor pillars SP ( Figure 4 The gate dielectric layer 150 is formed on the sidewalls of the recessed region RR. The gate dielectric layer 150 may include, for example, a thermal oxide layer or a silicon oxide layer.

[0096] A horizontal dielectric layer PL can be formed to cover the surfaces of the layers exposed in the recessed region RR and the trench T. For example, the horizontal dielectric layer PL can be formed to conformally cover the surfaces of the dielectric pattern 110, the outer sidewalls of the charge storage structure SL exposed in the recessed region RR, and the sidewalls of the gate dielectric layer 150 exposed in the recessed region RR. The horizontal dielectric layer PL can be formed using a deposition process with excellent step coverage. For example, the horizontal dielectric layer PL can be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The horizontal dielectric layer PL may include a silicon oxide layer (e.g., SiO2) or a high-k dielectric layer (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

[0097] The recessed regions RR can be filled with a conductive material to form gate electrodes 120a, 120b, 120c_1, and 120c_2. The formation of the gate electrodes 120a, 120b, 120c_1, and 120c_2 may include forming a conductive layer to fill the recessed regions RR, followed by an etching process in which the conductive layer is removed from the trench T but partially retained in the recessed regions RR. After the formation of the gate electrodes 120a, 120b, 120c_1, and 120c_2, a common source region CSR can be formed in the substrate 100 exposed to the trench T. An ion implantation process can be performed to form the common source region CSR. The common source region CSR may have a different conductivity type than that of the substrate 100.

[0098] A common source contact structure (CSP) can be formed in a trench T. The CSP can include spacers 171 and a common source contact plug 173. Spacers 171 can cover the sidewalls of the trench T. The common source contact plug 173 can fill the interior of the trench T surrounded by spacers 171. Spacers 171 can be formed to fill the trench T with a dielectric material (e.g., a silicon oxide layer or a silicon nitride layer). The common source contact plug 173 can include one or more of a conductive material (e.g., tungsten, copper, or aluminum) and a metal nitride (e.g., titanium nitride or tantalum nitride).

[0099] Return to reference Figure 4 The second interlayer dielectric layer ILD2 can be formed on the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 can cover the top surface of the first interlayer dielectric layer ILD1 and the top surface of the common source contact structure CSP. Cell contact plug CCP ( Figure 4A cell contact plug CCP can be formed to penetrate the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2. The cell contact plug CCP can directly contact the pad P of the vertical structure VS. A first bit line BL1, a second bit line BL2, a third bit line BL3, a fourth bit line BL4, and a fifth bit line BL5 can be formed on the second interlayer dielectric layer ILD2. The first bit line BL1 to the fifth bit line BL5 can be formed to extend in a first direction X and have an electrical connection with the cell contact plug CCP.

[0100] According to some exemplary embodiments conceived in this invention, the third vertical structure may not be linearly arranged with the first and fifth vertical structures, and the center of the third vertical structure may be arranged to be spaced apart in a fourth direction from a first reference line passing through the centers of the first and fifth vertical structures. Therefore, adjacent first to fifth bit lines can have electrical connections with the first to fifth vertical structures penetrating the first and second string select gate electrodes without any electrical short circuit between them, thereby allowing the first to fifth vertical structures penetrating the first string select gate electrodes to correspond to the first to fifth vertical structures penetrating the second string select gate electrodes.

[0101] According to some exemplary embodiments of the present invention, when viewed in a top view, the first to fifth bit lines may be tilted relative to a first direction. Therefore, adjacent first to fifth bit lines may have electrical connections with the first to fifth vertical structures penetrating the first and second string select gate electrodes without any electrical short circuit between them, thereby allowing the first to fifth vertical structures penetrating the first string select gate electrodes to correspond to the first to fifth vertical structures penetrating the second string select gate electrodes.

[0102] Although the invention has been described in conjunction with some exemplary embodiments of the inventive concept shown in the accompanying drawings, those skilled in the art will understand that various substitutions, changes and modifications can be made without departing from the scope of the inventive concept.

[0103] This application claims priority to Korean Patent Application No. 10-2019-0062640, filed on May 28, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor memory device, comprising: A stacked structure on a substrate and including multiple gate electrodes; The first vertical structure, the second vertical structure, the third vertical structure, the fourth vertical structure, and the ninth vertical structure penetrate the stacked structure and are arranged sequentially in a Z-shape along the first direction; The first line extends in the first direction; as well as The fifth line extends in the first direction. The first bit line vertically overlaps the second vertical structure and the fourth vertical structure, and the centers of the second vertical structure and the fourth vertical structure are spaced apart from the first bit line by the same distance. The fifth bit line vertically overlaps the first vertical structure, the third vertical structure, and the ninth vertical structure. The plurality of gate electrodes includes a first string of select gate electrodes and a second string of select gate electrodes spaced apart in the first direction. The first vertical structure, the second vertical structure, the third vertical structure, the fourth vertical structure, and the ninth vertical structure penetrate the first string of select gate electrodes. The first vertical structure and the ninth vertical structure are separated from the first bit line by a first distance, and the third vertical structure is located between the first vertical structure and the ninth vertical structure in the first direction. The third vertical structure is spaced apart from the first bit line by a second distance, and The first distance is greater than the second distance.

2. The three-dimensional semiconductor memory device according to claim 1, The first vertical structure, the second vertical structure, and the third vertical structure together define the shape of an scalene triangle. The second, third, and fourth vertical structures together define the shape of an inverted scalene triangle.

3. The three-dimensional semiconductor memory device according to claim 1, The first minimum distance between the first vertical structure and the second vertical structure is greater than the second minimum distance between the second vertical structure and the third vertical structure. The third minimum distance between the third vertical structure and the fourth vertical structure is equal to the second minimum distance.

4. The three-dimensional semiconductor memory device according to claim 1, The three-dimensional semiconductor memory device further includes a fifth vertical structure, a sixth vertical structure, a seventh vertical structure, and an eighth vertical structure, wherein the fifth vertical structure, the sixth vertical structure, the seventh vertical structure, and the eighth vertical structure penetrate the second string of select gate electrodes and correspond to the first vertical structure, the second vertical structure, the third vertical structure, and the fourth vertical structure, respectively.

5. The three-dimensional semiconductor memory device according to claim 4, further comprising: A separating pattern is formed between the first string of select gate electrodes and the second string of select gate electrodes, and extends in a second direction that intersects the first direction; as well as Multiple dummy vertical structures penetrate the separating pattern and the stacking structure.

6. The three-dimensional semiconductor memory device of claim 1, further comprising a second bit line, a third bit line, and a fourth bit line extending on the stacked structure and in the first direction. The first line is connected to the fourth vertical structure. The second bit line is connected to the second vertical structure. The third bit line is connected to the third vertical structure; and The fourth bit line is connected to the first vertical structure.

7. The three-dimensional semiconductor memory device according to claim 1, The stacking structure includes a first stacking structure, and The three-dimensional semiconductor memory device further includes: The second stacked structure includes a second plurality of gate electrodes on the substrate and is spaced apart from the first stacked structure in the first direction; The dielectric pattern penetrates the first stacked structure, the second stacked structure, and the substrate; Lower substrate; A peripheral circuit structure, situated between the lower substrate and the substrate, includes transistors; and The peripheral circuit contact plug penetrates the through-dielectric pattern and connects to the transistor.

8. A three-dimensional semiconductor memory device, comprising: A stacked structure comprising multiple gate electrodes sequentially stacked on a substrate; The first vertical structure, the second vertical structure, the third vertical structure, the fourth vertical structure, and the fifth vertical structure penetrate the stacked structure and are arranged sequentially in a Z-shape along the first direction; as well as Multiple bit lines extend in the first direction on the stacked structure. The plurality of gate electrodes includes a first string of select gate electrodes and a second string of select gate electrodes spaced apart in the first direction. The first vertical structure, the second vertical structure, the third vertical structure, the fourth vertical structure, and the fifth vertical structure penetrate the first string of select gate electrodes. The first minimum distance between the first vertical structure and the second vertical structure is greater than the second minimum distance between the second vertical structure and the third vertical structure, and is equal to the fourth minimum distance between the fourth vertical structure and the fifth vertical structure. The third vertical structure is located between the first vertical structure and the fifth vertical structure in the first direction. The plurality of bit lines include a first bit line that vertically overlaps the second vertical structure and the fourth vertical structure, and a second bit line that vertically overlaps the first vertical structure, the third vertical structure and the fifth vertical structure.

9. The three-dimensional semiconductor memory device according to claim 8, The third minimum distance between the third vertical structure and the fourth vertical structure is different from the fourth minimum distance. The second minimum distance is equal to the third minimum distance.

10. The three-dimensional semiconductor memory device according to claim 8, further comprising: It includes a plurality of gate electrodes sequentially stacked on the stacked structure and an on-stack structure between the stacked structure and the bit line; as well as The sixth, seventh, eighth, ninth, and tenth vertical structures penetrate the upper stacked structure. The sixth vertical structure is located on the first vertical structure. The seventh vertical structure is located on the second vertical structure. The eighth vertical structure is located on the third vertical structure. The ninth vertical structure is located on the fourth vertical structure, and The tenth vertical structure is located on the fifth vertical structure.

11. The three-dimensional semiconductor memory device according to claim 8, The line passing through the center of the first vertical structure and the center of the fifth vertical structure is parallel to the first direction, and The center of the third vertical structure is spaced apart from the line.

12. A three-dimensional semiconductor memory device, comprising: A stacked structure on a substrate includes a first string of select lines and a second string of select lines spaced apart in a first direction; A plurality of first vertical structures and a plurality of second vertical structures penetrate the first string of selection lines and the second string of selection lines, wherein the first vertical structures are spaced apart from the second vertical structures in the first direction; Multiple third vertical structures penetrate the first string of selection lines and the second string of selection lines, the third vertical structures being spaced apart from lines passing through the center of the first vertical structure and the center of the second vertical structure by a first distance; as well as The first line extends across the stacked structure. The first line connects one of the plurality of third vertical structures that penetrates the first string of selection lines to one of the plurality of second vertical structures that penetrates the second string of selection lines.

13. The three-dimensional semiconductor memory device according to claim 12, The side surfaces of the stacked structure are perpendicular to the top surface of the substrate, and When viewed from above, the sidewall of the first bit line extending across the side surface of the stacked structure forms an acute or obtuse angle with the side surface of the stacked structure.

14. The three-dimensional semiconductor memory device according to claim 12, further comprising: Multiple fourth vertical structures penetrate the first string of selection lines and the second string of selection lines, the fourth vertical structures being spaced apart from the lines at the first distance; as well as Multiple fifth vertical structures penetrate the first and second selection lines, and the fifth vertical structures are spaced apart from the lines by the first distance. Wherein, one of the plurality of third vertical structures is collinear with one of the plurality of fourth vertical structures and one of the plurality of fifth vertical structures along the first direction, and The one of the plurality of fourth vertical structures is located between the one of the plurality of third vertical structures and the one of the plurality of fifth vertical structures.

15. The three-dimensional semiconductor memory device according to claim 14, The one of the plurality of third vertical structures, the one of the plurality of first vertical structures, and the one of the plurality of fourth vertical structures collectively define a triangular shape. The one of the plurality of first vertical structures, the one of the plurality of fourth vertical structures, and the one of the plurality of second vertical structures adjacent to the one of the plurality of fourth vertical structures collectively define an inverted triangular shape, and The one of the plurality of fourth vertical structures, the one of the plurality of second vertical structures adjacent to the one of the plurality of fourth vertical structures, and the one of the plurality of fifth vertical structures together define a triangular shape.

16. The three-dimensional semiconductor memory device according to claim 12, further comprising: Multiple fourth vertical structures penetrate the first string of selection lines and the second string of selection lines; Multiple fifth vertical structures penetrate the first and second selection lines; as well as The second, third, and fourth bit lines extend parallel to the first bit line across the stacked structure and are inclined relative to the first direction. The second bit line connects one of the plurality of second vertical structures that penetrates the first string of selection lines to one of the plurality of first vertical structures that penetrates the second string of selection lines. The third bit line connects one of the plurality of fourth vertical structures that penetrates the first string of select lines to one of the plurality of third vertical structures that penetrates the second string of select lines. The fourth bit line connects one of the plurality of fifth vertical structures that penetrates the first string of select lines to one of the plurality of fourth vertical structures that penetrates the second string of select lines.

17. The three-dimensional semiconductor memory device of claim 16, wherein the first bit line is between the second bit line and the third bit line spaced apart along a second direction intersecting the first direction.

18. The three-dimensional semiconductor memory device according to claim 12, further comprising: A separating pattern, between the first string of selection lines and the second string of selection lines, the separating pattern extending in a second direction intersecting the first direction; as well as Multiple dummy vertical structures penetrate the separating pattern and the stacking structure.

19. The three-dimensional semiconductor memory device according to claim 12, The stacking structure includes a first stacking structure. The three-dimensional semiconductor memory device further includes: The second stacked structure includes a plurality of gate electrodes on the substrate and is spaced apart from the first stacked structure in the first direction; The dielectric pattern penetrates the first stacked structure, the second stacked structure, and the substrate; Lower substrate; A peripheral circuit structure, situated between the lower substrate and the substrate, includes transistors; and The peripheral circuit contact plug penetrates the through-dielectric pattern and connects to the transistor.

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