Enables high-speed command address interface for random reads

Abstract

The present invention is entitled "Enabling a high-speed command address interface for random reads". The present invention discloses a memory device, which includes a memory controller to send or receive input / output ("I / O") data via an I / O signal, and to send command data, address data, or parameter data via another signal in parallel with sending or receiving the I / O data. The memory device also includes a memory module communicatively coupled to the memory controller. The memory module receives command data, address data, or parameter data from the memory controller to perform an operation.

Description

Background Art

[0001] The following description is provided to aid the reader's understanding. No information provided or references cited are admitted to be prior art.

[0002] Computing techniques for processing data typically require that executable code and data be copied from a non-volatile memory array into a volatile memory before the executable code is applied to the data. The results of the processing are then returned to the non-volatile memory array. Reading information (e.g., data and executable code) from or writing information (e.g., data) to the non-volatile memory array occurs through communication between a memory controller and memory modules of the non-volatile memory array. However, current techniques for communication between a memory controller and memory modules have limitations. Summary of the invention

[0003] According to some aspects of the present disclosure, a memory device is disclosed. The memory device includes a memory controller having programming instructions to send or receive input / output ("I / O") data via an I / O signal, and to send command data, address data, or parameter data via another signal in parallel with sending or receiving the I / O data. The memory device also includes a memory module communicatively coupled to the memory controller. The memory module receives command data, address data, or parameter data from the memory controller to perform an operation.

[0004] According to some other aspects of the present disclosure, a non-transitory computer-readable medium having computer-readable instructions stored thereon is disclosed. The instructions, when executed by a memory module, cause the memory module to perform a process including: receiving a first read command from a memory controller; transmitting data to the memory controller in response to the first read command; and receiving a second read command from the memory controller in parallel with transmitting the data to the memory controller.

[0005] According to other aspects of the present disclosure, a non-transitory computer-readable medium having computer-readable instructions stored thereon is disclosed. The instructions, when executed by a memory controller, cause the memory controller to perform a process comprising: sending a clock signal to a memory module; and sending command data, address data, or parameter data to the memory module relative to the clock signal. The memory controller sends at least one bit of the command data, the address data, or the parameter data during each pulse of the clock signal. The process also includes: sending a command latch enable ("CLE") signal and an address latch enable ("ALE") signal indicating that the command data, the address data, or the parameter data is being sent; and receiving input / output ("I / O") data from the memory module in parallel with sending the command data, the address data, or the parameter data to the memory module.

[0006] The foregoing summary is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the following drawings and detailed descriptions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is an exemplary block diagram of a computing system according to some embodiments of the present disclosure.

[0008] Figure 2 is a more detailed illustration of some embodiments according to the present disclosure Figure 1 An exemplary block diagram of a memory controller and memory modules of a computing system of FIG.

[0009] Figure 3 is a diagram showing some embodiments according to the present disclosure Figure 2 An exemplary block diagram of a first embodiment of communication between a memory controller and a memory module.

[0010] Figure 4 According to some embodiments of the present disclosure Figure 3 An exemplary logic block diagram of logic blocks associated with a memory module.

[0011] Figure 5A and Figure 5B is a diagram showing some embodiments according to the present disclosure Figures 2 to 4 An exemplary timing diagram of communication between a memory controller and a memory module.

[0012] Figure 6 is a diagram showing some embodiments according to the present disclosure Figure 2 An exemplary block diagram of a second embodiment of communication between a memory controller and a memory module.

[0013] Figure 7 According to some embodiments of the present disclosure Figure 6 An exemplary logic block diagram of logic blocks associated with a memory module.

[0014] Figure 8 According to some embodiments of the present disclosure Figure 7 An exemplary logic diagram of a decoder used in a logic block diagram of FIG.

[0015] Fig. 9A and Fig. 9B is a diagram showing the first mode according to some embodiments of the present disclosure Figures 6 to 8 An exemplary timing diagram of communication between a memory controller and a memory module.

[0016] FIG. 10A to FIG. 10C is a diagram showing some embodiments according to the present disclosure Figures 3 to 9B An exemplary timing diagram of an application of an embodiment of the present invention.

[0017] Fig.11 is a diagram showing some embodiments according to the present disclosure Figures 3 to 9B An exemplary timing diagram of another application of an embodiment of the present invention.

[0018] Fig.12 is a diagram showing the operation in the second mode according to some embodiments of the present disclosure Figures 6 to 8 An exemplary timing diagram of communication between a memory controller and a memory module.

[0019] The above and other features of the present disclosure will become apparent from the following description and the appended claims in conjunction with the accompanying drawings. It should be understood that these drawings depict only several embodiments according to the present disclosure and are therefore not to be considered as limiting the scope thereof. The present disclosure will be described in more detail and in greater detail through the use of the accompanying drawings. DETAILED DESCRIPTION

[0020] In the following detailed description, reference is made to the accompanying drawings which form a part of the detailed description. In the accompanying drawings, similar symbols generally identify similar parts unless the context otherwise indicates. The exemplary embodiments described in the detailed description, drawings and claims are not intended to be limiting. Other embodiments may be utilized and other changes may be made without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the various aspects of the present disclosure as generally described herein and shown in the drawings may be arranged, substituted, combined and designed into a wide variety of different configurations, all of which are expressly contemplated and become a part of the present disclosure.

[0021] The present disclosure relates to a computing system with a memory device. The memory device includes a memory controller that communicates with one or more memory modules. The memory controller is configured to read data from the one or more memory modules or write data to the one or more memory modules. In order to communicate with a first memory module in the one or more memory modules, the memory controller is connected to the first memory module via a plurality of buffers (also referred to herein as "pins") and a communication bus. For example, the memory controller and the first memory module may each be connected via a chip enable ("CEN") buffer, an address latch enable ("ALE") buffer, a command latch enable ("CLE") buffer, and an input / output ("I / O") buffer. The buffer that is sending information may be referred to as a transmitter buffer, and the buffer that is receiving information may be referred to as a receiver buffer.

[0022] In order to communicate with the first memory module, the memory controller selects the first memory module by asserting the CEN signal sent from the memory controller to the first memory module via its corresponding CEN buffer. "Asserting" a signal means making the signal valid. For example, in some embodiments, the CEN signal may be a low-level active signal. In other words, when the CEN signal is at a logic low level (e.g., logic level 0), the CEN signal may be considered to be "asserted" or valid. On the other hand, since the CEN signal is a low-level active signal, when the CEN signal is at a logic high level (e.g., logic level 1), the CEN signal may be considered to be "disabled". Similarly, for high-level active signals, when those signals are at a logic high level (e.g., logic level 1), they are "asserted", and when those signals are at a logic low level (e.g., logic level 0), they are "disabled".

[0023] In addition to asserting the CEN signal, the memory controller asserts the ALE signal and the CLE signal to send the address control signal and the command control signal to the first memory module via its corresponding ALE buffer and CLE buffer. The address control signal and the command control signal may indicate the operation that the memory controller expects the first memory module to perform. For example, in order to perform a read operation for reading data from the first memory module, the command control signal and the address control signal may include a read command, and in order to perform a write operation, the command control signal and the address control signal may include a write command. Before the CEN signal is asserted, the first memory module does not respond to the control signal from the memory controller. After the CEN signal is asserted, the first memory module begins to respond to the control signal received from the memory controller. Therefore, when the first memory module receives the asserted CEN signal, the first memory module begins to respond to the ALE and CLE control signals.

[0024] The CLE / ALE control signal forms the command / address path of the first memory module. Compared with the data transmission speed, the command / address path operates at a lower frequency (e.g., a write cycle time of about 20 nanoseconds and 50MHz). Sending the CLE / ALE control signal also requires the memory controller to send the corresponding command and address data to the first memory module respectively. The command / address data can be sent from the memory module to the first memory module on the I / O signal via the corresponding I / O buffer. The I / O signal is also used to promote the I / O data transmission between the first memory module and the memory controller. For example, for a write command to write data to the first memory module, the memory controller can send the I / O data to the memory module via the I / O signal. Similarly, for a read command, the memory controller can receive the data being read from the first memory module via the I / O signal. Therefore, the I / O signal is used to send both -I / O data and command / address code. In some embodiments, parameter data can also be sent by the I / O signal. Although I / O signals are used to transmit I / O data, command data, address data, and parameter data, only one of those types of data may be transmitted on an I / O signal at a given time.

[0025] The I / O signal may be split within two different paths within the first memory module. A first path of the two different paths may include a data path in which I / O data is sent to be written to the first memory module or received from the first memory module for sending to the memory controller. A second path of the two different paths may include a decoding path that decodes command / address control signals, parameter data, and command / address data to read or write data. Data transmission speeds (e.g., transmitting I / O data between the memory controller and the first memory module) continue to increase, while command / address path speeds (e.g., transmitting command / address / parameter data to the first memory module) have largely remained stagnant. The command / address path speed may become a bottleneck, particularly in those applications that require reading or writing a series of data (e.g., video, real-time imaging, etc.). Without increasing the command / address path speed, the speed at which data operations can be performed is ultimately limited, regardless of the speed at which data can be read from or written to the first memory module. However, even increasing the command / address path speed does not increase the overall throughput that much because I / O data and command / address / parameter data use the same I / O signals for sending, and only one of those types of data can be sent via the I / O signals.

[0026] Therefore, the present disclosure provides a technical solution for increasing the overall throughput by implementing the parallel transmission of I / O data and command / address / parameter data. By being able to send I / O data in parallel with command / address / parameter data, the memory controller can send commands simultaneously with read / write data without waiting for the I / O signal to become idle. Therefore, the present disclosure provides two embodiments for implementing the parallel transmission of I / O data and command / address / parameter data. The first embodiment includes providing a new data latch enable ("DLE") buffer on the memory controller and the first memory module. The DLE buffer can be used to send command / address / parameter data via the DLE signal, and the I / O signal can be used to send I / O data. Therefore, the I / O data can be sent in parallel with the command / address / parameter data. In some embodiments, the memory controller can send command / address / parameter data serially via the DLE signal with a one-bit increment relative to the clock signal. The first memory module can receive serial data from the DLE signal and convert the serial data into parallel data after a plurality of clock pulses have passed. For example, when the command / address / parameter data includes eight bits of data, each bit of the command / address / parameter data can be sent during one pulse of the clock signal. The first memory module may count eight pulses of the clock signal and convert serial data received in the previous eight pulses into parallel data. The parallel data indicates command / address / parameter data that the first memory module may use to perform an operation (eg, a read or write operation).

[0027] A second embodiment includes sending command / address / parameter data on CLE and ALE signals that also send command / address control signals. The CLE and ALE signals may include a header portion indicating the command / address / parameter data control signal. The first memory module may decode the header portion to determine whether the information received on the CLE and ALE signals after the header portion is command data, address data, or parameter data. By using the CLE and ALE signals to send command / address / parameter data, no additional buffers are required on the memory controller and the first memory module.

[0028] Advantageously, sending command / address / parameter data and I / O data in parallel reduces data access time, thereby increasing overall system throughput. For applications such as low-latency flash memory where the total read time (tRead) has been significantly reduced (e.g., from 55 microseconds to 5 microseconds), the time required to transmit command / address / parameter data becomes a major bottleneck. By sending command / address / parameter data in parallel with I / O data, at least some of the time required to send command / address / parameter data can be shielded during the I / O data transfer time, thereby increasing throughput. In some embodiments, a four-die read operation with a tRead time of about five microseconds on a low-latency flash memory can take a total of about 29,320 nanoseconds instead of about 29,320 nanoseconds to read data from four dies, thereby increasing performance by about 0.71%. Other memory applications can also benefit from shielding at least some of the command / address / parameter data transfer time during the I / O data transfer time.

[0029] In addition, in some embodiments, the calibration time can be masked during the I / O data transfer time. As data transfer speeds increase, various calibration sequences need to be run on the first memory module to maintain performance. These calibration sequences (e.g., ZQ calibration) can be sent as commands by the memory controller to the first memory module. The calibration sequence can be sent in parallel with the I / O data transfer, thereby masking the calibration time. In some embodiments, running the calibration sequence in parallel with the I / O data transfer can reduce the total operation time from about 14,280 nanoseconds to about 11,270 nanoseconds, thereby increasing performance by about 21%.

[0030] Reference now Figure 1 , shows an exemplary block diagram of a computing system 100 according to some embodiments of the present disclosure. The computing system 100 includes a host device 105 associated with a memory device 110. The host device 105 may be configured to receive input from one or more input devices 115 and provide output to one or more output devices 120. The host device 105 may be configured to communicate with the memory device 110, the input device 115, and the output device 120 via appropriate interfaces 125A, 125B, and 125C, respectively. The computing system 100 may be implemented in a variety of computing devices, such as computers (e.g., desktop computers, laptop computers, etc.), tablet computers, personal digital assistants, mobile devices, wearable computing devices (such as smart watches, other handheld or portable devices), or any other computing unit suitable for performing operations using the host device 105.

[0031] Input devices 115 may include any of a variety of input technologies, such as a keyboard, stylus, touch screen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote control, input port, one or more buttons, dial, joystick, and any other input peripheral associated with host device 105 and allowing an external source (such as a user) to enter information (e.g., data) into the host device and send instructions to the host device. Similarly, output devices 120 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, light emitting diode, headset, plotter, speech generating device, video device, global positioning system, and any other output peripheral configured to receive information (e.g., data) from host device 105. "Data" input into and / or output from host device 105 may include any of a variety of text data, graphic data, video data, sound data, position data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 100.

[0032] Although not shown, the host device 105 may include one or more processing units that can be configured to execute instructions for running one or more applications. In some embodiments, the instructions and data required for running one or more applications may be stored in the memory device 110. In such cases, the host device 105 may request the memory device 110 to retrieve data and instructions, which may then be stored at least temporarily in the memory on the host device. The host device 105 may also be configured to store the results of running one or more applications in the memory device 110. Therefore, the host device 105 may be configured to request the memory device 110 to perform various operations. For example, the host device 105 may request the memory device 110 to read data, write data, update or delete data, and / or perform management or other operations.

[0033] The memory device 110 includes a memory controller 130, which can be configured to read data from or write data to a non-volatile memory array 135. The non-volatile memory array 135 may include one or more memory modules, such as memory modules 140A-140N. Each of the memory modules 140A-140N may include any of a variety of non-volatile memory types. For example, in some embodiments, one or more of the memory modules 140A-140N may include a NAND flash memory core. In other embodiments, one or more of the memory modules 140A-140N may include a NOR flash memory core, a static random access memory (SRAM) core, a dynamic random access memory (DRAM) core, a magnetoresistive random access memory (MRAM) core, a phase control memory (PCM) core, a resistive random access memory (ReRAM) core, a 3D XPoint memory core, a ferroelectric random access memory (FeRAM) core, and other types of memory cores suitable for use within the non-volatile memory array 135.

[0034] The memory modules 140A-140N may be individually and independently controlled by the memory controller 130. In other words, the memory controller 130 may be configured to communicate individually and independently with each of the memory modules 140A-140N. As discussed in more detail below, the memory modules 140A-140N may remain in a standby state until the memory controller 130 desires to establish communication with one of the memory modules by generating a chip select signal or a chip enable signal. The memory controller 130 may be configured as a logic block or circuit that receives instructions from the host device 105 and performs operations according to those instructions. For example, the memory controller 130 may be configured to read data from one or more of the memory modules 140A to 140N or write data to one or more of the memory modules 140A-140N in response to instructions received from the host device 105. The memory controller 130 may be located on the same die as the non-volatile memory array 135 or on a different die.

[0035] It should be understood that Figure 1Only some of the components of the computing system 100 are shown and described in the accompanying drawings. However, the computing system 100 may include other components, such as various batteries and power supplies, networking interfaces, routers, switches, external memory systems, controllers, etc. In general, the computing system 100 may include any of a variety of hardware, software, and / or firmware components that are necessary or considered desirable to perform the functions described herein. Similarly, the host device 105, the input device 115, the output device 120, and the memory device 110 including the memory controller 130 and the non-volatile memory array 135 may include other hardware, software, and / or firmware components that are considered necessary or desirable in performing the functions described herein.

[0036] Now go to Figure 2 , shows a memory controller 200 communicating with a memory module 205 according to some embodiments of the present disclosure. The memory controller 200 is similar to Figure 1 The memory controller 130 and the memory module 205 are similar to Figure 1 140N. Although the memory controller 200 has been shown as communicating only with the memory module 205, it should be understood that the memory controller is also configured to establish communication with each of the memory modules (e.g., memory modules 140A-140N) in the associated non-volatile memory array (e.g., non-volatile memory array 135). The memory controller 200 includes logic / circuitry to select one of the memory modules (e.g., memory module 205) to perform an operation, and when the memory module is selected, send command, address, and data information to the memory module for performing the operation. Therefore, in order to communicate with the memory module 205, the memory controller 200 generates a plurality of signals.

[0037] For example, the memory controller 200 may generate a chip enable ("CEN") signal 210 to activate or select the memory module 205 for communication. As discussed above, the non-volatile memory array (e.g., the non-volatile memory array 135) may include a plurality of memory modules (e.g., the memory modules 140A-140N). Unused memory modules may remain in a standby state to save energy. In the standby state, the memory module will not respond to any control signal from the memory controller. When it is desired to activate the memory module, the memory controller asserts the CEN signal. After the CEN signal is asserted, the activated memory module begins to respond to control signals from the memory controller.

[0038] Thus, when the memory controller 200 desires to activate the memory module 205, the memory controller generates the CEN signal 210. In some embodiments, the CEN signal 210 is an active low signal, which means that the CEN signal is valid or asserted at a logic low level (e.g., a logic level 0 or a low voltage (0 volts)) and is invalid or disabled at a logic high level (e.g., a logic level 1 or a high voltage (e.g., 5 volts)). Thus, when communication with the memory module 205 is not desired, the CEN signal 210 may remain disabled. To activate the memory module 205, the memory controller 200 may switch the CEN signal 210 from a logic high level to a logic low level. In other embodiments, the CEN signal 210 may be an active high signal, wherein the CEN signal may be valid at a logic high level.

[0039] The memory controller 200 may also generate an address latch enable (“ALE”) signal 215 and a command latch enable (“CLE”) signal 220. The ALE signal 215 is a control signal that can be used to activate an address bus connected between the memory controller 200 and the memory module 205. The CLE signal 220 is a control signal that can be used to activate a command bus between the memory controller 200 and the memory module 205. In some embodiments, the ALE signal 215 and the CLE signal 220 may be active high signals. In other words, in some embodiments, the ALE signal 215 and the CLE signal 220 may be asserted at a logic high level and may be disabled at a logic low level. The combination of the logic levels of the ALE signal 215 and the CLE signal 220 may be used to indicate whether command data, address data, parameter data, or input / output (“I / O”) data is to be sent to the memory module 205. I / O data may also be received from the memory module 205. In some embodiments, the logic levels of the ALE signal 215 and the CLE signal 220 may be implemented according to the following truth table 1:

[0040]

[0041]

[0042] Truth Table 1

[0043] Therefore, when the memory module 205 receives the ALE signal 215 and the CLE signal 220, both of which are at a logic low level, the memory module knows that the memory controller 200 is sending parameter data. The parameter data indicates the mode in which the data is latched into the I / O register of the memory module 205. Any data sent to the memory module 205 is latched relative to the rising edge or the falling edge of the clock signal. In the single data rate ("SDR") mode, the data is latched on either the rising edge or the falling edge of the clock signal. In the double data rate ("DDR") mode (also referred to as the switching mode herein), the data is latched on both the rising edge or the falling edge of the clock signal. The parameter data indicates the mode for latching the data. The parameter data also indicates how to perform data transmission between the memory controller 200 and the memory module 205. For example, the parameter data may define the slew rate control, input termination, output impedance, etc. of the data transmission. By changing the parameter data, the mode may be changed. In some embodiments, the SDR mode may be used by default, and the SDR mode may be changed to the DDR mode by changing the parameter data. In other embodiments, the DDR mode may be used by default, and the DDR mode may be changed to the SDR mode by changing parameter data.

[0044] When the memory module 205 receives the ALE signal 215 at a logic low level and the CLE signal 220 at a logic high level, the memory module knows that the memory controller 200 is sending command data, which is latched into the command register of the memory module 205. Similarly, when the memory module 205 receives the ALE signal 215 at a logic high level and the CLE signal 220 at a logic low level, the memory module knows that the memory controller 200 is sending address data, and the address data is latched into the address register of the memory module. When both the ALE signal 215 and the CLE signal 220 are at a logic high level, the memory module 205 understands that I / O data will be written to the memory module or read from the memory module. The data to be written or the data to be read can be latched in the I / O register of the memory module 205.

[0045] Thus, by switching the logic levels of the ALE signal 215 and the CLE signal 220 , the memory controller 200 may send address data, I / O data, command data, and / or parameter data to the memory module 205 .

[0046] The memory controller 200 also generates an I / O signal 225 for sending I / O data to the memory module 205. The memory controller 200 also receives I / O data read from the memory module 205 via the I / O signal 225. The memory controller 200 further generates a data latch enable ("DLE") signal 230 for sending command data, address data, or parameter data to the memory module 205. In addition, the CEN signal 210, the ALE signal 215, the CLE signal 220, the I / O signal 225, and the DLE signal 230 may be clock synchronization signals such that the state of each of those signals changes or switches relative to the rising and / or falling edges of the clock signal based on the SDR mode or DDR mode used. Therefore, the memory controller 200 may generate a CLK signal 235. In some embodiments, the CLK signal 235 may be a write enable ("WEN") clock signal, specifically when a write operation is to be performed on the memory module 205. Although only CEN signal 210 , ALE signal 215 , CLE signal 220 , I / O signal 225 , DLE signal 230 , and CLK signal 235 are discussed herein, memory controller 200 may include additional signals that may be needed or deemed desirable to facilitate communication between memory controller 200 and memory module 205 .

[0047] In some embodiments, each of the CEN signal 210, the ALE signal 215, the CLE signal 220, the DLE signal 230, and the CLK signal 235 may be a one-bit wide signal, while the I / O signal 225 may be an eight-bit wide signal. In other embodiments, one or more of the CEN signal 210, the ALE signal 215, the CLE signal 220, the I / O signal 225, the DLE signal 230, and the CLK signal 235 may have other bit widths. In addition, each of the CEN signal 210, the ALE signal 215, the CLE signal 220, the I / O signal 225, the DLE signal 230, and the CLK signal 235 may be sent from the memory controller 200 via a first buffer and received by the memory module 205 via a corresponding second buffer. For example, the CEN signal 210 may be sent from the memory controller 200 via a first CEN buffer 240 and received by the memory module 205 via a second CEN buffer 245. Similarly, the ALE signal 215, CLE signal 220, I / O signal 225, DLE signal 230, and CLK signal 235 may be sent from the memory controller 200 via the first ALE buffer 250, the first CLE buffer 255, the first I / O buffer 260, the first DLE buffer 265, and the first CLK buffer 270, respectively, and received at the memory module 205 via the second ALE buffer 275, the second CLE buffer 280, the second I / O buffer 285, the second DLE buffer 290, and the second CLK buffer 295, respectively. The buffer that is transmitting is considered a transmitter buffer, and the buffer that is receiving is considered a receive buffer.

[0048] Thus, based on instructions received from a host device (e.g., host device 105), memory controller 200 generates one or more control signals (e.g., CEN signal 210, ALE signal 215, CLE signal 220, I / O signal 225, DLE signal 230, and CLK signal 235) and sends those control signals to memory module 205. Memory module 205 performs one or more operations upon receiving the control signals.

[0049] refer to Figure 3, shows an exemplary block diagram for sending command data or address data or parameter data in parallel with I / O data between a memory controller 300 and a memory module 305 according to some embodiments of the present disclosure. The command data or address data or parameter data is typically sent from the memory controller 300 to the memory module 305. The I / O data may be sent from the memory controller 300 to the memory module 305 (e.g., when the I / O data is to be written to the memory module) or from the memory module to the memory controller (e.g., when the I / O data is to be read from the memory module). When the memory controller 300 desires to establish communication with the memory module 305, the memory controller asserts the CEN signal 310A. When the CEN signal 310A is asserted, the memory controller 300 may send the CLE signal 310B, the ALE signal 310C, the WEN signal 310D, and the DLE signal 310E to the memory module 305. Each of these signals is sent via a corresponding buffer on the memory controller 300. The CLE signal 310B is similar to the CLE signal 220 , the ALE signal 310C is similar to the ALE signal 215 , the WEN signal 310D is similar to the CLK signal 235 , and the DLE signal 310E is similar to the DLE signal 230 .

[0050] The memory controller 300 may also send I / O data to be written to the memory module 305 via an I / O signal 310F, or receive I / O data read from the memory module via an I / O signal. The I / O signal 310F is sent or received via an I / O buffer on the memory controller 300. Although the I / O signal 310F has been shown as being divided into two four-bit parts each for sending or receiving I / O data via two separate buffers, in some embodiments, all eight bits sent via the I / O signal may be sent via a single buffer. In some embodiments, each bit of the I / O data sent or received via the I / O signal 310F may be assigned its own buffer, so that in order to send or receive eight bits of data, eight separate buffers may be used. One or more buffers on the memory controller 300 may be used to send or receive I / O data at other granularities. The I / O data may be transmitted between the memory controller 200 and the memory module 305 synchronously with the DQS signal 310G, which is a clock signal for transmitting I / O data between the memory controller and the memory module.

[0051] The memory module 305 receives the CEN signal 310A as a CEN signal 310H. Upon receiving the CEN signal 310H, the memory module 305 may generate an internal CEN signal that may be used to activate other buffers of the memory module for responding to control signals received from the memory module. Thus, upon receiving the internal CEN signal, the memory module 305 may receive the CLE signal 310B as a CLE signal 310I, receive the ALE signal 310C as an ALE signal 310J, receive the WEN signal 310D as a WEN signal 310K, receive the DLE signal 310E as a DLE signal 310L, receive the I / O signal 310F as an I / O signal 310M, and receive the DQS signal 310G as a DQS signal 310N. The memory module 305 may receive these control signals from the memory controller 300 via buffers on the memory module before transferring them to the appropriate logic blocks within the memory module. The I / O data sent via I / O signal 310F and I / O signal 310M may be sent to latch module 315 of memory module 305 and latched therein in synchronization with the clock of DQS signal 310N. Latch module 315 may temporarily store I / O data 320 before sending it to logic block 325, and specifically to data path block 330 of the logic block, for writing the I / O data into the memory module. In some embodiments, instead of latch module 315, another mechanism may be used to temporarily store I / O data sent via I / O signal 310F and I / O signal 310M. For example, in some embodiments, a flip-flop, a buffer, a register, or other temporary storage mechanism may be used.

[0052] Additionally, the CLE signal 310I, the ALE signal 310J, the WEN signal 310K, and the DLE signal 310L may be directed to a logic block 335 of the memory module 305. In some embodiments, the CLE signal 310I and the ALE signal 310J may be transferred to the logic block 335 via a CLE / ALE driver 340. In other embodiments, the CLE signal 310I and / or the ALE signal 310J may be transferred directly to the logic block 335. In some embodiments, either or both of the WEN signal 310K and the DLE signal 310L may also be transferred to the logic block 335 via one or more driver modules. Within the logic block 335, the bit sequence received serially via the DLE signal 310L is converted into a parallel command data, address data, or parameter data input ("DIN") 345. In some embodiments, the command data, address data, and parameter data may be eight bits wide. In such cases, the DLE signal 310L may serially transmit each bit of the command data, address data, or parameter data, any of which is transmitted by the memory controller 300 via the DLE signal 310E. The memory module 305 may convert the eight bits received serially into one parallel eight-bit data. Although the command data, address data, and parameter data are described herein as being eight bits wide, in other embodiments, one or more of the command data, address data, and parameter data may have other bit widths.

[0053] DIN 345 ​​is sent to logic block 325, and specifically to decode block 350 of the logic block, to decode command data, address data, and parameter data from memory controller 300 and write I / O data 320 into memory module 305. In addition, logic block 335 converts CLE signal 310I, ALE signal 310J, and WEN signal 310K into a form understood by logic block 325. Figure 4 The details of logic block 335 are discussed.

[0054] In addition to the DIN 345, the logic block 335 generates a first modified clock signal 355 for command data and address data and a second modified clock signal 360 for parameter data. The first modified clock signal 355, the second modified clock signal 360, and the CLE signal 310B and the ALE signal 310C may be transferred to a delay block 365. The delay block 365 adjusts the duty cycle or pulse width of the first modified clock signal 355 and the second modified clock signal 360 within the block 365A to generate a modified CLE signal 370A, a modified ALE signal 370B, and a command / address clock 370C. The multiplexer 375 of the delay block 365 is configured to select between the internal clock 380 or the second modified clock signal 360 based on the power-on reset control signal 385 to select the parameter data to be used, and generates a parameter data clock 370D. For example, during startup, the multiplexer 375 may be configured to select the internal clock 380 to enable the memory module 305 to use the parameter data mode (e.g., SDR mode or DDR mode) selected as the default mode or selected in the previous operation. During the current operation, if it is desired to change the parameter data mode, the multiplexer 375 may select the second modified clock 3601 to achieve the change of the parameter data mode.

[0055] The modified CLE signal 370A, the modified ALE signal 370B, the command / address clock 370C, and the parameter data clock 370D are all input to the decode block 350 of the logic block 325. Based on the modified CLE signal 370A, the modified ALE signal 370B, the command / address clock 370C, and the parameter data clock 370D, and the DIN 345, the decode block 350 enables the I / O data 320 to be written to the memory module 305. The decode block 350 may include a plurality of latches and other decoding logic to interpret the modified CLE signal 370A, the modified ALE signal 370B, the command / address clock 370C, and the parameter data clock 370D signals.

[0056] A read operation may also be performed in a similar manner. Instead of sending the I / O data from the memory controller 300 to the data path block 330, for a read operation, the data being read may be sent from the data path block to the memory controller via the I / O signal 310M and the I / O signal 310F along a reverse route. The data being read may be temporarily stored in the latch module 315 before being transferred to the memory controller 300.

[0057] It should be understood that Figure 3 Only some elements are shown. However, in other embodiments, other logic circuits and / or components may be used as may be required or deemed desirable in performing the functions described herein.

[0058] refer to Figure 4 , shows an exemplary logic block diagram 400 according to some embodiments of the present disclosure. The logic block diagram 400 corresponds to Figure 3 4. The logic block 400 includes a counter 405 that receives a WEN signal 410 as an input and generates a transition signal 415 as an output. The WEN signal 410 is similar to the WEN signal 310K. The counter 405 is configured to count clock pulses of the WEN signal 410 and generate the transition signal 415 when a specified number of pulses are counted. For example, as described above, the DLE signal 310E and the DLE signal 310L are single bit signals configured to send an eight bit sequence. In some embodiments and as described with respect to Figure 5A and Figure 5B As explained in more detail in the timing diagram of , each bit of the DLE signal 310L can be sent in SDR mode relative to the rising edge or falling edge of the clock pulse of the WEN signal 410. Therefore, in order to send eight bits of command data or address data or parameter data via the DLE signal 310L, eight clock pulses of the WEN signal 410 are required. Therefore, when counting eight pulses of the WEN signal 410, the counter 405 generates a transition signal 415 indicating that eight bits of data have been received by the DLE signal 310L. The counter 405 can be implemented in any of a variety of suitable ways.

[0059] Transition signal 415 may be combined with WEN signal 410 via AND gate 420 to generate WEN derivative ("WEND") signal 425. WEND signal 425 is a trigger for other elements of logic block diagram 400 to generate other signals. AND gate 420 implements a logical combination on two input signals to generate one output signal. AND gate 420 operates according to the following truth table 2:

[0060] Input A Input B Output 0 0 0 0 1 0 1 0 0 1 1 1

[0061] Truth Table 2

[0062] Therefore, only when all inputs to the AND gate are at a logic high level, the AND gate 420 also outputs a logic high level (e.g., a logic level "1"). If any of the inputs to the AND gate 420 is at a logic low level (e.g., a logic level "0"), the output of the AND gate is a logic low level. Therefore, when both the WEN signal 410 and the transition signal 415 are also at a logic high level, the WEND signal 425 is at a logic high level, and when either the WEN signal or the transition signal is at a logic low level, the WEND signal is at a logic low level.

[0063] The WEND signal 425 is input to a serial-in-parallel-out ("SIPO") block 430 and a flip-flop 435. The SIPO block 430 also receives the WEN signal 410 and the DLE signal 440. The DLE signal 440 is similar to the DLE signal 310L. Via the DLE signal 440, the SIPO block 430 serially receives each bit sent via the DLE signal. Since the WEND signal 425 is generated after eight clock pulses of the WEN signal 410 and since each bit of data sent on the DLE signal 440 is about the pulse of the WEN signal, by the time the WEND signal is generated, the SIPO block 430 has received eight bits of data from the DLE signal. Therefore, upon receiving the WEND signal 425, the SIPO block 430 converts the eight bits of data received serially into a parallel eight-bit data input ("DIN") 445 via the DLE signal 440. The DIN 445 is similar to the DIN 345, which is sent to the decoding block 350 of the logic block 325. In some embodiments, SIPO block 430 can be a sequence of shift registers. In other embodiments, SIPO block 430 can be implemented in other ways to receive a sequence of one-bit data and convert all bits into one parallel data.

[0064] Flip-flop 435 also receives WEND signal 425. Flip-flop 435 can be used to latch the last received ALE / CLE signal. Therefore, flip-flop 435 receives ALE signal 450 and CLE signal 455, and latches those signals when WEND signal 425 is switched. ALE signal 450 and CLE signal 455 are similar to ALE signal 310J and CLE signal 310I, respectively. Flip-flop 435 receives ALE signal 450 and CLE signal 455, and generates derivative ALE signal 460 and derivative CLE signal 465. Derivative ALE signal 460 and derivative CLE signal 465 have the same values ​​as ALE signal 450 and CLE signal 455, respectively. For example, if ALE signal 450 is at a logic high level and CLE signal 455 is at a logic low level when input into flip-flop 435, derivative ALE signal 460 is also at a logic high level and derivative CLE signal 465 is also at a logic low level. Trigger 435 can be implemented in any of a number of suitable ways.

[0065] The derivative ALE signal 460, the derivative CLE signal 465, and the parameter data signal 470 are input to a logic OR gate 475A. The OR gate 475A generates an output signal 475B that enables a clock signal for the logic block 325 to be generated only when command data, address data, or parameter data is to be sent to the logic block. The OR gate 475A implements logic separation on three input signals to generate one output signal. The OR gate 475A can operate according to the truth table 3:

[0066]

[0067]

[0068] Truth Table 3

[0069] Thus, when at least one of the inputs is at a logic high level, OR gate 475A generates a logic high level (e.g., logic level "1") output, and generates a logic low level (e.g., logic level "0") when all inputs are at a logic low level. Thus, when at least one of derivative ALE signal 460, derivative CLE signal 465, or parameter data signal 470 is at a logic high level, output signal 475B is at a logic high level. When all of derivative ALE signal 460, derivative CLE signal 465, and parameter data signal 470 are at a logic low level, output signal 475B is at a logic low level.

[0070] Output signal 475B is input into logic AND gate 475C together with WEND signal 425. AND gate 475C is implemented using the above truth table 2. Therefore, when WEND signal 425 is switched and when command data, address data or parameter data is sent to logic block 325 indicated by output signal 475B at a logic high level, AND gate 475C generates a first modified clock signal 475D. The first modified clock signal 475D is similar to the first modified clock signal 355. WEND signal 425 is also input into logic AND gate 475E together with parameter data signal 475F. When both WEND signal 425 and parameter data signal 475F are at a logic high level, AND gate 475E implemented according to the above truth table 2 generates a second modified clock signal 480. The second modified clock signal 480 is similar to the second modified clock signal 360.

[0071] The first modified clock signal 475D may be sent to a delay block 485A, and the second modified clock signal 480 may be sent to a delay block 485B. Delay blocks 485A and 485B may be used to increase the pulse width of the first modified clock signal 475D and the second modified clock signal 480, respectively. Delay block 485A increases the pulse width of the first modified clock signal 475D to generate a first width increased signal 485C, while delay block 485B increases the pulse width of the second modified clock signal 480 to generate a second width increased signal 485D. The first width increased signal is input into an OR gate 490A together with the first modified clock signal 475D to generate a first modified signal 495A. Similarly, the second width increased signal 485D is input into an OR gate 490B together with the second modified clock signal 480 to generate a second modified signal 495B. OR gates 490A and 490B are implemented according to the above truth table 3, but have two inputs instead of three inputs.

[0072] In addition, delay block 485A, delay block 485B, OR gate 490A and OR gate 490B are similar to block 365A. In some embodiments, delay block 485A, delay block 485B, OR gate 490A and OR gate 490B can be combined into a single delay block, such as Figure 3 As shown in relation to block 365A. In addition, delay block 485A, delay block 485B, OR gate 490A and OR gate 490B may be part of logic block 335, such as Figure 4 as shown, or separated from the logic block, such as Figure 3 As shown. OR gates (e.g., OR gate 490A and OR gate 490B) are Figure 3 Not shown in FIG.

[0073] although Figure 4The SDR mode has been described, but in some embodiments, the logic block diagram 400 can be implemented according to the DDR mode. In the DDR mode, the DLE signal 440 can send one bit of command data, address data, or parameter data on each rising and falling edge of the WEN signal 410. The operation of the counter 405 can be modified based on the bit width of the command data, address data, or parameter data sent on the DLE signal 440 to count the appropriate number of pulses of the WEN signal 410. For example, when the command data, address data, or parameter data sent on the DLE signal 440 is eight bits wide, in the DDR mode, the counter 405 can be configured to count four pulses of the WEN signal 410 (because two bits are received on each pulse) before switching the transition signal 415. In addition, although the DLE signal 440 has been described as one bit wide, in other embodiments, the DLE signal 440 can be configured to send more than one bit of data at a time. The operation of the counter 405 can be modified based on the number of pulses required for all bits of the command data, address data, or parameter data sent on the DLE signal 440.

[0074] Now go to Figure 5A and Figure 5B , shows a timing diagram 500 according to some embodiments of the present disclosure. The timing diagram 500 consists of Figure 4 The elements of the logic block diagram 400 are implemented. Therefore, in combination Figure 4 To discuss the timing diagram 500. In addition, Figure 5A and Figure 5B A portion of a timing diagram 500 is shown. Thus, Figure 5B The portion of the timing diagram shown is Figure 5AContinuation of the timing diagram portion of . For readability purposes only, the timing diagram 500 has been divided into the timing diagram portion. The timing diagram 500 includes a CEN signal 505, a CLE signal 510, an ALE signal 515, an I / O signal 520, and a WEN signal 525. In some embodiments, each of the CEN signal 505, the CLE signal 510, the ALE signal 515, and the WEN signal 525 may be a one-bit wide signal, and the I / O signal 520 may be eight-bit wide. The WEN signal 525 is a clock signal received by a memory module (e.g., memory module 205) from a memory controller (e.g., memory controller 200) to write data to the address of the memory module. In some embodiments, the WEN signal 525 is an active low signal. In addition, the timing diagram 500 is shown according to the SDR mode, in which the various transitions discussed below are about the rising edge of the WEN signal 525. In some embodiments, various transitions may be in SDR mode with respect to the falling edge of WEN signal 525. Alternatively, timing diagram 500 may be modified for DDR mode in which transitions occur at both the rising and falling edges of WEN signal 525, thereby doubling throughput relative to SDR mode.

[0075] To activate the memory module, the memory controller asserts the CEN signal, which the memory module receives as the CEN signal 505. Since the CEN signal 505 is an active low signal, the CEN signal is at a logic high level by default. When it is desired to activate the memory module, the memory controller switches the CEN signal, which in turn switches the CEN signal 505 to a logic low level. The CEN signal 505 remains at a logic low level until the operation being performed in the memory module is completed. Once the operation being performed in the memory module is completed, the memory controller switches the CEN signal back to the default state logic high level. When the CEN signal 505 is asserted, the CLE signal 510 and the ALE signal 515 may be asserted.

[0076] The memory controller may send address / command / parameter data control signals via CLE and ALE signals. The memory module may receive the CLE signal from the memory controller as CLE signal 510 and receive the ALE signal from the memory controller as ALE signal 515. Thus, if Figure 5AAs shown, after the CEN signal 505 is asserted, the CLE signal 510 switches to a logic high level during the time period 530A, while the ALE signal 515 remains at a logic low level during the same time period. Therefore, as can be seen in the above truth table 1, the combination of the CLE signal 510 and the ALE signal 515 instructs the memory controller to send the command control signal during the time period 530A. In addition to the CLE signal and the ALE signal, the memory controller begins to send command data (corresponding to the command control signal indicated by the CLE / ALE signal) to the memory module, which receives the command data via the DLE signal 535. Conventionally, the memory controller sends the command data via the I / O signal, which will be received by the memory module at the I / O signal 520. The command data is sent via the DLE signal 535 instead of the I / O signal 520, and the I / O signal remains available to send / receive the I / O data in parallel with the command data.

[0077] For purposes of explanation, the command control signal sent by the memory controller via the CLE signal 510 and the ALE signal 515 is a read command. Figure 5A The timing diagram portion corresponds to the first read command, while Figure 5B The timing diagram portion of corresponds to the second read command. If the timing diagram 500 is for a write command, the memory controller will Figure 5A However, since timing diagram 500 is for a read command, the memory controller does not send any I / O data. Figure 5B As shown, I / O data is received by the memory controller from the memory module.

[0078] The DLE signal 535 is configured to send a bit of data during each pulse of the WEN signal 525. The "pulse" of the WEN signal 525 is intended to represent the duration between the rising edge of the WEN signal and the next rising edge of the WEN signal in this article. The data sent via the DLE signal 535 is latched in the SIPO block 430 after the next rising edge of the WEN signal 525. Therefore, as shown in the figure, the DLE signal 535 can send a bit D0 during the pulse of the WEN signal 525, and the bit D0 can be latched into the SIPO block 430 after the rising edge 530B of the WEN signal 525. Similarly, during eight pulses of the WEN signal 525, the DLE signal 535 can latch eight bits of data with one increment. At the rising edge 530C of the eighth pulse of the WEN signal 525, the eight serially received bits sent by the DLE signal 535 are latched in the SIPO block 430. After sending eight bits of command data, the DLE signal 535 may begin sending another command data, address data, or parameter data.

[0079] In addition, a counter 540 similar to the counter 405 counts eight pulses of the WEN signal 525 (e.g., increasing from 000 to 111). At the eighth count corresponding to the rising edge 530C, the counter 540 switches the transition signal 545. The transition signal 545 is similar to the transition signal 415. Therefore, at the rising edge 530C, the transition signal 545 transitions to a high logic level within one pulse 530D. After one pulse 530D, the transition signal 545 switches back to a low logic level and remains at a low logic level until the counter 540 counts eight pulses of the WEN signal 525 again. Transitioning the transition signal 545 to a logic high level switches the WEND signal 550, which is similar to the WEND signal 425. Therefore, when the transition signal 545 switches to a logic high level within one pulse 530D, the WEND signal 550 also switches to a logic high level within half a pulse 530E.

[0080] Switching the WEND signal 550 to a logic high level triggers the SIPO block 430 to output the eight bits of data (D0-D7) received from the DLE signal 535 during the time period 530A as eight bits of DIN 555. DIN 555 is similar to DIN 445. In addition, switching the WEND signal 550 to a logic high level triggers the flip-flop 435 for generating the derivative ALE signal 560 and the derivative CLE signal 565. Since the ALE signal 515 and the CLE signal 510 have transitioned from their low logic levels and high logic levels, respectively, at the rising edge 530C of the WEN signal 525, the logic levels of the ALE signal and the CLE signal are latched by the flip-flop 435 and recreated to generate the derivative ALE signal 560 and the derivative CLE signal 565. Figure 5A and Figure 5B As can be seen, derivative ALE signal 560 and derivative CLE signal 565 have the same logic levels as ALE signal 515 and CLE signal 510 , respectively.

[0081] In addition, switching the WEND signal 550 to a logic high level triggers the generation of the first modified clock signal 475D and the second modified clock signal 480, and thereby generates the first modified signal 495A and the second modified signal 495B, respectively. Figure 5A and Figure 5B 5 is shown as signal 570. The frequency of signal 570 is equal to one eighth of the frequency of WEN signal 525. In other words, signal 570 is equal to the duration of eight pulses of WEN signal 525. In other words, signal 570 has an increased pulse width relative to WEN signal 525.

[0082] In targeting Figure 5AWhen the first read command in sends all command data, parameter data and address data, the I / O data 575 is read and transmitted, such as Figure 5B When I / O data 575 is transmitted on I / O signal 520, the memory controller may start to send another read command, which is received by the memory module via CLE signal 510, ALE signal 515 and DLE signal 535, as shown. Figure 5B Thus, by using DLE signal 535, at least some of the time required to send command data, address data, and parameter data may be masked or hidden by the time required to send I / O data via I / O signal 520 to increase the data transfer rate, thereby increasing performance.

[0083] Reference now Figure 6 , shows an exemplary block diagram for facilitating communication between a memory controller 600 and a memory module 605 according to some embodiments of the present disclosure. When the memory controller 600 desires to establish communication with the memory module 605, the memory controller asserts the CEN signal 610A to enable the memory module 605 to begin responding to control signals received after the CEN signal. The memory controller 600 also sends a CLE signal 610B, an ALE signal 610C, a WEN signal 610D, an I / O signal 610E, and a DQS signal 610F to the memory module 605. Each of these signals is sent via a corresponding buffer on the memory controller 600. Figure 3 different, Figure 6 610F and DQS signal 610F are similar to DQS signal 310G and are used to transmit data between memory controller 600 and memory module 605.

[0084] The memory module 605 receives various control signals from the memory controller 600 via buffers on the memory module before transferring those signals to the appropriate logic blocks within the memory module. Thus, the memory module 605 receives the CEN signal 610A as the CEN signal 610G, the CLE signal 610B as the CLE signal 610H, the ALE signal 610C as the ALE signal 610I, the WEN signal 610D as the WEN signal 610J, the I / O signal 610E as the I / O signal 610K, and the DQS signal 610F as the DQS signal 610L from the memory controller 600. The I / O data sent via the I / O signal 610E and the I / O signal 610K are sent to the latch module 615 within the memory module 605 for temporary storage before being sent as the I / O data 620 to the logic block 625, and specifically to the data path block 630 of the logic block for writing the I / O data into the memory module for a write command. For a read command, the data path block 630 may also be used to transfer data read from the memory module 605 to the I / O data 620, which may optionally be temporarily stored in the latch module 615 before being sent to the memory controller 600 via the I / O signal 610E. The latch module 615, the logic block 625, and the data path block 630 are similar to the latch module 315, the logic block 325, and the data path block 330, respectively.

[0085] The CLE signal 610H, the ALE signal 610I, and the WEN signal 610J are directed to the logic block 635 of the memory module 605. In some embodiments, the CLE signal 610H and the ALE signal 610I may be transferred to the logic block 635 via the CLE / ALE driver 640. In other embodiments, the CLE signal 610H and / or the ALE signal 610I may be transferred directly to the logic block 635, and in some embodiments, the WEN signal 610J may also be transferred to the logic block via a driver module. Figure 7 Logic block 635 is described in more detail in . Logic block 635 generates data input ("DIN") 645, which is sent to logic block 625, and specifically to decode block 650 of the logic block to decode various commands from memory controller 600 and write I / O data 620 to or read I / O data 620 from memory module 605.

[0086] In addition, the logic block 635 converts the CLE signal 610H, the ALE signal 610I, and the WEN signal 610J into a form understood by the decode block 650. Therefore, in addition to the DIN 645, the logic block 635 generates a first modified clock signal 655 for the command control signal and the address control signal and a second modified clock signal 660 for the control signal of the parameter data. The first modified clock signal 655 is similar to the first modified clock signal 355, and the second modified clock signal 660 is similar to the second modified clock signal 360. The first modified clock signal 655 and the second modified clock signal 660, as well as the CLE signal 610B and the ALE signal 610C, are transferred to the delay block 665. The delay block 665 is similar to the delay block 365. Delay block 665 generates a modified CLE signal 670A, a modified ALE signal 670B, a modified command / address clock 670C via block 665A, and a modified parameter data clock 670D via multiplexer 665B, all of which are input into decode block 650 for use in performing the operation requested by memory controller 600.

[0087] Go to Figure 7 , shows an exemplary logic block diagram 700 according to some embodiments of the present disclosure. The logic block diagram 700 shows Figure 6 Logic block 700 includes a counter 705 that receives a WEN signal 710 as an input and generates a transition signal 715 as an output. WEN signal 710 is similar to WEN signals 410 and 610J. Counter 705 is similar to counter 405. Thus, counter 705 is configured to count clock pulses of WEN signal 710 and generate transition signal 715 when a specified number of pulses are counted.

[0088] In some embodiments, command data, address data or parameter data can be sent by CLE signal and ALE signal (e.g., CLE signal 610H, ALE signal 610I). Therefore, CLE signal and ALE signal can be used to send command data / address data / parameter data and control signals indicating whether CLE signal and ALE signal are to send command data, address data or parameter data. CLE and ALE signals may include a header portion sent before command data or address data or parameter data is sent. The header portion corresponds to the control signal portion of CLE signal and ALE signal. In some embodiments, the header portion may be sent in one pulse of WEN signal 710. In other embodiments, the header portion may be sent in multiple pulses of WEN signal 710. Upon receiving the header portion, counter 705 may start counting pulses of WEN signal 710. In some embodiments, both CLE signal and ALE signal can be used to send command data / address data / parameter data. In such cases, if an eight-bit value is to be sent, four bits may be sent on CLE signal, and four bits may be sent on ALE signal. Furthermore, since each bit of data can be sent during one pulse of the WEN signal 710, sending eight bits of data (four bits on the CLE signal and four bits on the ALE signal) will require four pulses of the WEN signal. Therefore, the counter 705 can switch the transition signal 715 when the header portion is received, then count four pulses after the header portion, and switch the transition signal again after four pulses.

[0089] The transition signal 715 can be combined with the WEN signal 710 via the AND gate 720 to generate a WEN derivative ("WEND") signal 725. The WEND signal 725 is a trigger for other elements of the logic block diagram 700 to generate other signals. The AND gate 720 can be implemented according to the above-mentioned truth table 2, so that only when all inputs to the AND gate are at a logic high level, the AND gate 720 also outputs a logic high level (e.g., a logic level "1"). If any of the inputs to the AND gate 720 is at a logic low level (e.g., a logic level "0"), the output of the AND gate is a logic low level. Therefore, when the WEN signal 710 and the transition signal 715 are at a logic high level, the WEND signal 725 is also at a logic high level, and when any of the WEN signal or the transition signal is at a logic low level, the WEND signal is at a logic low level.

[0090] Logic block diagram 700 also includes latch 730A and decoder 730B. Latch 730A can be used for temporarily storing the position being sent on CLE signal and ALE signal. Therefore, latch 730A receives CLE signal 735A and ALE signal 735B as input and the position is stored therein. Latch 730A can be realized in any suitable manner. Latch 730A can generate data 735C, which is input in SIPO block 740. Transition signal 715 also can be input in latch 730A to indicate that eight bits of whole sequence have been received. In some embodiments, when receiving transition signal, latch 730A can delete the data stored therein and wait to receive next group of eight bits from CLE signal 735A and ALE signal 735B.

[0091] Decoder 730B is used to decode the header portion of CLE signal 735A and ALE signal 735B. In some embodiments, decoder 730B can decode the header portion by implementing the above-mentioned truth table 1. Therefore, based on the logic levels of CLE signal 735A and ALE signal 735B in the header portion, decoder 730B can determine whether the data sent on CLE signal and ALE signal immediately after the header portion is command data, address data or parameter data. Therefore, the header portion provides control signals for CLE signal 735A and ALE signal 735B. For example, if CLE signal 735A is at a logic low level in the header portion and ALE signal 735B is also at a logic low level in the header portion, decoder 730B can determine that the data that appears next on those signals is parameter data. If the CLE signal 735A is at a logic low level and the ALE signal 735B is at a logic high level in the header portion, the decoder 730B can determine that the data that appears next on those signals is address data, and if the CLE signal 735A is at a logic high level and the ALE signal 735B is at a logic low level in the header portion, the decoder can determine that the data that appears next on those signals is command data. If the CLE signal 735A is at a logic high level and the ALE signal 735B is also at a logic high level in the header portion, the decoder 730B can determine that I / O data will be written to the memory module or I / O data will be read from the memory module, and the I / O data will be sent on the I / O signal. Therefore, the decoder 730B does not expect any data to be transmitted via the CLE signal 735A and the ALE signal 735B. Figure 8 The logic circuitry of decoder 730B is discussed in more detail in . Decoder 730B may also receive transition signal 715 as an input. Switching of transition signal 715 may enable decoder 730B to distinguish between the header portion and command data / address data / parameter data on CLE signal 735A and ALE signal 735B.

[0092] When decoding the header portion of the CLE signal 735A and the ALE signal 735B, the decoder 730B generates a command signal 735D and an address signal 735E. The command signal 735D may be at the same logic level as the CLE signal 735A, and the address signal 735E may be at the same logic level as the ALE signal 735B. In addition, the decoder 730B may continue to generate the command signal 735D and the address signal 735E until the next header portion is received as indicated by the switching of the transition signal 715.

[0093] Data 735C from latch 730A is sent to SIPO block 740. SIPO block 740 is similar to SIPO block 430 in that SIPO block 740 receives data in a serial manner and outputs data in a parallel manner. SIPO block 740 also receives WEND signal 725 and WEN signal 710 as input. SIPO block 740 receives the bit pairs sent via CLE signal 735A and ALE signal 735B via data 735C. Since WEND signal 725 is generated after four clock pulses of WEN signal 710, by the time WEND signal is generated, SIPO block 740 has received four bit pairs from latch 730A. Upon receiving WEND signal 725, SIPO block 740 converts four bit pairs into parallel eight-bit data input ("DIN") 745. DIN 745 is similar to DIN 645 sent to decoding block 650 of logic block 625.

[0094] The command signal 735D and the address signal 735E from the decoder 730B are input into the flip-flop 750. The flip-flop 750 also receives the WEND signal 725. The flip-flop 750 is similar to the flip-flop 435. Therefore, the flip-flop 750 can be used to latch or temporarily store the command signal 735D and the address signal 735E, and generate the derivative ALE signal 755A and the derivative CLE signal 755B, which are input into the logic OR gate 760 together with the parameter data signal 755C. The OR gate 760 is similar to the OR gate 475. Therefore, the OR gate 760 generates an output signal 765, which enables the clock signal for the logic block 625 to be generated only when any of the command data or the address data or the parameter data is to be sent to the logic block. The OR gate 760 is implemented according to the above-mentioned truth table 3. Thus, when at least one of the inputs is at a logic high level, the OR gate 760 generates a logic high level (e.g., logic level "1") output, and generates a logic low level (e.g., logic level "0") when all inputs are at a logic low level. Thus, when at least one of the derivative ALE signal 755A, the derivative CLE signal 755B, or the parameter data signal 755C is at a logic high level, the output signal 765 is at a logic high level. When all of the derivative ALE signal 755A, the derivative CLE signal 755B, and the parameter data signal 755C are at a logic low level, the output signal 765 is at a logic low level.

[0095] The output signal 765 is input into a logic AND gate 770 along with the WEND signal 725. The AND gate 770 is implemented using the above-mentioned truth table 2. Therefore, when the WEND signal 725 transitions to a logic high level and when command data, address data, or parameter data is sent to the logic block 625 indicated by the output signal 765 at a logic high level, the AND gate 770 generates a first modified clock signal 775. The first modified clock signal 775 is similar to the first modified clock signal 655. The WEND signal 725 is also input into a logic AND gate 780 along with the parameter data signal 785. When both the WEND signal 725 and the parameter data signal 785 are at a logic high level, the AND gate 780 implemented according to the above-mentioned truth table 2 generates a second modified clock signal 790. The second modified clock signal 790 is similar to the second modified clock signal 660.

[0096] The first modified clock signal 775 is input into a delay block 795A, and the second modified clock signal 790 is input into a delay block 795B. The delay block 795 is similar to the delay block 485A, and the delay block 795B is similar to the delay block 485B. The delay block 795A and the delay block 795B are used to increase the pulse width of the first modified clock signal 775 and the second modified clock signal 790, respectively. The delay block 795A generates a first width increased signal 795C, and the delay block 795B generates a second width increased signal 795D. The first width increased signal 795C is input into an OR gate 795E together with the first modified clock signal 775, and the second width increased signal 795D is input into an OR gate 795F together with the second modified clock signal 790. The OR gate 7958E and the OR gate 795F can be implemented according to the above truth table 3, but with two inputs instead of three inputs. The output from OR gate 795E is a first modified signal 795G having an increased pulse width, and the output from OR gate 795F is a second modified signal 795H having an increased pulse width.

[0097] Reference Figure 8 , shows a logic circuit of a decoder 800 according to some embodiments of the present disclosure. The decoder 800 is similar to the decoder 730B. The decoder 800 receives the CLE signal 805 and the ALE signal 810 as inputs into the first AND gate 815 and the second AND gate 820. The ALE signal 810 is inverted before being input into the first AND gate 815. Similarly, the CLE signal 805 is inverted before being input into the second AND gate 820. The CLE signal 805 is similar to the CLE signal 735A, and the ALE signal 810 is similar to the ALE signal 735B. The first AND gate 815 and the second AND gate 820 are implemented according to the above-mentioned truth table 2, so that the outputs of the first AND gate and the second AND gate are at a logic high level only when all inputs entering their respective gates are at a logic high level.

[0098] Decoder 800 may generate command signal 825 from first AND gate 815 and address signal 830 from second AND gate 820. Command signal 825 is similar to command signal 735D, and address signal 830 is similar to address signal 735E. Decoder 800 may be implemented according to the following truth table 4:

[0099] CLE ALE Order address 0 0 0 0 0 1 0 1 1 0 1 0 1 1 invalid invalid

[0100] Truth Table 4

[0101] refer to Fig. 9A and Fig. 9B , shows a timing diagram 900 according to some embodiments of the present disclosure. The timing diagram 900 consists of Figure 7Therefore, the timing diagram 900 is combined with the logic block diagram 700. Figure 7 In addition, Fig. 9A and Fig. 9B A portion of a timing diagram 900 is shown. Thus, Fig. 9B The portion of the timing diagram shown is Fig. 9A For readability purposes only, timing diagram 900 is divided into Fig. 9A and Fig. 9B In addition, for the purpose of explanation, the timing diagram 900 is directed to a read command. Fig. 9A The timing diagram portion corresponds to the first read command, while Fig. 9B The portion of the timing diagram corresponds to the second read command. Therefore, the memory controller does not send any I / O data. Fig. 9B As shown, I / O data is received by the memory controller from the memory module.

[0102] The timing diagram 900 includes a CEN signal 905, a CLE signal 910, an ALE signal 915, an I / O signal 920, and a WEN signal 925. In some embodiments, each of the CEN signal 905, the CLE signal 910, the ALE signal 915, and the WEN signal 925 may be a one-bit wide signal, while the I / O signal 920 may be eight bits wide. In some embodiments and as shown in FIG900, the WEN signal 925 is an active low signal. In addition, the timing diagram 900 is shown according to an SDR mode, in which the various transitions discussed below are with respect to the rising edge of the WEN signal 925. In some embodiments, the various transitions may be with respect to the falling edge of the WEN signal 925 in the SDR mode. Alternatively, the timing diagram 900 may be modified for a DDR mode in which transitions occur at both the rising and falling edges of the WEN signal 925, thereby doubling the throughput relative to the SDR mode. The timing diagram for the DDR mode is described below. Fig.12 Shown in.

[0103] In order to activate a memory module (e.g., memory module 605), a memory controller (e.g., memory controller 600) asserts a CEN signal, which is received at the memory module as a CEN signal 905. Since the CEN signal 905 is an active low signal, the CEN signal is at a logic high level by default. When it is desired to activate the memory module, the memory controller switches the CEN signal 905 to a logic low level. The CEN signal 905 remains at a logic low level until the operation being performed in the memory module is completed. Once the operation performed in the memory module is completed, the memory controller switches the CEN signal back to the default state logic high level. When the CEN signal 905 is asserted (e.g., at a logic low level), the memory module begins to respond to the CLE signal, the ALE signal, and the WEN signal received from the memory controller.

[0104] During the first pulse of the WEN signal 925, the CLE signal 910 and the ALE signal 915 transmit a header portion 930A. The header portion 930A shows the CLE signal 910 at a logic high level and the ALE signal 915 at a logic low level. Upon receiving the CLE signal 910 and the ALE signal 915, the decoder 730B can decode those signals according to the above-mentioned truth table 1 and determine that the header portion corresponds to the command control signal. Therefore, the decoder 730B can determine that the data transmitted on the CLE signal 910 and the ALE signal 915 after the header portion 930A is the command data corresponding to the command control signal. Therefore, after the first rising edge 930B of the WEN signal 925, the CLE signal 910 and the ALE signal 915 each begin to transmit a command data bit - one bit is transmitted during each clock pulse of the WEN signal 925. For example, during the first pulse after header portion 930A, CLE signal 910 may transmit bit D0, while ALE signal 915 may transmit bit D1 during the same pulse. Each bit transmitted via CLE signal 910 and ALE signal 915 in one pulse is latched in latch 730A at the next rising edge of WEN signal 925.

[0105] The output of the latch is shown in the timing diagram as data signal 935. Thus, bits D0 and D1 are latched in latch 730A as data bit 930D ​​after rising edge 930C of WEN signal 925, bits D2 from CLE signal 910 and D3 from ALE signal 915 are latched as data bit 930F after rising edge 930E of WEN signal 925, and so on. In addition, decoder 730B generates command signal 940 and address signal 945 when switching transition signal 950 generated by counter 955. At rising edge 930B of WEN signal 925, counter 955 starts counting WEN clock pulses. Since two bits (one on CLE signal 910 and another on ALE signal 915) are sent on each pulse of WEN signal 925, counter 955 counts four pulses after rising edge 930B. At the fifth rising edge 930G, the counter switches the transition signal 950. Therefore, at the fifth rising edge 930G, the transition signal 950 transitions to a high logic level within one pulse 930H. After one pulse 930H, the transition signal 950 switches back to a low logic state and remains in a low logic state until the counter 955 counts four pulses of the WEN signal 525. Transitioning the transition signal 950 to a logic high level switches the WEND signal 960 within half a pulse. The WEND signal 960 is similar to the WEND signal 725.

[0106] The data signal 935, along with the WEND signal 960 and the WEN signal 925, is input into the SIPO block 740, which combines the four-bit pairs from the data signal into the eight-bit DIN signal 965, as indicated by portion 930I. The DIN signal 965 is similar to the DIN 745. In addition, switching the WEND signal 960 to a logic high level triggers the flip-flop 750 for generating the derivative ALE signal 970 and the derivative CLE signal 975. Since the ALE signal 915 and the CLE signal 910 send the command data bits after the header portion 930A, the logic levels of the ALE signal and the CLE signal from the header portion are recreated by the flip-flop 750 to generate the derivative ALE signal 970 and the derivative CLE signal 975. The derivative ALE signal 970 and the derivative CLE signal 975 have the same logic levels as the ALE signal 915 and the CLE signal 910, respectively.

[0107] In addition, switching the WEND signal 960 to a logic high level triggers the generation of the first modified clock signal 775 and the second modified clock signal 790 as well as the first modified signal 795G and the second modified signal 795H. Only the first modification 795G is shown as signal 980 in the timing diagram 900. One pulse of the signal 980 is equal to the total duration of five pulses (one pulse for the header portion 930A and four pulses for the command data) of the WEN signal 925. In addition, one pulse of the signal 980 has a duty cycle that is 2.5 times the duty cycle of each pulse of the WEN signal 925.

[0108] Furthermore, although command data, address data, or parameter data is transmitted by the CLE signal 910 and the ALE signal 915 , the I / O signal 920 may be used to transmit data that needs to be written to or read from the memory module. Fig. 9B shows the data output operation during the reading of data from the memory module. Fig. 9B As shown, the memory controller may begin sending the second read command while the I / O data 985 for the first read command is being sent by the memory module on the I / O signal 920. Thus, by using the CLE signal 910 and the DLE signal 915, at least some of the time required to send command data, address data, or parameter data may be masked or hidden by the time required to send the I / O data via the I / O signal 920 to increase the data transfer rate, thereby increasing performance.

[0109] Go to FIG. 10A to FIG. 10C , shows exemplary timing diagrams 1000A, 1000B, and 1000C according to some embodiments of the present disclosure, which illustrate an application of sending command data / address data / parameter data in parallel with I / O data. Timing diagrams 1000A-1000C illustrate multi-die (e.g., multiple memory modules per die) read operations for low-latency flash memory. Fig. 10AThe problem associated with completing a read command in parallel in each of four dies, i.e., Die 0, Die 1, Die 2, and Die 3, is shown. Completing a read command by a die may include multiple read command portions. For example, to read data from Die 0, the associated memory controller first sends a read command portion 1005A (e.g., a read control signal and corresponding command / address / parameter data). Upon receiving the read command portion 1005A, Die 0 begins decoding the read command portion 1005A to read the data. The internal time at which the memory module decodes the read command portion 1005A and reads the data is shown as read time 1010A. The memory controller may know the duration of the read time 1010A. After the read time 1010A has passed, the memory controller may issue a data output command 1015A to the memory module to receive the data read by the memory module during the read time 1010A. Upon receiving the data output command 1015A, the memory module may decode the data output command 1015A during a time period 1020A and begin a data output operation during a time period 1025A.

[0110] Similarly, to read data from die 1-3, the memory controller may issue a read command that includes a read command portion 1005A, a read time 1010A, a data output command 1015A, and a time period 1020A for decoding the data output command, and a time period 1025A for transmitting data. The memory controller may interleave the sending of the read command portion 1005A and the data output command 1015A on die 0-3 so that those commands are sent while the memory module decodes those signals and the I / O signals are available to send those commands. For example, the memory controller may send the read command portion 1005A on die 1 during the read time 1010A of die 0. Thus, during the read time 1010A of die 0, the I / O signals may be available to send the read command portion 1005A on die 1. Similarly, when the memory controller sends the read command portion 1005A on Die 2, both Die 0 and Die 1 are during read time 1010A and I / O signals are available to send the read command portion on Die 2. When the memory controller sends the read command portion 1005A on Die 3, Dies 0-2 are in read time 1010A.

[0111] Likewise, when the memory controller sends the data output command 1015A on Die 1, Die 0 decodes the data output command and the I / O signals are available during time period 1020A. Similarly, when the memory controller sends the data output command 1015A on Die 2, the I / O signals are available because that die is during time period 1020A decoding the data output command. Thus, the memory controller can issue the read command portion 1005A and the data output command 1015A in parallel on Die 0-2.

[0112] However, during the time period 1025A when die 0 is transmitting data to the memory controller via the I / O signals, the memory controller cannot send any additional commands on die 1-3 via the I / O signals in a conventional mechanism. Therefore, the memory controller cannot send a data output command 1015A on die 3 that coincides with the data transmission on die 0 because the command data and I / O data typically use the same I / O signals. Therefore, the memory controller can send a data output command 1015A on die 3 via the I / O signals or receive data from die 0 during the overlapping time period 1030. Therefore. FIG. 10A to FIG. 10C 1 shows the problem of reading data on multiple dies in parallel in the conventional mechanism. To circumvent the above problem, the memory controller in the conventional mechanism needs to wait until the data output operation on die 0 is completed before issuing a command on die 3. In fact, if the data output operations from die 1 and die 2 overlap with the command issuance for die 3, the memory controller may need to wait until the data output operations from die 1 and die 2 are also completed, such as Fig. 10B Similarly, Die 1 needs to wait until the data output operation on Die 0 is completed before commencing its data transfer, as indicated by wait time period 1035 .

[0113] Therefore, if Fig. 10B As shown, the memory controller waits to issue a data output command 1015A on die 3 until the data output operation during time period 1025A is completed on die 0-2. Therefore, conventional mechanisms for reading data in low-latency flash memory have reduced throughput. To increase throughput, command data and I / O data can be sent in parallel, as discussed in the present disclosure. Specifically and as Fig. 10C As shown, by using the present disclosure, the memory controller can issue a data output command 1015A on Die 3 while simultaneously reading I / O data from Die 0 during time period 1025A on Die 0. This is because command data can be sent in parallel with I / O data using the present disclosure, thereby increasing throughput.

[0114] Go to Fig.11, a timing diagram 1100 is shown according to some embodiments of the present disclosure. Generally speaking, certain sequences such as ZQ calibration sequences may be run on memory modules from time to time. Running these calibration sequences requires sending commands from the memory controller to the memory modules being calibrated. When the calibration sequence commands are being sent, data cannot be sent to or received from the memory modules in conventional mechanisms because they use the same I / O signals to transmit both command data and I / O data, as shown in timing diagram 1105. However, using the teachings of the present disclosure, the memory controller can send calibration sequence commands and I / O data in parallel, as shown in timing diagram 1110, thereby increasing throughput.

[0115] refer to Fig.12 , an exemplary timing diagram 1200 according to some embodiments of the present disclosure is shown. Timing diagram 1200 is similar to timing diagram 900, but is in DDR mode. Therefore, data is latched at each edge (e.g., rising edge and falling edge) of the clock signal. Therefore, when the CEN signal 1205 switches to a logic low level, the WEN signal 1210, the CLE signal 1215, and the ALE signal 1220 are asserted. Since the operation is in DDR mode, at the first edge 1225A of the WEN signal 1210, the header information 1225B is sent by the CLE signal 1215 and the ALE signal 1220. After the header information 1225B, the CLE signal 1215 and the ALE signal 1220 begin to send bits of command data / address data / parameter data, which are latched after each rising edge or falling edge of the WEN signal 1210. For example, bits D0 and D1 are latched after edge 1225C of the WEN signal 1210, bits D2 and D3 are latched after edge 1225D of the WEN signal, and so on.

[0116] In addition, the counter 1230 can count each edge of the WEN signal 1210, rather than counting pulses as in the SDR mode. Thus, when five switching edges (one edge for the header information 1225B and four edges for the data bits D0-D7) are counted, the counter 1230 switches the transition signal 1235, as indicated by edge 1225E. In addition, the transition signal 1235 switches the WEND signal 1240. The switching of the WEND signal 1240 triggers the generation of the derivative CLE signal 1245, the derivative ALE signal 1250, and the DIN 1255 in a manner similar to that discussed above.

[0117] Therefore, the present disclosure provides a mechanism to send command data / address data / parameter data in parallel with I / O data, thereby increasing performance and throughput.

[0118] The subject matter described herein sometimes illustrates the different parts that are contained in different other parts or are connected with different other parts.It should be understood that the architecture of such description is only exemplary, and in fact many other architectures that realize the same function can be realized.In a conceptual sense, any arrangement of the parts to realize the same function is effectively "associated" so that the desired function is realized.Therefore, any two parts that are combined to realize a specific function herein can be regarded as "associated" with each other so that the desired function is realized, and have nothing to do with the architecture or intermediate parts.Similarly, any two parts that are so associated can also be regarded as "operably connected" or "operably coupled" to realize the desired function, and any two parts that can be so associated can also be regarded as "operably coupled" to realize the desired function.The specific example of operably coupling includes but is not limited to physically matchable and / or physically interactive parts and / or wirelessly interactive and / or wirelessly interactive parts and / or logically interactive and / or logically interactive parts.

[0119] With respect to the use of substantially any plural and / or singular terms herein, those skilled in the art may translate from the plural to the singular and / or from the singular to the plural, as appropriate to the context and / or application. For sake of clarity, the various singular / plural permutations may be expressly set forth herein.

[0120] It will be understood by those skilled in the art that, in general, the terms used herein, especially in the appended claims (e.g., the subject matter of the appended claims), are generally meant to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", the term "including" should be interpreted as "including but not limited to", etc.). It will also be understood by those skilled in the art that if a specific number of introduced claim statements is intended to be introduced, such intent will be explicitly stated in the claim, and in the absence of such statement, no such intent is present. For example, to aid understanding, the following appended claims may include the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim recitation introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim recitation to an invention containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"); the same is true when the definite article used to introduce the claim recitation is used. Furthermore, even if a specific number of introduced claim recitations is explicitly stated, those skilled in the art will recognize that such recitation should generally be interpreted to mean at least the number of the recitations (e.g., the unmodified recitation of "two recitations" generally means at least two recitations, or two or more recitations, in the absence of other modifiers). Furthermore, in those cases where a conventional convention similar to “at least one of A, B, and C, etc.” is used, generally such construction is meant in the sense that one skilled in the art would understand the conventional convention (e.g., “a system having at least one of A, B, and C” would include but is not limited to systems having A alone, B alone, C alone, both A and B, both A and C, both B and C, and / or both A, B, and C, etc.). In those cases where a conventional convention similar to “at least one of A, B, or C, etc.” is used, generally such construction is meant in the sense that one skilled in the art would understand the conventional convention (e.g., “a system having at least one of A, B, or C” would include but is not limited to systems having A alone, B alone, C alone, both A and B, both A and C, both B and C, and / or both A, B, and C, etc.). Those skilled in the art will further appreciate that, in practice, any disjunctive words and / or phrases presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to contemplate the possibility of including one, either or both of the terms.For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B." Furthermore, unless otherwise indicated, the use of the terms "approximately," "about," "around," "substantially," etc. means plus or minus ten percent.

[0121] The foregoing description of exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting in terms of the precise forms disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed embodiments. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. A memory device, comprising: A memory controller having programmed instructions to: Sending or receiving input / output I / O data via I / O signals through one or more I / O buffers; sending command data, address data, or parameter data serially through another buffer via another signal in parallel with sending or receiving the I / O data through the one or more I / O buffers; and A memory module is communicatively coupled to the memory controller, wherein the memory module is configured to receive the command data, the address data, or the parameter data from the memory controller and convert the serial command data, the address data, or the parameter data into parallel data to perform an operation. 2 . The memory device of claim 1 , wherein the memory controller transmits the command data, the address data, or the parameter data to the memory module via a data latch enable (DLE) signal.

3. The memory device of claim 2, wherein the memory controller further sends: Command Latch Enable CLE signal; and The address latch enables the ALE signal. The CLE signal and the ALE signal are control signals indicating whether the DLE signal is transmitting the command data, the address data, or the parameter data.

4. The memory device of claim 1, wherein: The one or more I / O buffers consist of eight first I / O buffers, and the another buffer is a first DLE buffer for sending a DLE signal to the memory module; and The memory module includes a second DLE buffer for receiving the DLE signal from the memory controller and eight second I / O buffers for receiving or transmitting the I / O signal. 5 . The memory device of claim 1 , wherein the memory controller is configured to serially send the command data, the address data, or the parameter data in 1-bit increments.

6. The memory device of claim 5, wherein: The memory module includes a counter for counting a number of pulses of a clock signal received from the memory controller, each of the 1-bit increments being relative to a pulse of the clock signal sent by the memory controller; The counter generates a transition signal when counting the number of pulses; and The memory module converts the serially received 1-bit increments into parallel data upon receiving a modified clock signal generated based on the transition signal.

7. The memory device of claim 1, wherein: The operations include a first read operation and a second read operation; and The memory controller receives the I / O data from the memory module via the I / O signal for the first read operation in parallel with sending a command for the second read operation to the memory module.

8. The memory device of claim 1, wherein: The memory controller sends the command data, the address data or the parameter data via a command latch enable CLE signal and an address latch enable ALE signal; and The CLE signal includes a CLE header, and the ALE signal includes an ALE header, a combination of the CLE header and the ALE header indicating whether the CLE signal and the ALE signal are transmitting the command data, the address data, or the parameter data. 9 . The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the command data when the CLE header is asserted and the ALE header is disabled.

10. The memory device of claim 8, wherein the CLE signal and the ALE signal transmit the address data when the ALE header is asserted and the CLE header is disabled.

11. The memory device of claim 8, wherein the CLE signal and the ALE signal transmit the parameter data when the CLE header is disabled and the ALE header is disabled. 12 . The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the CLE header and the ALE header, respectively, before transmitting the command data, the address data, or the parameter data. 13 . The memory device of claim 8 , wherein the CLE signal and the ALE signal serially transmit the command data, the address data, or the parameter data in 1-bit increments.

14. A non-transitory computer readable medium having stored thereon computer readable instructions, the computer readable instructions, when executed by a memory module, causing the memory module to perform a process comprising: receiving a first read command from a memory controller; transmitting data to the memory controller as parallel data via a plurality of data buffers in response to the first read command; receiving a second read command as serial data from the memory controller via another buffer separate from the plurality of data buffers in parallel with transmitting the data to the memory controller; as well as The serial data is converted into parallel data of the second read command.

15. The non-transitory computer readable medium of claim 14, wherein receiving the first read command and the second read command comprises: receiving a clock signal from the memory controller; receiving a data latch enable DLE signal from the memory controller, wherein the DLE signal serially transmits command data, address data, or parameter data from the memory controller in 1-bit increments relative to pulses of the clock signal; receiving a command latch enable CLE signal and an address latch enable ALE signal indicating whether the DLE signal is sending the command data, the address data, or the parameter data; generating a modified clock signal while counting said number of pulses; as well as The serially received 1-bit increments are converted into parallel data upon receipt of the modified clock.

16. The non-transitory computer readable medium of claim 15, further comprising: converting the CLE signal into a derivative CLE signal, wherein a logic level of the derivative CLE signal is the same as the logic level of the CLE signal; as well as The ALE signal is converted into a derivative ALE signal, wherein the logic level of the derivative ALE signal is the same as the logic level of the ALE signal.

17. The non-transitory computer readable medium of claim 14, wherein receiving the first read command and the second read command comprises: receiving a clock signal from the memory controller; decoding a header of a command latch enable CLE signal and an address latch enable ALE signal received from the memory controller to determine whether the CLE signal and the ALE signal are transmitting command data, address data, or parameter data after the header, and wherein the CLE signal and the ALE signal transmit the command data, the address data, or the parameter data serially in 1-bit increments relative to a pulse of the clock signal; generating a modified clock signal while counting said number of pulses; as well as The serially received 1-bit increments are converted into parallel data upon receipt of the modified clock signal.

18. A non-transitory computer readable medium having stored thereon computer readable instructions, the computer readable instructions, when executed by a memory controller, causing the memory controller to perform a process comprising: sending a clock signal to a memory module; sending command data, address data or parameter data to the memory module via a data latch enable DLE signal relative to the clock signal, wherein the memory controller sends at least one bit of the command data, the address data or the parameter data during each pulse of the clock signal; Sending a command latch enable CLE signal and an address latch enable ALE signal indicating that the command data, the address data or the parameter data is being sent; as well as Input / output (I / O) data is received from the memory module via an I / O signal in parallel with sending the command data, the address data, or the parameter data to the memory module.

19. The non-transitory computer-readable medium of claim 18, wherein sending the command data, the address data, or the parameter data via the data latch enable (DLE) signal comprises sending the command data, the address data, or the parameter data serially in 1-bit increments.

20. The non-transitory computer readable medium of claim 18, wherein the process further comprises: sending a header in the CLE signal and the ALE signal, wherein the header indicates whether the CLE signal and the ALE signal are sending the command data, the address data, or the parameter data after the header; and The I / O data is received in parallel via I / O signals.

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