Electrostatic protection structure for high voltage tolerance circuits

Abstract

The present invention discloses an electrostatic protection structure for a high voltage tolerance circuit. The present invention adds a common P-well first NMOS tube string and a second NMOS tube string on the basis of SCR to form a new electrostatic protection structure. The electrostatic protection structure has a low trigger voltage Vt1, and there is no risk of gate breakdown and no latch-up problem.

Description

Technical Field

[0001] The invention relates to an electrostatic protection structure for a high voltage tolerance circuit, and belongs to the field of integrated circuit (IC) design. Background Art

[0002] Electrostatic discharge (ESD) protection is an important part of integrated circuit (IC) design. As the process becomes more advanced, the current tends to be concentrated, making the heat dissipation problem more serious. Therefore, the device is more likely to be burned, causing its ESD protection capability to become a reliability bottleneck.

[0003] Common electrostatic protection devices include NMOS tubes and thyristors (SCR). In circuit applications, it is often the case that only a few signals are high-voltage signals, while most signals and power supplies are low-voltage. This is called a high-voltage tolerant application. At this time, in terms of process implementation, many processes will not develop high-voltage devices for individual high-voltage signals, but often hope to use only low-voltage devices for circuit design, thereby greatly saving manufacturing costs.

[0004] The DC withstand voltage of the low-voltage NMOS gate is low and can be easily broken down by high-voltage signals. Figure 1 As shown, the trigger (turn-on) voltage of the thyristor is determined by the reverse breakdown voltage of the N-well-P-well, and this voltage is usually very high because the doping concentration of the well is very low, so this structure can be used in the ESD protection design of high-voltage signals (because the N-well-P-well junction is not easily broken down by high-voltage signals).

[0005] However, traditional thyristors have the following disadvantages: 1. The trigger voltage Vt1 is too high; 2. Once turned on, the hysteresis voltage Vh and hysteresis current Ih are very low. Therefore, when used in chips, there is a risk of latch-up. Usually during the latch-up test, Vh is lower than the power supply voltage and Ih is less than 200mA, latch-up will occur, causing the device to burn out.

[0006] In order to reduce the trigger voltage Vt1, predecessors invented the following Figure 2 The low voltage triggered SCR structure shown is LVTSCR. LVTSCR is an NMOS structure embedded in the traditional SCR. Similar to the trigger mechanism of NMOS, the gate is coupled to a higher potential so that the NMOS channel is partially turned on, which effectively increases the leakage current. The leakage current caused by the reverse PN junction of the N+ / P well is much greater than the leakage current of the N+ / P well under the same reverse bias voltage because the N+ concentration is much higher than the N well. Therefore, only a lower voltage is needed to trigger the parasitic transistor to turn on and finally form a PNPN positive feedback path.

[0007] Although the LVTSCR trigger voltage Vt1 is low and has strong discharge protection capability, the risk of latch-up has not been improved. In addition, due to the existence of the gate, the low-voltage gate still has the risk of breakdown when used for ESD protection in high-voltage tolerance applications. Summary of the invention

[0008] The present invention provides an electrostatic protection structure for a high voltage tolerance circuit, which solves the problem disclosed in the background technology.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0010] An electrostatic protection structure for a high voltage tolerance circuit, comprising a plurality of SCRs and a plurality of second NMOS tube strings;

[0011] All SCRs share a common cathode and a common anode, the SCR is embedded with a first NMOS tube string, the source of the first NMOS tube string is connected to the cathode, the drain of the first NMOS tube string is connected to the anode through the N-well, the drain of the second NMOS tube string is connected to the anode, the source of the second NMOS tube string is connected to the cathode, the gate of the last NMOS tube in the first NMOS tube string is connected to the cathode, the gates of the remaining NMOS tubes in the first NMOS tube string are externally connected to a control voltage that they can withstand, the gate of the last NMOS tube in the second NMOS tube string is connected to the cathode through a resistor, the gates of the remaining NMOS tubes in the second NMOS tube string are externally connected to a control voltage that they can withstand, and all SCRs, NMOS tubes of the first NMOS tube string, and NMOS tubes of the second NMOS tube string share a P-well.

[0012] All SCRs, the first NMOS tube string and the second NMOS tube string are integrally formed.

[0013] The gates of the remaining NMOS tubes in the first NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

[0014] The gates of the remaining NMOS tubes in the second NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

[0015] An electrostatic protection structure for a high voltage tolerance circuit includes a plurality of electrostatic protection units connected in parallel.

[0016] Each electrostatic protection unit includes a plurality of SCRs and a plurality of second NMOS tube strings. All SCRs in each electrostatic protection unit share a cathode and an anode. The SCR is embedded with a first NMOS tube string. The source of the first NMOS tube string is connected to the cathode. The drain of the first NMOS tube string is connected to the anode through an N-well. The drain of the second NMOS tube string is connected to the anode. The source of the second NMOS tube string is connected to the cathode. The gate of the last-stage NMOS tube in the first NMOS tube string is connected to the cathode. The gates of the remaining NMOS tubes in the first NMOS tube string are externally connected to a control voltage that they can withstand. The gate of the last-stage NMOS tube in the second NMOS tube string is connected to the cathode through a resistor. The gates of the remaining NMOS tubes in the second NMOS tube string are externally connected to a control voltage that they can withstand. All SCRs, NMOS tubes of the first NMOS tube string, and NMOS tubes of the second NMOS tube string in each electrostatic protection unit share a P-well.

[0017] All electrostatic protection units are integrally formed, and a plurality of electrostatic protection units form electrostatic protection unit pairs in pairs, and the electrostatic protection unit pairs share a P-well.

[0018] The gates of the remaining NMOS tubes in the first NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

[0019] The gates of the remaining NMOS tubes in the second NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

[0020] Beneficial effects achieved by the present invention: The present invention adds a common P-well first NMOS tube string and a second NMOS tube string on the basis of SCR, forming a new electrostatic protection structure, the trigger voltage Vt1 of the electrostatic protection structure is low, there is no risk of gate breakdown, and there is no latch-up problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a cross-sectional view of the SCR device;

[0022] Figure 2 is a cross-sectional view of a LVTSCR device;

[0023] Figure 3 It is an electrostatic protection structure;

[0024] Figure 4 Schematic diagram of the transmission line pulse TLP curve that characterizes the ESD capability of the device. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0026] The electrostatic protection structure for high voltage tolerance circuit includes several SCRs and several second NMOS tube strings. All SCRs have a common cathode and a common anode, the SCRs are embedded with the first NMOS tube string, and all SCRs, the first NMOS tube string and the second NMOS tube string are integrally formed, that is, arranged on the same substrate.

[0027] The source of the first NMOS tube string is connected to the cathode, the drain of the first NMOS tube string is connected to the anode through the N-well, the drain of the second NMOS tube string is connected to the anode, the source of the second NMOS tube string is connected to the cathode, the gate of the last NMOS tube in the first NMOS tube string is connected to the cathode, the gates of the remaining NMOS tubes in the first NMOS tube string are externally connected to a control voltage that they can withstand, the gate of the last NMOS tube in the second NMOS tube string is connected to the cathode through a resistor, the gates of the remaining NMOS tubes in the second NMOS tube string are externally connected to a control voltage that they can withstand, and all SCRs, NMOS tubes of the first NMOS tube string, and NMOS tubes of the second NMOS tube string share a P-well.

[0028] The gates of the remaining NMOS tubes in the first NMOS tube string are respectively connected to a power supply or a circuit for inputting a control voltage (i.e., the control voltage of the input gate is controlled by an external circuit); the gates of the remaining NMOS tubes in the second NMOS tube string are respectively connected to a power supply or a circuit for inputting a control voltage.

[0029] The number of NMOS tubes in the above NMOS tube string is determined according to the voltage difference between the cathode and the anode, wherein the second NMOS tube string can be one or more, and when there are multiple second NMOS tube strings, the multiple second NMOS tube strings are connected in parallel, and then the drain and source are connected to the anode and cathode respectively. The above SCR can be one or more, and when there are multiple SCRs, the multiple SCRs share a common cathode and a common anode, that is, are connected in parallel.

[0030] The following example takes a second NMOS tube string and an SCR as an example. Figure 3 It includes an SCR, a first NMOS tube string and a second NMOS tube string, wherein the dotted lines in the figure are all parasitic devices, which are consistent with traditional SCR and NMOS tubes. The SCR, the first NMOS tube string and the second NMOS tube string are integrally formed, and the first NMOS tube string and the second NMOS tube string are both formed by two NMOS tubes connected in series.

[0031] The source of the first NMOS tube string is connected to the cathode of the SCR, the gate of the last NMOS tube in the first NMOS tube string is connected to the cathode of the SCR, the drain of the first NMOS tube string is connected to the anode of the SCR through the N well, the gate of the first-stage NMOS tube in the first NMOS tube string is connected to the power supply (VDD), the drain of the second NMOS tube string is connected to the anode of the SCR, the source of the second NMOS tube string is connected to the cathode of the SCR, the gate of the last NMOS tube in the second NMOS tube string is connected to the cathode of the SCR through a resistor, and the gate of the first-stage NMOS tube in the second NMOS tube string is connected to the power supply (VDD).

[0032] Figure 3 The electrostatic protection structure in the circuit adopts 0.18um process, the NMOS tube is 3.3V, the power supply is also 3.3V, the high voltage signal is 5V (that is, the normal working voltage of the anode is as high as 5V), the DC withstand voltage of the gate of the NMOS tube is 3.3V, and the two reverse PN junctions of N-well-P well and N+-P well are usually greater than 5V because the doping concentration of the well is very light.

[0033] Since the anode high voltage signal is 5V and the power supply is 3.3V, the drain-gate voltage difference of the first-stage NMOS tube in the second NMOS tube string is 1.7V, which is less than the operating voltage of the NMOS tube (3.3V), so the first-stage NMOS tube in the second NMOS tube string is safe. In fact, the upper limit of the high voltage signal is twice that of the NMOS tube (i.e., 6.6V). The gate of the first-stage NMOS tube in the second NMOS tube string is connected to VDD, so that the first-stage NMOS channel is turned on, and the source voltage of the first-stage NMOS tube in the second NMOS tube string is clamped by the voltage of the gate VDD (slightly less than VDD), so the second-stage (i.e., the last-stage) NMOS tube in the second NMOS tube string is also safe, that is, there is no risk of breakdown of the gate of the NMOS tube in the second NMOS tube string. Similarly, there is no risk of breakdown of the gate of the NMOS tube in the first NMOS tube string.

[0034] On the left side of the SCR in the figure, there is an N-well resistor R1 (parasitic resistor) on the path generated by the leakage current from the anode to the cathode. R1 limits the speed at which the leakage current increases. On the right side of the SCR, the leakage current path is similar to that of a simple NMOS, without such a current-limiting resistor. Therefore, the parasitic transistor T3 can be triggered earlier. In addition, a resistor is added between the gate and cathode of the second-stage NMOS tube in the second NMOS tube string, which can further increase the gate coupling voltage. The RC delay effect makes the NMOS tube communication open time longer, thereby further increasing the leakage current, and can also trigger the parasitic transistor T3 earlier (the trigger point of T3 corresponds to the trigger voltage Vt1), so the trigger voltage Vt1 is lower.

[0035] like Figure 4As shown, the parasitic transistor T3 is first triggered and forms a hysteresis to point A. As the voltage of the electrostatic protection structure increases and the current gradually increases, the potential of the base P well of the parasitic transistor T2 will slowly rise until the parasitic transistor T2 is turned on, thereby forming a positive feedback mechanism of the SCR. A secondary hysteresis occurs at point B, which hysteresis returns to Vh. Although the Vh of this structure is still relatively low, the latch effect is affected by Ih in addition to Vh. Since the second NMOS tube string is turned on first, this structure will effectively increase Ih and solve the latch problem. When the SCR is completely turned on, its strong discharge capability can also be fully utilized.

[0036] Figure 3 The structure in can be used as an electrostatic protection unit, and multiple electrostatic protection units are connected in parallel, that is, all cathodes are connected together, and all anodes are connected together, so as to form a new electrostatic protection structure, all electrostatic protection units are formed in one piece, and several electrostatic protection units form electrostatic protection unit pairs in pairs, and the electrostatic protection unit pairs share a P well. The principle of this structure is consistent with the above, and it can also achieve a low trigger voltage Vt1, no gate breakdown risk, and no latch-up.

[0037] The present invention adds a common P-well first NMOS tube string and a second NMOS tube string on the basis of SCR to form a new electrostatic protection structure. The electrostatic protection structure has a low trigger voltage Vt1, no gate breakdown risk, and no latch-up problem.

[0038] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An electrostatic protection structure for a high voltage tolerance circuit, characterized in that: comprising a plurality of SCRs and a plurality of second NMOS tube strings; All SCRs share a common cathode and a common anode, the SCR is embedded with a first NMOS tube string, the source of the first NMOS tube string is connected to the cathode, the drain of the first NMOS tube string is connected to the anode through the N-well, the drain of the second NMOS tube string is connected to the anode, the source of the second NMOS tube string is connected to the cathode, the gate of the last NMOS tube in the first NMOS tube string is connected to the cathode, the gates of the remaining NMOS tubes in the first NMOS tube string are externally connected to a control voltage that they can withstand, the gate of the last NMOS tube in the second NMOS tube string is connected to the cathode through a resistor, the gates of the remaining NMOS tubes in the second NMOS tube string are externally connected to a control voltage that they can withstand, and all SCRs, NMOS tubes of the first NMOS tube string, and NMOS tubes of the second NMOS tube string share a P-well.

2. The electrostatic protection structure for a high voltage tolerance circuit according to claim 1, characterized in that: All SCRs, the first NMOS tube string and the second NMOS tube string are integrally formed.

3. The electrostatic protection structure for a high voltage tolerance circuit according to claim 1, characterized in that: The gates of the remaining NMOS tubes in the first NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

4. The electrostatic protection structure for a high voltage tolerance circuit according to claim 1, characterized in that: The gates of the remaining NMOS tubes in the second NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

5. An electrostatic protection structure for a high voltage tolerance circuit, characterized in that: It includes multiple electrostatic protection units connected in parallel. Each electrostatic protection unit includes a plurality of SCRs and a plurality of second NMOS tube strings. All SCRs in each electrostatic protection unit share a cathode and an anode. The SCR is embedded with a first NMOS tube string. The source of the first NMOS tube string is connected to the cathode. The drain of the first NMOS tube string is connected to the anode through an N-well. The drain of the second NMOS tube string is connected to the anode. The source of the second NMOS tube string is connected to the cathode. The gate of the last-stage NMOS tube in the first NMOS tube string is connected to the cathode. The gates of the remaining NMOS tubes in the first NMOS tube string are externally connected to a control voltage that they can withstand. The gate of the last-stage NMOS tube in the second NMOS tube string is connected to the cathode through a resistor. The gates of the remaining NMOS tubes in the second NMOS tube string are externally connected to a control voltage that they can withstand. All SCRs, NMOS tubes of the first NMOS tube string, and NMOS tubes of the second NMOS tube string in each electrostatic protection unit share a P-well.

6. The electrostatic protection structure for a high voltage tolerance circuit according to claim 5, characterized in that: All electrostatic protection units are integrally formed, and a plurality of electrostatic protection units form electrostatic protection unit pairs in pairs, and the electrostatic protection unit pairs share a P-well.

7. The electrostatic protection structure for a high voltage tolerance circuit according to claim 5, characterized in that: The gates of the remaining NMOS tubes in the first NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

8. The electrostatic protection structure for a high voltage tolerance circuit according to claim 5, characterized in that: The gates of the remaining NMOS tubes in the second NMOS tube string are respectively connected to a power source or a circuit for inputting a control voltage.

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