Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. In addition, the semiconductor device includes a source / drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0065304, filed on June 3, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device. Background Technology

[0004] Recently, semiconductor devices have been designed to scale down in size. Furthermore, with the increasing demand for semiconductor devices with high operating speed and precision, extensive research has been conducted on optimizing the structure of transistors included in semiconductor devices. As a scaling technique to improve the density of integrated circuit devices, a semiconductor device including a FinFET with a channel having a three-dimensional structure has been developed, in which active fins are formed on a substrate, and the gate is formed using these active fins. Summary of the Invention

[0005] One aspect of the present invention is to provide a semiconductor device having a channel with a three-dimensional structure and improved electrical properties.

[0006] According to one aspect of the present invention, a semiconductor device includes a substrate. The semiconductor device may include a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on the substrate and extending in a first direction. The semiconductor device may include a semiconductor capping layer located on an upper surface of the fin structure and extending along opposite side surfaces of the fin structure in a second direction intersecting the first direction. The semiconductor device may include a gate electrode located on the semiconductor capping layer and extending in the second direction. The semiconductor device may include a gate insulating film located between the semiconductor capping layer and the gate electrode. Additionally, the semiconductor device may include source / drain regions connected to one of the side surfaces of the fin structure in the first direction. The plurality of first semiconductor patterns may include silicon-germanium (SiGe), and the plurality of second semiconductor patterns may include silicon (Si). Each of the plurality of first semiconductor patterns may have a first germanium (Ge) concentration gradient that increases toward its first center in its vertical thickness direction. The first Ge content in the first center of each of the first semiconductor patterns may be in a first range of 25% to 35%.

[0007] According to one aspect of the present invention, a semiconductor device includes a substrate. The semiconductor device may include a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on the substrate. The semiconductor device may include a gate electrode located on an upper surface of the fin structure and extending along opposite side surfaces of the fin structure. The semiconductor device may include a gate insulating film located between the fin structure and the gate electrode. Additionally, the semiconductor device may include source / drain regions, respectively connected to opposite side surfaces of the fin structure. The plurality of first semiconductor patterns may include silicon-germanium (SiGe). Each of the plurality of first semiconductor patterns may have a germanium (Ge) concentration gradient increasing toward its center along its vertical thickness. The Ge content at the center of each of the first semiconductor patterns may be in the range of 25% to 35%.

[0008] According to one aspect of the present invention, a semiconductor device includes a substrate. The semiconductor device may include a first transistor located in a first region of the substrate. The first transistor may include a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate. The first transistor may include a first gate electrode surrounding the plurality of channel layers. The first transistor may include a first gate insulating film located between the plurality of channel layers and the first gate electrode. The first transistor may include first source / drain regions located on opposite side surfaces of the plurality of channel layers and connected to each of the plurality of channel layers. The semiconductor device may include a second transistor located in a second region of the substrate. The second transistor may include a fin structure having a plurality of alternately stacked first semiconductor patterns and a plurality of second semiconductor patterns. The second transistor may include a second gate electrode located on an upper surface and a side surface of the fin structure. The second transistor may include a second gate insulating film located between the fin structure and the second gate electrode. The second transistor may include second source / drain regions located on the side surfaces of the fin structure and connected to the plurality of first semiconductor patterns. Additionally, the plurality of first semiconductor patterns may include silicon-germanium (SiGe) with a germanium (Ge) content in the range of 25% to 35%. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention;

[0011] Figure 2A It is along Figure 1 The cross-sectional views taken by lines A1-A1' and B1-B1', and Figure 2B It is along Figure 1 Cross-sectional views taken from lines A2-A2' and B2-B2';

[0012] Figure 3A and Figure 3B It is a graph showing the Ge content distribution along the thickness direction of the fin structure;

[0013] Figure 4A and Figure 4B It is a graph showing the Ge content distribution along the width direction of the fin structure;

[0014] Figure 5A and Figure 5B This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention;

[0015] Figures 6 to 11 This is a perspective view illustrating the main processes of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

[0016] Figure 12A , Figure 13A , Figure 14A and Figure 15A This is a cross-sectional view (A1-A1', A2-A2') illustrating the process of forming a gate structure in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0017] Figure 12B , Figure 13B , Figure 14B and Figure 15B This is a cross-sectional view (B1-B1', B2-B2') illustrating a process for forming a gate structure in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention; and

[0018] Figure 16 This is a cross-sectional view illustrating an example embodiment of a semiconductor device according to the present invention. Detailed Implementation

[0019] In the following description, embodiments of the inventive concept will be illustrated with reference to the accompanying drawings.

[0020] Figure 1 This is a plan view illustrating an example embodiment of a semiconductor device according to a concept of the present invention. Figure 2A It is along Figure 1 The cross-sectional views taken by lines A1-A1' and B1-B1', and Figure 2B It is along Figure 1 The cross-sectional view taken from lines A2-A2' and B2-B2'.

[0021] Reference Figure 1 , Figure 2A and Figure 2BThe semiconductor device 100 according to the example embodiment may include a substrate 101 and a first transistor TR1 and a second transistor TR2 respectively disposed in a first region I and a second region II of the substrate 101.

[0022] The first transistor TR1 and the second transistor TR2 can be formed by the first active structure ACT1 and the second active structure ACT2, as well as the first gate structure G1 and the second gate structure G2, respectively, formed in the active region 104.

[0023] Active region 104 may be disposed on substrate 101. Substrate 101 may be a semiconductor substrate. For example, substrate 101 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Active region 104 may protrude from substrate 101 in a direction perpendicular to the upper surface of substrate 101 and may extend in a first direction (e.g., the X direction) parallel to the upper surface of substrate 101. In some embodiments, although active region 104 is shown as a single active region, active region 104 may be configured as a plurality of active regions 104 parallel to each other in a second direction (e.g., the Y direction) intersecting the first direction.

[0024] An insulating layer 105 may be disposed on the substrate 101 on both sides (e.g., opposite sides) of the active region 104. The insulating layer 105 may extend in a first direction and may have portions spaced apart from each other in a second direction, with the active regions 104 therebetween. The insulating layer 105 may include oxides, nitrides, and / or oxynitrides. In some embodiments, the insulating layer 105 may expose the upper sidewalls of the active region 104. The upper surface of the insulating layer 105 may be at a level below the upper surface of the active region 104 (e.g., at a height from the substrate 101).

[0025] The first active structure ACT1 and the second active structure ACT2 can be set on the active region 104. (See plan view) Figure 1 In the active region 104, a first active structure ACT1 and a second active structure ACT2 can be configured to be superimposed on the active region 104. The first active structure ACT1 and the second active structure ACT2 can extend along the upper surface of the active region 104 in a first direction. The first active structure ACT1 may include a channel layer CH and a first source / drain region SD1 connected (e.g., electrically connected) to both sides (e.g., opposite sides) of the channel layer CH in the first direction, and the second active structure ACT2 may include a fin structure FS serving as a channel and a second source / drain region SD2 connected (e.g., electrically connected) to both sides (e.g., opposite sides) of the fin structure FS in the first direction.

[0026] The first active structure ACT1 and the second active structure ACT2 can be arranged along the upper surface of the active region 104 in a first direction. When multiple first active structures ACT1 and multiple second active structures ACT2 are formed, the first active structures ACT1 and the second active structures ACT2 can be arranged to be spaced apart from each other in a second direction. Furthermore, when multiple active regions 104 are formed, the first active structure ACT1 and / or the second active structure ACT2 can be disposed in each of the active regions 104.

[0027] Reference Figure 2A The diagram shows a cross-sectional view of the first transistor TR1 disposed in the first region I of the substrate 101 along lines A1-A1' and B1-B1'.

[0028] The channel layer CH of the first transistor TR1 may include a plurality of semiconductor patterns spaced apart in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction). The semiconductor pattern of the lowermost channel layer CH may be spaced apart from the active region 104 in a direction perpendicular to the upper surface of the substrate 101. The channel layer CH may be disposed between and may contact the first source / drain regions SD1. Each of the first source / drain regions SD1 may contact a side surface of the channel layer CH. Each of the channel layers CH may connect the first source / drain regions SD1 to each other. Although the number of channel layers CH is shown as three, the inventive concept is not limited thereto. The channel layer CH may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0029] A first gate structure G1 may be disposed on and intersect with a first active structure ACT1. The first gate structure G1 may extend in a second direction to intersect with the active region 104 and the isolation insulating layer 105. In a plan view, a channel layer CH may be stacked with the first gate structure G1, and first source / drain regions SD1 may be disposed on both sides (e.g., opposite sides) of the first gate structure G1. In some embodiments, the first gate structure G1 may extend in a second direction to intersect with a plurality of first active structures ACT1.

[0030] The first gate structure G1 may include a gate electrode GE, a first gate insulating film GI1 located between the gate electrode GE and the channel layer CH, a gate spacer GS located on the side surface of the gate electrode GE, and a gate overlay pattern GP located on the gate electrode GE. The first gate insulating film GI1 may extend between the gate electrode GE and the gate spacer GS, and the uppermost surface of the first gate insulating film GI1 may be substantially coplanar with the upper surface of the gate electrode GE.

[0031] The gate electrode GE can cover the uppermost surface of the channel layer CH and can cover the two side surfaces of the channel layer CH in the second direction. The gate electrode GE can extend in the second direction to cover the upper surface of the isolation insulating layer 105. The gate electrode GE can fill the space between the channel layers CH and the space between the lowermost channel layer CH and the active region 104. The first gate insulating film GI1 can be configured to surround the surface of each of the channel layers CH to be inserted between the channel layer CH and the gate electrode GE, and each of the channel layers CH can be spaced apart from the gate electrode GE, and the first gate insulating film GI1 is inserted between each of the channel layers CH and the gate electrode GE. The first gate insulating film GI1 can extend along the bottom surface of the gate electrode GE. That is, the first gate insulating film GI1 can be inserted between the gate electrode GE and the isolation insulating layer 105 and between the gate electrode GE and the active region 104.

[0032] Thus, in the first transistor TR1 disposed in the first region I of the substrate 101, the gate electrode GE, the channel layer CH and the first source / drain region SD1 can constitute a gate-all-around (GAA) type field-effect transistor.

[0033] Conversely, the structure of the second transistor TR2 disposed in the second region II of the substrate 101 is different from that of the GAA-type field-effect transistor.

[0034] Reference Figure 2B The second transistor TR2 includes a fin structure FS extending in a first direction (e.g., the X direction) on the active region 104. The fin structure FS includes a plurality of first semiconductor patterns 151 and a plurality of second semiconductor patterns 152 alternately stacked in a direction perpendicular to the upper surface of the substrate 101 (e.g., the Z direction).

[0035] A fin structure FS may be disposed between and in contact with the second source / drain regions SD2. The second source / drain regions SD2 may commonly contact two side surfaces of the fin structure FS in a first direction (e.g., the X direction). The fin structure FS (specifically, the second semiconductor pattern 152) may serve as a channel. At least each of the second semiconductor patterns 152 may connect the second source / drain regions SD2 to each other. A plurality of second semiconductor patterns 152 may be located at substantially the same level as the plurality of channel layers CH and may comprise the same semiconductor material. The first semiconductor pattern 151 may comprise a material having etch selectivity relative to the second semiconductor pattern 152.

[0036] In some embodiments, the first semiconductor pattern 151 may include silicon germanium (SiGe) with a germanium (Ge) content in the range of 25% to 35%, and the second semiconductor pattern 152 may include SiGe with a relatively low silicon (Si) content or germanium (Ge) content.

[0037] Figure 3A The section a1-a2 shows the... Figure 2B The image shows the Ge content distribution in the stacking direction of the fin structure FS (i.e., in the direction perpendicular to the upper surface of the substrate, e.g., the Z direction).

[0038] Reference Figure 3A The Ge content (C) of the first semiconductor pattern 151 T The first semiconductor pattern 151 is composed of SiGe ranging from 25% to 35%, and the second semiconductor pattern 152 represents the content distribution of Si. A discontinuity in the content distribution is shown at the boundary between the first semiconductor pattern 151 and the second semiconductor pattern 152.

[0039] Ge content distribution can compensate for discontinuities to prevent performance degradation due to bandgap discontinuities when operating the finned FS as a channel. For example, thermal diffusion can be used to introduce a gradient in the vertical direction (e.g., the Z-direction) of the Ge content distribution. Figure 3B As shown, the Ge content distribution can be configured to have a gradient increasing toward the center in the thickness (e.g., vertical) direction in each of the plurality of first semiconductor patterns 151. That is, each of the plurality of first semiconductor patterns 151 has a Ge concentration gradient increasing toward the center in its thickness direction, and the Ge content C T The range at the center of each of the first semiconductor patterns 151 can be 25% to 35%.

[0040] Semiconductor capping layer 155 ( Figure 2B The gate electrode GE can be configured to surround the fin structure FS in a second direction (e.g., the Y direction). A semiconductor capping layer 155 can be disposed on the upper surface of the fin structure FS and on two side surfaces in the second direction, and can extend between the gate electrode GE and the insulating layer 105. The semiconductor capping layer 155 may include silicon (Si).

[0041] In the region of the fin structure FS that contacts multiple second semiconductor patterns, the content distribution of Ge can be altered through thermal diffusion of the element. Figure 4A It shows Figure 2B The Ge content distribution in the second direction (e.g., the Y direction) in the b1-b2 section of the fin structure FS shown in the figure.

[0042] like Figure 4AAs shown, in each of the plurality of first semiconductor patterns 151, Ge element is diffused into a semiconductor capping layer 155 made of silicon, and may have a Ge concentration gradient increasing toward the center in a second direction. Here, the Ge content in the center of each of the first semiconductor patterns 151 may be in the range of 25% to 35%.

[0043] Second gate structure G2 ( Figure 1 and Figure 2B The second gate structure G2 can be disposed on and intersect with the second active structure ACT2. The second gate structure G2 can extend in a second direction to intersect with the active region 104 and the isolation insulating layer 105. In a plan view, the fin structure FS can be stacked with the second gate structure G2, and each second source / drain region SD2 can be commonly disposed on both sides (e.g., opposite sides) of the second gate structure G2. In some example embodiments, the second gate structure G2 can extend in a second direction to intersect with multiple second active structures ACT2.

[0044] The second gate structure G2 may include a gate electrode GE, a second gate insulating film GI2 located between the gate electrode GE and the semiconductor capping layer 155, a gate spacer GS located on the side surface of the gate electrode GE, and a gate overlay pattern GP located on the gate electrode GE. The second gate insulating film GI2 may extend between the gate electrode GE and the gate spacer GS, and the uppermost surface of the second gate insulating film GI2 may be substantially coplanar with the upper surface of the gate electrode GE.

[0045] In the second transistor TR2, as Figure 2B As shown, the gate electrode GE can cover the upper surface of the fin structure FS and its two side surfaces in the second direction. The gate electrode GE can extend in the second direction to cover the upper surface of the insulating layer 105. The second gate insulating film GI2 can be interposed between the semiconductor capping layer 155 and the gate electrode GE to cover the upper surface of the fin structure FS and its two side surfaces in the second direction. The second gate insulating film GI2 can extend along the bottom surface of the gate electrode GE.

[0046] As described above, the second transistor TR2 disposed in the second region II of the substrate 101 can be a field-effect transistor, and... Figure 2A Unlike the first transistor TR1 with GAA type shown, this field-effect transistor has a structure using a fin structure FS surrounded by a semiconductor capping layer 155 as a channel.

[0047] Specifically, the first transistor TR1 can be disposed in a first region I of the substrate 101, and the first region I of the substrate 101 can be a memory cell region in which multiple memory cells are formed or a logic cell region in which logic transistors are disposed. As an example, the first transistor TR1 can be a portion of the memory cell transistors constituting multiple SRAM cells. As another example, the first transistor TR1 can be a portion of the logic transistors constituting the processor core.

[0048] In addition, the second transistor TR2 can be disposed in the second region II of the substrate 101, and the second region II of the substrate 101 can be the peripheral circuit region constituting the power supply circuit.

[0049] The second transistor TR2 can be designed to operate at a higher voltage than the first transistor TR1. Therefore, the thickness t2 of the second gate insulating film GI2 can be greater than the thickness t1 of the first gate insulating film GI1. In some embodiments, the second gate insulating film GI2 can have a thickness t2 that is 50% or more greater than the thickness t1 of the first gate insulating film GI1. For example, the thickness t1 of the first gate insulating film GI1 can be 2 nanometers (nm) or less, and the thickness t2 of the second gate insulating film GI2 can be in the range of 3 nm to 10 nm.

[0050] Each gate electrode GE may include a doped semiconductor, a conductive metal nitride, and / or a metal. Each gate insulating pattern GI may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high-dielectric film. For example, the second gate insulating film GI2 may include a silicon oxide film and a silicon nitride film located on the silicon oxide film. The high-dielectric film may include a material with a dielectric constant higher than that of the silicon oxide film, such as a hafnium oxide film (HfO), an aluminum oxide film (AlO), or a tantalum oxide film (TaO). Each of the gate spacer GS and the gate cover pattern GP may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0051] like Figure 1 As shown, the first transistor TR1 and the second transistor TR2 are illustrated as transistors of different conductivity types formed in different conductive wells W1 and W2. For example, the first transistor TR1 may be a P-type metal-oxide-semiconductor field-effect transistor (P-MOSFET) formed in an n-type well W1, and the second transistor TR2 may be an N-type metal-oxide-semiconductor field-effect transistor (N-MOSFET) formed in a p-type well W2. However, the inventive concept is not limited thereto. Therefore, in some embodiments, the first transistor TR1 and the second transistor TR2 may comprise transistors of the same conductivity type formed in the same conductive well.

[0052] The first source / drain region SD1 and the second source / drain region SD2 can be epitaxial layers selectively grown using semiconductor layers on the bottom and side surfaces of the active region 104 as seed layers. When the first transistor TR1 is a P-MOSFET, the first source / drain region SD1 can include a material that provides compressive strain to the channel layer CH. For example, the first source / drain region SD1 can include a SiGe layer with a lattice constant greater than that of Si. The first source / drain region SD1 can have P-type conductivity. Conversely, when the first transistor TR1 is an N-MOSFET, the first source / drain region SD1 can include a semiconductor material that provides tensile strain to the channel layer CH. For example, the first source / drain region SD1 can include a SiC layer with a lattice constant smaller than that of Si, or a Si layer with a substantially the same lattice constant as the substrate 101. The first source / drain region SD1 can have N-type conductivity.

[0053] Meanwhile, the second source / drain region SD2 may have the same or similar epitaxial layer as the first source / drain region SD1. For example, the first source / drain region SD1 and the second source / drain region SD2 may include a SiGe epitaxial layer or a silicon phosphide (SiP) epitaxial layer.

[0054] Depending on the composition of the epitaxial layer constituting the second source / drain region SD2, the Ge content distribution of the first semiconductor pattern 151 in the second transistor TR2 in the first direction (e.g., the X direction) can vary. Figure 4B This shows that when the second source / drain region SD2 includes a relatively low Ge content (C SD SiGe epitaxial layer Figure 2B The diagram shows the Ge content distribution of the b1-b2 cross section of the second transistor TR2. Although the Ge content is slightly lower in the region of the first semiconductor pattern 151 adjacent to and in contact with the second source / drain region SD2, it can be seen that the Ge content remains at a relatively high level (e.g., 25% to 35%) in the inner region of the first semiconductor pattern 151. As mentioned above, the Ge content distribution of the first semiconductor pattern 151 in the first direction (e.g., the X direction) can be varied according to the composition of the epitaxial layer constituting the second source / drain region SD2.

[0055] An interlayer insulating film 123 may be disposed on the first source / drain region SD1 and the second source / drain region SD2. A gate structure may be located within the interlayer insulating film 123. The upper surface of the interlayer insulating film 123 may be substantially coplanar with the upper surface of the gate overlay pattern GP. The interlayer insulating film 123 may comprise a silicon oxide film or a silicon oxynitride film.

[0056] The first contact plug CT1 and the second contact plug CT2 are respectively connected (e.g., electrically connected) to the first source / drain region SD1 and the second source / drain region SD2. Figure 1The first contact plug CT1 can be configured to penetrate the interlayer insulating film 123. The first contact plug CT1 can contact the first source / drain region SD1, and the second contact plug CT2 can contact the second source / drain region SD2. The first contact plug CT1 and the second contact plug CT2 can comprise conductive metal nitrides and / or metals. For example, the first contact plug CT1 and the second contact plug CT2 can comprise metal nitrides such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN) and / or metals such as Ti, W, or Ta. In some embodiments, the lower surface of the second contact plug CT2 can be located within a recess in the second source / drain region SD2 and can be at a level below the upper surface of the uppermost second semiconductor pattern 152 in the second semiconductor pattern 152.

[0057] Figure 5A and Figure 5B This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

[0058] Reference Figure 5A and Figure 5B It is understood that, in addition to the introduction of internal spacers IS, the semiconductor device according to the example embodiment and Figure 1 , Figure 2A and Figure 2B The semiconductor device 100 shown is similar. Therefore, unless otherwise specified, reference can be made to the semiconductor device 100 shown. Figure 1 , Figure 2A and Figure 2B The description of the same or similar components of the semiconductor device 100 shown herein is used to understand the meaning. Figure 5A and Figure 5B Components.

[0059] and Figure 1 , Figure 2A and Figure 2B The semiconductor device 100 shown is different. Figure 5A The first transistor shown may include internal spacers IS disposed between each of the first source / drain regions SD1 and the gate electrode GE. The internal spacers IS may be disposed on one side of the gate electrode GE. The internal spacers IS and the channel layers CH may be alternately disposed in a direction perpendicular to the upper surface of the substrate 101. Each of the first source / drain regions SD1 may contact the channel layer CH and may be spaced apart from the gate electrode GE, with the internal spacers IS interposed between each of the first source / drain regions SD1 and the gate electrode GE. A first gate insulating film GI1 may be interposed between the gate electrode GE and each of the channel layers CH, and may extend between the gate electrode GE and each of the internal spacers IS. The channel layers CH may collectively provide the channel region CH1. Each of the internal spacers IS may contact the first gate insulating film GI1.

[0060] and Figure 5A Similar to the first transistor shown in the figure, Figure 5B The second transistor shown may further include an internal spacer IS disposed between each of the second source / drain regions SD2 and the first semiconductor pattern 151. Each of the second source / drain regions SD2 is in contact with the second semiconductor pattern 152, but may be spaced apart from the first semiconductor pattern 151, and the internal spacer IS is interposed between each of the second source / drain regions SD2 and the first semiconductor pattern 151.

[0061] The internal spacer IS (also referred to as the "second internal spacer") of the second transistor can be formed in the same process as the internal spacer IS (also referred to as the "first internal spacer") of the first transistor. The internal spacer layers of the first transistor and the second transistor may include the same insulating material.

[0062] In some example embodiments, a recess is formed in the source / drain (see...). Figure 10 Following this and the epitaxial growth at the source / drain (see...) Figure 11 Previously, the first semiconductor pattern 151 could be formed by selectively etching the first semiconductor pattern 151 locally and filling the etched portion with insulating material, etc.

[0063] Thus, the internal spacer IS can be disposed between multiple channel layers CH on both sides (e.g., opposite sides) of the gate electrode GE in the first direction, and the internal spacer IS can be disposed between multiple second semiconductor patterns 152 on both sides (e.g., opposite sides) of multiple first semiconductor patterns 151 in the first direction. For example, the internal spacer IS may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon carbon oxynitride (SiOCN), silicon carbon boron nitride (SiBCN), and / or silicon oxynitride (SiOC).

[0064] In the following description, a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

[0065] Figures 6 to 11 This is a perspective view illustrating the main processes (specifically, the processes for forming the fin structure and the dummy gate structure) of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. For ease of description, the process will be described by dividing it into main processes focused on the manufacturing processes of the first transistor TR1 and the second transistor TR2.

[0066] Reference Figure 6 A stacked structure ST is formed on a substrate 101 in which a first semiconductor layer 111 and a second semiconductor layer 112 are alternately stacked.

[0067] Substrate 101 may include a first region I and a second region II. For example, the first region I may be a memory cell or a logic region, and the second region II may be a peripheral circuit region such as a power supply circuit. A second semiconductor layer 112 and a first semiconductor layer 111 may be alternately formed on a first semiconductor layer 111 in contact with substrate 101. The uppermost layer of the stacked structure ST may be the second semiconductor layer 112, but is not limited thereto. The first semiconductor layer 111 and the second semiconductor layer 112 may be formed using, for example, epitaxial growth methods, but are not limited thereto.

[0068] The first semiconductor layer 111 and the second semiconductor layer 112 may each comprise materials with different etch selectivity. For example, in the first region I, the first semiconductor layer 111 may serve as a sacrificial layer for forming a gate electrode, and the second semiconductor layer 112 may serve as a channel layer. In this case, even when etching the first semiconductor layer 111, the semiconductor layer 112 may retain almost no etchability. The first semiconductor layer 111 may comprise SiGe, such as SiGe with a Ge content of 25% to 35%. The second semiconductor layer 112 may comprise, for example, one of Si and a group III-V compound semiconductor.

[0069] Subsequently, a first mask pattern M1 and a second mask pattern M2 extending in a first direction (e.g., the X direction) are formed on the stacked structure ST. The first mask pattern M1 and the second mask pattern M2 may be formed from at least one material selected from silicon oxide film, silicon nitride film and silicon oxynitride film.

[0070] Next, refer to Figure 7 The stacked structure ST can be etched using the first mask pattern M1 and the second mask pattern M2 as masks to form the first fin structure AF1 and the second fin structure AF2.

[0071] In an example embodiment, protrusions (or active regions) 104 corresponding to the first fin structure AF1 and the second fin structure AF2 can be formed by etching the stacked structure ST down to a portion of the upper surface of the substrate 101, and an isolation insulating layer 105 can be formed around the protrusions 104. The isolation insulating layer 105 may partially cover the side surfaces of the protrusions 104. The upper surface of the isolation insulating layer 105 may be formed on the substrate 101 as lower than the upper surface of the protrusions 104. That is, the protrusions 104 on the substrate 101 may protrude above the isolation insulating layer 105. The first fin structure AF1 and the second fin structure AF2 may include a first semiconductor pattern 151 and a second semiconductor pattern 152, respectively, alternately stacked in a first region I and a second region II of the substrate 101.

[0072] Subsequently, referring to Figure 8 A semiconductor capping layer 155 can be formed on the second fin structure AF2, and an etch stop layer 131 and a dummy gate layer can be sequentially formed on the first fin structure AF1 and the second fin structure AF2. Subsequently, an etching process is performed using a third mask pattern M3 and a fourth mask pattern M4 to form the first dummy gate electrode DG1 and the second dummy gate electrode DG2.

[0073] The first dummy gate electrode DG1 and the second dummy gate electrode DG2 may intersect with a portion of the first fin structure AF1 and a portion of the second fin structure AF2, respectively, to form the first dummy gate electrode DG1 and the second dummy gate electrode DG2 extending in the second direction Y. In this etching process, the semiconductor capping layer 155 and the etch stop layer 131 may also be patterned together with the first dummy gate electrode DG1 and the second dummy gate electrode DG2.

[0074] like Figure 8 As shown, the lower portion of the second dummy gate electrode DG2 includes a semiconductor capping layer 155 intersecting a portion of the second fin structure AF2. The semiconductor capping layer 155 may be configured to directly contact the upper surface of said portion of the second fin structure AF2 and its two (e.g., opposite) side surfaces in a second direction. The semiconductor capping layer 155 may be formed of the same material as the second semiconductor pattern 152. For example, the semiconductor capping layer 155 may include silicon (Si). For example, the first dummy gate electrode DG1 and the second dummy gate electrode DG2 may be, respectively, polycrystalline silicon and amorphous silicon. For example, the etch stop layer 131 may be formed of at least one layer selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0075] Next, refer to Figure 9 Gate spacers GS can be formed on the sidewalls of the first dummy gate electrode DG1 and the second dummy gate electrode DG2.

[0076] Specifically, a spacer film covering the first dummy gate electrode DG1, the second dummy gate electrode DG2, the first fin structure AF1, and the second fin structure AF2 is formed on the substrate 101. Subsequently, the spacer film can be etched back to form gate spacers GS retained on the sidewalls of the first dummy gate electrode DG1 and the second dummy gate electrode DG2.

[0077] The gate spacer GS may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon oxynitride (SiOCN), and combinations thereof. Figure 9 In the diagram, the gate spacer GS is shown as a single layer, but the inventive concept is not limited thereto and can have a multilayer structure.

[0078] Subsequently, referring to Figure 10The portion of the first fin structure AF1 exposed on both sides (e.g., opposite sides) of the first dummy gate electrode DG1 and the gate spacer GS is removed to form a first recess R1 in the first fin structure AF1. Similarly, the portion of the second fin structure AF2 exposed on both sides (e.g., opposite sides) of the second dummy gate electrode DG2 and the gate spacer GS is removed to form a second recess R2 in the second fin structure AF2.

[0079] In some embodiments, the formation processes of the first recess R1 and the second recess R2 can be performed simultaneously. When forming the first recess R1 and the second recess R2, a portion of the active region 104 in contact with the substrate 101 can be left as an epitaxial seed, but this is not a limitation. Alternatingly stacked first semiconductor patterns 151 and second semiconductor patterns 152 can be exposed through the side surfaces of the first recess R1 and the second recess R2. If desired, an optional etching process for forming internal spacers can also be performed. For example, in the case of the second transistor TR2, after forming the recesses and before forming the first source / drain region SD1 and the second source / drain region SD2, the side surfaces of the first semiconductor pattern 151 can be selectively etched locally, and internal spacers IS can be formed in the etched spaces.

[0080] Next, refer to Figure 11 Epitaxial growth processes can be performed on the first fin structure AF1 and the second fin structure AF2 to fill the first recess R1 and the second recess R2. Epitaxial growth processes for the first recess R1 and the second recess R2 can be performed simultaneously using a single process.

[0081] Epitaxial growth on both sides of the first dummy gate electrode DG1 and the second dummy gate electrode DG2 can provide a first source / drain region SD1 and a second source / drain region SD2. The epitaxial growth process can be performed using the surface of the active region 104 exposed to the bottom surface of the first recess R1 and the second recess R2, and the first semiconductor pattern 151 and the second semiconductor pattern 152 exposed to the side surfaces of the first recess R1 and the second recess R2 as seed layers. The first source / drain region SD1 and the second source / drain region SD2 can have various shapes defined as crystallographically stable surfaces during the growth process. For example, the first source / drain region SD1 and the second source / drain region SD2 can have a pentagonal cross-section. Meanwhile, when the first source / drain region SD1 and the second source / drain region SD2 comprise silicon (Si) and / or silicon carbide (SiC) doped with n-type impurities, the cross-section of the first source / drain region SD1 and the second source / drain region SD2 can be hexagonal or a polygon with gently sloping angles.

[0082] In the following text, reference will be made to Figures 12A to 15B This describes the process for forming a gate structure in a method for manufacturing a semiconductor device according to an example embodiment.

[0083] Specifically, Figure 12A , Figure 13A , Figure 14A and Figure 15A It is a cross-sectional view taken along line A1-A1' and line A2-A2' for each major process, and Figure 12B , Figure 13B , Figure 14B and Figure 15B It is a cross-sectional view taken along line B1-B1' and line B2-B2' for each major process.

[0084] Figure 12A and Figure 12B Showing the target Figure 11 The section shown includes sections taken along lines A1-A1' and A2-A2', as well as sections taken along lines B1-B1' and B2-B2'.

[0085] Reference Figure 12A and Figure 12B The first source / drain region SD1 contacts the side surface of the first fin structure AF1 located in the lower part of the first dummy gate electrode DG1 and the gate spacer GS (i.e., with the first semiconductor pattern 151 and the second semiconductor pattern 152). Similarly, the second source / drain region SD2 contacts the second fin structure AF2 disposed in the lower part of the second dummy gate electrode DG2 and the gate spacer GS.

[0086] At the same time, refer to Figure 12B The etch stop layer 131 can be in direct contact with the first fin structure AF1, but the semiconductor capping layer 155 can be formed to be in direct contact with the second fin structure AF2, and the etch stop layer 131 can be provided on the semiconductor capping layer 155.

[0087] Subsequently, referring to Figure 13A and Figure 13B The interlayer insulating film 123 can be formed to cover the first source / drain region SD1 and the second source / drain region SD2, the first dummy gate electrode DG1 and the second dummy gate electrode DG2 and the gate spacer GS, and then the interlayer insulating film 123 can be planarized until the first dummy gate electrode DG1 and the second dummy gate electrode DG2 are exposed.

[0088] In this planarization process, the third mask pattern M3 and the fourth mask pattern M4 can be removed. The interlayer insulating film 123 may include at least one of a low dielectric constant material, an oxide film, a nitride film, and an oxide nitride film. The low dielectric constant material may include, for example, flexible oxide (FOX), Tonen silazane (TOSZ), undoped silicon glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-reinforced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or combinations thereof.

[0089] Next, refer to Figure 14A and Figure 14B The first dummy gate electrode DG1 and the second dummy gate electrode DG2 can be removed, and the etch stop layer 131 can be selectively removed through the exposed area. Subsequently, a selective etching process is performed on the second semiconductor pattern 152.

[0090] According to this process, such as Figure 14A As shown, a first opening region H1 and a second opening region H2 can be formed between the gate spacers GS. When the side surfaces of the first semiconductor pattern 151 and the second semiconductor pattern 152 of the first fin structure AF1 are exposed through the first opening region H1 in the second direction, the second semiconductor pattern 152 of the second fin structure AF2 is not exposed because it is still covered by the semiconductor capping layer 155 in the second opening region H2.

[0091] In the first region I, the first semiconductor pattern 151 can be removed using an etchant with a higher etching rate for the first semiconductor pattern 151 than for the second semiconductor pattern 152. Multiple spaces h, each corresponding to the first semiconductor pattern 151, can be formed. Consequently, in the first region I, the second semiconductor pattern 152 can provide a channel layer CH by connecting the first source / drain region SD1 in a first direction.

[0092] Alternatively, even when the same etching process is applied to the second region II, the first semiconductor pattern 151 is not exposed by the semiconductor capping layer 155, so that the structure of the second fin structure AF2 can remain unchanged.

[0093] Next, refer to Figure 15A and Figure 15BThe first gate insulating film GI1 can be formed in the first region I along the outer periphery of the second semiconductor pattern 152, the sidewalls of the gate spacer GS, and the exposed first source / drain region SD1. Additionally, the second gate insulating film GI2 can be formed on the surface of the second fin structure AF2 (i.e., the upper surface of the semiconductor capping layer 155 in the second region II and the sidewalls of the gate spacer GS).

[0094] The first gate insulating film GI1 and the second gate insulating film GI2 can be formed conformally, and the first gate insulating film GI1 and the second gate insulating film GI2 can be formed by another insulating film forming process. As mentioned above, the thickness of the second gate insulating film GI2 can be greater than the thickness of the first gate insulating film GI1.

[0095] Subsequently, a gate electrode GE can be formed on the first gate insulating film GI1 and the second gate insulating film GI2 to extend in the second direction Y. Specifically, in the first region I, the gate electrode GE can be formed in the space between the gate spacers GS, the space between the channel layers CH, and the space between the lowermost channel layer CH and the active region 104.

[0096] On the other hand, in the second region II, a gate electrode GE can be formed between the sidewalls of the gate spacer GS. The gate electrode GE can be disposed between the second gate insulating films GI2 and on the upper surface of the fin structure FS, and can extend along the side surface of the fin structure FS in the second direction.

[0097] Figure 16 A cross-sectional view of a semiconductor device according to an example embodiment of the present invention is shown.

[0098] Reference Figure 16 It is understood that, apart from the difference in the structure of the semiconductor capping layer 155', the semiconductor device according to the example embodiment is similar to... Figure 5B The semiconductor device (specifically, the second transistor) shown is similar. Therefore, unless otherwise stated, reference can be made to... Figure 2B and Figure 5B The description of the same or similar components of the semiconductor device (specifically, the second transistor) shown is used to understand the meaning. Figure 16 The components shown in the image.

[0099] The gate spacer GS can be disposed on both side surfaces of the gate electrode GE in the first direction. In some embodiments, the semiconductor capping layer 155' can extend along the inner side surface of the gate spacer GS and the upper and two side surfaces of the fin structure FS. Figure 5BUnlike the semiconductor device shown, no semiconductor capping layer 155' is introduced before the formation of the second dummy gate electrode DG2, and the semiconductor capping layer 155' can be understood as the result of the removal of the second dummy gate electrode DG2 and the etch stop layer 131.

[0100] As described above, according to exemplary embodiments of the present invention, a semiconductor device with a three-dimensional channel structure can be provided that has improved electrical properties.

[0101] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; A fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on the substrate and extending in a first direction; A semiconductor capping layer is located on the upper surface of the fin structure and extends along the opposite side surface of the fin structure in a second direction intersecting the first direction; A gate electrode, which is located on the semiconductor capping layer and extends in the second direction; A gate insulating film is located between the semiconductor capping layer and the gate electrode; as well as Source / drain region, which is connected to one of the side surfaces of the fin structure in the first direction. Wherein, the plurality of first semiconductor patterns include silicon-germanium, and the plurality of second semiconductor patterns include silicon, and Each of the plurality of first semiconductor patterns has a first germanium concentration gradient that increases toward its first center in its vertical thickness direction, and the first germanium content in the first center of each of the plurality of first semiconductor patterns is in a first range of 25% to 35%.

2. The semiconductor device according to claim 1, wherein, The plurality of second semiconductor patterns and the semiconductor capping layer comprise the same semiconductor material.

3. The semiconductor device according to claim 1, wherein, The semiconductor capping layer includes silicon.

4. The semiconductor device according to claim 3, wherein, Each of the plurality of first semiconductor patterns has a second germanium concentration gradient that increases toward its second center in the second direction, and the second germanium content in the second center of each of the plurality of first semiconductor patterns is in a second range of 25% to 35%.

5. The semiconductor device according to claim 1, further comprising: Internal spacers are located on opposite side surfaces of the plurality of first semiconductor patterns in the first direction. The internal spacers are located between the plurality of second semiconductor patterns.

6. The semiconductor device according to claim 5, wherein, The internal spacers include silicon nitride, silicon carbonitride, silicon oxynitride, silicon boron nitride, silicon carbon oxynitride, silicon carbon boron nitride, and / or silicon oxynitride.

7. The semiconductor device according to claim 1, further comprising: Gate spacers are located on opposite side surfaces of the gate electrode in the first direction.

8. The semiconductor device according to claim 7, wherein, The semiconductor capping layer extends between the gate electrode and the inner sidewall of the gate spacer.

9. The semiconductor device according to claim 1, wherein, The gate insulating film includes a silicon oxide film.

10. The semiconductor device according to claim 9, wherein, The gate insulating film also includes a silicon nitride film located on the silicon oxide film.

11. The semiconductor device according to claim 1, wherein, The source / drain region includes a silicon-germanium epitaxial layer or a silicon phosphide epitaxial layer.

12. The semiconductor device of claim 1, further comprising a contact plug connected to the source / drain region.

13. The semiconductor device according to claim 12, wherein, The lower surface of the contact plug is located in the recess of the source / drain region and is at a level below the upper surface of the uppermost of the plurality of second semiconductor patterns.

14. A semiconductor device, comprising: Substrate; A fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on the substrate; A gate electrode is located on the upper surface of the fin structure and extends along the opposite side surface of the fin structure; A gate insulating film is located between the fin structure and the gate electrode; as well as Source / drain regions, which are respectively connected to the opposite side surfaces of the fin structure. The plurality of first semiconductor patterns include silicon and germanium, each of the plurality of first semiconductor patterns having a germanium concentration gradient that increases toward its center along its vertical thickness, and the germanium content at the center of each of the plurality of first semiconductor patterns being in the range of 25% to 35%.

15. The semiconductor device of claim 14, further comprising: A semiconductor capping layer is located between the fin structure and the gate insulating film. The plurality of second semiconductor patterns and the semiconductor capping layer comprise silicon.

16. The semiconductor device of claim 14, further comprising: Internal spacers are located on opposite side surfaces of the plurality of first semiconductor patterns. The internal spacer is adjacent to the source / drain region and is located between the plurality of second semiconductor patterns.

17. A semiconductor device, comprising: Substrate; A first transistor, located in a first region of the substrate, the first transistor comprising: Multiple channel layers are spaced apart from each other in a direction perpendicular to the upper surface of the substrate; A first gate electrode surrounds the plurality of channel layers; A first gate insulating film is located between the plurality of channel layers and the first gate electrode; and First source / drain regions, respectively located on opposite side surfaces of the plurality of channel layers and connected to each of the plurality of channel layers; and A second transistor, located in a second region of the substrate, the second transistor comprising: A fin structure having alternating stacked first semiconductor patterns and multiple second semiconductor patterns; The second gate electrode is located on the upper and side surfaces of the fin structure; A second gate insulating film is located between the fin structure and the second gate electrode; and The second source / drain regions are located on the side surfaces of the fin structure and are connected to the plurality of first semiconductor patterns. The plurality of first semiconductor patterns include silicon-germanium with a germanium content ranging from 25% to 35%, and Each of the plurality of first semiconductor patterns has a germanium concentration gradient that increases toward its center in the said direction.

18. The semiconductor device of claim 17, further comprising: A semiconductor capping layer is located between the fin structure and the second gate insulating film.

19. The semiconductor device according to claim 17, wherein, The thickness of the second gate insulating film is greater than the thickness of the first gate insulating film.

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