Noise amplifier circuit and memory device including the same

Abstract

A noise amplification circuit and a memory device including the noise amplification circuit. A data transmission circuit and a memory device including the data transmission circuit are provided. The data transmission circuit includes: a first regulator, the first regulator is provided with an external voltage to output a first internal voltage; a second regulator, the second regulator is configured in the same manner as the first regulator and is provided with an external voltage to output a second internal voltage; an amplifier, the amplifier is configured to amplify noise between the first internal voltage and the second internal voltage to output an amplified voltage; and a plurality of peripheral circuits, the plurality of peripheral circuits being operated by being provided with the first internal voltage.

Description

Technical Field

[0001] Various embodiments of the present invention generally relate to a noise amplification circuit and a memory device including the noise amplification circuit. Background Art

[0002] The memory device may store, output or erase data using an external voltage. The memory device may include a memory cell array for storing data, a peripheral circuit for performing operations such as a program operation, a read operation or an erase operation, and control logic for controlling the peripheral circuit.

[0003] The peripheral circuit can generate voltages for various operations and includes various circuits for transmitting addresses and data. Because the peripheral circuit operates using an external voltage, when fluctuations occur in the external voltage, jitter occurs during the data transmission operation, thereby reducing the reliability of the peripheral circuit. Summary of the invention

[0004] According to one embodiment, a noise amplification circuit may include: a first regulator, which is provided with an external voltage to output a first internal voltage; a second regulator, which is configured in the same manner as the first regulator and is provided with an external voltage to output a second internal voltage; an amplifier, which is configured to amplify noise between the first internal voltage and the second internal voltage to output an amplified voltage; and a plurality of peripheral circuits, which operate by being provided with the first internal voltage.

[0005] According to one embodiment, a memory device may include: a memory cell array configured to store data; a peripheral circuit configured to program data to the memory cell array, read the stored data, or erase the stored data; and a logic circuit configured to control the peripheral circuit, wherein the peripheral circuit includes an input circuit that switches an external voltage to a first internal voltage and a second internal voltage and receives data through a data pad using the first internal voltage and the second internal voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram showing a general data transmission circuit;

[0007] Figure 2 is a diagram showing data jitter caused by fluctuation of external voltage;

[0008] Figure 3 It is shown Figure 1 The circuit diagram of the noise passing filter is shown;

[0009] Figure 4is a diagram showing a noise amplifying circuit and a data transmission circuit including the noise amplifying circuit according to one embodiment;

[0010] Figure 5 is a detailed circuit diagram showing an LDO according to one embodiment;

[0011] Figure 6 It is shown Figure 4 The circuit diagram of the amplifier shown;

[0012] Figure 7 is a diagram showing a memory device;

[0013] Figure 8 It is shown Figure 7 A diagram of a first embodiment of an input circuit is shown;

[0014] Fig. 9 It is shown Figure 7 A diagram of a second embodiment of an input circuit is shown;

[0015] Fig.10 is a circuit diagram showing a power detector included in an input circuit;

[0016] Fig.11 is a circuit diagram showing a VCDL circuit included in an input circuit; and

[0017] Fig.12 is a diagram showing a memory system. DETAILED DESCRIPTION

[0018] The advantages and features of the present disclosure and methods for implementing the same will become clear from the embodiments described below with reference to the accompanying drawings. However, they may be implemented in different forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the embodiments to those skilled in the art.

[0019] It should be understood that when an element is referred to as being "coupled" or "connected" to a specific element, it may be "directly coupled or connected" to the specific element, or may be "indirectly coupled or connected" to the specific element with intermediate elements therebetween. In the specification, when an element is referred to as "comprising" or "including" a component, it does not exclude other components, but may also include other components, unless a contrary description is specifically given in the context.

[0020] Various embodiments may be directed to a noise amplification circuit capable of compensating for jitter when transmitting data and a memory device including the noise amplification circuit.

[0021] Figure 1 is a diagram showing a general data transmission circuit;

[0022] Reference Figure 1 The data transmission circuit 1000 may include a plurality of circuits 110 to 140 operating with an external voltage VCCE. For example, the data transmission circuit 1000 may include a noise pass filter 110, an amplifier 120, a voltage controlled delay line (VCDL) circuit 130, and a data output component 140.

[0023] When the external voltage VCCE fluctuates, the noise pass filter 110 can detect the fluctuated voltage and output it as noise. For example, the noise pass filter 110 can compare the external voltage VCCE with the reference voltage Vref, and output the voltage difference detected according to the comparison result as the noise voltage Vnf. The noise pass filter 110 may include a capacitor. The reference voltage Vref may be generated by various methods. For example, the reference voltage Vref may be a bandgap voltage or a voltage generated by a reference voltage generating circuit (not shown).

[0024] However, in general, since the capacitor has a large size, the area occupied by the noise passing filter 110 in the area of ​​the data transmission circuit 1000 increases. Figure 3 A circuit for noise passing filter 110 is described.

[0025] The amplifier 120 may operate with the external voltage VCCE and amplify the noise voltage Vnf to output the amplified voltage Vamp. However, since the amplifier 120 operates with the external voltage VCCE directly supplied thereto, when the noise NS1 appears in the external voltage VCCE, the level of the amplified voltage Vamp outputted from the amplifier 120 may become irregular.

[0026] The VCDL circuit 130 can operate with the external voltage VCCE, and control the frequency or delay time of the first clock 1CLK according to the amplified voltage Vamp to output the second clock 2CLK. However, since the VCDL circuit 130 also operates with the external voltage VCCE directly supplied thereto, when the noise NS1 appears in the external voltage VCCE, the second clock 2CLK may be output irregularly.

[0027] The data output component 140 can operate with the external voltage VCCE, receive the first data 1DATA in response to the second clock 2CLK, and output the second data 2DATA. The second data 2DATA can be the amplified first data 1DATA. However, because the data output component 140 also operates with the external voltage VCCE directly supplied thereto, when the noise NS1 appears in the external voltage VCCE, jitter may occur in the data output component 140; therefore, the noise NS2 may appear in the second data 2DATA.

[0028] As described above, since the fluctuation of the external voltage VCCE causes noise NS1 during the data transmission operation, the fluctuation of the external voltage VCCE may also generate noise NS2 to the second data 2DATA finally output from the data transmission circuit 1000. Therefore, the reliability of the device including the data transmission circuit 1000 may be degraded.

[0029] Figure 2 is a diagram showing data jitter caused by fluctuation of external voltage.

[0030] Reference Figure 2 Because the fluctuation of the external voltage VCCE causes noise NS, jitter JT, that is, the change of the data waveform, occurs. When jitter JT occurs, the amplitude or frequency of the data changes. Therefore, noise NS2 appears in the second data 2DATA that is finally output.

[0031] Figure 3 It is shown Figure 1 A circuit diagram of the noise pass filter 110 is shown.

[0032] Reference Figure 3 , the noise pass filter 110 may include a first comparator COM1, a plurality of resistors R1 and R2, and a capacitor CAP. For example, the first comparator COM1 may compare a reference voltage Vref with an external voltage VCCE to output a noise voltage Vnf through a second node N2. The first resistor R1 may be coupled between a terminal to which the reference voltage Vref is applied and the first node N1. The reference voltage Vref may be applied to an input terminal - of the first comparator COM1 through the first resistor R1.

[0033] The external voltage VCCE may be applied to the other input terminal + of the first comparator COM1. The second resistor R2 and the capacitor CAP may be connected in parallel between the first node N1 and the second node N2. The capacitor CAP may perform a function of charging the reference voltage Vref and stably providing the reference voltage Vref to the first comparator COM1. Since the first comparator COM1 compares the reference voltage Vref stably provided thereto with the external voltage VCCE and outputs a voltage difference according to the comparison result, a noise voltage Vnf corresponding to the noise occurring in the external voltage VCCE may be output through the second node N2.

[0034] However, since the capacitor CAP charged with the reference voltage Vref basically includes two electrodes and an insulating layer formed between the electrodes, the capacitor CAP may have a larger size than a general transistor. Therefore, since noise passes through the filter 110, there is a limitation in reducing the size of the data transmission circuit 1000.

[0035] In the following, in order to reduce the increase in size of the data transmission circuit 1000 and reduce the decrease in data reliability due to the noise of the external voltage, Figure 4 The data transmission circuit 2000 to be shown in FIG. 2 may be configured by adopting a voltage regulator instead of the non-noise pass filter 110 .

[0036] Figure 4 is a diagram showing a noise amplifying circuit 2100 according to one embodiment and a data transmission circuit 2000 including the noise amplifying circuit 2100 .

[0037] Reference Figure 4 , the data transmission circuit 2000 may include a noise amplification circuit 2100 , a clock controller 240 , and a data output component 250 .

[0038] The noise amplifying circuit 2100 may include an internal power supply circuit 200 and an amplifier 230 .

[0039] The internal power supply circuit 200 may switch an external voltage VCCE to an internal voltage VCCI, and includes a plurality of regulators 210 and 220 for switching. For example, the regulators 210 and 220 may include a first low dropout regulator (LDO) (LDO1) 210 and a second LDO (LDO2) 220. The LDO may be a DC linear regulator having a smaller size than other DC-DC regulators and having little switching noise.

[0040] According to one embodiment, the internal power supply circuit 200 may include at least two LDOs as described above.

[0041] For example, LDO1 210 may be supplied with external voltage VCCE and switch the supplied external voltage VCCE to output the first internal voltage VCCI1. The first internal voltage VCCI1 may be supplied as a power source for the remaining circuits 230, 240, and 250 except LDO2 220 among the circuits of the data transmission circuit 2000.

[0042] LDO2 220 may be provided with the same external voltage VCCE as the external voltage VCCE provided to LDO1 210, and outputs a second internal voltage VCCI2. LDO2 220 is configured in the same manner as LDO1 210, and operates with the same external voltage VCCE as LDO1 210. Therefore, the second internal voltage VCCI2 may be the same as the first internal voltage VCCI1. For example, the internal power supply circuit 200 may include a plurality of regulators, and the external voltage VCCE may be commonly provided to the regulators to output a plurality of internal voltages based on the external voltage.

[0043] For example, LDO1 210 and LDO2 220 do not include capacitors and thus may be configured to have a ratio Figure 3 The noise passing filter 110 shown in FIG. 1 is smaller in size. In addition, since LDO1 210 and LDO2 220 do not output the first internal voltage VCCI1 and the second internal voltage VCCI2 through the comparator, voltage switching does not occur, and LDO1 210 and LDO2 220 can have smaller switching noise than the noise passing filter 110. Therefore, even when noise NS occurs in the external voltage VCCE, the first internal voltage VCCI1 and the second internal voltage VCCI2 can be uniformly output without being affected by the noise NS. Figure 5 The circuit configurations of LDO1 210 and LDO2 220 are described.

[0044] The amplifier 230 can operate using the first internal voltage VCCI1 and the second internal voltage VCCI2, and amplify the noise between the first internal voltage VCCI1 and the second internal voltage VCCI2 to output the amplified voltage Vamp. For example, when a voltage difference occurs between the first internal voltage VCCI1 and the second internal voltage VCCI2, the voltage difference may become noise. The amplifier 230 can amplify the noise to output the amplified voltage Vamp. In addition, since the second internal voltage VCCI2 is uniformly provided by the LDO2 220, the amplifier 230 can also uniformly output the amplified voltage Vamp. In one embodiment, the first regulator 210 can output the first internal voltage VCCI1, and the first internal voltage VCCI1 can be used as a power supply for the clock controller 240, the data output component 250 and the amplifier 230.

[0045] The clock controller 240 may operate using the first internal voltage VCCI1, control the frequency or delay of the first clock 1CLK according to the amplified voltage Vamp, and output the second clock 2CLK. For example, the clock controller 240 may be implemented as a voltage controlled delay line (VCDL).

[0046] The data output component 250 may operate using the first internal voltage VCCI1, receive the first data 1DATA in response to the second clock 2CLK, and output the second data 2DATA. The second data 2DATA may be the amplified first data 1DATA.

[0047] Since the amplifier 230, the clock controller 240 and the data output component 250 all operate using the first internal voltage VCCI1 from which noise is eliminated, noise in the data output component 250 can also be eliminated so that jitter does not occur. Therefore, the data output component 250 can output the second data 2DATA in which noise is compensated.

[0048] Figure 5 2 is a detailed circuit diagram showing an LDO according to one embodiment. Each of LDO1 210 and LDO2 220 can be configured as follows: Figure 5 The LDO is configured in the same manner as shown.

[0049] Reference Figure 5 , the LDO may include a second comparator COM2 , a plurality of resistors R3 and R4 , and a first switch SW1 .

[0050] The third resistor R3 and the fourth resistor R4 may be connected in series with each other between a third node N3 to which an external voltage VCCE is applied and a ground terminal GND. A voltage divided by the third resistor R3 and the fourth resistor R4 (i.e., a divided voltage) may be applied to a fourth node N4 between the third resistor R3 and the fourth resistor R4. The divided voltage applied to the fourth node N4 may be applied to an input terminal - of the second comparator COM2, and a reference voltage Vref may be applied to another input terminal + of the second comparator COM2.

[0051] The second comparator COM2 may compare the divided voltage with the reference voltage Vref and output the comparison voltage through the fifth node N5 .

[0052] The first switch SW1 may include an NMOS transistor that is coupled between the third node N3 and the sixth node N6 and operates in response to a comparison voltage applied to the fifth node N5. For example, when the external voltage VCCE increases, the divided voltage of the fourth node N4 increases, and when the divided voltage increases, the comparison voltage of the fifth node N5 may be reduced by the second comparator COM2. Because the conduction level of the first switch SW1 decreases when the comparison voltage decreases, the first internal voltage VCCI1 or the second internal voltage VCCI2 output through the sixth node N6 may decrease. Alternatively, in the case where the external voltage VCCE decreases, when the conduction level of the first switch SW1 increases, the first internal voltage VCCI1 or the second internal voltage VCCI2 output through the sixth node N6 may increase. In addition, the first internal voltage VCCI1 or the second internal voltage VCCI2 may be output as a voltage lower than the external voltage VCCE by the threshold voltage of the first switch SW1.

[0053] because Figure 4 Each of LDO1 210 and LDO2 220 shown may be configured in accordance with Figure 5 configured in the same manner as the LDO shown, so the Figure 4 and Figure 5 In the two embodiments shown, each of the first internal voltage VCCI1 and the second internal voltage VCCI2 can be output at the same level. Figure 5 The circuit shown is a basic LDO circuit, so the LDO circuit can be designed in the same way as Figure 5 The circuit shown is configured in different ways.

[0054] Figure 6 It is shown Figure 4 A circuit diagram of amplifier 230 is shown.

[0055] Reference Figure 6 , the amplifier 230 may include fifth and sixth resistors R5 and R6 and a third comparator COM3 .

[0056] The first internal voltage VCCI1 may be applied to the input terminal − of the third comparator COM3 through the fifth resistor R5 , and the second internal voltage VCCI2 may be applied to the input terminal + of the third comparator COM3 through the sixth resistor R6 .

[0057] The third comparator COM3 may compare the first internal voltage VCCI1 and the second internal voltage VCCI2 and amplify a voltage difference between the first internal voltage VCCI1 and the second internal voltage VCCI2 to output an amplified voltage Vamp.

[0058] As described above, since the first internal voltage VCCI1 and the second internal voltage VCCI2 operate in response to the same external voltage VCCE, and Figure 4 As shown, the outputs of LDO1 210 and LDO2 220 are respectively configured to be identical to each other, so the voltage difference between the first internal voltage VCCI1 and the second internal voltage VCCI2 can be very small.

[0059] Therefore, the change of the amplified voltage Vamp output from the amplifier 230 may not be large, so Figure 4 The clock controller 240 shown can output a second clock 2CLK which has almost no difference from the first clock 1CLK, and Figure 4 The data output component 250 shown can output the second data 2DATA without jitter.

[0060] Although the external voltage VCCE fluctuates, the internal power supply circuit 200 can be used in various circuits to mitigate reliability degradation. According to one embodiment, a memory device using the internal power supply circuit 200 as described above will be described below.

[0061] Figure 7 is a diagram showing a memory device 3000;

[0062] Reference Figure 7 The memory device 3000 may include a memory cell array 310 for storing data, peripheral circuits 320, 330, 340, 350 and 360 for performing program operations, read operations and erase operations, and a logic circuit 370 for controlling the peripheral circuits 320, 330, 340, 350 and 360.

[0063] The memory cell array 310 may include volatile memory cells or nonvolatile memory cells.

[0064] The peripheral circuits 320 , 330 , 340 , 350 , and 360 may include a voltage generator 320 , a row decoder 330 , a page buffer group 340 , a column decoder 350 , and an input / output circuit 360 .

[0065] The voltage generator 320 may generate an operation voltage Vop for various operations in response to the operation signal OPS.

[0066] The row decoder 330 may select a memory block or at least one word line included in the memory cell array 310 in response to the row address RADD.

[0067] The page buffer group 340 may temporarily store and transfer data during a program operation or a read operation in response to a page buffer signal PBSIG.

[0068] The column decoder 350 may transfer data between the column lines CL and the page buffer group 340 in response to the column address CADD.

[0069] The input / output circuit 360 may transmit the command CMD and the address ADD received through the data pad DQ to the logic circuit 370, and transmit the data received through the data pad DQ to the column line CL. Alternatively, the input / output circuit 360 may output the data received via the column line CL through the data pad DQ. In addition, the input / output circuit 360 may transmit a data strobe clock to an external device, and receive a data strobe clock from the external device through the data strobe pad DQS. The external device may be a controller that controls the memory device 3000.

[0070] The input / output circuit 360 may include an input circuit Rx and an output circuit Tx for input / output of a command, address, or data. The input circuit Rx may be used when receiving a command, address, and data from an external device. The output circuit Tx may be used when outputting data read from the memory cell array 310 to an external device.

[0071] Since the input circuit Rx and the output circuit Tx should transmit data without error, when jitter may occur, the jitter may become a factor that reduces the reliability of the memory device 3000. Therefore, in order to mitigate the jitter generated due to the change of the external voltage VCCE, each of the input circuit Rx and the output circuit Tx may include Figure 4 The internal power supply circuit 200 is shown.

[0072] In this regard, the input circuit Rx including the internal power supply circuit 200 will be described as an embodiment as follows.

[0073] Figure 8 It is shown Figure 7 FIG. 1 is a diagram of a first embodiment of an input circuit Rx shown in FIG.

[0074] Reference Figure 8 , the input circuit Rx( 1 ) according to the first embodiment may include a noise amplifying circuit 800 , a data buffer 820 , a VCDL circuit 830 , and a first latch LAT1 ( 840 ).

[0075] The noise amplifying circuit 800 may include the internal power supply circuit 200 and a power (PWR) detector 810 .

[0076] The internal power circuit 200 may be supplied with an external voltage VCCE and generate first and second internal voltages VCCI1 and VCCI2. The first and second internal voltages VCCI1 and VCCI2 may be provided as power supplies for the remaining circuits 810, 820, 830, and 840 except the internal power circuit 200.

[0077] The PWR detector 810 may amplify a voltage difference between the first internal voltage VCCI1 and the second internal voltage VCCI2 to output a first amplified voltage Vamp1 and a second amplified voltage Vamp2 .

[0078] The data buffer 820 may operate using the second internal voltage VCCI2 and transmit the data DATA received through the data pad DQ to the VCDL circuit 830. For example, when the width of the data DATA is 8 bits, the data pad DQ may include 8 data pads DQ0 to DQ7 DQ<0:7>.

[0079] The VCDL circuit 830 may operate using the second internal voltage VCCI2 to control a delay time of the data DATA received from the data buffer 820 according to the first amplified voltage Vamp1 and the second amplified voltage Vamp2 to be output to the first latch LAT1 .

[0080] The first latch LAT1 may operate with the second internal voltage VCCI2 and output the data DATA received from the VCDL circuit 830 through the column line CL. The data DATA loaded into the column line CL may be transmitted to the Figure 7 Column decoder 350 is shown.

[0081] Since the input circuit Rx(1) according to the first embodiment supplies power to the internal circuit by using the internal power circuit 200, and the PWR detector 810 compares the first internal voltage VCCI1 and the second internal voltage VCCI2 which are similar to each other and outputs the first amplified voltage Vamp1 and the second amplified voltage Vamp2, the occurrence of jitter can be slowed down while data is transmitted to the column line CL through the data pad DQ, the data buffer 820, the VCDL circuit 830, and the first latch LAT1. Therefore, the reliability of the data DATA transmitted to the column line CL can be improved.

[0082] Fig. 9 It is shown Figure 7 FIG. 2 is a diagram of a second embodiment of an input circuit Rx shown in FIG.

[0083] exist Fig. 9 Detailed Description of the Invention An input circuit Rx(2) according to a second embodiment different from the first embodiment will be shown.

[0084] The input circuit Rx(2) according to the second embodiment can receive data or a data strobe clock through a plurality of data pads DQ0 to DQ3 DQ<0:3> and DQ4 to DQ7 DQ<4:7> and data strobe pads DQS_1 and DQS_2. According to the data pads DQ0 to DQ3 DQ<0:3> and DQ4 to DQ7 DQ<4:7> and the data strobe pads DQS_1 and DQS_2, the circuits included in the input circuit Rx(2) can be classified into a plurality of transmission groups TRG1, TRG2, and TRG3. The circuits included in each of the transmission groups TRG1, TRG2, and TRG3 can be operated in common using the second internal voltage VCCI2 generated from the internal power supply circuit 200. For example, the first transmission group TRG1 may include a circuit for transmitting data input through the data pads DQ0 to DQ3 DQ<0:3>, the second transmission group TRG2 may include a circuit for transmitting a data selection clock input through the data selection pads DQS_1 and DQS_2, and the third transmission group TRG3 may include a circuit for transmitting data input through the data pads DQ4 to DQ7 DQ<4:7>.

[0085] The data DATA0 to DATA3 DATA<0:3> transmitted from the first transmission group TRG1 may be output to the column line CL through the first latch LAT1, and the data DATA4 to DATA7 DATA<4:7> transmitted from the third transmission group TRG3 may be output to the column line CL through the second latch LAT2. The data strobe clock transmitted from the second transmission group TRG 2 may be output to the first latch LAT1 or the second latch LAT2, and the first latch LAT1 or the second latch LAT2 may output the data DATA0 to DATA3 DATA<0:3> or the data DATA4 to DATA7 DATA<4:7> to the column line CL in response to the data strobe clock alternately output from the second transmission group TRG 2.

[0086] The internal power supply circuit 200 may include a first LDO (LDO1) 210 and a second LDO (LDO2) 220. The LDO1 210 may generate a first internal voltage VCCI1 in response to an external voltage VCCE, and the LDO2 220 may generate a second internal voltage VCCI2 in response to the external voltage VCCE. The LDO1 210 and the LDO2 220 are similar to those described above with reference to Figure 5 The circuits described are the same, so their detailed description will be omitted.

[0087] The first internal voltage VCCI1 may be applied to each of the first power (PWR) detector 1PWR Detector, the second PWR detector 2PWR Detector, and the third PWR detector 3PWR Detector included in the first transmission group TRG1, the second transmission group TRG2, and the third transmission group TRG3, respectively. The second internal voltage VCCI2 may be commonly provided to the first transmission group TRG1, the second transmission group TRG2, and the third transmission group TRG3, the first latch LAT1, and the second latch LAT2.

[0088] The first transmission group TRG1 may include a first power detector 1PWR Detector, a first VCDL circuit VCDL1, and a first data buffer DATA Buffer1. The first power detector 1PWR Detector may compare a first internal voltage VCCI1 with a second internal voltage VCCI2, and amplify a voltage difference between the first internal voltage VCCI1 and the second internal voltage VCCI2 to output a first amplified voltage Vamp1 and a second amplified voltage Vamp2. The first data buffer DATABuffer1 may operate with the second internal voltage VCCI2, and transmit data DATA0 to DATA3 DATA<0:3> received from the data pads DQ0 to DQ3 DQ<0:3> to the first VCDL circuit VCDL1. The first VCDL circuit VCDL1 may operate with the second internal voltage VCCI2, and transmit data DATA0 to DATA3 DATA<0:3> received from the first data buffer DATA Buffer1 to the first latch LAT1 in response to the first amplified voltage Vamp1 and the second amplified voltage Vamp2.

[0089] The second transmission group TRG2 may include a second power detector 2PWR Detector, second and third VCDL circuits VCDL2 and VCDL3, and a second data buffer DATA Buffer2. The second power detector 2PWR Detector may compare the first internal voltage VCCI1 and the second internal voltage VCCI2, and amplify the voltage difference between the first internal voltage VCCI1 and the second internal voltage VCCI2 to output a first amplified voltage Vamp1 and a second amplified voltage Vamp2. The second data buffer DATA Buffer2 may operate with the second internal voltage VCCI2, transmit the first data strobe clock L1E received from the first data strobe pad DQS_1 to the second VCDL circuit VCDL2, and transmit the second data strobe clock L2E received from the second data strobe pad DQS_2 to the third VCDL circuit VCDL3. The second data strobe clock and the third data strobe clock may have opposite levels to each other.

[0090] The second VCDL circuit VCDL2 may operate with the second internal voltage VCCI2 and transfer the first data strobe clock L1E received from the second data buffer DATA Buffer2 to the first latch LAT1 in response to the first amplified voltage Vamp1 and the second amplified voltage Vamp2.

[0091] The third VCDL circuit VCDL3 may operate with the second internal voltage VCCI2 and transfer the second data strobe clock L2E received from the second data buffer DATA Buffer2 to the second latch LAT2 in response to the first amplified voltage Vamp1 and the second amplified voltage Vamp2.

[0092] The first latch LAT1 may transfer data DATA0 to DATA3 DATA<0:3> to the column line CL in response to the first data strobe clock L1E. For example, whenever the first data strobe clock L1E has a high level, the first latch LAT1 may transfer data DATA0 to DATA3 DATA<0:3> to the column line CL.

[0093] The second latch LAT2 may transfer data DATA4 to DATA7 DATA<4:7> to the column line CL in response to the second data strobe clock L2E. For example, whenever the second data strobe clock L2E has a high level, the second latch LAT2 may transfer data DATA4 to DATA7 DATA<4:7> to the column line CL.

[0094] The third transmission group TRG3 may include a third power detector 3PWR Detector, a fourth VCDL circuit VCDL4, and a third data buffer DATA Buffer3. The third power detector 3PWR Detector may compare the first internal voltage VCCI1 and the second internal voltage VCCI2, and amplify the voltage difference between the first internal voltage VCCI1 and the second internal voltage VCCI2 to output the first amplified voltage Vamp1 and the second amplified voltage Vamp2. The third data buffer DATABuffer3 may operate with the second internal voltage VCCI2, and transmit the data DATA4 to DATA7 DATA<4:7> received from the data pads DQ4 to DQ7 DQ<4:7> to the fourth VCDL circuit VCDL4. The fourth VCDL circuit VCDL4 may operate with the second internal voltage VCCI2, and transmit the data DATA4 to DATA7 DATA<4:7> received from the third data buffer DATA Buffer3 to the second latch LAT2 in response to the first amplified voltage Vamp1 and the second amplified voltage Vamp2.

[0095] exist Fig. 9 In the input circuit Rx(2) shown, 4-bit data can be transmitted in response to one data strobe clock. However, the number of data bits and the data strobe clock are not limited thereto.

[0096] According to the data pads DQ0 to DQ3 DQ<0:3> and DQ4 to DQ7 DQ<4:7> and the data strobe pads DQS_1 and DQS_2, Fig. 9 The input circuit Rx(2) shown is divided into a first transmission group TRG1, a second transmission group TRG2, and a third transmission group TRG3, and each of the first transmission group TRG1, the second transmission group TRG2, and the third transmission group TRG3 can generate and operate a first amplified voltage Vamp1 and a second amplified voltage Vamp2 in response to a first internal voltage VCCI1 and a second internal voltage VCCI2 generated from an internal power supply circuit 200. Therefore, the occurrence of jitter can be mitigated in the input circuit Rx(2) as described above, compared with a general input circuit in which a plurality of circuits share an amplified voltage during a data transmission operation.

[0097] Will refer to Fig.10 Detailed Description Figure 8 The power detector PWR Detector shown and Fig. 9 The circuit of each of the first power detector 1PWR Detector, the second power detector 2PWR Detector and the third power detector 3PWR Detector shown in FIG. Fig.11The circuit of the VCDL circuit is described in detail.

[0098] Fig.10 is a detailed circuit diagram showing a power detector included in the input circuit.

[0099] Reference Fig.10 The power detector PWR Detector may include a first detection circuit 101, a second detection circuit 102 and a fourth comparator COM4.

[0100] The first detection circuit 101 may output a second sub-internal voltage VCCI_2 in response to the second internal voltage VCCI2 and the enable signal EN. The first detection circuit 101 may include a second switch SW2 and a third switch SW3. The second switch SW2 may include a PMOS transistor that is coupled between the seventh node N7 and the eighth node N8 and transmits the second internal voltage VCCI2 to the eighth node N8 in response to the voltage of the eighth node N8. The third switch SW3 may include a PMOS transistor that is coupled between the eighth node N8 and the ground terminal GND and couples the eighth node N8 and the ground terminal GND together in response to the enable signal EN. According to one embodiment, the enable signal EN may be from Figure 7 The logic circuit 370 output is shown and can be Figure 7 The input / output circuit 360 shown in FIG. 1 is internally generated. Since the conduction level of the third switch SW3 is adjusted according to the level of the enable signal EN, the voltage of the eighth node N8 can also be adjusted. In addition, the conduction level of the second switch SW2 is adjusted according to the voltage of the eighth node N8. Therefore, the voltage of the eighth node N8 can be adjusted in response to the enable signal EN and the level of the second internal voltage VCCI2. Since the enable signal EN has a predetermined voltage, according to this embodiment, the voltage of the eighth node N8 can be adjusted in response to the second internal voltage VCCI2. Therefore, the second sub-internal voltage VCCI_2 can be adjusted.

[0101] The second detection circuit 102 may output the first sub-internal voltage VCCI_1 in response to the first internal voltage VCCI1 and the enable signal EN. The second detection circuit 102 may include a fourth switch SW4 and a fifth switch SW5. The fourth switch SW4 may include a PMOS transistor that is coupled between the ninth node N9 and the tenth node N10 and transmits the first internal voltage VCCI1 to the tenth node N10 according to the voltage of the tenth node N10. The fifth switch SW5 may include a PMOS transistor that is coupled between the tenth node N10 and the ground terminal GND and couples the tenth node N10 and the ground terminal GND together in response to the enable signal EN. The enable signal EN may be the same as the enable signal applied to the first detection circuit 101. Since the conduction level of the fifth switch SW5 is adjusted according to the level of the enable signal EN, the voltage of the tenth node N10 may also be adjusted. In addition, the conduction level of the fourth switch SW4 is adjusted according to the voltage of the tenth node N10. Therefore, the voltage of the tenth node N10 can be adjusted in response to the level of the enable signal EN and the first internal voltage VCCI1. Because the enable signal EN has a predetermined voltage, according to this embodiment, the voltage of the tenth node N10 can be adjusted in response to the first internal voltage VCCI1. Therefore, the first sub-internal voltage VCCI_1 can be adjusted.

[0102] The fourth comparator COM4 can compare the first sub-internal voltage VCCI_1 with the second sub-internal voltage VCCI_2 to output the voltage difference between the first sub-internal voltage VCCI_1 and the second sub-internal voltage VCCI_2 as the first amplified voltage Vamp1, and output the second amplified voltage Vamp2 having an opposite level to the first amplified voltage Vamp1 while outputting the first amplified voltage Vamp1.

[0103] Fig.11 is a circuit diagram showing a VCDL circuit included in an input circuit.

[0104] Reference Fig.11 , the VCDL circuit may operate using the second internal voltage VCCI2, delay the received data DATA and output it. The VCDL circuit according to this embodiment may include a capacitor CAP.

[0105] The capacitor CAP may be connected between a first inverter IN1 that inverts the received data DATA and a second inverter IN2 that inverts the data transmitted from the first inverter IN1 for output. The capacitor CAP may include two electrodes. One electrode may include a PMOS transistor, and the other electrode may include an NMOS transistor. The bulk of the PMOS transistor included in the electrodes of the capacitor CAP may be commonly connected to the sixth switch SW6. The sixth switch SW6 may include a PMOS transistor that transmits the second internal voltage VCCI2 to the bulk of the PMOS transistor in response to the first amplified voltage Vamp1. The bulk of the NMOS transistor included in the electrodes of the capacitor CAP may be commonly connected to the seventh switch SW7. The seventh switch SW7 may include an NMOS transistor that couples the bulk of the NMOS transistor to the ground terminal GND in response to the second amplified voltage Vamp2.

[0106] Because the VCDL circuit provides a predetermined delay to the received data and outputs the delayed data, the circuit can Fig.11 Various structures other than the circuit shown can be implemented.

[0107] Fig.12 is a diagram showing a memory system.

[0108] Reference Fig.12 , the memory device 3000 may be included in a memory system including a controller 3100 and a host 4000 .

[0109] For example, the host 4000 may transmit a request RQ such as a program request, a read request, or an erase request to the controller 3100 , transmit data to the controller 3100 during a program operation, and receive read data during a read operation.

[0110] The controller 3100 may generate a command CMD in response to a request RQ received from the host 4000 , transmit the generated command CMD or address ADD to the memory device 3000 , or output data DATA read from the memory device 3000 to the host 4000 .

[0111] Figure 4 The internal power supply circuit 200 shown may be used not only for the memory device 3000 but also for the controller 3100 or the host 4000 .

[0112] As described above, according to the present disclosure, when data is transmitted, an internal voltage can be stably supplied and jitter can be eliminated.

[0113] Examples of implementations have been disclosed herein, and although specific terms have been used, various changes in form and detail may be made to the examples of implementations described above without departing from the spirit and scope of the present disclosure. Therefore, it should be understood by those skilled in the art that the scope of the present disclosure should not be limited to the examples of implementations described above, and may cover the scope of the following claims and their equivalents.

[0114] CROSS-REFERENCE TO RELATED APPLICATIONS

[0115] This application claims the priority of Korean Patent Application No. 10-2019-0066070 filed on June 4, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A noise amplification circuit, the noise amplification circuit comprising: a first voltage regulator, the first voltage regulator being provided with an external voltage to output a first internal voltage; a second regulator configured in the same manner as the first regulator and supplied with the external voltage to output a second internal voltage; an amplifier configured to amplify noise between the first internal voltage and the second internal voltage to output an amplified voltage; as well as A plurality of peripheral circuits are provided, and the plurality of peripheral circuits operate by being supplied with the first internal voltage.

2. The noise amplifier circuit according to claim 1, wherein: The first internal voltage output from the first regulator is output from the noise amplifying circuit and is received by the amplifier to output the amplified voltage, and The amplifier receives the second internal voltage output from the second regulator.

3. The noise amplifier circuit according to claim 1, wherein: The first regulator includes a low dropout regulator (LDO).

4. The noise amplifier circuit according to claim 3, wherein: The low dropout regulator LDO includes a first switch configured to receive the external voltage and output the first internal voltage to the amplifier.

5. The noise amplifier circuit according to claim 4, wherein: The first switch includes a transistor that is turned on or off in response to a comparison voltage based on a reference voltage and a divided voltage of the external voltage.

6. The noise amplifier circuit according to claim 3, wherein: The low dropout regulator LDO comprises: a first resistor and a second resistor, wherein the first resistor and the second resistor divide the external voltage to output a divided voltage; a first comparator that compares the divided voltage with a reference voltage to output a comparison voltage; and A first switch is configured to output a voltage lower than the external voltage by a threshold voltage as the first internal voltage in response to the comparison voltage.

7. The noise amplification circuit according to claim 6, wherein: coupling a node where the first resistor and the second resistor are coupled together to a first input terminal of the first comparator, and The reference voltage is applied to another input terminal of the first comparator.

8. The noise amplifier circuit according to claim 6, wherein: The first switch includes an NMOS transistor that is turned on or off in response to the comparison voltage.

9. The noise amplifier circuit according to claim 1, wherein: The amplifier includes a second comparator that amplifies a voltage difference between the first internal voltage and the second internal voltage to output the amplified voltage.

10. A memory device, the memory device comprising: a memory cell array configured to store data; a peripheral circuit configured to program data into the memory cell array, read stored data, or erase stored data; as well as a logic circuit configured to control the peripheral circuit, Among them, the peripheral circuit includes an input circuit, which switches an external voltage into a first internal voltage and a second internal voltage, amplifies noise between the first internal voltage and the second internal voltage to output an amplified voltage, and receives data through a data pad using the first internal voltage and the second internal voltage.

11. The memory device according to claim 10, wherein: The peripheral circuit comprises: a voltage generator that generates an operating voltage for various operations in response to an operating signal; a row decoder that selects at least one word line in response to a row address; a page buffer group that temporarily stores and transmits program data or read data in response to a page buffer signal; a column decoder that transfers data between the column lines and the page buffer group in response to a column address; and An input / output circuit includes the input circuit, wherein the input / output circuit transmits and receives data through the data pad, or receives a command and an address from a controller and transmits the command and the address to the logic circuit.

12. The memory device according to claim 11, wherein: The input circuit comprises: an internal power supply circuit including a plurality of regulators configured to commonly receive the external voltage, and the internal power supply circuit is configured to output the first internal voltage and the second internal voltage based on the external voltage; a power detector that amplifies the noise between the first internal voltage and the second internal voltage to output a first amplified voltage and a second amplified voltage; a data buffer that operates with the second internal voltage and receives data through the data pad; a voltage-controlled delay line VCDL circuit that operates with the second internal voltage and controls a delay time of data output from the data buffer in response to the first amplified voltage and the second amplified voltage to output the data; and A latch is provided which operates with the second internal voltage and outputs data received from the voltage controlled delay line VCDL circuit through the column line.

13. The memory device according to claim 12, wherein: The internal power supply circuit comprises: a first regulator, the first regulator being supplied with the external voltage to output the first internal voltage; and A second regulator is configured in the same manner as the first regulator and is supplied with the external voltage to output the second internal voltage.

14. The memory device according to claim 12, wherein: The first amplified voltage and the second amplified voltage are output as voltages having levels opposite to each other.

15. The memory device according to claim 11, wherein: The input circuit comprises: an internal power supply circuit including a plurality of regulators configured to commonly receive the external voltage, and the internal power supply circuit is configured to output the first internal voltage and the second internal voltage based on the external voltage; a first transmission group that receives data from a first data pad among the data pads and outputs the data to a first latch; a second transmission group that receives data from a second data pad among the data pads and outputs the data to a second latch; and A third transmission group receives data strobe clocks from a data strobe pad and transmits each of the data strobe clocks to the first latch or the second latch.

16. The memory device of claim 15, wherein: The internal power supply circuit comprises: a first low dropout regulator LDO, the first low dropout regulator LDO being provided with the external voltage to output the first internal voltage; and a second low dropout regulator LDO configured in the same manner as the first low dropout regulator LDO and supplied with the external voltage to output the second internal voltage.

17. The memory device of claim 15, wherein: The first transmission group includes: a power detector that amplifies a voltage difference between the first internal voltage and the second internal voltage to output a first amplified voltage and a second amplified voltage; a data buffer that operates using the second internal voltage and outputs data received from the first data pad; and A voltage-controlled delay line VCDL circuit operates with the second internal voltage and controls a delay time of data received from the data buffer in response to the first amplified voltage and the second amplified voltage to output the data to the first latch.

18. The memory device of claim 15, wherein: The second transmission group includes: a power detector that amplifies a voltage difference between the first internal voltage and the second internal voltage to output a first amplified voltage and a second amplified voltage; a data buffer that operates using the second internal voltage and outputs data received from the second data pad; and A voltage-controlled delay line VCDL circuit operates with the second internal voltage, controls a delay time of data received from the data buffer in response to the first amplified voltage and the second amplified voltage, and outputs the data to the second latch.

19. The memory device of claim 15, wherein: The third transmission group includes: a power detector that amplifies a voltage difference between the first internal voltage and the second internal voltage to output a first amplified voltage and a second amplified voltage; a data buffer receiving and outputting a first data strobe clock and a second data strobe clock applied to the data strobe pad; a first voltage-controlled delay line VCDL circuit that operates with the second internal voltage and transmits the first data strobe clock to the first latch in response to the first amplified voltage and the second amplified voltage; and A second voltage-controlled delay line VCDL circuit operates with the second internal voltage and transmits the second data strobe clock to the second latch in response to the first amplified voltage and the second amplified voltage.

20. The memory device of claim 19, wherein: The second data strobe clock has a level opposite to that of the first data strobe clock.

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