Memory modules

Abstract

A non-volatile dual in-line memory module (NVDIMM) supporting a DRAM cache mode and an operating method for the NVDIMM are provided. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory for the NVM chip. When the read latency (RL) of the DRAM chip and the write latency (WL) of the NVM chip are consistent with each other, the controller sends a read command to the DRAM chip with reference to the cache address of data requested to be written from the host to the NVM chip, and sends a write command to the NVM chip with reference to the address of the data requested to be written.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 857,562, filed in the U.S. Patent Office on June 5, 2019, and Korean Patent Application No. 10-2019-0112369, filed in the Korean Intellectual Property Office on September 10, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a memory system, and more particularly, to a non-volatile dual inline memory module (NVDIMM) for supporting a dynamic random-access memory (DRAM) cache mode and a method for operating the NVDIMM. Background Art

[0004] In the field of information processing devices such as servers, there is an increasing demand for high-speed access to large amounts of data, such as databases (DBs) in the era of big data. Data loading capacity is a bottleneck in the computing power of information processing devices such as servers that process big data. To further improve the performance of information processing devices, it is conceivable to install large memories on the central processing unit (CPU) memory bus with a high throughput bandwidth.

[0005] A memory module that includes volatile and non-volatile memory mounted on the CPU memory bus is being developed. This type of memory module is called an NVDIMM. An NVDIMM can include a combination of volatile memory (such as DRAM) and flash memory. Alternatively, an NVDIMM can include a combination of DRAM and rewritable 3D cross-point resistive memory.

[0006] NVDIMM combines the high-speed processing technology of DRAM with the large capacity of non-volatile memory. With the growing demand for big data, cloud computing, artificial intelligence (AI), and high-speed networks, NVDIMM is attracting attention. Summary of the Invention

[0007] Embodiments of the present disclosure provide a non-volatile dual in-line memory module (NVDIMM) for supporting a DRAM cache mode and an operating method of the NVDIMM.

[0008] According to one aspect of an example embodiment, a memory module is provided, the memory module including: a first internal data line; a second internal data line; a volatile memory chip connected to the first internal data line; a non-volatile memory chip connected to the second internal data line; a controller connected to the volatile memory chip and the non-volatile memory chip via the first internal data line and the second internal data line, the controller being configured to apply a first command related to first data of the volatile memory chip to the volatile memory chip, and to apply a second command related to second data of the non-volatile memory chip; and a first data buffer connected to the volatile memory chip and the controller via the first internal data line, and to a second data buffer outside the memory module, wherein the controller is further configured to perform control at a time point when a first waiting time of the first command and a second waiting time of the second command coincide with each other, so that: the first data is moved from the volatile memory chip to the non-volatile memory chip, or the second data is moved from the non-volatile memory chip to the volatile memory chip.

[0009] According to one aspect of an example embodiment, a memory module is provided, the memory module including: a first internal data line; a second internal data line; a volatile memory chip connected to the first internal data line; a non-volatile memory chip connected to the second internal data line; a controller connected to the volatile memory chip and the non-volatile memory chip via the first internal data line and the second internal data line, the controller being configured to apply a first command associated with first data of the volatile memory chip to the volatile memory chip at a first time, and to apply a second command associated with second data of the non-volatile memory chip at a second time; and a first data buffer connected to the volatile memory chip and the controller via the first internal data line, the first data buffer being connected to a second data buffer outside the memory module, wherein the controller is further configured to apply a second command to the first internal data line at a second time before the first data is output, and to control the volatile memory chip as a cache memory of the non-volatile memory chip at a time point when a first waiting time of the first command and a second waiting time of the second command coincide with each other.

[0010] According to one aspect of an example embodiment, a method for operating a memory module is provided, the memory module including: a nonvolatile memory chip, a volatile memory chip, and a controller configured to control the volatile memory chip and the nonvolatile memory chip so that the volatile memory chip operates as a cache memory of the nonvolatile memory chip, the operating method including: receiving, by the controller, a write request from a host to the nonvolatile memory chip; sending, by the controller, a first read command to the volatile memory chip with reference to a cache address of first data requested to be written to the nonvolatile memory chip; sending, by the controller, a first write command to the nonvolatile memory chip with reference to a cache address of second data requested to be written; and configuring, by the controller, first data output from the volatile memory chip as second data in response to the first read command, and controlling writing of the second data to the nonvolatile memory chip, wherein, after applying the first read command, a first write command is applied through the first read command before outputting the first data to a first internal data line of the memory module, and the second data is written to the nonvolatile memory chip at a time point at which a read latency of the first read command and a write latency of the first write command coincide with each other.

[0011] According to one aspect of an example embodiment, a method for operating a memory module is provided, the memory module including a nonvolatile memory chip, a volatile memory chip, and a controller configured to control the volatile memory chip and the nonvolatile memory chip so that the volatile memory chip operates as a cache memory of the nonvolatile memory chip, the method comprising: receiving, by the controller, a read request from a host to the nonvolatile memory chip; sending, by the controller, a first read command to the nonvolatile memory chip with reference to an address of first data requested to be read from the nonvolatile memory chip; sending, by the controller, a first write command to the volatile memory chip with reference to a cache address of the first data requested to be read; and configuring, by the controller, second data output from the nonvolatile memory chip as first data associated with the first write command in response to the first read command, and controlling writing of the first data to the volatile memory chip, wherein, after applying the first read command, a first write command is applied by the first read command before outputting the second data to a second internal data line of the memory module, and the first data is written to the volatile memory chip at a time point when a read latency of the first read command and a write latency of the first write command coincide with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects of the example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1is a block diagram illustrating a memory system according to an example embodiment;

[0014] Figure 2 is a diagram illustrating an example of a non-volatile dual in-line memory module (NVDIMM);

[0015] Figure 3 It shows Figure 2 A timing diagram of the NVDIMM operation method in FIG;

[0016] Figure 4 It shows that according to Figure 3 A timing diagram of the NVDIMM process;

[0017] Figure 5 It shows Figure 2 A timing diagram of the NVDIMM operation method in FIG;

[0018] Figure 6 It shows that according to Figure 5 A timing diagram of the NVDIMM process;

[0019] Figure 7 It shows Figure 2 A timing diagram of an operating method of the NVDIMMs (110 and 120);

[0020] Figure 8 It shows that according to Figure 7 A timing diagram of the NVDIMM process;

[0021] Figure 9 It shows Figure 2 A timing diagram of the NVDIMM operation method in FIG;

[0022] Figure 10 It shows that according to Figure 9 A timing diagram of the NVDIMM process;

[0023] Figure 11 and Figure 12 is a diagram of an address structure of an NVDIMM according to an example embodiment; and

[0024] Figure 13 and Figure 14 is used to describe Figure 2 Timing diagram of data movement operations of NVDIMM in . DETAILED DESCRIPTION

[0025] Figure 1 is a block diagram illustrating a memory system 100 according to example embodiments.

[0026] refer to Figure 1, the memory system 100 may include non-volatile dual in-line memory modules (NVDIMMs) 110 and 120 coupled to a host 105. The host 105 can access the NVDIMMs 110 and 120. The host 105 may include a server, a server array or server farm, a web server, a network server, an internet server, a workstation, a minicomputer, a mainframe computer, a network appliance, a distributed computing system, a multi-processor system, a processor-based system, or a combination thereof. The host 105 may include a processor (e.g., a CPU core), a processor cache, and a memory controller that controls the NVDIMMs 110 and 120. In the present embodiment, two NVDIMMs 110 and 120 in the memory system 100 are described. However, the embodiments of the present disclosure are not limited thereto, and the memory system 100 may include various other numbers of memory modules.

[0027] Some examples may be described using expressions such as "connected" and / or "coupled" and their derivatives. These terms are not necessarily synonymous with each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. Additionally, the term "combined" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0028] like Figure 1 As shown, NVDIMMs 110 and 120 may be homogeneous NVDIMMs of the same type. It should be understood that NVDIMMs (110 and 120) are examples and do not limit the scope of technical protection of the claims. According to example embodiments, NVDIMMs 110 and 120 may be heterogeneous NVDIMMs of different types.

[0029] Each of the NVDIMMs 110 and 120 may include a plurality of memory chips, such as a non-volatile memory (NVM) chip 111 and a volatile memory chip 112 (hereinafter referred to as a "dynamic RAM (DRAM) chip"). In addition, each of the NVDIMMs 110 and 120 may include a plurality of data buffers 113 connected to the DRAM chip 112. Each of the data buffers 113 may be implemented as a single chip corresponding one-to-one to the DRAM chip 112. In addition, each of the NVDIMMs 110 and 120 may include a controller (CTRL) 114 connected to the NVM chip 111, the DRAM chip 112, and the data buffers 113. The CTRL 114 may be implemented as a single chip that controls the NVM chip 111, the DRAM chip 112, and the data buffers 113. According to an embodiment, the CTRL 114 may be implemented with multiple chips.

[0030] The NVM chip 111 may include a nonvolatile memory device that stores data in a nonvolatile manner. For example, the NVM chip 111 may include a flash memory device including flash memory cells. Alternatively, the NVM chip 111 may include a memory device including resistive memory cells, such as phase change RAM (PRAM), resistive RAM (RRAM), and magnetic RAM (MRAM).

[0031] DRAM chip 112 may represent a volatile memory device. DRAM chip 112 may include clock-synchronous DRAM, such as synchronous DRAM (SDRAM). For example, DRAM chip 112 may include memory devices such as double data rate (DDR) synchronous DRAM (SDRAM) (DDR SDRAM), low power DDR (LPDDR) SDRAM (LPDR SDRAM), graphics DDR (GDDR) SDRAM (GDDR SDRAM), and RAMbus DRAM (RDRAM).

[0032] The NVDIMMs 110 and 120 may be mounted on DIMM sockets (the DIMM sockets are mounted on the motherboard of the memory system 100) and contact the memory bus 130. The memory bus 130 may be referred to as a signal line formed on the surface of the motherboard or a signal line formed inside the motherboard of the memory system 100. The host 105 may be connected to the NVDIMMs 110 and 120 via the memory bus 130. The memory bus 130 may include a command / address / control (C / A, hereinafter referred to as "CA") bus 132 and a data (DQ) bus 134.

[0033] The command signals, address signals, and / or control signals required for accessing the NVDIMMs 110 and 120 from the host 105 may be transmitted via the CA bus. When the NVDIMM 110 is the target memory module accessed by the host 105, the host 105 may transmit the command signals, address signals, and / or control signals for writing to / reading from the NVDIMM 110 to the NVDIMM 110 via the CA bus 132. When the NVDIMM 120 is the target memory module, the host 105 may transmit the command signals, address signals, and / or control signals for writing to / reading from the NVDIMM 120 to the NVDIMM 120 via the CA bus 132.

[0034] Data transmitted between the host 105 and the NVDIMMs 110 and 120 may be transmitted via the DQ bus 134. When the NVDIMM 110 is the target memory module, the host 105 may transmit data to be written into the NVDIMM 110 to the NVDIMM 110 via the DQ bus 134 and receive data to be read from the NVDIMM 110 via the DQ bus 134. When the NVDIMM 120 is the target memory module, the host 105 may transmit data to be written into the NVDIMM 120 to the NVDIMM 120 via the DQ bus 134 and receive data to be read from the NVDIMM 120 via the DQ bus 134.

[0035] The memory system 100 may include an error correcting code (ECC) engine to correct error bits in signals sent to the NVDIMMs 110 and 120 via the CA bus 132 and error bits in data sent via the DQ bus 134. The ECC engine can be implemented as a hardware circuit comprising a custom very-large-scale integration (VLSI) circuit or an off-the-shelf semiconductor (such as a gate array, logic chip, transistor, and other discrete components). The ECC engine can be implemented with a programmable hardware device (such as a programmable gate array, programmable gate logic, and a programmable gate device). In addition, the ECC engine can be implemented by software including executable code, objects, procedures, or functions. Hereinafter, data sent via the CA bus 132 and / or the DQ bus 134 can be understood as error-corrected data.

[0036] In each of the NVDIMMs 110 and 120, a plurality of DRAM chips 112 may be driven in response to a first chip select signal CS0, and a plurality of NVM chips 111 may be driven in response to a second chip select signal CS1. In an embodiment, a plurality of DRAM chips 112 may be driven in response to the second chip select signal CS1, and a plurality of NVM chips 111 may be driven in response to the first chip select signal CS0.

[0037] When the NVDIMM 110 is the target memory module, the first chip select signal CS0 and the second chip select signal CS1 may be applied from the host 105 to the CTRL 114 via the CA bus 132. When the first chip select signal CS0 is activated, the CTRL 114 may control a write operation to the DRAM chip 112 or a read operation from the DRAM chip 112. When the second chip select signal CS1 is activated, the CTRL 114 may control a write operation to the NVM chip 111 or a read operation from the NVM chip 111.

[0038] When the CTRL 114 of the NVDIMM 110 controls a write operation of the DRAM chip 112 based on the first chip select signal CS0, data to be written to the DRAM chip 112 may be applied to the data buffer 113 via the DQ bus 134. The CTRL 114 may receive the data DQ to be written from the data buffer 113 and provide the received data DQ as the data DQ to be written to the DRAM chip 112. The CTRL 114 may control the writing of the data DQ to be written to the DRAM chip 112. When the CTRL 114 of the NVDIMM 110 controls a read operation of the DRAM chip 112 based on the first chip select signal CS0, the CTRL 114 may control such that the data DQ read from the DRAM chip 112 is sent to the DQ bus 134 via the data buffer 113 and provided to the host 105.

[0039] For example, when the NVM chip 111 of the NVDIMM 110 includes flash memory, the CTRL 114 may include a flash transition layer (FTL) structure and / or a mapping table structure. The CTRL 114 may manage write, read, and erase operations of the NVM chip 111 by using the FTL structure and / or the mapping table structure. The FTL structure may perform an address translation operation that converts an address (e.g., a logical address) provided from the host 105 into a physical address representing the physical location of a memory cell to be actually accessed in the NVM chip 111. The FTL structure may generate a physical address in the conversion operation for the logical address based on a mapping unit of a specific size and provide the generated physical address to the NVM chip 111. The mapping table structure may store mapping information between the logical address from the host 105 and the physical address of the NVM chip 111 corresponding to the logical address. The CTRL 114 may convert the logical address into a physical address with reference to the mapping information. The NVM chip 111 may write (or program) the data DQ to be written to the memory cell corresponding to the physical address.

[0040] When the CTRL 114 of the NVDIMM 110 controls a write operation of the NVM chip 111 based on the second chip select signal CS1, the data DQ to be written to the NVM chip 111 can be provided to the data buffer 113 via the DQ bus 134. The CTRL 114 can convert a logical address provided by the host 105 into a physical address, provide the physical address to the NVM chip 111, and provide the data DQ to be written from the data buffer 113 to the NVM chip 111 as the data DQ to be written. The NVM chip 111 can write (or program) the data DQ to be written to the memory cell corresponding to the physical address. When the CTRL 114 of the NVDIMM 110 controls a read operation of the NVM chip 111 based on the second chip select signal CS1, the CTRL 114 can convert a logical address provided by the host 105 into a physical address, and provide the physical address to the NVM chip 111. The NVM chip 111 can read the data DQ from the memory cell corresponding to the physical address. CTRL 114 may receive data DQ read from NVM chip 111, process the data DQ through a data access unit, and provide the processed data DQ as read data DQ of data buffer 113. CTRL 114 may control the read data DQ of data buffer 113 to be transmitted and provided to host 105 via DQ bus 134.

[0041] Similarly, in NVDIMM 120, multiple DRAM chips 112 can be driven in response to a first chip select signal CS0, and multiple NVM chips 111 can be driven in response to a second chip select signal CS1. When NVDIMM 120 is the target memory module, the first chip select signal CS0 and the second chip select signal CS1 can be applied from host 105 to CTRL 114 via CA bus 132. When the first chip select signal CS0 is activated, CTRL 114 can control write operations to DRAM chips 112 or read operations from DRAM chips 112. When the second chip select signal CS1 is activated, CTRL 114 can control write operations to NVM chips 111 or read operations from NVM chips 111.

[0042] The NVDIMMs 110 and 120 may support a DRAM cache mode, wherein in the DRAM cache mode, the plurality of DRAM chips 112 operate as cache memory for the NVM chip 111. The NVDIMMs 110 and 120 may receive a write request from the NVM chip 111 from the host 105, and when the read latency (RL) of the plurality of DRAM chips 112 matches the write latency (WL) of the NVM chip 111, send a read command to the plurality of DRAM chips 112 with reference to the cache address of the data DQ requested to be written to the NVM chip 111, and send a write command to the NVM chip 111 with reference to the address of the data DQ requested to be written. The NVDIMMs (110 and 120) can receive a read request from the NVM chip 111 from the host 105, and when the WLs of the plurality of DRAM chips 112 match the RLs of the plurality of NVM chips 111, send a read command to the NVM chip 111 with reference to the address of the data DQ requested to be read from the NVM chip 111, and send a write command to the plurality of DRAM chips 112 with reference to the cache address of the data DQ requested to be read. The NVDIMMs 110 and 120 can recover tag information from the address of the data DQ requested to be written to / read from the NVM chip 111, and control the plurality of DRAM chips 112 to operate as cache memory with reference to the recovered tag information.

[0043] Figure 2 is an example diagram illustrating an NVDIMM according to example embodiments.

[0044] refer to Figure 2 , NVDIMMs (e.g., NVDIMMs 110 and 120) may include: NVM chips 111a and 111b; DRAM chips 112a, 112b, 112c, 112d, 112e, 112f, 112g, 112h, 112i, and 112j; data buffers 113a, 113b, 113c, 113d, 113e, 113f, 113g, 113h, 113i, and 113j; and CTRL 114. Data buffers 113a, 113b, 113c, 113d, 113e, 113f, 113g, 113h, 113i, and 113j may be connected to DQ bus 134, and CTRL 114 may be connected to CA bus 132 and coupled to a host (e.g., Figure 1105). CTRL 114 may be connected to DRAM chips 112a to 112j via first internal command address line 201, and to NVM chips 111a and 111b via second internal command address line 202. Additionally, CTRL 114 may be connected to DRAM chips 112a to 112j via first internal data line 203, and to NVM chips 111a and 111b via second internal data line 204.

[0045] CTRL 114 may receive command signals, address signals, and / or control signals from host 105 via CA bus 132. CTRL 114 may determine whether the received command signals, address signals, and / or control signals correspond to NVM chips 111a and 111b or DRAM chips 112a to 112j.

[0046] When the received command signals, address signals, and / or control signals are related to NVM chips 111a and 111b, CTRL 114 may transmit the command signals, address signals, and / or control signals related to the NVM chips to NVM chips 111a and 111b via second internal command and address lines 202. In this case, second internal command and address lines 202 may include a second chip select signal CS1 line, and second chip select signal CS1 may be in an active state. In response to a write command and address received via second internal command and address lines 202, NVM chips 111a and 111b may receive write data to be written to NVM chips 111a and 111b via second internal data lines 204. In response to a read command and address received via second internal command and address lines 202, NVM chips 111a and 111b may output read data read from NVM chips 111a and 111b to second internal data lines 204. Read data read from NVM chips 111a and 111b may exhibit non-deterministic characteristics, such as a varying read latency distribution. The total data read latency of NVM chips 111a and 111b may vary widely, but widely varying read latencies are unacceptable. Therefore, CTRL 114 may include an NVM buffer 116, wherein NVM buffer 116 is configured such that, after considering a deterministic upper bound on the read latency of NVM chips 111a and 111b, the read latency of NVM chips 111a and 111b has a constant, deterministic characteristic. In some embodiments, NVM buffer 116 is coupled to external buffer 117 via data lines and control lines. External buffer 117 is coupled to CA bus 132 via control lines and to data bus 134 via data lines. In some embodiments, NVDIMMs 110 and 120 may include an NVM controller that controls NVM chips 111a and 111b separately from CTRL 114. NVM buffer 116 may be included in the NVM controller. It is assumed that the read data read from the NVM chips 111a and 111b to be described below have a uniform read latency through the NVM buffer 116. Note that the timing diagrams ( Figure 3 、 5 , 7, 9, 13 and 14) are not necessarily drawn to scale.

[0047] When the received command signal, address signal, and / or control signal is related to the DRAM chips 112a to 112j, the CTRL 114 can transmit the command signal, address signal, and / or control signal related to the DRAM chips to the DRAM chips 112a to 112j via the first internal command address line 201. In this case, the first internal command address line 201 may include a first chip select signal CS0 line, and the first chip select signal CS0 may be in an active state. In response to the write command and address received via the first internal command address line 201, the DRAM chips 112a to 112j can receive write data to be written to the DRAM chips 112a to 112j via the first internal data line 203. In response to the read command and address received via the first internal command address line 201, the DRAM chips 112a to 112j can output read data to be read from the DRAM chips 112a to 112j via the first internal data line 203.

[0048] Figure 3 It shows Figure 2 A timing diagram of the operation method of the NVDIMMs 110 and 120 in FIG. Figure 3 In which the host (for example, Figure 1 The timing diagram of the host 105 and the NVDIMMs 110 and 120 operating based on the clock signal CK according to the communication protocol or standard shows a timing diagram of responding to a write request from the host 105 to the NVM chip 111. In the following, it is assumed that the write request to the NVDIMM 110 occurs at Figure 1 NVDIMMs 110 and 120 of the memory system 100.

[0049] refer to Figure 2 and 3 , NVDIMM 110 may receive a write request from host 105 to NVM chip 111. Typically, host 105 may verify whether the data segment requested to be written to NVM chip 111 is in a state of being cached in DRAM chip 112. After host 105 verifies whether a cache hit has occurred, in the case of a cache hit, host 105 may send a cache flush request to DRAM chip 112.

[0050] However, in this embodiment, the host 105 may not need to verify whether a cache hit has occurred. In other words, the host 105 can issue a write request without determining the cache status (such as cache hit and cache miss) of the DRAM chip 112. The CTRL 114 of the NVDIMM 110 can then receive the write request from the host 105 to the NVM chip 111.

[0051] At time point T1, CTRL 114 may read a cache area corresponding to a cache address of data requested to be written to NVM chip 111 in DRAM chip 112. To this end, CTRL 114 may receive an activate command ACT associated with DRAM chip 112 with reference to the cache address (e.g., a row address) via CA bus 132. DRAM chip 112 may receive the cache address and activate command ACT from CTRL 114 via first internal command address line 201, and perform a row activate operation in response to the cache address and activate command ACT.

[0052] At time point T2, CTRL 114 may receive a read command RD related to DRAM chip 112 with reference to a cache address (e.g., a column address) via CA bus 132. DRAM chip 112 may receive the cache address and read command RD from CTRL 114 via the first internal command address line 201, and perform a read operation in response to the cache address and read command RD. DRAM chip 112 may perform a read operation after a read wait time RL from the time point at which the read command RD has been received, and output read data RD_DATA. The read data RD_DATA output from DRAM chip 112 may be provided to CTRL 114 via the first internal data line 203 of NVDIMM 110. In this case, CTRL 114 may control the read data RD_DATA output from DRAM chip 112 via data buffer 113 not to be provided to DQ bus 134.

[0053] In an interval in which the active command ACT at the time point T1 and the read command RD at the time point T2 are applied to the DRAM chip 112 , the first chip select signal CS0 line among the first internal command address lines 201 may be provided in an active state.

[0054] At time point T3, CTRL 114 may receive an address XADR of data requested to be written to NVM chip 111 via CA bus 132. NVM chip 111 may receive address XADR from CTRL 114 via second internal command address line 202. For ease of description, an "X" indicator may be intended to be associated with NVM chip 111. For example, address XADR, commands (XWR and XRD), signals (XR_RDY and XR_SEND), and data XRD_DATA associated with NVM chip 111 may include an "X" indicator.

[0055] At time point T4, CTRL 114 may receive a first write command XWR associated with NVM chip 111 via CA bus 132. The first write command XWR may be applied via read command RD before the operation of outputting read data RD_DATA of DRAM chip 112 to first internal data line 203 is completed. NVM chip 111 may receive the first write command XWR from CTRL 114 via second internal command address line 202 and perform a write operation in response to address XADR and the first write command XWR. NVM chip 111 may perform the write operation after a first write wait time XWL from the time point when the first write command XWR is received.

[0056] At time point T5, CTRL 114 may configure the read data RD_DATA of DRAM chip 112 provided via first internal data line 203 as write data WR_DATA, and provide the second write data WR_DATA to NVM chip 111 via second internal data line 204. NVM chip 111 may write data XWR_DATA to the memory cell corresponding to address XADR. In other words, CTRL 114 may refresh the read data RD_DATA of DRAM chip 112 to NVM chip 111.

[0057] In the interval in which the address XADR at time point T3, the first write command XWR at time point T4, and the first write data XWR_DATA at time point T5 are applied to the NVM chip 111, the second chip selection signal CS1 line among the second internal command address lines 202 may be provided in an activated state.

[0058] In this case, time point T5 may be a time point at which read data RD_DATA is output to first internal data line 203 after a read wait time RL from a time point at which read command RD is received, and may be configured to coincide with a time point at which NVM chip 111 performs a write operation after a first write wait time XWL from a time point at which first write command XWR is received. Thus, read data RD_DATA of DRAM chip 112 may be directly transmitted to NVM chip 111 via internal data line 203 as first write data XWR_DATA of NVM chip 111, and may be refreshed.

[0059] At time point T6, the CTRL 114 may receive a second write command WR via the CA bus 132. The DRAM chip 112 may receive the cache address and the second write command WR from the CTRL 114 via the first internal command address line 201 and perform a write operation in response to the cache address and the second write command WR. The DRAM chip 112 may perform the write operation after a second write wait time WL from the time point when the second write command WR has been received.

[0060] At time point T7, the CTRL 114 may receive the second write request data WR_DATA via the DQ bus 134. After a second write wait time WL from the time point when the second write command WR has been received, the DRAM chip 112 may receive the requested second write data WR_DATA via the first internal data line 203 and write the requested second write data WR_DATA into the memory cell corresponding to the cache address.

[0061] In the aforementioned caching operation of the NVDIMM 110, it will be appreciated that the interval between time point T1 and time point T6 does not carry any data DQs related to the caching operation on the DQ bus 134. The host 105 can be aware that during the period between time point T1 and time point T6, no data DQs related to the caching operation of the NVDIMM 110 are loaded onto the DQ bus 134. During this interval, the host 105 can use the DQ bus 134 to perform data transactions with other devices connected to the DQ bus 134. As used herein, the term "other device" connected to the DQ bus 134 can be any one or a combination of various structures (e.g., one or more circuits, one or more dies, one or more modules, one or more devices, one or more systems). Therefore, even during the caching operation of the NVDIMM 110, the host 105 can effectively use the DQ bus 134.

[0062] Figure 4 It shows that according to Figure 3 FIG. 1 is a timing diagram of the process of the NVDIMM 110.

[0063] Combine Figure 2 and Figure 3 refer to Figure 4 , the host 105 can issue a write request to the NVM chip 111 of the NVDIMM 110 .

[0064] An active command ACT may be provided from the host 105 to the DRAM chip 112 (S41). The host 105 may provide the DRAM chip 112 with a cache address of data requested to be written into the NVM chip 111, along with the active command ACT.

[0065] A read command RD may be provided from the host 105 to the DRAM chip 112 (S42). The host 105 may provide the cache address of the DRAM chip 112 together with the read command RD to the DRAM chip 112. The DRAM chip 112 may perform a read operation in response to the cache address and the read command RD. The DRAM chip 112 may perform the read operation after a read latency RL from the time point when the read command RD has been received, and output read data RD_DATA.

[0066] An address XADR of data requested to be written into the NVM chip 111 may be provided from the host 105 to the NVM chip 111 ( S43 ).

[0067] A first write command XWR may be provided from the host 105 to the NVM chip 111 (S44). The NVM chip 111 may perform a write operation in response to the address XADR and the first write command XWR. The NVM chip 111 may perform the write operation after a first write wait time XWL from the time point when the first write command XWR has been received.

[0068] The time point at which the DRAM chip 112 outputs the read data RD_DATA to the first internal data line 203 of the NVDIMM 110 after the read wait time RL from the time point at which the read command RD has been received in operation S42, and the time point at which the NVM chip 111 performs the write operation after the first write wait time XWL from the time point at which the first write command XWR has been received in operation S44 can be configured to match each other.

[0069] The read data RD_DATA of the DRAM chip 112 may be provided to the NVM chip 111 via the second internal data line 204 (S45). The NVM chip 111 may write the received read data RD_DATA as the first write data XWR_DATA.

[0070] A second write command WR may be provided from the host 105 to the DRAM chip 112 (S46). The DRAM chip 112 may perform a write operation in response to the second write command WR. The DRAM chip 112 may perform the write operation after a second write wait time WL from the time point at which the second write command WR has been received.

[0071] The second write data WR_DATA requested to be written to the NVM chip 111 may be provided from the host 105 to the DRAM chip 112 (S47). The DRAM chip 112 may write the second write data WR_DATA requested to be written after a second write wait time WL from the time point when the second write command WR has been received.

[0072] Figure 5 It shows Figure 2 A timing diagram of the operating method of the NVDIMMs 110 and 120 in FIG. Figure 5 Cache line refresh operations are shown performed in an interleaved manner between the DRAM chip 112 and the NVM chip 111 and associated with write requests from the host 105 to the NVM chip 111 of the NVDIMM 110 .

[0073] In an example embodiment, the amount of data associated with a refresh operation can be represented by the number of data blocks. A data block can be the amount of data transferred between DRAM chip 112 and NVM chip 111. In addition, a data block can be an ECC execution unit used to correct error bits in CTRL 114. For example, a read command RD to DRAM chip 112 can be associated with four data blocks in a write request to NVM chip 111. Therefore, for a cache line refresh operation associated with these four data blocks, host 105 can provide first to fourth read commands RD1 to RD4 to DRAM chip 112, and provide first to fourth write commands XWR1 to XWR4 to NVM chip 111.

[0074] refer to Figure 2 and Figure 5 , the CTRL 114 of the NVDIMM 110 may receive a write request from the host 105 to the NVM chip 111 .

[0075] At time T1, CTRL 114 may receive an activation command ACT associated with DRAM chip 112 via CA bus 132 by referencing the cache address of the data requested to be written to NVM chip 111 in DRAM chip 112, thereby reading the cache area corresponding to the cache address. DRAM chip 112 may receive the cache address and activation command ACT from CTRL 114 via first internal command address line 201, and perform a row activation operation in response to the cache address and activation command ACT. In this case, the first chip select signal CS0 line among the first internal command address lines 201 may be provided to DRAM chip 112 in an active state.

[0076] At time point T2a, CTRL 114 may receive an address XADR of data requested to be written to NVM chip 111 via CA bus 132. NVM chip 111 may receive address XADR from CTRL 114 via second internal command address line 202. In this case, a second chip select signal CS1 line among second internal command address lines 202 may be provided to NVM chip 111 in an active state.

[0077] At time T3_1, CTRL 114 may receive a first read command RD1 associated with DRAM chip 112 via CA bus 132, referring to the cache address. DRAM chip 112 may receive the cache address and first read command RD1 from CTRL 114 via first internal command address line 201 and perform a read operation in response to the cache address and read command RD1. DRAM chip 112 may perform a read operation and output first read data RD_DATA after a read latency RL from the time the first read command RD1 was received. The first read data RD1_DATA output from DRAM chip 112 may be provided to CTRL 114 via first internal data line 203. In this case, CTRL 114 may control, via data buffer 113, the first read data RD1_DATA on first internal data line 203 from being provided to DQ bus 134.

[0078] At time T4_1, CTRL 114 may receive a first write command XWR1 associated with NVM chip 111 via CA bus 132. The first write command XWR1 may be applied via the first read command RD1 before the operation of outputting the first read data RD1_DATA of DRAM chip 112 to first internal data line 203 is completed. NVM chip 111 may receive the first write command XWR1 from CTRL 114 via second internal command address line 202 and perform a write operation in response to the address XADR and the first write command XWR1. NVM chip 111 may perform the write operation after a write wait time XWL from the time the first write command XWR1 is received.

[0079] At time point T5_1, CTRL 114 may configure the first read data RD1_DATA of DRAM chip 112 provided via first internal data line 203 as a first data block, configure the first read data RD1_DATA as first write data XWR1_DATA, and provide the first write data XWR1_DATA to NVM chip 111. In other words, CTRL 114 may refresh the first read data RD1_DATA of DRAM chip 112 as first write data XWR1_DATA to NVM chip 111 via second internal data line 204. NVM chip 111 may write the first write data XWR1_DATA into a memory cell associated with address XADR of the data requested to be written.

[0080] At time point T3_2, CTRL 114 may receive a second read command RD2 associated with DRAM chip 112 via CA bus 132, with reference to the cache address. Command XWR2 is received at time point T4_2. At time point T5_2, events similar to those at time point T5_1 (data provided to NVM chip 111) occur. DRAM chip 112 may receive the cache address and the second read command RD2 from CTRL 114 via first internal command address line 201 and perform a read operation in response to the cache address and the second read command RD2. DRAM chip 112 may perform the read operation and output second read data RD2_DATA after a read latency RL from the time point at which the second read command RD2 was received. The second read data RD2_DATA output from DRAM chip 112 may be provided to CTRL 114 via first internal data line 203. In this case, CTRL 114 may control, via data buffer 113, that the second read data RD2_DATA on first internal data line 203 is not provided to DQ bus 134.

[0081] At time point T4_2, CTRL 114 may receive a second write command XWR2 associated with NVM chip 111 via CA bus 132. The second write command XWR2 may be applied via second read command RD2 before the operation of outputting second read data RD2_DATA of DRAM chip 112 to first internal data line 203 is completed. NVM chip 111 may receive the second write command XWR2 from CTRL 114 via second internal command address line 202 and perform a write operation in response to address XADR and the second write command XWR2. NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the second write command XWR2 is received.

[0082] At time point T5_2, CTRL 114 may configure the second read data RD2_DATA of DRAM chip 112 provided via first internal data line 203 as a second data block, configure the second read data RD2_DATA as second write data XWR2_DATA, and provide the second write data XWR2_DATA to NVM chip 111. In other words, CTRL 114 may refresh the second read data RD2_DATA of DRAM chip 112 as second write data XWR2_DATA to NVM chip 111 via second internal data line 204. NVM chip 111 may write the second write data XWR2_DATA into a memory cell associated with address XADR of the data requested to be written.

[0083] At time T3_3, CTRL 114 may receive a third read command RD3 associated with DRAM chip 112 via CA bus 132, referring to the cache address. DRAM chip 112 may receive the cache address and third read command RD3 from CTRL 114 via first internal command address line 201 and perform a read operation in response to the cache address and third read command RD3. DRAM chip 112 may perform the read operation and output third read data RD3_DATA after a read latency RL from the time the third read command RD3 was received. The third read data RD3_DATA output from DRAM chip 112 may be provided to CTRL 114 via first internal data line 203. In this case, CTRL 114 may control, via data buffer 113, that the third read data RD3_DATA on first internal data line 203 is not provided to DQ bus 134.

[0084] At time point T4_3, CTRL 114 may receive a third write command XWR3 associated with NVM chip 111 via CA bus 132. The third write command XWR3 may be applied via third read command RD3 before the operation of outputting third read data RD3_DATA of DRAM chip 112 to first internal data line 203 is completed. NVM chip 111 may receive the third write command XWR3 from CTRL 114 via second internal command address line 202 and perform a write operation in response to address XADR and the third write command XWR3. NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the third write command XWR3 is received.

[0085] At time point T5_3, CTRL 114 may configure the third read data RD3_DATA of DRAM chip 112 provided via first internal data line 203 as a third data block, configure the third read data RD3_DATA as third write data XWR3_DATA, and provide the third write data XWR3_DATA to NVM chip 111. In other words, CTRL 114 may refresh the third read data RD3_DATA of DRAM chip 112 as third write data XWR3_DATA to NVM chip 111 via second internal data line 204. NVM chip 111 may write the third write data XWR3_DATA into a memory cell associated with address XADR of the data requested to be written.

[0086] At time point T3_4, CTRL 114 may receive a fourth read command RD4 associated with DRAM chip 112 via CA bus 132, with reference to the cache address. DRAM chip 112 may receive the cache address and fourth read command RD4 from CTRL 114 via first internal command address line 201 and perform a read operation in response to the cache address and fourth read command RD4. DRAM chip 112 may perform the read operation and output fourth read data RD4_DATA after a read latency RL has elapsed since receiving fourth read command RD4. The fourth read data RD4_DATA output from DRAM chip 112 may be provided to CTRL 114 via first internal data line 203. In this case, CTRL 114 may control, via data buffer 113, that the fourth read data RD4_DATA on first internal data line 203 is not provided to DQ bus 134.

[0087] At time point T4_4, CTRL 114 may receive a fourth write command XWR4 associated with NVM chip 111 via CA bus 132. The fourth write command XWR4 may be applied via fourth read command RD4 before the operation of outputting fourth read data RD4_DATA of DRAM chip 112 to first internal data line 203 is completed. NVM chip 111 may receive the fourth write command XWR4 from CTRL 114 via second internal command address line 202 and perform a write operation in response to address XADR and the fourth write command XWR4. NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the fourth write command XWR4 is received.

[0088] At time point T5_4, CTRL 114 may configure the fourth read data RD4_DATA of DRAM chip 112 provided via first internal data line 203 as a fourth data block, configure the fourth read data RD4_DATA as fourth write data XWR4_DATA, and provide the fourth write data XWR4_DATA to NVM chip 111. In other words, CTRL 114 may refresh the fourth read data RD4_DATA of DRAM chip 112 as fourth write data XWR4_DATA to NVM chip 111 via second internal data line 204. NVM chip 111 may write the fourth write data XWR4_DATA into a memory cell associated with address XADR of the data requested to be written.

[0089] As described above, in a cache line refresh operation that is performed in an interleaved manner between the DRAM chip 112 and the NVM chip 111 and is associated with a write request from the host 105 to the NVM chip 111 of the NVDIMM 110, the DQ bus 134 may not be loaded with any data DQ associated with the cache line refresh operation. During an interval in which no data DQ associated with the cache line refresh operation of the NVDIMM 110 is loaded on the DQ bus 134, the host 105 may perform data transaction operations with (a plurality of) other devices connected to the DQ bus 134. Therefore, even in an interleaved cache line refresh operation of the NVDIMM 110, the DQ bus 134 may be effectively utilized.

[0090] Figure 6 It shows that according to Figure 5 FIG. 1 is a timing diagram of the process of the NVDIMM 110.

[0091] Combine Figure 2 and Figure 5 refer to Figure 6 , the NVDIMM 110 may be associated with a write request from the host 105 to the NVM chip 111 and may perform cache line refresh operations in an interleaved manner between the DRAM chip 112 and the NVM chip 111 .

[0092] An active command ACT may be provided from the host 105 to the DRAM chip 112 (S61). The host 105 may provide the DRAM chip 112 with a cache address of data requested to be written into the NVM chip 111, along with the active command ACT.

[0093] An address XADR of data requested to be written into the NVM chip 111 may be provided from the host 105 to the NVM chip 111 ( S62 ).

[0094] A first read command RD1 may be provided from the host 105 to the DRAM chip 112 (S63). The host 105 may provide the first cache address of the DRAM chip 112 together with the first read command RD1 to the DRAM chip 112. The DRAM chip 112 may perform a read operation in response to the first cache address and the first read command RD1. The DRAM chip 112 may perform the read operation and output the first read data RD_DATA after a read latency RL from the time point when the first read command RD1 has been received.

[0095] A first write command XWR1 may be provided from the host 105 to the NVM chip 111 (S64). The NVM chip 111 may perform a write operation in response to the address XADR and the first write command XWR1. The NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the first write command XWR1 has been received.

[0096] When the time point at which the DRAM chip 112 outputs the first read data RD1_DATA to the CTRL 114 via the first internal data line 203 after the read latency RL from the time point at which the first read command RD1 has been received and the time point at which the NVM chip 111 performs a write operation after the write latency time from the time point at which the first write command XWR has been received match each other, the CTRL 114 may provide the first read data RD1_DATA of the DRAM chip 112 to the NVM chip 111 via the second internal data line 204 (S65). The NVM chip 111 may write the received first read data RD1_DATA as the first write data XWR1_DATA.

[0097] A second read command RD2 may be provided from the host 105 to the DRAM chip 112 (S66). The host 105 may provide the second cache address of the DRAM chip 112 together with the second read command RD2 to the DRAM chip 112. The DRAM chip 112 may perform a read operation in response to the second cache address and the second read command RD2. The DRAM chip 112 may perform the read operation and output the second read data RD2_DATA after a read latency RL from the time point when the second read command RD2 has been received.

[0098] A second write command XWR2 may be provided from the host 105 to the NVM chip 111 (S67). The NVM chip 111 may perform a write operation in response to the address XADR and the second write command XWR2. The NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the second write command XWR2 has been received.

[0099] When the time point at which the DRAM chip 112 outputs the second read data RD2_DATA to the CTRL 114 via the first internal data line 203 after the read wait time RL from the time point at which the second read command RD2 has been received and the time point at which the NVM chip 111 performs a write operation after the write wait time XWL from the time point at which the second write command XWR2 has been received match each other, the CTRL 114 may provide the second read data RD2_DATA of the DRAM chip 112 to the NVM chip 111 via the second internal data line 204 (S68). The NVM chip 111 may write the received second read data RD2_DATA as the second write data XWR2_DATA.

[0100] The host 105 may provide a third read command RD3 to the DRAM chip 112 (S69). The host 105 may provide the third cache address of the DRAM chip 112 together with the third read command RD3 to the DRAM chip 112. The DRAM chip 112 may perform a read operation in response to the third cache address and the third read command RD3. The DRAM chip 112 may perform a read operation and output third read data RD3_DATA after a read latency RL from the time point when the third read command RD3 has been received.

[0101] The host 105 may provide a third write command XWR3 to the NVM chip 111 (S70). The NVM chip 111 may perform a write operation in response to the address XADR and the third write command XWR3. The NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the third write command XWR3 has been received.

[0102] When the time point at which the DRAM chip 112 outputs the third read data RD3_DATA to the CTRL 114 via the first internal data line 203 after the read wait time RL from the time point at which the third read command RD3 has been received and the time point at which the NVM chip 111 performs a write operation after the write wait time XWL from the time point at which the third write command XWR3 has been received match each other, the CTRL 114 may provide the third read data RD3_DATA of the DRAM chip 112 to the NVM chip 111 via the second internal data line 204 (S71). The NVM chip 111 may write the received third read data RD3_DATA as the third write data XWR3_DATA.

[0103] A fourth read command RD4 may be provided from the host 105 to the DRAM chip 112 (S72). The host 105 may provide the fourth cache address of the DRAM chip 112 together with the fourth read command RD4 to the DRAM chip 112. The DRAM chip 112 may perform a read operation in response to the fourth cache address and the fourth read command RD4. The DRAM chip 112 may perform a read operation and output fourth read data RD4_DATA after a read latency RL from the time point at which the fourth read command RD4 has been received.

[0104] A fourth write command XWR4 may be provided from the host 105 to the NVM chip 111 (S73). The NVM chip 111 may perform a write operation in response to the address XADR and the fourth write command XWR4. The NVM chip 111 may perform the write operation after a write wait time XWL from the time point when the fourth write command XWR4 has been received.

[0105] When the time point at which the DRAM chip 112 outputs the fourth read data RD4_DATA to the CTRL 114 via the first internal data line 203 after the read wait time RL from the time point at which the fourth read command RD4 has been received and the time point at which the NVM chip 111 performs a write operation after the write wait time XWL from the time point at which the fourth write command XWR4 has been received match each other, the CTRL 114 may provide the fourth read data RD4_DATA of the DRAM chip 112 to the NVM chip 111 via the second internal data line 204 (S74). The NVM chip 111 may write the received fourth read data RD4_DATA as the fourth write data XWR4_DATA.

[0106] Figure 7 It shows Figure 2 A timing diagram of an operation method of the NVDIMMs (110 and 120) in FIG. Figure 7 A timing diagram is shown in response to a read request from the host 105 to the NVM chip 111.

[0107] refer to Figure 2 and Figure 7 , the NVDIMM 110 may receive a read request from the host 105 to the NVM chip 111 .

[0108] At time point Ta, host 105 may read the cache area corresponding to the first cache address of data requested to be written to NVM chip 111 in DRAM chip 112. To this end, CTRL 114 may receive an activate command ACT related to DRAM chip 112 from host 105 via CA bus 132 with reference to the first cache address.

[0109] At time point Tb, CTRL 114 may receive a first read command RD1 associated with DRAM chip 112 from host 105 with reference to the first cache address via CA bus 132. DRAM chip 112 may receive the first cache address and the first read command RD1 from CTRL 114 via first internal command address line 201, and perform a read operation in response to the first cache address and the read command RD1.

[0110] At time point Tc, after a read latency RL from the time point when the first read command RD1 has been received, the DRAM chip 112 may output the first read data RD1_DATA to the DQ bus 134 via the first internal data line 203 and the data buffer 113. In this case, the CTRL 114 may transmit the first read data RD1_DATA together with ECC information including a cache hit signal to the host 105. The host 105 may verify that the first read data RD1_DATA of the DQ bus 134 is a cache hit.

[0111] At time point Td, CTRL 114 may receive a second read command RD2 associated with DRAM chip 112 from host 105 with reference to the second cache address via CA bus 132. DRAM chip 112 may receive the second cache address and the second read command RD2 from CTRL 114 via first internal command address line 201, and perform a read operation in response to the second cache address and the second read command RD2.

[0112] At time point Te, after a read latency RL from the time point when the second read command RD2 has been received, the DRAM chip 112 may output the second read data RD2_DATA to the DQ bus 134 via the first internal data line 203 and the data buffer 113. In this case, the CTRL 114 may transmit the second read data RD2_DATA together with ECC information including a cache miss signal to the host 105. The host 105 may verify that the second read data RD2_DATA of the DQ bus 134 is meaningless due to a cache miss.

[0113] At time point Tf, host 105 may verify a cache miss of DRAM chip 112 and issue a fill request for the requested read data to NVM chip 111. Therefore, CTRL 114 may receive an address XADR of the data requested to be read from NVM chip 111 via CA bus 132. NVM chip 111 may receive address XADR from CTRL 114 via second internal command address line 202.

[0114] At time point Tg, CTRL 114 may receive a third read command XRD associated with NVM chip 111 via CA bus 132. Third read command XRD may include a read identification (RID) number of host 105. Host 105 may use the RID number to identify a read command associated with data transmitted to host 105. NVM chip 111 may receive the third read command XRD from CTRL 114 via second internal command address line 202 and perform a read operation in response to the address XADR and the third read command XRD.

[0115] At the time point Th, the CTRL 114 may toggle or transition the read ready signal XR_RDY to transmit a read ready signal XR_RDY to the host 105 to store the read data associated with the third read command XRD in the NVM buffer 116 and indicate that the CTRL 114 is ready to transmit the read data associated with the third read command XRD to the host 105. According to an embodiment, the CTRL 114 may toggle or transition the read ready signal XR_RDY to transmit the read ready signal XR_RDY to the host 105, wherein the read ready signal XR_RDY indicates that the read data associated with the third read command XRD stored in the NVM buffer 116 has been stored in the DRAM chip 112 and that the read data is ready to be transmitted to the host 105.

[0116] At time point Ti, the host 105 may toggle or transition the read send signal XR_SEND to send a read send signal XR_SEND to the CTRL 114 to detect the transition of the read ready signal XR_RDY and indicate that the host 105 is ready to receive read data associated with the third read command XRD. The host 105 may send the read send signal XR_SEND to the CTRL 114 at any time and regardless of timing parameters. When the read send signal XR_SEND is sent to the CTRL 114, the host 105 may control the amount of communication on the DQ bus 134 through timing.

[0117] At time points Th and Ti, the read ready signal XR_RDY and the read send signal XR_SEND exchanged between the host 105 and the CTRL 114 of the NVDIMM 110 may be sent through pins that were not used in the previous protocol (e.g., DDR4). Alternatively, in the current protocol (e.g., DDR5), the read ready signal XR_RDY and the read send signal XR_SEND may be sent via dedicated pins assigned to the read ready signal XR_RDY and the read send signal XR_SEND, respectively.

[0118] At time point Tj, in response to the read send signal XR_SEND received via the CA bus 132, the CTRL 114 may output read data XRD_DATA associated with the third read command XRD via the second internal data line 204 and the NVM buffer 116 of the CTRL 114, and may transmit the XRD_DATA to the host 105. In addition, when the read data XRD_DATA is transmitted to the host 105, the RID number may be transmitted to the host 105 via the RID pin.

[0119] Figure 8 It shows that according to Figure 7 FIG. 1 is a timing diagram of the process of the NVDIMM 110.

[0120] Combine Figure 2 and Figure 7 refer to Figure 8 , the host 105 can issue a write request to the NVM chip 111 of the NVDIMM 110 .

[0121] An active command ACT may be provided from the host 105 to the DRAM chip 112 (S81). The host 105 may provide the DRAM chip 112 with a first cache address of data requested to be read from the NVM chip 111, along with the active command ACT.

[0122] A first read command RD1 may be provided from the host 105 to the DRAM chip 112 (S82). The host 105 may provide the first cache address of the DRAM chip 112 together with the first read command RD1 to the DRAM chip 112.

[0123] The DRAM chip 112 may perform a read operation in response to the first cache address and the first read command RD1 (S83). The DRAM chip 112 may perform a read operation and transmit first read data RD1_DATA via the first internal data line 203, the data buffer 113, and the DQ bus 134 after a read latency RL from the first read command RD1.

[0124] The host 105 may verify that the first read data RD1_DATA transmitted via the DQ bus 134 is a cache hit ( S84 ).

[0125] A second read command RD2 may be provided from the host 105 to the DRAM chip 112 (S85). The host 105 may provide the second cache address of the DRAM chip 112 together with the second read command RD2 to the DRAM chip 112. The DRAM chip 112 may perform a read operation in response to the second cache address and the second read command RD2.

[0126] The DRAM chip 112 may perform a read operation and transmit second read data RD2_DATA to the host 105 via the first internal data line 203 , the data buffer 113 , and the DQ bus 134 after a read latency RL from the second read command RD2 ( S86 ).

[0127] The host 105 may verify that the second read data RD2_DATA transmitted via the DQ bus 134 is a cache miss (S87). The host 105 may verify the cache miss of the DRAM chip 112 and issue a fill request for the requested read data to the NVM chip 111.

[0128] When the host 105 issues a fill request, an address XADR of data requested to be read from the NVM chip 111 may be provided from the host 105 to the NVM chip 111 ( S88 ).

[0129] The third read command XRD may be provided from the host 105 to the NVM chip 111 (S89). The NVM chip 111 may perform a read operation in response to the address XADR and the third read command XRD.

[0130] The host 105 may receive a read ready signal XR_RDY from the CTRL 114 ( S90 ), the read ready signal XR_RDY indicating that read data associated with the third read command XRD is ready to be sent to the host 105 .

[0131] The host 105 may detect the transition of the read ready signal XR_RDY and transmit a read send signal XR_SEND to the CTRL 114 ( S91 ), the read send signal XR_SEND indicating that the host 105 is ready to receive read data associated with the third read command XRD.

[0132] The NVM chip 111 may transmit read data XRD_DATA associated with the third read command XRD to the host 105 via the second internal data line 204, the NVM buffer 116 of the CTRL 114, and the DQ bus 134 (S92). In other words, the NVM chip 111 may transmit the read data XRD_DATA as read-requested data to the host 105.

[0133] Figure 9 It shows Figure 2 A timing diagram of the operation method of the NVDIMM 110 in FIG. Figure 9 111 , the host 105 may request a cache line fill to allow the NVM chip 111 of the NVDIMM 110 to store data requested to be read from the DRAM chip 112, and a cache line fill operation performed in response to the cache line fill request from the host 105 is shown. The cache line fill operation may be performed sequentially or in an interleaved manner, depending on the number of data blocks sent between the DRAM chip 112 and the NVM chip 111. For example, a write command to the DRAM chip 112 may be associated with four data blocks in a read request to the NVM chip 111. Therefore, the host 105 may provide first to fourth read commands XRD1 to XRD4 to the NVM chip 111 and first to fourth write commands WR1 to WR4 to the DRAM chip 112 to perform cache line fill operations associated with the four data blocks between the DRAM chip 112 and the NVM chip 111.

[0134] refer to Figure 2 and Figure 9 , the CTRL 114 of the NVDIMM 110 may receive a read request from the host 105 to the NVM chip 111 .

[0135] At time point Ta, CTRL 114 may receive an address XADR of data requested to be read from NVM chip 111 via CA bus 132. NVM chip 111 may receive address XADR from CTRL 114 via second internal command address line 202. In this case, a second chip select signal CS1 line among second internal command address lines 202 may be provided to NVM chip 111 in an active state.

[0136] At time point Tb, CTRL 114 may receive an activation command ACT related to DRAM chip 112 via CA bus 132 by referencing the cache address of the data requested to be read from NVM chip 111 in DRAM chip 112, thereby storing the cache area corresponding to the cache address. DRAM chip 112 may receive the cache address and activation command ACT from CTRL 114 via first internal command address line 201, and perform a row activation operation in response to the cache address and activation command ACT. In this case, the first chip select signal CS0 line among the first internal command address lines 201 may be provided to DRAM chip 112 in an active state.

[0137] At time Tc_1, CTRL 114 may receive a first read command XRD1 associated with NVM chip 111 via CA bus 132. NVM chip 111 may receive the first read command XRD1 from CTRL 114 via second internal command address line 202 and perform a read operation in response to address XADR and the first read command XRD1. NVM chip 111 may perform the read operation after a read wait time XRL from the time the first read command XRD1 was received. First read data XRD1_DATA output from NVM chip 111 may be loaded onto first internal data line 203 via second internal data line 204 and NVM buffer 116 of CTRL 114. In this case, CTRL 114 may control, via data buffer 113, that the first read data XRD1_DATA on first internal data line 203 is not provided to DQ bus 134.

[0138] At time point Td_1, CTRL 114 may receive a first write command WR1 associated with DRAM chip 112 via CA bus 132 with reference to the cache address. The first write command WR1 may be applied via the first read command XRD1 before the operation of outputting the first read data XRD1_DATA of NVM chip 111 to first internal data line 203 is completed. DRAM chip 112 may receive the cache address and the first write command WR1 from CTRL 114 via first internal command address line 201 and perform a write operation in response to the cache address and the first write command WR1. DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the first write command WR1 was received.

[0139] At time Te_1, CTRL 114 may configure the first read data XRD1_DATA output from NVM chip 111 on first internal data line 203 as a first data block, configure the first read data XRD1_DATA as first write data WR1_DATA, and provide the first write data WR1_DATA to DRAM chip 112. In other words, CTRL 114 may fill DRAM chip 112 with the first read data XRD1_DATA of NVM chip 111 as the first write data WR1_DATA. DRAM chip 112 may write the first write data WR1_DATA into a memory cell associated with a cache address of the data requested to be read.

[0140] At time Tc_2, CTRL 114 may receive a second read command XRD2 associated with NVM chip 111 via CA bus 132. NVM chip 111 may receive the second read command XRD2 from CTRL 114 via second internal command address line 202 and perform a read operation in response to the address XADR and the second read command XRD2. NVM chip 111 may perform the read operation after a read wait time XRL from the time of receiving the second read command XRD2. Second read data XRD2_DATA output from NVM chip 111 may be loaded onto first internal data line 203 via second internal data line 204 and NVM buffer 116 of CTRL 114. In this case, CTRL 114 may control, via data buffer 113, that the second read data XRD2_DATA on first internal data line 203 is not provided to DQ bus 134.

[0141] At time point Td_2, CTRL 114 may receive a second write command WR2 associated with DRAM chip 112 via CA bus 132 with reference to the cache address. The second write command WR2 may be applied via the second read command XRD2 before the operation of outputting the first read data XRD1_DATA of NVM chip 111 to first internal data line 203 is completed. DRAM chip 112 may receive the cache address and the second write command WR2 from CTRL 114 via first internal command address line 201 and perform a write operation in response to the cache address and the second write command WR2. DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the second write command WR2 is received.

[0142] At time Te_2, CTRL 114 may configure the second read data XRD2_DATA output from NVM chip 111 on first internal data line 203 as a second data block, configure the second read data XRD2_DATA as second write data WR2_DATA, and provide the second write data WR2_DATA to DRAM chip 112. In other words, CTRL 114 may fill DRAM chip 112 with the second read data XRD2_DATA of NVM chip 111 as the second write data WR2_DATA. DRAM chip 112 may write the second write data WR2_DATA into a memory cell associated with the cache address of the data requested to be read.

[0143] At time Tc_3, CTRL 114 may receive a third read command XRD3 associated with NVM chip 111 via CA bus 132. NVM chip 111 may receive the third read command XRD3 from CTRL 114 via second internal command address line 202 and perform a read operation in response to the address XADR and the third read command XRD3. NVM chip 111 may perform the read operation after a read wait time XRL from the time the third read command XRD3 is received. Third read data XRD3_DATA output from NVM chip 111 may be loaded onto first internal data line 203 via second internal data line 204 and NVM buffer 116 of CTRL 114. In this case, CTRL 114 may control the third read data XRD3_DATA on first internal data line 203 to not be provided to DQ bus 134 via data buffer 113.

[0144] At time point Td_3, CTRL 114 may receive a third write command WR3 associated with DRAM chip 112 via CA bus 132 with reference to the cache address. The third write command WR3 may be applied via third read command XRD3 before the operation of outputting the first read data XRD1_DATA of NVM chip 111 to first internal data line 203 is completed. DRAM chip 112 may receive the cache address and third write command WR3 from CTRL 114 via first internal command address line 201 and perform a write operation in response to the cache address and third write command WR3. DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the third write command WR3 is received.

[0145] At time Te_3, CTRL 114 may configure the third read data XRD3_DATA output from NVM chip 111 on first internal data line 203 as a third data block, configure the third read data XRD3_DATA as third write data WR3_DATA, and provide the third write data WR3_DATA to DRAM chip 112. In other words, CTRL 114 may fill DRAM chip 112 with the third read data XRD3_DATA of NVM chip 111 as the third write data WR3_DATA. DRAM chip 112 may write the third write data WR3_DATA into a memory cell associated with the cache address of the data requested to be read.

[0146] At time Tc_4, CTRL 114 may receive a fourth read command XRD4 associated with NVM chip 111 via CA bus 132. NVM chip 111 may receive fourth read command XRD4 from CTRL 114 via second internal command address line 202 and perform a read operation in response to address XADR and fourth read command XRD4. NVM chip 111 may perform the read operation after a read wait time XRL from the time of receiving fourth read command XRD4. Fourth read data XRD4_DATA output from NVM chip 111 may be loaded onto first internal data line 203 via second internal data line 204 and NVM buffer 116 of CTRL 114. In this case, CTRL 114 may control fourth read data XRD4_DATA on first internal data line 203 to not be provided to DQ bus 134 via data buffer 113.

[0147] At time point Td_4, CTRL 114 may receive a fourth write command WR4 associated with DRAM chip 112 via CA bus 132 with reference to the cache address. The fourth write command WR4 may be applied via fourth read command XRD4 before the operation of outputting fourth read data XRD4_DATA of NVM chip 111 to first internal data line 203 is completed. DRAM chip 112 may receive the cache address and fourth write command WR4 from CTRL 114 via first internal command address line 201 and perform a write operation in response to the cache address and fourth write command WR4. DRAM chip 112 may perform the write operation after a write wait time WL from the time point when fourth write command WR4 is received.

[0148] At time Te_4, CTRL 114 may configure the fourth read data XRD4_DATA output from NVM chip 111 on first internal data line 203 as a third data block, configure the fourth read data XRD4_DATA as fourth write data WR4_DATA, and provide the fourth write data WR4_DATA to DRAM chip 112. In other words, CTRL 114 may fill DRAM chip 112 with the fourth read data XRD4_DATA of NVM chip 111 as the fourth write data WR4_DATA. DRAM chip 112 may write the fourth write data WR4_DATA into a memory cell associated with the cache address of the data requested to be read.

[0149] As described above, during a cache line fill operation performed in an interleaved manner between the DRAM chip 112 and the NVM chip 111 and associated with a read request from the host 105 to the NVM chip 111 of the NVDIMM 110, the DQ bus 134 may not be loaded with any data DQs associated with the cache line fill operation. During an interval in which no data DQs associated with the cache line fill operation of the NVDIMM 110 are loaded on the DQ bus 134, the host 105 may perform data transaction operations with (a plurality of) other devices connected to the DQ bus 134. Therefore, even during a cache line fill operation of the NVDIMM 110, the DQ bus 134 may be effectively utilized.

[0150] Figure 10 It shows that according to Figure 9 FIG. 1 is a timing diagram of the process of the NVDIMM 110.

[0151] Combine Figure 2 and Figure 9 refer to Figure 10 , the NVDIMM 110 may perform an interleaved cache line fill operation between the DRAM chip 112 and the NVM chip 111 in relation to a read request from the host 105 to the NVM chip 111 .

[0152] An address XADR of data requested to be read from the NVM chip 111 may be provided from the host 105 to the NVM chip 111 ( S100 ).

[0153] An active command ACT may be provided from the host 105 to the DRAM chip 112 ( S101 ). The host 105 may provide the DRAM chip 112 with a cache address of data requested to be read from the NVM chip 111 , along with the active command ACT.

[0154] A first read command XRD1 may be provided from the host 105 to the NVM chip 111 (S102). The NVM chip 111 may perform a read operation in response to the address XADR and the first read command XRD1. The DRAM chip 112 may perform a read operation and transmit first read data XRD1_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after a read wait time XRL from the time point when the first read command XRD1 is received.

[0155] A first write command WR1 may be provided from the host 105 to the DRAM chip 112 (S103). The host 105 may provide the first cache address of the DRAM chip 112 together with the first write command WR1 to the DRAM chip 112. The DRAM chip 112 may perform a write operation in response to the first cache address and the first write command WR1. The DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the first write command WR1 has been received.

[0156] When the time point at which the NVM chip 111 outputs the first read data XRD1_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after the read wait time XRL from the time point at which the first read command XRD1 has been received and the time point at which the DRAM chip 112 performs a write operation after the write wait time WL from the time point at which the first write command WR1 has been received match each other, the first read data XRD1_DATA of the NVM chip 111 may be provided to the DRAM chip 112 via the first internal data line 203 (S104). The DRAM chip 112 may write the received first read data XRD1_DATA as the first write data WR1_DATA.

[0157] A second read command XRD2 may be provided from the host 105 to the NVM chip 111 (S105). The NVM chip 111 may perform a read operation in response to the address XADR and the second read command XRD2. The NVM chip 111 may perform a read operation and transmit second read data XR2_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after a read wait time XRL from the time point when the second read command XRD2 is received.

[0158] A second write command WR2 may be provided from the host 105 to the DRAM chip 112 (S106). The host 105 may provide the second cache address of the DRAM chip 112 together with the second write command WR2 to the DRAM chip 112. The DRAM chip 112 may perform a write operation in response to the second cache address and the second write command WR2. The DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the second write command WR2 has been received.

[0159] When the time point at which the NVM chip 111 outputs the second read data XRD2_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after the read wait time XRL from the time point at which the second read command XRD2 has been received and the time point at which the DRAM chip 112 performs a write operation after the write wait time WL from the time point at which the second write command WR2 has been received match each other, the second read data XRD2_DATA of the NVM chip 111 may be provided to the DRAM chip 112 via the first internal data line 203 (S107). The DRAM chip 112 may write the received second read data XRD2_DATA as the second write data WR2_DATA.

[0160] A third read command XRD3 may be provided from the host 105 to the NVM chip 111 (S108). The NVM chip 111 may perform a read operation in response to the address XADR and the third read command XRD3. The NVM chip 111 may perform a read operation and transmit third read data XR3_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after a read wait time XRL from the time point when the third read command XRD3 is received.

[0161] A third write command WR3 may be provided from the host 105 to the DRAM chip 112 (S109). The host 105 may provide the third cache address of the DRAM chip 112 together with the third write command WR3 to the DRAM chip 112. The DRAM chip 112 may perform a write operation in response to the third cache address and the third write command WR3. The DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the third write command WR3 has been received.

[0162] When the time point at which the NVM chip 111 outputs the third read data XRD3_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after the read wait time XRL from the time point at which the third read command XRD3 has been received and the time point at which the DRAM chip 112 performs a write operation after the write wait time WL from the time point at which the third write command WR3 has been received match each other, the third read data XRD3_DATA of the NVM chip 111 may be provided to the DRAM chip 112 via the first internal data line 203 (S110). The DRAM chip 112 may write the received third read data XRD3_DATA as the third write data WR3_DATA.

[0163] A fourth read command XRD4 may be provided from the host 105 to the NVM chip 111 (S110). The NVM chip 111 may perform a read operation in response to the address XADR and the fourth read command XRD4 (S111). The NVM chip 111 may perform a read operation and transmit fourth read data XRD4_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after a read wait time XRL from the time point when the fourth read command XRD4 has been received.

[0164] A fourth write command WR4 may be provided from the host 105 to the DRAM chip 112 (S112). The host 105 may provide the fourth cache address of the DRAM chip 112 together with the fourth write command WR4 to the DRAM chip 112. The DRAM chip 112 may perform a write operation in response to the fourth cache address and the fourth write command WR4. The DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the fourth write command WR4 has been received.

[0165] When the time point at which the NVM chip 111 outputs the fourth read data XRD4_DATA to the first internal data line 203 via the second internal data line 204 and the NVM buffer 116 of the CTRL 114 after the read wait time XRL from the time point at which the fourth read command XRD4 has been received and the time point at which the DRAM chip 112 performs a write operation after the write wait time WL from the time point at which the fourth write command WR4 has been received match each other, the fourth read data XRD4_DATA of the NVM chip 111 may be provided to the DRAM chip 112 via the first internal data line 203 (S113). The DRAM chip 112 may write the received fourth read data XRD4_DATA as the fourth write data WR4_DATA.

[0166] Figure 11 and Figure 12 is a diagram of an address structure of an NVDIMM 110 according to an example embodiment. Figure 11 , it is assumed that the cache line size of the DRAM chip 112 is approximately 64 bytes, the DRAM chip 112 is implemented in approximately 1 gigabyte (GB), and the NVM chip 111 is implemented in approximately 16 GB.

[0167] refer to Figure 2 and Figure 11To support the cache mode of the DRAM chip 112, a ratio of approximately 1 GB of the DRAM chip 112 to approximately 16 GB of the NVM chip 111 may be used to represent a corresponding structure of approximately 1:16. The NVM chip 111 may be divided into sixteen regions (111_1, 111_2, 111_3, ..., 111_16), and the sixteen regions (111_1 to 111_16) may be addressed by four bits of tag information (TAG).

[0168] When requesting to write to the NVM chip 111, the host 105 may send the address XADR of the data requested to be written to the NVM chip 111 to the NVDIMM 110 via the CA bus 132. For example, the data write request may occur in the area corresponding to "ABCD" of the address XADR of the NVM chip 111 in the host 105. The address "A" of the "ABCD" of the address XADR of the NVM chip 111 may indicate the tag information in the cache line (112_1, 112_2, 112_3, ..., 112_16) of the DRAM chip 112.

[0169] The host 105 may verify whether the data requested to be written is cached in the DRAM chip 112. To verify whether the DRAM chip 112 has a cache hit, the host 105 may send a read request to the DRAM chip 112 for a cache line corresponding to the address “BCD” among the cache lines (112_1, 112_2, 112_3, . . . , 112_16) of the DRAM chip 112.

[0170] The DRAM chip 112 may output data for a cache line (e.g., 112_1) corresponding to the address "BCD" provided from the host 105. The cache line 112_1 corresponding to the address "BCD" may include user data 1101 stored in the cache line 112_1 and ECC information 1104. The ECC information 1104 may include parity information for detecting and correcting errors that occur in the user data 1101 written to or read from the corresponding cache line (112_1, 112_2, 112_3, ..., 112_16). In addition, the ECC information 1104 may include parity information for detecting and correcting errors that may occur at addresses accessed by the DRAM chip 112.

[0171] refer to Figure 12, the address “ABCD” of the address XADR of the data requested to be written to / read from the NVM chip 111, provided from the host 105, may include an address bit 1201 corresponding to the address “A” and an address bit 1202 corresponding to the address “BCD.” The address bits 1201 corresponding to the address “A” and the address bits 1202 corresponding to the address “BCD” provided to the NVM chip 111 may be provided to the NVM chip 111 via the CA bus 132, based on determination of a cache hit / cache miss for the cache lines (112_1, 112_2, 112_3, . . . , 112_16) of the DRAM chip.

[0172] However, in order to verify the cache status of the DRAM chip 112 (such as cache misses and cache hits), when a read request for a cache line (112_1, 112_2, 112_3, ..., 112_16) from the host is sent to the DRAM chip 112, only the cache address bit 1204 corresponding to the address "BCD" may be provided, without providing the address bit 1201 (1203) corresponding to the address "A". The cache address bit 1204 corresponding to the address "BCD" may be referred to as the cache address of the data requested to be written to the NVM chip 111. In this case, the CTRL 114 of the NVDIMM 110 may only load the cache address bit 1204 corresponding to the address "BCD" onto the CA bus 132, and it may be known that the address bit 1201 corresponding to the address "A" (i.e., tag information) has not been loaded.

[0173] Each of the cache lines (112_1, 112_2, 112_3, ..., 112_16) may include parity information (P0 to P3) of address bits (1201 and 1202) (or A0 to A36) as described below. In the following description, "XOR" indicates an exclusive OR operation.

[0174] P0=XOR{A0,A4,A8,A12,…,A32,A36}

[0175] P1=XOR{A1,A5,A9,A13,…,A33}

[0176] P2=XOR{A2,A6,A10,A14,…,A34}

[0177] P3=XOR{A3,A7,A11,A15,…,A35}

[0178] Parity information P0 to P3 can be provided by using an XOR function on a set of address bits A0 to A36 (A0, A1, A2, A3, A4...A10, A11, A12,...A17, A18, A19, A20, A21, A22, A31, A32, Ad33, A34, A35 and A36).

[0179] The CTRL 114 of the NVDIMM 110 may know the mapping relationship between the address “BCD” corresponding to the cache address bits 1204 (C0, C1, C2 C3, ... C9, C10, BA0, BA1, ..., BG3, R0, R1, R2, R3, R4, ... R12, R13, and R14) and the address bits A4 to A36 of the address bits 1202. Therefore, the CTRL 114 of the NVDIMM 110 may be configured to recover the address “A”, i.e., the tag information, by using the parity bits P0 to P3 provided as the ECC information 1104 and the address bits A4 to A36 of the address bits 1202 corresponding to the cache address bits 1204.

[0180] When the address "A" of the data requested to be written is lost, or as a preparation for the case where an error occurs in the address "A" of the data requested to be written, the CTRL 114 can restore the address "A". The tag information 1205 restored by the CTRL 114 can be configured with four bits (M1, M2, M3, and M4). The CTRL 114 can store the restored tag information 1205 and the cache address bits 1204 as a DRAM address. Thereafter, as Figure 3 As shown, the CTRL 114 may output the read data RD_DATA from the DRAM chip 112 to the internal data line 203 with reference to the restored tag information 1205 and the cache address bit 1204 , and may refresh so that the read data RD_DATA is written as the write data XWR_DATA to the NVM chip 111 .

[0181] In this manner, the CTRL 114 can recover the address “A”, i.e., tag information, and even “ABCD” of the address XADR of the data requested to be read from the NVM chip 111, which is provided from the host 105. The CTRL 114 can recover the address “A”, i.e., tag information, by using A4 to A36 of the address bits 1202 corresponding to the cache address bits 1204 of the data requested to be read from the NVM chip 111, and the address parity bits provided to the ECC information 1104. Figure 12As shown, CTRL 114 can refer to the restored tag information 1205 and the cache address bit 1204, output the first read data (e.g., XRD1_DATA) from the NVM chip 111 to the internal data line 203, and can refresh so that the first read data XRD1_DATA is written as the first write data (e.g., WR1_DATA) to the DRAM chip 112.

[0182] In the above-described embodiments, a process has been described in which the DRAM chip 112 of the NVDIMM 110 operates as a cache memory for the NVM chip 111. For example, in the cache operation of the NVDIMM 110, read data according to the read latency RL of the DRAM chip 112 and write data according to the write latency XWL of the NVM chip 111 are arranged to match each other on the first internal data line 203 and the second internal data line 204, or read data according to the read latency XRL of the NVM chip 111 and write data according to the write latency WL of the DRAM chip 112 are arranged to match each other on the first data line 203 and the second data line 204. However, the operation in which data according to the read latency RL / write latency WL of the DRAM chip 112 and data according to the write latency XWL / read latency XRL of the NVM chip 111 are matched with each other in the internal data lines can be applied to a data movement operation between the NVM chip 111 and the DRAM chip 112.

[0183] Figure 13 and Figure 14 is used to describe Figure 2 FIG. 1 is a timing diagram of data movement operations of the NVDIMM 110 in FIG. Figure 13 is a timing diagram of data movement from the DRAM chip 112 to the NVM chip 111. Figure 14 is a timing diagram of data movement from the NVM chip 111 to the DRAM chip 112.

[0184] refer to Figure 13 , the NVDIMM 110 may receive a data movement request from the host 105 from the DRAM chip 112 to the NVM chip 111 .

[0185] At time point T1m, the CTRL 114 may receive a row address and an active command ACT of the DRAM chip 112 for which data movement is requested via the CA bus 132. The DRAM chip 112 may receive the row address and the active command ACT from the CTRL 114 via the first internal command address line 201 and perform a row active operation in response to the row address and the active command ACT.

[0186] At time point T2m, CTRL 114 may receive the column address and activation command ACT of the DRAM chip 112 for which data movement is requested via CA bus 132. DRAM chip 112 may receive the column address and read command RD from CTRL 114 via the first internal command address line 201 and perform a read operation in response to the column address and read command RD. DRAM chip 112 may perform the read operation and output read data RD_DATA after a read wait time RL from the time point when the read command RD is received. The read data RD_DATA output from DRAM chip 112 may be output to the first internal data line 203 of NVDIMM 110. In this case, CTRL 114 may control the read data RD_DATA of DRAM chip 112 on the first internal data line 203 via data buffer 113 so as not to be provided to DQ bus 134.

[0187] At time point T3m, CTRL 114 may receive address XADR of NVM chip 111, to which read data RD_DATA of DRAM chip 112 read at a request of data movement via CA bus 132 is to be written. NVM chip 111 may receive address XADR from CTRL 114 via second internal command address line 202.

[0188] At time point T4m, CTRL 114 may receive a write command XWR from NVM chip 111 associated with address XADR via CA bus 132. Write command XWR may be applied via read command RD before the operation of outputting read data RD_DATA of DRAM chip 112 to first internal data line 203 is completed. NVM chip 111 may receive write command XWR from CTRL 114 via second internal command address line 202 and perform a write operation in response to address XADR and write command XWR. NVM chip 111 may perform the write operation after a write wait time XWL from the time point when write command XWR is received.

[0189] At time point T5m, CTRL 114 may perform a data shift operation so that read data RD_DATA of DRAM chip 112 is written to NVM chip 111. When the time point at which DRAM chip 112 outputs read data RD_DATA to internal data line 203 after a read latency RL from a time point at which read command RD has been received and the time point at which NVM chip 111 performs a write operation after a write latency XWL from a time point at which write command XWR has been received coincide with each other, CTRL 114 may configure the read data RD_DATA of DRAM chip 112 loaded on internal data line 203 as write data XWR_DATA and provide the write data XWR_DATA to NVM chip 111. NVM chip 111 may write write data XWR_DATA to a memory cell corresponding to address XADR.

[0190] refer to Figure 14 , the NVDIMM 110 may receive a data movement request from the host 105 from the NVM chip 111 to the DRAM chip 112 .

[0191] At time point T1v, CTRL 114 may receive an address XADR of data requested to be moved to NVM chip 111 via CA bus 132. NVM chip 111 may receive address XADR from CTRL 114 via second internal command address line 202.

[0192] At time point T2v, CTRL 114 may receive a row address and an active command ACT related to DRAM chip 112 via CA bus 132 to store data requested to be moved from NVM chip 111 to DRAM chip 112. DRAM chip 112 may receive the row address and active command ACT from CTRL 114 via first internal command address line 201 and perform a row active operation in response to the row address and active command ACT.

[0193] At time T3v, CTRL 114 may receive a read command XRD associated with NVM chip 111 via CA bus 132. NVM chip 111 may receive read command XRD from CTRL 114 via second internal command address line 202 and perform a read operation in response to address XADR and read command XRD. NVM chip 111 may perform the read operation after a read wait time XRL from the time when read command XRD was received. Read data XRD_DATA output from NVM chip 111 may be output to first internal data line 203 via second internal data line 204 and NVM buffer 116 of CTRL 114. NVDIMM buffer 116 may store the read data output from NVM chip 111 and then transmit a read ready signal XR_RDY to CTRL 114, indicating that the read data XRD_DATA is ready to be transmitted to DRAM chip 112. In this case, the CTRL 114 may control the read data XRD_DATA of the NVM chip 111 on the first internal data line 203 not to be provided to the DQ bus 134 via the data buffer 113 .

[0194] At time point T4v, CTRL 114 may receive a write command WR via CA bus 132 with reference to a column address associated with DRAM chip 112. The write command WR may be applied via read command XRD before the operation of outputting read data XRD_DATA of NVM chip 111 to first internal data line 203 is completed. DRAM chip 112 may receive the column address and write command WR from CTRL 114 via first internal command address line 201 and perform a write operation in response to the column address and write command WR. DRAM chip 112 may perform the write operation after a write wait time WL from the time point when the write command WR is received.

[0195] At time point T5v, CTRL 114 may perform a data shift operation so that read data XRD_DATA of NVM chip 111 is written to DRAM chip 112. When a time point at which NVM chip 111 outputs read data XRD_DATA to internal data line 203 after a read wait time XRL from a time point at which read command XRD has been received and a time point at which DRAM chip 112 performs a write operation after a write wait time WL from a time point at which write command WR has been received coincide with each other, CTRL 114 may configure read data XRD_DATA of NVM chip 111 loaded on internal data line 203 as write data WR_DATA and provide the write data XWR_DATA to DRAM chip 112. DRAM chip 112 may write data XWR_DATA to a memory cell corresponding to address XADR.

[0196] While example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A memory module, comprising: a first internal data line; Second internal data line; a volatile memory chip connected to the first internal data line; a non-volatile memory chip connected to the second internal data line; a controller connected to the volatile memory chip and the nonvolatile memory chip via the first internal data line and the second internal data line, the controller being configured to: apply a first command associated with first data of the volatile memory chip to the volatile memory chip at a first time, and apply a second command associated with second data of the nonvolatile memory chip to the nonvolatile memory chip at a second time, wherein the second time is different from the first time; and a data buffer connected to the volatile memory chip and the controller via the first internal data line, The controller is further configured to: at a time point when a first waiting time of the first command and a second waiting time of the second command coincide with each other, control the volatile memory chip and the non-volatile memory chip to: moving the first data from the volatile memory chip to the nonvolatile memory chip, or The second data is moved from the non-volatile memory chip to the volatile memory chip.

2. The memory module according to claim 1, wherein: The controller is further configured to: applying the first command at the first time, applying the second command at a second time after the first time, at a third time, when the first waiting time of the first command and the second waiting time of the second command coincide with each other, outputting the first data to the first internal data line, and The first data is moved from the first internal data line to the nonvolatile memory chip as the second data.

3. The memory module according to claim 2, wherein: The controller is further configured to control the data buffer so that the first data is not provided to a data bus outside the memory module.

4. The memory module according to claim 2, wherein: The controller is further configured to apply the second command at the second time before outputting the first data to the first internal data line.

5. The memory module according to claim 1, wherein The controller is further configured to: receiving, via a command address bus external to the memory module, a data move request associated with moving the first data from the volatile memory chip to the nonvolatile memory chip, receiving a read command directed to the volatile memory chip via the command address bus, the read command being associated with a first address of the first data requested to be read from the volatile memory chip, sending the read command as the first command to the volatile memory chip, receiving a second address indicating a location in the nonvolatile memory chip where the first data is to be written, receiving a write command associated with the non-volatile memory chip, sending the write command as the second command to the nonvolatile memory chip, configuring the first data output from the volatile memory chip to the first internal data line after a read latency of the read command and after a write latency of the write command as the second data, and Controlling writing of the second data into the nonvolatile memory chip. The memory module according to claim 5 , wherein: The controller is further configured to: receiving an activate command directed to the volatile memory chip via the command address bus with reference to the first address of the volatile memory chip before sending the read command to the volatile memory chip, and The activate command is sent to the volatile memory chip.

7. The memory module according to claim 5, wherein: The controller is further configured to: receiving the second address of the nonvolatile memory chip via the command address bus before sending the write command to the nonvolatile memory chip, and The second address is sent to the nonvolatile memory chip.

8. The memory module according to claim 1, wherein: The controller is further configured to: After applying the first command at a first time, applying the second command to the second internal data line at a second time, wherein the second time is after the first time and before the second data is output, outputting the second data to the second internal data line at a third time after the second time, wherein the second wait time of the second command and the first wait time of the first command coincide with each other at the third time, and The second data is moved as the first data from the second internal data line to the volatile memory chip.

9. The memory module according to claim 8, wherein: The controller further includes a non-volatile memory buffer, and the controller and the non-volatile memory buffer are configured to have a read latency of the second data to the second internal data line having a constant deterministic characteristic.

10. The memory module according to claim 8, wherein: The controller is further configured to: receiving, via a command address bus external to the memory module, a data move request associated with moving the second data from the nonvolatile memory chip to the volatile memory chip, receiving, via the command address bus, a read command associated with a second address of the second data requested to be read from the nonvolatile memory chip, sending the read command as the second command to the nonvolatile memory chip, receiving a first address indicating a location in the volatile memory chip where the first data is to be written, receiving a write command associated with the volatile memory chip, sending the write command as the first command to the volatile memory chip, configuring the second data output from the nonvolatile memory chip to the second internal data line via the second internal data line and the controller after a read latency of the read command as the first data after a write latency of the write command, and Controlling writing of the first data into the volatile memory chip. The memory module according to claim 10 , wherein: The controller is further configured to: receiving the second address of the nonvolatile memory chip via the command address bus before sending the read command to the nonvolatile memory chip, and The second address is sent to the nonvolatile memory chip.

12. The memory module according to claim 10, wherein: The controller is further configured to: receiving an activate command directed to the volatile memory chip via the command address bus with reference to the first address of the volatile memory chip before sending the write command to the volatile memory chip, and The activate command is sent to the volatile memory chip.

13. A memory module comprising: Volatile memory chips; non-volatile memory chips; and The controller is configured as: receiving an address for requesting data access to the nonvolatile memory chip via a command address bus, receiving parity information about the address, when a cache address associated with the address is provided to the volatile memory chip, restoring tag information indicating a cache mapping between the nonvolatile memory chip and the volatile memory chip based on the parity information about the address and the cache address, thereby controlling the volatile memory chip to function as a cache memory of the nonvolatile memory chip, receiving a write request directed to the nonvolatile memory chip via the command address bus, and At a time point where a first waiting time of a read request directed to the volatile memory chip at a first time and a second waiting time of a write request directed to the non-volatile memory chip at a second time coincide with each other, and based on the tag information and the cache address and in response to the write request, control is performed to write the first data output from the volatile memory chip as second data to the non-volatile memory chip, wherein the second time is different from the first time.

14. A memory module comprising: a first internal data line; Second internal data line; a volatile memory chip connected to the first internal data line; a non-volatile memory chip connected to the second internal data line; a controller connected to the volatile memory chip and the nonvolatile memory chip via the first internal data line and the second internal data line, the controller being configured to: apply a first command associated with first data of the volatile memory chip to the volatile memory chip at a first time, and apply a second command associated with second data of the nonvolatile memory chip to the nonvolatile memory chip at a second time, wherein the second time is different from the first time; and a data buffer connected to the volatile memory chip and the controller via the first internal data line, Wherein, the controller is further configured to: At the second time, applying the second command before outputting the first data to the first internal data line, and At a time point when a first latency of the first command and a second latency of the second command coincide with each other, the volatile memory chip is controlled to function as a cache memory of the nonvolatile memory chip.

15. The memory module according to claim 14, wherein: The controller is further configured to control the data buffer so that the first data is not provided to a data bus outside the memory module.

16. The memory module according to claim 14, wherein: The controller is further configured to apply the second command at the second time before outputting the first data to the first internal data line.

17. The memory module according to claim 14, wherein: The controller is further configured to have a read latency, wherein the read latency has a constant deterministic characteristic of the second data of the non-volatile memory chip.

18. The memory module according to claim 14, wherein: The controller is further configured to: receiving a write request directed to the non-volatile memory chip via a command address bus external to the memory module, receiving a first read command directed to the volatile memory chip via the command address bus, the first read command being associated with a cache address of the second data requested to be written to the non-volatile memory chip, sending the first read command to the volatile memory chip, receiving, via the command address bus, a first write command associated with a nonvolatile memory address of the second data requested to be written into the nonvolatile memory chip, sending the first write command to the non-volatile memory chip, configuring first data output from the volatile memory chip to the first internal data line after a read latency time of the first read command as the second data after a write latency time of the first write command, and Controlling writing of the second data into the nonvolatile memory chip.

19. The memory module according to claim 18, wherein: The controller is further configured to: receiving an activate command directed to the volatile memory chip via a command address bus with reference to the cache address before sending the first read command to the volatile memory chip, and The activate command is sent to the volatile memory chip.

20. The memory module according to claim 18, wherein The controller is further configured to: receiving the nonvolatile memory address of the second data requested to be written to the nonvolatile memory chip via a command address bus before sending the first write command to the nonvolatile memory chip, and The nonvolatile memory address is sent to the nonvolatile memory chip.

21. The memory module according to claim 18, wherein The controller is configured to: receiving a second read command directed to the volatile memory chip via the command address bus, the second read command being associated with a cache address of third data requested to be written to the non-volatile memory chip, sending the second read command to the volatile memory chip, receiving a second write command associated with a nonvolatile memory address of the third data requested to be written into the nonvolatile memory chip, sending the second write command to the non-volatile memory chip, configuring the fourth data of the volatile memory chip output to the first internal data line after the read wait time of the second read command as third data after the write wait time of the second write command, and Controlling writing of the third data into the nonvolatile memory chip.

22. The memory module according to claim 14, wherein The controller is further configured to: receiving a read request for the nonvolatile memory chip via a command address bus, receiving a first read command associated with a nonvolatile memory address of the second data requested to be read from the nonvolatile memory chip, sending the first read command to the non-volatile memory chip, receiving a first write command directed to the volatile memory chip, the first write command being associated with a cache address of the second data requested to be read from the non-volatile memory chip, sending the first write command to the volatile memory chip, configuring the second data read from the nonvolatile memory chip after the read latency of the first read command and output to the first internal data line via the second internal data line and the controller as the first data after the write latency of the first write command, and Controlling writing of the first data into the volatile memory chip.

23. The memory module according to claim 22, wherein: The controller is further configured to: receiving the nonvolatile memory address of the nonvolatile memory chip via the command address bus before sending the first read command to the nonvolatile memory chip, and The nonvolatile memory address is sent to the nonvolatile memory chip.

Images