Method for calibrating output timing, and corresponding master device and slave device

Abstract

A method for calibrating output timing, and a corresponding master device and slave device are provided herein. The master device and the slave device are coupled via an interface communication. The method includes: receiving one or more continuous first signal edges indicating a synchronization event from the master device; recovering a reference clock of the master device based on the one or more continuous first signal edges; and transmitting one or more predetermined second signal edges to the master device. The one or more predetermined second signal edges are generated by the slave device using the recovered reference clock. Additionally, the method includes: receiving data indicating one or more sampled values ​​of the master device for one or more predetermined second signal edges from the master device. The method includes: adjusting the output timing based on a comparison of the one or more predetermined second signal edges with one or more sampled values ​​of the master device for the one or more predetermined second signal edges.

Description

Technical Field

[0001] The present disclosure relates to output timing calibration for a slave device. Specifically, examples relate to a method for a slave device for calibrating output timing for transmitting data to a master device, and a method for a master device for enabling a slave device communicatively coupled to the master device via an interface to calibrate output timing. Other examples relate to a master device and a slave device. Background Art

[0002] For a master and slave devices coupled via an interface (e.g., a bus), the master device provides a reference clock used by the master and slave devices for timing and sampling operations of the respective outputs of the master and slave devices. In such a system, significant transmission line delays and input / output (I / O) delays may occur compared to the duration of a single symbol. Further, the round-trip delay of the system (i.e., the time interval between sending data from device A to device B and receiving data from device B at device A) depends on the structure of the system as well as the temperature.

[0003] It is difficult for the master device to select the correct sampling point to sample the signal received from the slave device. For example, if different slave devices exhibit different round-trip delays, the sampling point of the master device should be different for each slave device. Summary of the invention

[0004] Therefore, it may be necessary to calibrate the output timing of the slave device to facilitate sampling by the master device.

[0005] This need may be met by the subject matter of the appended claims.

[0006] One example relates to a method for calibrating output timing of data transmission to a master device from a slave device. The master device and the slave device are coupled via an interface communication. The method includes: receiving one or more continuous first signal edges indicating a synchronization event from the master device. Further, the method includes: recovering a reference clock of the master device based on the one or more continuous first signal edges. The method includes: transmitting one or more predetermined second signal edges to the master device. The one or more predetermined second signal edges are generated by the slave device using the recovered reference clock. Additionally, the method includes: receiving data indicating one or more sampled values ​​of the master device for one or more predetermined second signal edges from the master device. The method includes: adjusting the output timing based on a comparison of the one or more predetermined second signal edges with one or more sampled values ​​of the master device for one or more predetermined second signal edges.

[0007] Another example relates to a method for a master device for enabling a slave device coupled to the master device via an interface communication to calibrate output timing. The method includes: transmitting one or more consecutive first signal edges indicating a synchronization event to the slave device. The one or more consecutive first signal edges are generated using a reference clock of the master device. Further, the method includes: sampling one or more predetermined second signal edges received from the slave device using the reference clock to obtain sampled values ​​for the one or more predetermined second signal edges. The method also includes: transmitting data indicating one or more sampled values ​​for the one or more predetermined second signal edges to the slave device.

[0008] Another example relates to a slave device, which is suitable for calibrating the output timing for transmitting data to a master device. The master device and the slave device are coupled via an interface communication. The slave device includes a receiver circuit, which is configured to receive one or more continuous first signal edges indicating a synchronization event from the master device. Further, the slave device includes a processing circuit, which is configured to recover the reference clock of the master device based on the one or more continuous first signal edges. The slave device also includes a transmitter circuit, which is configured to transmit one or more predetermined second signal edges to the master device. The one or more predetermined second signal edges are generated by the slave device using the recovered reference clock. The receiver circuit is also configured to receive data indicating one or more sampled values ​​of the master device for one or more predetermined second signal edges from the master device. The processing circuit is also configured to adjust the output timing based on the comparison of the one or more predetermined second signal edges with the one or more sampled values ​​of the master device for one or more predetermined second signal edges.

[0009] Another example relates to a master device, which is adapted to enable a slave device coupled to the master device via an interface communication to calibrate output timing. The master device includes a transmitter circuit, which is configured to transmit one or more continuous first signal edges indicating a synchronization event to the slave device, wherein the one or more continuous first signal edges are generated using a reference clock of the master device. Additionally, the master device includes a receiver circuit, which is configured to use the reference clock to sample one or more predetermined second signal edges received from the slave device to obtain sampled values ​​for the one or more predetermined second signal edges. The transmitter circuit is also configured to transmit data indicating one or more sampled values ​​for the one or more predetermined second signal edges to the slave device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Some examples of apparatus and / or methods are described below, by way of example only and with reference to the accompanying drawings, in which

[0011] Figure 1A flow chart illustrating an example of a method for a slave device for calibrating output timing of transmitting data to a master device;

[0012] Figure 2 A flow chart illustrating an example of a method for a master device for enabling a slave device communicatively coupled to the master device via an interface to calibrate output timing;

[0013] Figure 3 An example of a system including a master device and a slave device is illustrated;

[0014] Figure 4 illustrates an exemplary comparison of propagation delays for different slave devices;

[0015] Figure 5 illustrates exemplary output and sampling timing of a master device;

[0016] Figure 6 illustrates an example of a proposed signal flow for calibration;

[0017] Figure 7 illustrates another example of a proposed signal flow for calibration;

[0018] Figure 8 illustrates an exemplary signal flow after calibration;

[0019] Fig. 9 An example of a master device adapted to enable a slave device communicatively coupled to the master device via an interface to calibrate output timing is illustrated; and

[0020] Fig.10 An example of a slave device suitable for calibrating output timing for transmitting data to a master device is illustrated. DETAILED DESCRIPTION

[0021] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are illustrated. In the accompanying drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0022] Thus, although other examples can have various modifications and alternative forms, some specific examples thereof are shown in the drawings and described in detail later. However, this specific embodiment does not limit other examples to the specific forms described. Other examples may encompass all modifications, equivalent forms, and alternative forms falling within the scope of the present disclosure. Throughout the description of the drawings, identical or similar reference numerals refer to identical or similar elements, which, when compared to each other, may be implemented identically or in a modified form while providing identical or similar functions.

[0023] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, these elements may be directly connected or coupled via one or more intermediate elements. If two elements A and B are combined using "or", then in the absence of additional explicit or implicit definitions, it should be understood to disclose all possible combinations, i.e., only A, only B, and A and B. Alternative wording for the same combination is "at least one of A and B" or "A and / or B". The same applies to combinations of more than two elements, mutatis mutandis.

[0024] The terms used herein for the purpose of describing a specific example are not intended to limit other examples. Whenever a singular form such as "one", "an" and "the" is used and only a single element is not explicitly or implicitly defined as mandatory, other examples may also use multiple elements to implement the same function. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may use a single element or processing entity to implement the same function. Further, it should be understood that the terms "include", "have", "include" and / or "contain" specify the presence of the features, integers, steps, operations, processes, actions, elements and / or parts when used, but do not exclude the presence or increase of one or more other features, integers, steps, operations, processes, actions, elements, parts and / or any groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) are used herein according to the ordinary meaning in the art to which they belong.

[0026] The proposed calibration technique for calibrating the output timing of the slave device includes actions of the slave device itself and a master device coupled to the slave device via an interface communication. The master device and the slave device are electronic devices that communicate via an interface. In this regard, the master device has unidirectional control over the slave device. The interface can be any wired communication interface using any signaling level or method (e.g., low voltage differential signaling LVDS; complementary metal oxide semiconductor CMOS signaling; or transistor-transistor logic TTL signaling). For example, the interface can be a differential interface or a single-ended interface. The interface can, for example, use a parallel line terminal or a serial line terminal (i.e., the method 100 can also be used in the presence of reflections at the interface). It should be noted that the proposed calibration technique is not limited to a specific implementation of the interface.

[0027] The term "output timing" refers to a time instance when an electronic circuit such as a master device or a slave device outputs an output signal to an interface.

[0028] References below Figure 1 and Figure 2 Describe the calibration process. Figure 11 is a flow chart of a method 100 for a slave device to calibrate its output timing for transmitting data to a master device. In other words, the method 100 describes the steps performed by the slave device for output timing calibration. On the other hand, Figure 2 A flow chart of a method 200 for a master device for enabling a slave device to calibrate its output timing is illustrated. That is, the method 200 describes the steps performed by the master device for calibrating the output timing of a slave device.

[0029] Method 200 includes: transmitting 202 one or more continuous first signal edges indicating a synchronization event to a slave device. The one or more continuous first signal edges are generated using a reference clock of a master device. A reference clock (e.g., an oscillating signal) is a sequence of clock cycles used by a master device to output data to an interface and to sample data received via the interface. For example, the clock cycle of the reference clock can determine the length of a data symbol in a modulation scheme used by a master device and a slave device for data exchange. Method 100 includes: receiving 102 one or more continuous first signal edges indicating a synchronization event from a master device. A synchronization event is an event that allows a slave device to synchronize with a reference clock (time, timing) of a master device. A synchronization event can be indicated by a single first signal edge (e.g., a rising signal edge, i.e., a transition from a lower first signal level to a higher (higher) second signal level, or a falling signal edge) or a plurality of continuous first signal edges (e.g., a predetermined sequence of rising signal edges and falling signal edges). One or more continuous first signal edges allow information related to the phase and frequency of the reference clock of the master device to be encoded. In other words, the synchronization event can be any signal pattern that allows providing phase and frequency information of the reference clock. For example, a predetermined burst or code can be encoded as (encoded by) one or more consecutive first signal edges indicating a synchronization event.

[0030] As described above, the synchronization event allows the slave device to synchronize with the reference clock of the master device. Therefore, the method 100 includes: based on one or more continuous first signal edges, recovering 104 the reference clock of the master device. The recovery of the master device reference clock can be accomplished using known clock recovery techniques (e.g., using a phase-locked loop PLL or a delay-locked loop DLL at the slave device). The slave device decodes one or more continuous first signal edges using the recovered reference clock, so that the slave device can detect the synchronization event in the signal received from the master device.

[0031] Additionally, method 100 includes: in response to detecting a synchronization event, transmitting 106 one or more predetermined second signal edges to the master device via the interface. The one or more predetermined second signal edges are generated by the slave device using the recovered reference clock. For example, the slave device can output one or more predetermined second signal edges synchronized with the predetermined signal edge in one or more clock cycles of the recovered reference clock or a phase-shifted copy of the recovered reference clock. The one or more predetermined second signal edges are a single predetermined signal edge (e.g., a falling signal edge if the master device puts the interface at a high signal level) or a predetermined sequence of rising signal edges and falling signal edges. In some examples, the slave device can transmit one or more predetermined second signal edges, for example, in a predetermined time slot after one or more continuous first signal edges. In other words, after a predefined time span (e.g., a predefined number of clock cycles of the reference clock) from receiving one or more continuous first signal edges has passed, the slave device can transmit one or more predetermined second signal edges to the master device.

[0032] The master device receives one or more predetermined second signal edges. Thus, the method 200 includes: sampling 204 the one or more predetermined second signal edges using a reference clock to obtain sampled values ​​for the one or more predetermined second signal edges. For example, the master device may sample the one or more predetermined second signal edges at the predetermined signal edges within one or more clock cycles of the reference clock. The (multiple) sampled values ​​indicate (multiple) corresponding signal levels of the one or more predetermined second signal edges at (multiple) corresponding sampling times, wherein the (multiple) sampling times are based on (determined by) the reference clock of the master device.

[0033] Further, the method 200 includes: transmitting 206 data indicating one or more sampled values ​​of one or more predetermined second signal edges to the slave device via the interface. For example, the slave device can generate and transmit one or more continuous signal edges and / or signal levels indicating one or more sampled values ​​of one or more predetermined second signal edges. In other words, the master device can effectively "reflect" the edge data received from the slave device back to the slave device.

[0034] The method 100 respectively includes receiving 108 data indicating one or more sampled values ​​of one or more predetermined second signal edges of the master device from the master device. The slave device decodes the data indicating the one or more sampled values ​​of the master device using the recovered reference clock.

[0035] Additionally, the method 100 includes adjusting 110 (by the slave device itself) an output timing of the slave device based on a comparison of the one or more predetermined second signal edges with one or more sampled values ​​of the one or more predetermined second signal edges of the master device.

[0036] One or more predetermined second signal edges transmitted by the slave device to the master device represent a known data transition at the output of the slave device (e.g., driven low after the master device places the interface at a high signal level). Similarly, one or more sampled values ​​of the one or more predetermined second signal edges of the master device represent a known data transition at the input of the master device at the (multiple) sampling times of the master device. By comparing the sampled values ​​of the one or more predetermined second signal edges of the master device with the one or more predetermined second signal edges, the slave device can determine whether the one or more predetermined second signal edges are before or after the (multiple) sampling times (i.e., the reference clock of the master device) at the input of the master device. Thus, adjusting 108 the output timing may include comparing the one or more signal levels indicated by the one or more sampled values ​​of the master device with the one or more predetermined second signal edges to determine whether the one or more predetermined second signal edges are before or after the reference clock of the master device at the input of the master device.

[0037] Based on the comparison result, the slave device adjusts its output timing to compensate for the difference. For example, adjusting 108 the output timing may include: if one or more predetermined second signal edges are after the reference clock of the master device, shifting the output timing of the slave device to an earlier output timing (e.g., by a fraction of the reference clock or a predetermined time shift); or if one or more predetermined second signal edges are before the reference clock of the master device, shifting the output timing of the slave device to a later output timing (e.g., by a fraction of the reference clock or a predetermined time shift).

[0038] References Figure 1 and Figure 2 The proposed calibration process described can allow for rapid automatic adjustment of the output timing of the slave device so that the data of the slave device arrives at the master device in an optimized manner. For example, the data of the slave device can arrive at the master device at the optimal sampling time of the master device. In other words, after calibration, the data from the slave device to the master device can be synchronized with the sampling time of the master device (i.e., the reference clock of the master device).

[0039] Although the proposed calibration process is described above with only a single slave device in mind, it should be noted that the proposed calibration process can be used to similarly calibrate other slave devices that are communicatively coupled to a master device via an interface. The proposed calibration process allows the output timing of multiple slave devices to be adjusted independently of each other by executing the method steps described above for each slave device respectively. The output timing calibration of multiple slave devices can be completed one by one or in parallel. If multiple slave devices are communicatively coupled, calibrating the output timing of each slave device according to the proposed technology can allow the master device to sample the signals from all slave devices with the same sampling timing (e.g., by the same sampling circuit). Specifically, the proposed calibration process can allow compensation for different I / O delays and different propagation delays of slave devices. Therefore, the proposed calibration process can also allow avoiding conflicts in data (e.g., symbols) transmitted to the master device via an interface by different slave devices.

[0040] Methods 100 and 200 may be performed, for example, during startup of (multiple) slave devices to compensate for system tolerances. Alternatively or additionally, methods 100 and 200 may be performed between two payload data exchanges between a master device and a slave device. In other words, the proposed calibration process may be performed during regular operation to, for example, compensate for temperature drifts, etc.

[0041] In the following, other aspects of the proposed calibration process are described in conjunction with an exemplary implementation using a differential bus as an interface. However, it should be noted that the various aspects of the proposed calibration process described below are not limited to an implementation using a differential bus as an interface. In general, any interface may be used.

[0042] Figure 3 An example of a system 300 is illustrated that includes a master device 310 in accordance with the proposed technique, two slave devices 320 and 330 in accordance with the proposed technique, and a differential bus interface 340 that communicatively couples the master device 310 with the slave devices 320 and 330 .

[0043] The master device 310 includes a transmitter circuit 311 for transmitting data via the interface 340 and a receiver circuit 312 for receiving data from the interface 340. Figure 3In the example of , the transmitter circuit 311 and the receiver circuit 312 are schematically represented by corresponding driver circuits. However, it should be noted that the transmitter circuit 311 and the receiver circuit 312 may include additional elements or different elements (circuits). The master device 310 is coupled to the two differential signal lines D+ and D- of the interface 340 by means of terminals 313 and 314 (e.g., pins or contact pads). Although not shown, the master device 310 may include additional circuits such as memory or processing circuits (a single dedicated processor, a single shared processor, or multiple individual processors, some or all of which may be shared, digital signal processor hardware, application specific integrated circuits, or field programmable gate arrays).

[0044] Likewise, each of the slave devices 320 and 330 includes a respective transmitter circuit 321, 331 and a respective receiver circuit 322, 332. Further, the slave devices 320 and 330 include respective processing circuits 323, 333. The slave devices are coupled to two signal lines D+ and D- of the interface 340 by means of terminals 324, 325, 334 and 335. Although not shown, the slave devices 320 and 330 may include additional circuits such as memories.

[0045] The slave devices 320 and 330 are coupled to the interface 340 at different points of the interface. Therefore, the length of the signal (transmission) line(s) coupling the slave device 320 to the master device 310 is different from the length of the signal (transmission) line(s) coupling the slave device 330 to the master device 310. The different distances between the master device 310 and the two slave devices 320 and 330 result in different propagation delays (times) for signals transmitted from the slave devices 320 and 330 to the master device 310, and vice versa.

[0046] This is Figure 4 In the example shown in FIG. Figure 4 In the example of FIG. 3 , the distance from the slave device 320 to the master device 310 along the interface 340 is less than the distance from the slave device 330 to the master device 310 along the interface 340. In other words, the slave device 320 is arranged closer to the master device 310 than another slave device 330. Therefore, the propagation delay t of the signal exchanged between the slave device 320 and the master device 310 is PropA Less than the propagation delay t of the signal exchanged between another slave device 330 and the master device 310 PropB Further, each of slave devices 320 and 330 may exhibit different output timing.

[0047] Using the proposed calibration technique, the output timing of slave devices 320 and 330 can be aligned with the reference clock of the master device.

[0048] Although the system 300 includes two slave devices 320 and 330, the proposed calibration technique is described below only with respect to the slave device 320. It should be noted that the output timing of the other slave device 330 can be adjusted accordingly. Further, it should be noted that the proposed calibration technique can be used for systems including more or fewer slave devices than the system 300.

[0049] Figure 5 The operation of the master device 310 is schematically illustrated. Figure 5 The upper portion of FIG. 1 illustrates the reference clock (signal) 510 of the master device 310. Figure 5 In the example of FIG. 5 , it is assumed that the length (duration) of a data symbol used to exchange data between the master device 310 and the slave device 320 is equal to the length (duration) of a clock cycle of the reference clock 510 .

[0050] For ease of explanation, it is assumed that the master device generates an output synchronized with the leading edge of the reference clock 510 (i.e., the rising edge in this example), and the master device samples the input data synchronized with the trailing edge of the reference clock 510 (i.e., the falling edge in this example). In other words, the data sampling in the master device is performed with a phase offset of 180° compared to the data generation to hit the center of the data eye. However, it should be noted that a phase offset different from 180° can also be used.

[0051] Figure 5 The lower portion of illustrates the signal of signal line D+ as viewed at terminal 313 of master device 310. Since master device 310 generates its output at the leading edge of the internal symbol clock, master device 310 generates signal transitions between different signal levels (i.e., rising signal edges or falling signal edges) synchronized with the leading edge of reference clock 510. Figure 5 In the example of , the master device 310 outputs data in symbol slots -1 and 0 by generating signal transitions that are synchronized with the leading edges of clock cycles associated with symbol slots -1 and 0.

[0052] During symbol slot 1, signal line D+ is not driven, i.e., in a tri-state mode, to avoid collision between output data of master device 310 and input data from slave device 320. Starting from symbol slot 2, the symbol transmitted by slave device 320 arrives at terminal 313 of master device 310. Master device 310 samples the incoming data synchronized with the trailing edge of reference clock 510 to sample the symbol of slave device 320 at the center.

[0053] exist Figure 5In the example of , slave device 310 transmits input symbols such that the signal edge of the input symbols is fully aligned with the leading edge of reference clock 510 at terminal 313 of master device 310. To achieve this alignment, the output timing of slave device 320 is adjusted according to the proposed calibration technique.

[0054] References below Figure 6 and Figure 7 The calibration process is described in detail. Figure 6 and Figure 7 In the example of , for ease of description, it is assumed that the master device 310 transmits only one first signal edge, and the slave device 320 transmits only one second signal edge. However, it should be noted that in alternative examples, the master device 310 and the slave device 320 may transmit multiple signal edges respectively.

[0055] Figure 6 The upper part of illustrates the reference clock 510. The length (duration) of a data symbol of data exchanged between the master device 310 and the slave device 320 is again equal to the length (duration) of a clock period of the reference clock 510. Figure 6 The lower part of again illustrates the signal of the signal line D+ as observed at the terminal 313 of the master device 310 .

[0056] The master device 310 transmits a single first signal edge 601 to the slave device 320 synchronously with the leading edge of the clock cycle associated with the symbol time slot 0. The single first signal edge 601 indicates a synchronization event. During symbol time slot 1, the signal line D+ is not driven, i.e., in a tri-state mode, in order to avoid conflicts between the output data of the master device 310 and the input data from the slave device 320.

[0057] The single first signal edge 601 is received by the slave device 320 and decoded to detect the synchronization event. Further, the slave device 320 recovers the reference clock of the master device based on the single first signal edge 601 .

[0058] In response to detecting the synchronization event, the slave device 320 transmits a single second signal edge 602 to the master device in symbol time slot 2 (since the master device has the interface 340 at a high signal level, Figure 6 As described above, the slave device 320 generates a single second signal edge 602 based on the recovered reference clock. The master device receives the single second signal edge 602 at the terminal 313 via the interface 340. Subsequently, the master device 310 samples the single second signal edge 602 at the leading edge of the reference clock 510 to obtain a sampled value of the single second signal edge 602.

[0059] Depending on the output timing of the slave device 320, three different situations a) to c) may occur.

[0060] In case a), the output timing of the slave device 320 is such that at the terminal 313, the single second signal edge 602 is late relative to the reference clock 510 of the master device 310. That is, when the master device 320 samples the signal of the signal line D+ at the leading edge of the clock cycle associated with the symbol time slot 2, the single second signal edge 602 has not yet arrived at the terminal 313. Therefore, in case a), the sampled value of the single second signal edge 602 indicates a high signal level at the signal line D+. The master device 320 transmits a high signal level in the predefined symbol time slot m to indicate the sampled high signal level.

[0061] In case c), the output timing of the slave device 320 is such that at the terminal 313, the single second signal edge 602 is early relative to the reference clock 510 of the master device 310. That is, before the master device 320 samples the signal of the signal line D+ at the leading edge of the clock cycle associated with the symbol time slot 2, the single second signal edge 602 has arrived at the terminal 313. Therefore, in case b), the sampled value of the single second signal edge 602 indicates a low signal level at the signal line D+. The master device 320 transmits a low signal level in the predefined symbol time slot m to indicate the sampled low signal level.

[0062] In case b), the output timing of the slave device 320 is such that at the terminal 313, the single second signal edge 602 is substantially synchronized with respect to the reference clock 510 of the master device 310. That is, the single second signal edge 602 arrives at the terminal 313 substantially simultaneously with the master device 320 sampling the signal of the signal line D+ at the leading edge of the clock cycle associated with the symbol time slot 2. In case b), the sampled value of the single second signal edge 602 indicates a low signal level or a high signal level at the signal line D+, depending on statistical effects such as jitter of the reference clock. The chances of sampling the low signal level or the high signal level are (substantially) the same. Thus, the master device 320 transmits a low signal level or a high signal level in a predefined symbol time slot m to indicate the low signal level or the high signal level as sampled.

[0063] In each of cases a) to c), slave device 320 receives a low signal level or a high signal level in symbol slot m and compares the received signal to the single second signal edge 602 transmitted in symbol slot 2 .

[0064] In case a), the comparison of the high signal level in symbol slot m with the falling signal edge transmitted in symbol slot 2 informs the slave device 320 that the second signal edge 602 is behind the reference clock 510 of the master device 310 at the terminal 313. Therefore, the slave device 320 shifts its output timing to an earlier output timing so that the future signal edge outputted by the slave device 320 will arrive at the terminal 313 earlier than the second signal edge 602.

[0065] In case c), the comparison of the low signal level in symbol slot m with the falling signal edge transmitted in symbol slot 2 informs the slave device 320 that the second signal edge 602 is ahead of the reference clock 510 of the master device 310 at the terminal 313. Therefore, the slave device 320 shifts its output timing to a later output timing, so that the future signal edge outputted by the slave device 320 will arrive at the terminal 313 later than the second signal edge 602.

[0066] In case b), the comparison of the signal level indicated in symbol slot m with the falling edge of the signal transmitted in symbol slot 2 informs the slave device 320 that the second signal edge 602 at the terminal 313 has an equal probability of being before and after the reference clock 510 of the master device 310. Thus, if the proposed calibration process is repeated a number of times, the slave device will adjust its output timing so that the arrival time of future signal edges output by the slave device 320 switches to near the leading edge of the reference clock 510.

[0067] In summary (and taking into account that multiple signal edges may also be transmitted), the master device 310 may receive one or more predetermined second signal edges in a first predetermined time slot after one or more consecutive first signal edges (the slave device 320 may transmit one or more predetermined second signal edges accordingly). Similarly, the slave device 320 may receive data indicating one or more sampled values ​​of the master device 310 in a second predetermined time slot after one or more consecutive first signal edges (the master device 310 may transmit data indicating one or more sampled values ​​accordingly).

[0068] As described above, the master device 310 may transmit a plurality of consecutive first signal edges for indicating a synchronization event (the slave device 320 may receive a plurality of consecutive first signal edges accordingly). Similarly, the slave device 320 may transmit a plurality of predetermined second signal edges to the master device 310 (the master device 310 may receive a plurality of predetermined second signal edges accordingly). Thus, the master device 310 may transmit data indicating a plurality of sampled values ​​of a plurality of predetermined second signal edges (the slave device 320 may receive data indicating a plurality of sampled values ​​accordingly).

[0069] Similar to what was described above for the single second signal edge 602 transmitted in symbol time slot 2, the slave device 320 may transmit multiple predetermined second signal edges to the master device 310 (and the master device 310 may receive the multiple predetermined second signal edges accordingly) within a third predetermined time slot following one or more consecutive first signal edges.

[0070] Similar to what is described above for the signal level transmitted in symbol time slot m, the master device 310 may transmit data indicating multiple sampling values ​​of multiple predetermined second signal edges to the slave device 320 in a fourth predetermined time slot after one or more consecutive first signal edges (the slave device 320 may correspondingly receive data indicating multiple sampling values).

[0071] In other words, each synchronization event can insert multiple known signal transitions and multiple reflected edge samples of slave device 320 for example to speed up calibration. Further, multiple slave devices can be calibrated serially so that multiple known signal transitions and multiple reflected edge samples follow the synchronization event.

[0072] As described above, the proposed calibration process can be repeated several times. For example, the slave device 320 can transmit one or more predetermined second signal edges of a plurality of predetermined second signal edges to the master device 310 after receiving one or more consecutive first signal edges, and can also transmit one or more predetermined second signal edges of a plurality of predetermined second signal edges to the master device 310 after receiving one or more consecutive third signal edges indicating subsequent synchronization events from the master device 310, and so on. Thus, the master device 310 can sample one or more predetermined second signal edges of the received plurality of predetermined second signal edges each time, and transmit corresponding data indicating the sampled values ​​of one or more predetermined second signal edges of the plurality of predetermined second signal edges to the slave device 320, so that the slave device can iteratively adjust its output timing.

[0073] Figure 7 The diagram shows Figure 6 A calibration process similar to the one shown in the figure. Figure 6 Compared to the calibration process illustrated in , a third signal edge 603 indicative of a subsequent synchronization event is transmitted between the single second signal edge 602 and the signal level indicative of the signal level as sampled by the master device 620 .

[0074] exist Figure 7In the example of , after sampling the single second signal edge 602 in symbol slot 2, the master device 310 transmits a third single signal edge 603 synchronously with the leading edge of the clock cycle associated with the symbol slot s. The third single signal edge 603 indicates a subsequent synchronization event. After transmitting the subsequent synchronization event in symbol slot s, the master device 310 transmits a corresponding high signal level or low signal level in a predefined symbol slot s+2 to indicate the signal level sampled in symbol slot 2.

[0075] Based on the signal level in symbol slot s+2, slave device 320 adjusts its output timing similarly as described above.

[0076] In summary, the master device 310 may transmit one or more consecutive third signal edges indicating a subsequent synchronization event to the slave device 320 before transmitting data indicating one or more sampled values ​​of the one or more predetermined second signal edges. After receiving the one or more predetermined second signal edges from the slave device 320, the one or more consecutive third signal edges are transmitted to the slave device 320 (the slave device 320 may receive the one or more consecutive third signal edges accordingly). For example, the master device may transmit data indicating one or more sampled values ​​of the one or more predetermined second signal edges within a predetermined time slot after the one or more consecutive third signal edges (the slave device 320 may receive the data indicating the one or more sampled values ​​accordingly).

[0077] In other words, edge samples of the inserted known signal transitions of the slave device 320 and the reflections of the master device 310 may be generated after different synchronization events.

[0078] If multiple predetermined second signal edges are used, filtering can be used for multiple sampled values ​​received from the master device 310. For example, the proposed method for the slave device may also include filtering multiple sampled values ​​of multiple predetermined second signal edges of the master device before adjusting the output timing of the slave device based on the comparison of the multiple predetermined second signal edges with the multiple sampled values ​​of the master device. For example, before comparing one of the multiple predetermined second signal edges with the second signal edge, multiple sampled values ​​for the same signal edge in the multiple predetermined second signal edges may be averaged, and so on. In other words, multiple reflected edge samples may be filtered to determine the output timing adjustment.

[0079] In some examples, if the interface includes multiple communication lines for communicatively coupling a master device and a slave device, the slave device can receive one or more continuous first signal edges via one or more first communication lines of the interface. The one or more first communication lines of the interface are different from the one or more second communication lines of the interface used by the master device and the slave device to exchange payload data. In other words, the synchronization event does not have to be embedded in the data, and the synchronization event can be transmitted on an additional communication line. Alternatively, the slave device can receive one or more continuous first signal edges via one or more communication lines of the interface, and the one or more communication lines of the interface are also used by the master device and the slave device to exchange payload data.

[0080] Can be obtained from Figure 8 The effect of the proposed calibration procedure can be seen in Figure 8 The diagram illustrates the data exchange between the master device 310 and the slave devices 320 and 330 after the proposed calibration process. Figure 8 In the example of FIG. 3 , it is also assumed that the system 300 includes a third slave device. Each slave device has adjusted its output timing.

[0081] Figure 8 The upper portion of shows a reference clock 510 of the master device 310 . Figure 8 The lower part of again illustrates the signal of the signal line D+ as observed at the terminal 313 of the master device 310 .

[0082] The master device 310 transmits a single signal edge 801 to the slave device synchronously with the leading edge of the clock cycle associated with symbol time slot 0. The first signal edge 801 indicates a synchronization event. During symbol time slot 1, the signal line D+ is not driven, i.e., is in a tri-state mode, in order to avoid conflicts between the output data of the master device 310 and the input data from the slave device.

[0083] The slave devices transmit at different points in time because they are coupled to the interface at different distances from the master device 310 (e.g., closer slave devices may respond later). Due to the previous calibration of the output timing of the slave devices, the data blocks 810, 820 and 830 of the three slave devices arrive through the aligned data eye openings of the master device 310. As described above, the proposed calibration process may also allow compensation for the individual I / O delays of the master and slave devices. Due to the alignment of the slave data with the reference clock of the master device 310, a single undriven symbol time slot 840 and 850 between the data blocks 810, 820 and 830 as shown in case a) may be sufficient to avoid collisions. If the output timing of the individual slave devices is well adjusted, then as shown in case a) Figure 8 As shown in case b) in FIG. 1 , undriven symbol slots for avoiding collisions may be discarded (omitted).

[0084] In the following, reference Fig. 9 and Fig.10 More detailed examples of master and slave devices according to the proposed technology are described.

[0085] Fig. 9 An example of a master device 900 for enabling a slave device communicatively coupled to the master device to calibrate its output timing according to the proposed technique is illustrated.

[0086] The master device 900 includes a transmitter circuit 910, a receiver circuit 920, and a processing circuit 930. Further, the master device 900 includes two terminals 901 and 902 for coupling the transmitter circuit 910 and the receiver circuit 920 to a differential interface (indicated by different signal lines D+ and D-), which communicatively couples the master device 900 to the slave device.

[0087] The transmitter circuit 910 includes two flip-flop circuits 911 and 912 and a driver circuit 913 (eg, an amplifier). The flip-flop circuit 911 is used to enable / disable the driver circuit 913, while the flip-flop circuit 912 provides data to be transmitted to the driver circuit 913.

[0088] Processing circuit 930 provides reference clock signal 903 and output enable signal 904 (which indicates whether to enable / disable driver circuit 913) to flip-flop circuit 911. Thus, flip-flop circuit 911 supplies driver circuit 913 with enable signal 905, which is synchronized with the reference clock.

[0089] Further, processing circuit 930 provides reference clock signal 903 and data signal 909, which includes data to be sent to flip-flop circuit 912. Thus, flip-flop circuit 912 supplies driver circuit 913 with a data signal, which includes data to be transmitted and is synchronized with the reference clock.

[0090] The driver circuit 913 drives the signal levels on the signal lines D+ and D− of the differential interface according to the signals provided by the flip-flop circuits 911 and 912 .

[0091] The receiver circuit 920 includes a driver circuit 921 (e.g., an amplifier) ​​and two flip-flop circuits 922 and 923. The driver circuit 921 receives the signal levels on the signal lines D+ and D- of the differential interface and generates a single-ended reception signal based on the signal levels. The flip-flop circuits 922 and 923 sample the single-ended reception signal based on the reference clock signal 903. The flip-flop circuit 922 samples the single-ended reception signal synchronized with the leading edge of the reference clock signal 903, while the flip-flop circuit 923 samples the single-ended reception signal synchronized with the trailing edge of the reference clock signal 903.

[0092] Flip-flop circuit 923 is used to sample incoming data from the slave device at the center of the data eye in order to recover data from the slave device. Thus, flip-flop circuit 922 provides input data signal 908 including sampled input data. Flip-flop circuit 922 is used to sample one or more predetermined second signal edges, which are used to calibrate the slave device. Thus, flip-flop circuit 922 provides signal 907, which includes data indicating sampled values ​​of one or more predetermined second signal edges.

[0093] The data signal 909 is provided by the multiplexer circuit 931 of the processing circuit 930. The multiplexer circuit 931 can supply the output data signal 906 or signal 907 to the trigger circuit 912, and the signal 907 includes the data of the sampled value indicating one or more predetermined second signal edges. For example, the output data signal 906 can include data about the synchronization event, so that the multiplexer circuit 931 supplies the data about the synchronization event to the trigger circuit 912 as the data signal 909 (or if the slave device is not calibrated, it is the payload data). Thus, the driver circuit 913 transmits one or more continuous first signal edges indicating the synchronization event to the slave device via the signal lines D+ and D- of the differential interface. For example, the synchronization event can be a conversion from a low signal level to a high signal level. Based on the synchronization event, the reference clock can be recovered from the device, and the data transmitted by the master device 900 is decoded.

[0094] The signal 907 including data indicating the sampled values ​​of one or more predetermined second signal edges is delayed by the delay circuit 932 of the processing circuit 930. The multiplexer circuit 931 supplies the delayed data indicating the sampled values ​​of one or more predetermined second signal edges to the flip-flop circuit 912 as the data signal 909, so that the driver circuit 913 transmits the data indicating the sampled values ​​of one or more predetermined second signal edges within a predetermined time slot (e.g., in a predetermined symbol time slot as described above) after one or more consecutive first signal edges. In other words, the master device 900 can be configured to reflect the "edge data" of the slave device in a later (delayed) symbol time slot.

[0095] The master device 900 may allow data indicating one or more consecutive first signal edges indicating synchronization events and sampled values ​​indicating one or more predetermined second signal edges to be provided to the slave device so that the slave device may adjust its output timing according to the proposed technique.

[0096] Fig.10 An example of a slave device 1000 capable of calibrating the timing of its output for transmitting data to a master device is illustrated.

[0097] The slave device 1000 includes a receiver circuit 1010, a transmitter circuit 1020, and a processing circuit 1030. Further, the slave device 1000 includes two terminals 1001 and 1002 for coupling the receiver circuit 1010 and the transmitter circuit 1020 to a differential interface (indicated by different signal lines D+ and D-) that communicatively couples the slave device 1000 to a master device.

[0098] The receiver circuit 1010 includes a driver circuit 1011 (eg, an amplifier) ​​and a trigger circuit 1012. The driver circuit 1011 receives the signal level on the signal lines D+ and D- of the differential interface and generates a single-ended reception signal based on the signal level. The trigger circuit 1012 samples the single-ended reception signal.

[0099] The processing circuit 1030 includes a clock recovery circuit 1031, which is used to recover the reference clock of the master device. One or more consecutive first signal edges received from the master device via the differential interface indicate a synchronization event and include information related to the phase and frequency of the reference clock of the master device. The clock recovery circuit 1031 may, for example, include a PLL or a DLL to recover the reference clock of the master device using known clock recovery techniques. In other words, the slave device 1000 can recover the reference clock through the PLL or the DLL based on the synchronization event embedded in the data sent by the master device.

[0100] The recovered reference clock is delayed by 180° via the delay circuit 1032 of the processing circuit 1030 to provide a delayed copy of the reference clock to the flip-flop circuit 1012. The flip-flop circuit 1012 samples a single-ended received signal that is synchronized with the leading edge of the delayed reference clock (i.e., effectively synchronized with the trailing edge of the actual reference clock) to sample the received input data in the middle of the data eye. The flip-flop circuit 1012 provides an input data signal 1003 that includes the sampled input data.

[0101] The transmitter circuit 1020 includes two trigger circuits 1021 and 1022 and a driver circuit 1023 (e.g., an amplifier). The trigger circuit 1022 is used to enable / disable the driver circuit 1023, and the trigger circuit 1021 provides data to be transmitted to the driver circuit 1023. The driver circuit 1023 drives the signal level on the signal lines D+ and D- of the differential interface according to the signals provided by the trigger circuits 1021 and 1022. The trigger circuits 1021 and 1022 are controlled by the processing circuit 1030.

[0102] The processing circuit 1030 includes a phase adjustment circuit 1034. The phase adjustment circuit 1034 receives the input data signal 1003 from the flip-flop circuit 1012. If the input data signal 1003 includes one or more signal edges of a master device for indicating a synchronization event, the phase adjustment circuit 1034 controls the transmitter circuit 1020 to output one or more predetermined second signal edges via an AND gate 1035 and an OR gate 1036. In other words, the slave device can transmit a known data transition to the master device (e.g., driving the signal level to low after the master device has the interface at a high signal level).

[0103] Subsequently, the slave device 1000 receives data indicating one or more sampled values ​​of one or more predetermined second signal edges of the master device from the master device. The data indicating one or more sampled values ​​are provided to the phase adjustment circuit 1034 by means of the input data signal 1003. The phase adjustment circuit 1034 compares the one or more predetermined second signal edges with the one or more sampled values ​​of the one or more predetermined second signal edges of the master device to determine the adjustment of the output timing of the slave device 1000.

[0104] The clock recovery circuit 1031 provides multiple phase-shifted copies of the recovered reference clock. Based on the comparison of one or more predetermined second signal edges with one or more sampled values ​​of one or more predetermined second signal edges of the master device, the phase adjustment circuit 1034 controls the phase selection circuit 1033 of the processing device 1030 to select one of the multiple phase-shifted copies of the recovered reference clock. In other words, the phase selection circuit 1033 uses the edge data reflected by the master device to adjust the output timing of the slave device 1000.

[0105] The phase selection circuit 1033 supplies the selected copy of the recovered reference clock to the flip-flop circuits 1021 and 1022 of the transmitter device 1020, so that the flip-flop circuit 1022 enables / disables the driver circuit 1023 in synchronization with the signal leading edge of the selected copy of the recovered reference clock, and causes the flip-flop circuit 1021 to provide data to the driver circuit 1023, which is to be transmitted in synchronization with the signal leading edge of the selected copy of the recovered reference clock. In other words, the slave device 1000 can adjust its output timing by fractions of the clock period (e.g., the clock phase can be provided by the DLL).

[0106] If the slave device 1000 has not calibrated its output timing, the AND gate 1035 and the OR gate 1036 allow payload data or other data to be provided to be transmitted to the trigger circuits 1021 and 1022 of the transmitter device 1020, so that the trigger circuits 1021, 1022 control the driver circuit 1023 to drive the lines D+ and D- of the differential interface according to the data to be transmitted.

[0107] although Fig. 9 and Fig.10 Although not shown in the figure, the master device 900 and the slave device 1000 may optionally include other circuits and / or elements.

[0108] The examples described in this article can be summarized as follows:

[0109] Some examples relate to a method for calibrating output timing of data transmission to a master device from a slave device. The master device and the slave device are coupled via an interface communication. The method includes: receiving one or more continuous first signal edges indicating a synchronization event from the master device. Further, the method includes: recovering a reference clock of the master device based on the one or more continuous first signal edges. The method includes: transmitting one or more predetermined second signal edges to the master device. The one or more predetermined second signal edges are generated by the slave device using the recovered reference clock. Additionally, the method includes: receiving data indicating one or more sampled values ​​of the master device for one or more predetermined second signal edges from the master device. The method includes: adjusting the output timing based on a comparison of the one or more predetermined second signal edges with one or more sampled values ​​of the master device for the one or more predetermined second signal edges.

[0110] In some examples, adjusting the output timing includes: comparing one or more signal levels indicated by one or more sampled values ​​of the master device with one or more predetermined second signal edges to determine whether the one or more predetermined second signal edges are before or after a reference clock of the master device; and shifting the output timing of the slave device to an earlier output timing if the one or more predetermined second signal edges are after the reference clock of the master device; or shifting the output timing of the slave device to a later output timing if the one or more predetermined second signal edges are before the reference clock of the master device.

[0111] According to some examples, the slave device receives data indicative of one or more sampled values ​​of the master device within a predetermined time slot after one or more consecutive first signal edges.

[0112] In an alternative example, after receiving one or more consecutive third signal edges indicating a subsequent synchronization event from the master device, the slave device receives data indicating one or more sampled values ​​of the master device, wherein the one or more consecutive third signal edges are received by the slave device after transmitting one or more predetermined second signal edges to the master device.

[0113] In some examples, one or more consecutive first signal edges encode information about the phase and frequency of a reference clock of the master device.

[0114] According to some examples, the slave device transmits a plurality of predetermined second signal edges to the master device, and wherein the slave device receives data indicating a plurality of sampled values ​​of the master device for the plurality of predetermined second signal edges.

[0115] In some examples, the slave device transmits a plurality of predetermined second signal edges to the master device within predetermined time slots after one or more consecutive first signal edges.

[0116] In an alternative example, after receiving one or more consecutive first signal edges, the slave device transmits one or more predetermined second signal edges of a plurality of predetermined second signal edges to the master device; and after receiving one or more consecutive third signal edges indicating a subsequent synchronization event from the master device, the slave device further transmits one or more predetermined second signal edges of a plurality of predetermined second signal edges to the master device.

[0117] According to some examples, the method further includes filtering the plurality of sampled values ​​of the master device for the plurality of predetermined second signal edges before adjusting the output timing of the slave device based on the comparison of the plurality of predetermined second signal edges with the plurality of sampled values ​​of the master device.

[0118] In some examples, the interface includes a plurality of communication lines for communicatively coupling the master device and the slave device. The slave device receives one or more consecutive first signal edges via one or more first communication lines of the interface. The one or more first communication lines of the interface are different from one or more second communication lines of the interface, and the one or more second communication lines are used by the master device and the slave device to exchange payload data.

[0119] According to some examples, the method is performed during booting of the slave device.

[0120] In other examples, the method is performed between two payload data exchanges between a master device and a slave device.

[0121] Other examples relate to a method for a master device for enabling a slave device coupled to the master device via an interface communication to calibrate output timing. The method includes: transmitting one or more consecutive first signal edges indicating a synchronization event to the slave device. The one or more consecutive first signal edges are generated using a reference clock of the master device. Further, the method includes: sampling one or more predetermined second signal edges received from the slave device using the reference clock to obtain sampled values ​​for the one or more predetermined second signal edges. Additionally, the method includes: transmitting data indicating one or more sampled values ​​for the one or more predetermined second signal edges to the slave device.

[0122] According to some examples, the master device transmits data indicating one or more sampled values ​​for one or more predetermined second signal edges within a predetermined time slot after one or more consecutive first signal edges.

[0123] According to an alternative example, before transmitting data indicating one or more sampled values ​​for one or more predetermined second signal edges, the master device transmits one or more consecutive third signal edges indicating subsequent synchronization events to the slave device, wherein the one or more consecutive third signal edges are transmitted to the slave device after receiving the one or more predetermined second signal edges from the slave device.

[0124] In some examples, one or more consecutive first signal edges encode information about the phase and frequency of the reference clock.

[0125] According to some examples, the master device receives a plurality of predetermined second signal edges from the slave device, and wherein the master device transmits data indicative of a plurality of sampled values ​​for the plurality of predetermined second signal edges.

[0126] In some examples, the master device receives a plurality of predetermined second signal edges from the slave device within predetermined time slots after one or more consecutive first signal edges.

[0127] In an alternative example, after transmitting one or more consecutive first signal edges, the master device receives one or more predetermined second signal edges from the slave device, and after transmitting one or more consecutive third signal edges indicating a subsequent synchronization event, the master device further receives one or more predetermined second signal edges from the slave device.

[0128] According to some examples, the interface includes a plurality of communication lines for communicatively coupling a master device and a slave device. The master device transmits one or more consecutive first signal edges via one or more first communication lines of the interface. The one or more first communication lines of the interface are different from one or more second communication lines of the interface, and the one or more second communication lines are used by the master device and the slave device to exchange payload data.

[0129] In some examples, the method is performed during startup of the slave device.

[0130] In other examples, the method is performed between two payload data exchanges between a master device and a slave device.

[0131] Other examples relate to a slave device adapted to calibrate output timing for transmitting data to a master device. The master device and the slave device are coupled via an interface communication. The slave device includes a receiver circuit configured to receive one or more continuous first signal edges indicating a synchronization event from the master device. Further, the slave device includes a processing circuit configured to recover a reference clock of the master device based on one or more continuous first signal edges. The slave device also includes a transmitter circuit configured to transmit one or more predetermined second signal edges to the master device. The one or more predetermined second signal edges are generated by the slave device using the recovered reference clock. The receiver circuit is also configured to receive data indicating one or more sampled values ​​of the master device for one or more predetermined second signal edges from the master device. The processing circuit is also configured to adjust the output timing based on a comparison of one or more predetermined second signal edges with one or more sampled values ​​of the master device for one or more predetermined second signal edges.

[0132] Still other examples relate to a master device adapted to enable a slave device coupled to the master device via an interface communication to calibrate output timing. The master device includes a transmitter circuit configured to transmit one or more continuous first signal edges indicating a synchronization event to the slave device, wherein the one or more continuous first signal edges are generated using a reference clock of the master device. Additionally, the master device includes a receiver circuit configured to sample one or more predetermined second signal edges received from the slave device using a reference clock to obtain sampled values ​​for the one or more predetermined second signal edges. The transmitter circuit is also configured to transmit data indicating one or more sampled values ​​for the one or more predetermined second signal edges to the slave device.

[0133] Some examples relate to a system comprising a master device as described herein, at least one slave device as described herein, and an interface configured to communicatively couple the master device and the at least one slave device.

[0134] Examples relate to a non-transitory machine-readable medium having stored thereon a program having program code for causing the slave device to perform a method for calibrating output timing as described herein when the program is executed on programmable hardware of the slave device.

[0135] Other examples relate to a program having program code for causing a slave device to perform a method for calibrating output timing as described herein when the program is executed on programmable hardware of a slave device.

[0136] Other examples relate to a non-transitory machine-readable medium having stored thereon a program having program code for causing the master device to perform the method for enabling a slave device to calibrate output timing as described herein when the program is executed on programmable hardware of the master device.

[0137] Other examples relate to a program having program code for causing the master device to perform the method for enabling a slave device to calibrate output timing as described herein when the program is executed on programmable hardware of the master device.

[0138] Some examples relate to an apparatus comprising means for causing a slave device to perform a method for calibrating output timing as described herein.

[0139] Other examples relate to an apparatus comprising means for causing a master device to perform a method for enabling a slave device to calibrate output timing as described herein.

[0140] Examples of the present disclosure may enable fast output timing calibration for high-speed interfaces.

[0141] The various aspects and features mentioned and described and one or more of the previously detailed examples and figures may also be combined with one or more other examples in other examples to replace similar features in another example or to additionally introduce features into another example.

[0142] The description and drawings only illustrate the principles of the present disclosure. Furthermore, all examples listed herein are in principle and explicitly intended for illustrative purposes only, to help the reader understand the principles of the present disclosure and the ideas made by the (multiple) inventors to further develop the art. All statements herein citing the principles, aspects and examples of the present disclosure and their specific examples are intended to include their equivalents.

[0143] Block diagrams, for example, may illustrate high-level circuit diagrams that implement the principles of the present disclosure. Likewise, flow charts, flow diagrams, state transition diagrams, pseudocode, etc. may represent various processes, operations, or steps, which, for example, may be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such computers or processors are explicitly shown. Methods disclosed in the specification or claims may be implemented by an apparatus having means for performing each of the corresponding acts of such methods.

[0144] It should be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims will not be interpreted as being in a specific order unless explicitly or implicitly indicated, for example, for technical reasons. Therefore, unless multiple actions or functions are not interchangeable due to technical reasons, the disclosure of these actions or functions will not limit them to a specific order. Further, in some examples, a single action, function, process, operation or step may include or be decomposed into multiple sub-actions, functions, processes, operations or steps. Unless explicitly excluded, these sub-actions may be included and be part of the disclosure of the single action.

[0145] Furthermore, the following claims are hereby incorporated into the detailed description, where each claim can be independently presented as a separate example. Although each claim can be independently presented as a separate example, it should be noted that although a dependent claim may refer to a specific combination with one or more other claims in a claim, other examples may also include a combination of a dependent claim with the subject matter of a mutually dependent or independent claim. Unless it is indicated that a specific combination is not intended, such a combination is explicitly proposed herein. Furthermore, it is intended that the features of a claim are also included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

Claims

1. A method for calibrating output timing of data transmission to a master device from a slave device, wherein the master device and the slave device are communicatively coupled via an interface, the method comprising: receiving one or more consecutive first signal edges indicative of a synchronization event from the master device; recovering a reference clock of the master device based on the one or more consecutive first signal edges; transmitting one or more predetermined second signal edges to the master device, wherein the one or more predetermined second signal edges are generated by the slave device using the recovered reference clock; receiving, from the master device, data indicating one or more sampled values ​​of the master device for the one or more predetermined second signal edges, wherein the one or more sampled values ​​indicate respective signal levels of the one or more predetermined second signal edges at respective sampling times; as well as The output timing is adjusted based on a comparison of the one or more predetermined second signal edges and the one or more sampled values ​​of the master device for the one or more predetermined second signal edges.

2. The method of claim 1 , wherein adjusting the output timing comprises: comparing one or more signal levels indicated by the one or more sampled values ​​of the master device with the one or more predetermined second signal edges to determine whether the one or more predetermined second signal edges are before or after the reference clock of the master device; as well as shifting the output timing of the slave device to an earlier output timing if the one or more predetermined second signal edges are after the reference clock of the master device; or If the one or more predetermined second signal edges are before the reference clock of the master device, the output timing of the slave device is shifted to a later output timing.

3. A method according to claim 1 or 2, wherein the slave device receives the data indicating the one or more sampled values ​​of the master device after receiving one or more consecutive third signal edges indicating a subsequent synchronization event from the master device, wherein the one or more consecutive third signal edges are received by the slave device after transmitting the one or more predetermined second signal edges to the master device.

4. The method of claim 1 or 2, wherein the one or more consecutive first signal edges encode information about the phase and frequency of the reference clock of the master device.

5. The method according to claim 1 or 2, wherein the slave device transmits a plurality of predetermined second signal edges to the master device, and wherein the slave device receives data indicating a plurality of sampled values ​​of the master device for the plurality of predetermined second signal edges.

6. A method according to claim 1 or 2, wherein the interface includes multiple communication lines, and the multiple communication lines are used to communicatively couple the master device and the slave device, wherein the slave device receives the one or more continuous first signal edges via one or more first communication lines of the interface, and wherein the one or more first communication lines of the interface are different from one or more second communication lines of the interface, and the one or more second communication lines of the interface are used by the master device and the slave device to exchange payload data.

7. The method according to claim 1 or 2, wherein the method is performed between two payload data exchanges between the master device and the slave device.

8. A method for a master device for enabling a slave device communicatively coupled to the master device via an interface to calibrate output timing, the method comprising: transmitting one or more consecutive first signal edges indicating a synchronization event to the slave device, wherein the one or more consecutive first signal edges are generated using a reference clock of the master device; sampling one or more predetermined second signal edges received from the slave device using the reference clock to obtain sampling values ​​for the one or more predetermined second signal edges, wherein the one or more sampling values ​​indicate corresponding signal levels of the one or more predetermined second signal edges at corresponding sampling times; as well as Data indicative of one or more sampled values ​​for the one or more predetermined second signal edges is transmitted to the slave device.

9. The method of claim 8, wherein the one or more consecutive first signal edges encode information about a phase and a frequency of the reference clock.

10. The method of claim 8 or 9, wherein the master device receives a plurality of predetermined second signal edges from the slave device, and wherein the master device transmits data indicative of a plurality of sampled values ​​for the plurality of predetermined second signal edges.

11. A method according to claim 10, wherein after transmitting the one or more consecutive first signal edges, the master device receives one or more predetermined second signal edges of the multiple predetermined second signal edges from the slave device; and after transmitting one or more consecutive third signal edges indicating a subsequent synchronization event, the master device further receives one or more predetermined second signal edges of the multiple predetermined second signal edges from the slave device.

12. A method according to claim 8 or 9, wherein the interface includes multiple communication lines, and the multiple communication lines are used to communicatively couple the master device and the slave device, wherein the master device transmits the one or more continuous first signal edges via one or more first communication lines of the interface, and wherein the one or more first communication lines of the interface are different from one or more second communication lines of the interface, and the one or more second communication lines of the interface are used by the master device and the slave device to exchange payload data.

13. A slave device, adapted to calibrate output timing for transmitting data to a master device, wherein the master device and the slave device are communicatively coupled via an interface, the slave device comprising: a receiver circuit configured to receive one or more consecutive first signal edges indicative of a synchronization event from the master device; a processing circuit configured to recover a reference clock of the master device based on the one or more consecutive first signal edges; as well as a transmitter circuit configured to transmit one or more predetermined second signal edges to the master device, wherein the one or more predetermined second signal edges are generated by the slave device using the recovered reference clock; wherein the receiver circuit is further configured to receive data indicating one or more sampled values ​​of the master device for the one or more predetermined second signal edges from the master device, wherein the one or more sampled values ​​indicate respective signal levels of the one or more predetermined second signal edges at respective sampling times; and The processing circuit is further configured to adjust the output timing based on a comparison of the one or more predetermined second signal edges with the one or more sampled values ​​of the master device for the one or more predetermined second signal edges.

14. A master device adapted to enable a slave device communicatively coupled to the master device via an interface to calibrate output timing, the master device comprising: a transmitter circuit configured to transmit one or more consecutive first signal edges indicating a synchronization event to the slave device, wherein the one or more consecutive first signal edges are generated using a reference clock of the master device; as well as a receiver circuit configured to sample one or more predetermined second signal edges received from the slave device using the reference clock so as to obtain sampled values ​​for the one or more predetermined second signal edges, wherein the one or more sampled values ​​indicate corresponding signal levels of the one or more predetermined second signal edges at corresponding sampling times, The transmitter circuit is further configured to transmit data indicating the one or more sampled values ​​for the one or more predetermined second signal edges to the slave device.

15. A communication system comprising: The master device according to claim 14; at least one slave device according to claim 13; as well as An interface is configured to communicatively couple the master device and at least one of the slave devices.

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