Method for manufacturing a semiconductor flip chip package

Abstract

The present invention discloses a semiconductor flip chip package (10), comprising: a substrate (11), the substrate (11) comprising a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures (11.1) arranged on the first main surface; one or more pillars (12), the one or more pillars (12) being arranged on at least one of the conductive structures (11.1); a semiconductor die 13, the semiconductor die 13 comprising one or more contact pads (13.1) on its main surface, wherein the semiconductor die (13) is connected to the substrate (11) so that at least one of the contact pads (13.1) is connected to one of the pillars (12); and an encapsulant 14, the encapsulant 14 being arranged on the substrate (11) and the semiconductor die (13).

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor flip chip package, and to a semiconductor flip chip package. In particular, the present disclosure relates to manufacturing a semiconductor flip chip package in which the substrate is an interconnect substrate or a lead frame. Background Art

[0002] In semiconductor packaging, the requirement for good electrical performance with low parasitic inductance and capacitance and short interconnects has led to the addition of flip chip packaging to many packaging platform roadmaps. Flip chip mounting is a method of connecting a semiconductor die to a substrate (e.g., a circuit board or another die) using solder bumps deposited on the die pads. The solder bumps are deposited on the die pads on the top surface of the semiconductor die. In order to mount the die to the substrate, the die is flipped so that its top surface faces downward, and aligned so that its pads are aligned with the matching pads on the substrate. Finally, the solder bumps are reflowed to complete the interconnect. Regardless of the type of substrate on which the flip chip raised die is fixed, it is known that these flip chip technologies provide excellent electrical performance and also have a small form factor. Summary of the invention

[0003] A first aspect of the present disclosure relates to a method for manufacturing a semiconductor flip chip package, the method comprising: providing an interconnect substrate, in particular a molded interconnect substrate (MIS), the interconnect substrate comprising a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures arranged on the first main surface; forming one or more pillars on at least one of the conductive structures; providing a semiconductor die comprising one or more contact pads on its main surface; attaching the semiconductor die to the substrate so that at least one of the contact pads is connected to one of the pillars; and applying an encapsulant to the substrate and the semiconductor die.

[0004] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor flip chip package, the method comprising: providing a lead frame including a die pad and / or one or more leads; forming one or more columns at least in the die pad or on one or more of the leads; providing a semiconductor die including one or more contact pads on a major surface thereof; attaching the semiconductor die to one or more of the die pads or leads so that at least one of the contact pads is connected to one of the columns; and applying an encapsulant to the die pads, leads and semiconductor die.

[0005] A third aspect of the present disclosure relates to a semiconductor flip chip package, which includes: a substrate, the substrate including a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures arranged on the first main surface; one or more pillars, the one or more pillars are arranged on at least one of the conductive structures; a semiconductor die, the semiconductor die including one or more contact pads on its main surface, wherein the semiconductor die is connected to the substrate so that at least one of the contact pads is connected to one of the pillars; and an encapsulant, the encapsulant is arranged on the substrate and the semiconductor die.

[0006] A fourth aspect of the present disclosure relates to a semiconductor flip chip package, which includes: a lead frame, which includes a die pad and / or one or more leads; one or more pillars, which are arranged on the die pad or on one or more of the leads; a semiconductor die, which includes one or more contact pads on its main surface, wherein the semiconductor die is connected to one or more of the die pads or the leads so that at least one of the contact pads is connected to one of the pillars; and an encapsulant, which is arranged on the die pad, the leads and the semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and together with the description are used to explain the principles of the embodiments. Other embodiments and many of the expected advantages of the embodiments will be readily understood as they become better understood by reference to the following detailed description.

[0008] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0009] Figure 1 A flow chart showing an example of a method for manufacturing a semiconductor flip chip package according to the first aspect, the method including using a MIS substrate as a substrate for the semiconductor flip chip package.

[0010] Figure 2 include Figure 2 A to Figure 2 J, and shows the intermediate product ( Figure 2 A to Figure 2 I) and final semiconductor flip chip packaging ( Figure 2 J) is a schematic cross-sectional side view illustration for illustrating an example of a method for manufacturing a semiconductor flip chip package according to the first aspect.

[0011] Figure 3A schematic cross-sectional side view illustration of a semiconductor flip chip package is shown, the semiconductor flip chip package comprising: a substrate, the substrate comprising a conductive structure and a conductive pillar disposed on the conductive structure; and a semiconductor die, the semiconductor die comprising a contact pad, wherein the semiconductor die is connected to the conductive pillar with its contact pad.

[0012] Figure 4 A flow chart showing an example of a method for manufacturing a semiconductor flip chip package according to the second aspect, the method comprising utilizing a lead frame as a substrate for the semiconductor flip chip package.

[0013] Figure 5 include Figure 5 A to Figure 5 E, and shows the intermediate products ( Figure 5 A to Figure 5 D) and final semiconductor flip chip packaging ( Figure 5 E) is a schematic cross-sectional side view illustration for illustrating an example of a method for manufacturing a semiconductor flip chip package according to the second aspect.

[0014] Figure 6 A schematic cross-sectional side view illustration of a semiconductor flip chip package is shown, the semiconductor flip chip package comprising: a lead frame, the lead frame comprising leads and conductive pillars arranged on the leads; and a semiconductor die, the semiconductor die comprising contact pads, wherein the semiconductor die is connected to the conductive pillars with its contact pads.

[0015] Figure 7 A schematic cross-sectional side view illustration of two adjacent Cu pillars disposed on a lead of a lead frame is shown along with the drawn spatial dimensions of the conductive pillars.

[0016] Figure 8 A schematic cross-sectional side view illustration of an example of a conductive pillar comprising a silicone pillar having a copper spiral plated thereon on top of the silicone pillar is shown. DETAILED DESCRIPTION

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which specific embodiments in which the present invention may be practiced are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "rear", "front", "rear", etc. are used with reference to the directions in the (one or more) drawings described. Since the components of the embodiments may be placed in a plurality of different directions, the directional terms are used for illustrative purposes and are by no means restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0018] It should be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0019] As used in this specification, the terms "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" are not meant to mean that elements or layers must be in direct contact together; intermediate elements or layers may be provided between the elements that are "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled", respectively. However, according to the present disclosure, the above terms may also optionally have the following specific meanings: the elements or layers are in direct contact together, that is, no intermediate elements or layers are provided between the elements that are "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled", respectively.

[0020] In addition, the term "on" used in relation to a portion, element or material layer formed or located "on" a surface may be used herein to indicate that the portion, element or material layer is "directly" located (e.g., placed, formed on, deposited on, etc.) "on" the referenced surface, with one or more additional portions, elements or layers disposed between the referenced surface and the portion, element or material layer. However, the term "on" used in relation to a portion, element or material layer formed or located "on" a surface may also optionally have the following specific meaning: the portion, element or material layer is "directly" located (e.g., placed, formed on, deposited on, etc.) "on" the referenced surface, for example, in direct contact with the referenced surface.

[0021] Semiconductor flip chip packages containing semiconductor dies are described below. The semiconductor dies may be of different types, may be manufactured by different techniques, and may include, for example, integrated electrical, electro-optical, or electromechanical circuits and / or passive devices. For example, the semiconductor dies may be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits, or integrated passive devices. They may include control circuits, microprocessors, or micro-electromechanical components.

[0022] The method and semiconductor flip chip package include the manufacture of the pillar. The pillar can be made of a completely conductive material such as Cu or a Cu alloy, wherein the conductive material can include a solder layer on the top. The pillar can also be made of a conductive material such as Cu or a Cu alloy, wherein the material can include a silicone pillar on the top, wherein the silicone pillar includes a conductive layer or a spiral portion deposited on the surface of the silicone pillar.

[0023] The semiconductor flip chip package includes an encapsulant. The encapsulant can be a dielectric material and can be made of any suitable hard plastic, thermoplastic or thermosetting material, wherein any of the above materials can be manufactured by molding or printing, or can be a laminate (prepreg material) that can be made by lamination. The encapsulant can include a filling material. After its deposition, the encapsulant can only be partially hardened, and can be fully hardened after applying energy (e.g., heat, ultraviolet light, etc.) to form the encapsulant. Various techniques can be used to apply the encapsulant, such as transfer molding, compression molding, injection molding, powder molding, liquid molding, distribution, lamination or printing, distribution or injection of top sealing materials.

[0024] Detailed description

[0025] Figure 1 A flow chart is shown for illustrating an example of the method of the first aspect. Figure 1 The method 100 includes: providing a molded interconnect substrate (MIS) including a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures (110) disposed on the first main surface; forming one or more pillars (120) on at least one of the conductive structures; providing a semiconductor die (130) including one or more contact pads on its main surface; attaching the semiconductor die to a substrate such that at least one of the contact pads is connected to one of the pillars (140); and applying an encapsulant to the substrate and the semiconductor die (150).

[0026] according to Figure 1 In an example of a method, the pillars are formed by one or more of galvanic plating, etching, stamping, or stamping.

[0027] according to Figure 1 In an example of a method of manufacturing a conductive column, the column comprises a body made of Cu, Al or an alloy thereof, or is made of said body. The conductive column may further comprise a solder cap.

[0028] according to Figure 1 In an example of the method, the height of the pillars ranges from 20 μm to 120 μm, more specifically from 40 μm to 100 μm, more specifically from 40 μm to 80 μm, more specifically from 40 μm to 60 μm.

[0029] according to Figure 1 In an example of the method, the width of the pillars ranges from 40 μm to 120 μm, from 80 μm to 120 μm, or from 40 μm to 80 μm, more specifically from 50 μm to 70 μm.

[0030] according to Figure 1 In an example of the method, the column comprises a circular or rectangular cross-section.

[0031] according to Figure 1 An example of a method of applying a solder material layer on top of the column, and connecting the contact pad of the semiconductor die to the column by a soldering process. According to another example thereof, the solder material layer includes a Sn layer or a SnAg layer, in particular together with an intermediate Ni layer. The height of the solder material layer can be in the range of from 10μm to 40μm, more specifically from 15μm to 40μm, more specifically from 20μm to 40μm, more specifically from 25μm to 35μm. According to another example, the solder material layer can be deposited by one or more of electroplating, electroless plating, printing, dispensing, solder routing, spraying or placement.

[0032] according to Figure 1 In an example of the method, the contact pad and the pillar include copper or are made of copper or a copper alloy, and the method further includes connecting the contact pad of the semiconductor die to the pillar by Cu-Cu diffusion bonding. According to another example thereof, one or both of the surfaces of the contact pad and the pillar include one or more of copper nanograss, copper nanowires, or porous copper.

[0033] according to Figure 1 In an example of the method, connecting at least one of the contact pads to one of the pillars includes ultrasonic bonding.

[0034] according to Figure 1 In an example of a method, forming one or more pillars is performed additively by placing a mask over a substrate, the mask including mask openings defining the locations of the pillars to be formed, and then depositing material for the pillars into the mask openings.

[0035] according to Figure 1 In an example of a method of forming one or more electrically conductive pillars, forming the one or more electrically conductive pillars is performed subtractively by depositing the material of the pillars to be formed in the form of a continuous layer and then removing parts of the layer so that only the pillars remain.

[0036] according to Figure 1The method further comprises manufacturing a plurality of semiconductor flip chip packages by providing a panel including a large MIS substrate, providing a plurality of semiconductor dies, attaching the semiconductor dies to the panel, applying an encapsulant to the panel and the semiconductor dies, and singulating the panel into a plurality of semiconductor flip chip packages. According to another example thereof, the size of the panel is from 100x100mm 2 Up to 1000x1000mm 2 , more specifically from 200x200mm 2 Up to 900x900mm 2 , more specifically from 300x300mm 2 Up to 800x800mm 2 , more specifically from 400x400mm 2 Up to 800x800mm 2 , more specifically from 500x500mm 2 Up to 700x700mm 2 within the range.

[0037] according to Figure 1 An example of a method of further comprising providing a carrier substrate onto which the MIS substrate is built, and further comprising removing the carrier substrate after depositing the copper pillars or after depositing the solder bumps or after connecting the semiconductor die to the copper pillars.

[0038] Figure 2 include Figure 2 A to Figure 2 J, and shows an example of a method for manufacturing a semiconductor flip chip package according to the first aspect.

[0039] Figure 2 A shows providing a carrier substrate 210 comprising an intermediate electrically insulating layer 211, a first upper metal layer 212 and a second lower metal layer 213. The carrier substrate 210 serves as an auxiliary carrier and will be removed later. Another type of carrier comprising an upper metal layer may also be used.

[0040] Figure 2 B shows the deposition of a pattern of a first layer 220. The first layer 220 may be made of copper and may be deposited by galvanic plating, wherein the first metal layer 212 of the carrier substrate 210 serves as a seed layer. The patterning may be performed, for example, in a subtractive manner, i.e. by depositing a continuous copper layer and subsequently etching away the unneeded copper areas.

[0041] Figure 2 C shows the deposition of a first copper pillar 230 by galvanic plating. The first copper pillar 230 serves as a via to the next wiring layer.

[0042] Figure 2D shows overmolding of the structure by applying a first encapsulant 240, for example by transfer molding.

[0043] Figure 2 E shows grinding the first encapsulant 240 from above until the upper surface of the first copper pillar 230 is exposed to the outside.

[0044] Figure 2 F shows the deposition of a pattern of the second layer 250. The second layer 250 may also be made of copper and may be deposited by galvanic plating. The patterning may be performed by an additive process, for example, through an electroplated or electroless seed layer, or by a subtractive process, for example, by depositing a continuous copper layer and subsequently etching away unwanted copper areas.

[0045] Figure 2 G shows the deposition of a second copper pillar 260 by galvanic plating. The second copper pillar 260 serves as a connection to a pad of the semiconductor die.

[0046] Figure 2 H shows the deposition of solder bumps or balls 270 onto the upper surface of the second copper pillar 260. The solder layer is used to connect the second copper pillar 260 to the chip pad through a soldering process.

[0047] Figure 2 I shows the etch-back that removes the carrier substrate 210 and the first layer 220 from below.

[0048] Figure 2 J shows: providing a semiconductor die including a contact pad 281 disposed on one of its main surfaces; flipping the semiconductor die 280 so that its contact pad 281 faces downward; and aligning the semiconductor die 280 so that its contact pad 281 is aligned with a specific second conductive column 260 on the intermediate product. Finally, the solder bump 270 is reflowed to transform into a stable solder connection. Compared to conventional flip chip packaging, the solder connection is positioned closer to the semiconductor die 280. In other words, the distance between the solder connection and the surface of the semiconductor die 280 is less than the distance between the solder connection and the surface of the second layer 250.

[0049] Figure 2 J also shows that the structure is overmolded by applying a second encapsulant 290 such that the second encapsulant 290 is disposed on the upper surface of the first encapsulant 240 and fully embeds the semiconductor 280. Finally, solder balls 295 are connected to the exposed pads of the first layer 220.

[0050] Figure 3 A schematic cross-sectional illustration of a semiconductor flip chip package according to a third aspect is shown. Figure 3The semiconductor flip chip package 10 includes: a substrate 11, the substrate 11 includes a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures 11.1 arranged on the first main surface; one or more conductive pillars 12, the one or more conductive pillars 12 are arranged on at least one of the conductive structures 11.1; a semiconductor die 13, the semiconductor die 13 includes one or more contact pads 13.1 on its main surface, wherein the semiconductor die 13 is connected to the substrate 11 so that at least one of the contact pads 13.1 is connected to one of the conductive pillars 12; and an encapsulant 14, the encapsulant 14 is arranged on the substrate 11 and the semiconductor die 13.

[0051] according to Figure 3 In an example of a semiconductor flip chip package 10, the semiconductor flip chip package 10 further includes a bonding layer or a connecting layer 15, each of which is disposed between one of the conductive pillars 12 and one of the contact pads 13.1. The bonding layer 15 is used for a stable connection between the conductive pillars 12 and the contact pads 13.1. According to another example thereof, the distance between the bonding layer 15 and the surface of the semiconductor die 13 is less than the distance between the bonding layer 15 and the surface of the substrate 11.

[0052] according to Figure 3 In another example of the semiconductor flip chip package 10, each of the bonding layers 15 may include a solder connection layer, ie, a layer produced by a soldering process. In particular, the solder connection layer may include Sn or SnAg, and may additionally include an intermediate Ni layer.

[0053] according to Figure 3 In another example of the semiconductor flip chip package 10, each of the bonding layers 15 may include a layer produced by a Cu-Cu diffusion bonding process. According to another example thereof, in the Cu-Cu diffusion bonding process, one or both of the surfaces of the contact pad and the conductive pillar include one or more of copper nanograss, copper nanowires, or porous copper.

[0054] according to Figure 3 In another example of the semiconductor flip chip package 10 , each of the bonding layers 15 may include a layer produced by an ultrasonic bonding process.

[0055] according to Figure 3 In another example of a semiconductor flip chip package 10, the substrate 11 is a molded interconnect substrate (MIS) and further includes a first patterned metal layer 16, a second patterned metal layer 17, another encapsulant 18, and solder balls 19 attached to exposed portions of the first patterned metal layer 16, wherein the conductive structure 11.1 is part of the second patterned metal layer 17.

[0056] Further examples of the semiconductor flip chip package of the third aspect may be formed according to the examples described above in conjunction with the method according to the first aspect.

[0057] Figure 4 A flow chart is shown for illustrating an example of the method of the second aspect. Figure 4 Method 400 includes a method for manufacturing a semiconductor flip chip package, the method comprising: providing a lead frame, the lead frame including a die pad and one or more leads (410); forming one or more conductive pillars over the die pad (420); providing a semiconductor die including one or more contact pads on a major surface thereof (430); attaching the semiconductor die to the die pad such that at least one of the contact pads is connected to one of the conductive pillars (440); and applying an encapsulant to the die pad, the leads, and the semiconductor die (450).

[0058] according to Figure 4 In an example of a method, the conductive pillars are formed by galvanic plating.

[0059] according to Figure 4 In an example of the method, the conductive pillar includes Cu, Al or an alloy thereof, or is made of Cu, Al or an alloy thereof.

[0060] according to Figure 4 In an example of the method, the height of the pillars ranges from 20 μm to 120 μm, more specifically from 40 μm to 100 μm, more specifically from 40 μm to 80 μm, more specifically from 40 μm to 60 μm.

[0061] according to Figure 4 In an example of the method, the width of the pillars ranges from 40 μm to 120 μm, or from 80 μm to 120 μm, or from 40 μm to 80 μm, more specifically from 50 μm to 70 μm.

[0062] according to Figure 4 In an example of the method, the column comprises a circular or rectangular cross-section.

[0063] according to Figure 4 The method further comprises applying a solder material on top of the conductive pillar and connecting the contact pad of the semiconductor die to the conductive pillar by a soldering process. According to another example thereof, the solder material comprises a Sn layer or a SnAg layer, in particular together with an intermediate Ni layer.

[0064] according to Figure 4According to an example of the method, the contact pad and the conductive pillar include copper or are made of copper or a copper alloy, and the method further includes connecting the contact pad of the semiconductor die to the conductive pillar by Cu-Cu diffusion bonding. According to another example thereof, one or both of the surfaces of the contact pad and the conductive pillar include one or more of copper nanograss, copper nanowires or porous copper.

[0065] according to Figure 4 In an example of the method, connecting at least one of the contact pads to one of the conductive pillars includes ultrasonic bonding.

[0066] according to Figure 4 In an example of a method, forming one or more conductive pillars is performed additively by placing a mask over a substrate, the mask including mask openings defining the locations of the pillars to be formed, and then depositing material for the pillars into the mask openings.

[0067] according to Figure 4 In an example of a method of forming one or more electrically conductive pillars, forming the one or more electrically conductive pillars is performed subtractively by providing (in particular depositing) the material of the pillars to be formed in the form of successive layers and then removing parts of said layers so that only the pillars remain.

[0068] according to Figure 4 The method further comprises manufacturing a plurality of semiconductor flip chip packages by providing a panel including a plurality of lead frames, providing a plurality of semiconductor dies, attaching the semiconductor dies to the panel, applying an encapsulant to the panel and the semiconductor dies, and singulating the panel into a plurality of semiconductor flip chip packages. According to another example thereof, the size of the panel is from 100x100mm 2 Up to 1000x1000mm 2 , more specifically from 200x200mm 2 Up to 900x900mm 2 , more specifically from 300x300mm 2 Up to 800x800mm 2 , more specifically from 400x400mm 2 Up to 800x800mm 2 , more specifically from 500x500mm 2 Up to 700x700mm 2 within the range.

[0069] according to Figure 4 In an example of a method in which the width of the pillar is greater than the width of the lead.

[0070] according to Figure 4In an example of the method, forming the one or more conductive pillars is performed by stamping or precision stamping, wherein the lead frame is subjected to a stress high enough to induce plastic flow on the surface of the material.

[0071] Further examples of the method of the second aspect may be formed according to the examples or features described above in conjunction with the method according to the first aspect.

[0072] Figure 5 include Figure 5 A to Figure 5 E, and shows an example of a method for manufacturing a semiconductor flip chip package according to the second aspect.

[0073] Figure 5 A shows the provision of a lead frame 510 including a die pad 511 and one or more leads 512 .

[0074] Figure 5 B shows the formation of a conductive pillar 520 over the die pad 511 by, for example, galvanic plating.

[0075] Figure 5 C shows that solder bumps 530 are formed on the upper surface of conductive pillars 520 .

[0076] Figure 5 D shows providing a semiconductor die 540 including one or more contact pads 541 , and attaching the semiconductor die 540 to the die pad 511 such that each of the contact pads 541 is connected to one of the conductive pillars 520 .

[0077] Figure 5 E shows application of encapsulant 550 to die pad 511 , leads 512 , and semiconductor die 540 .

[0078] Figure 6 A schematic cross-sectional illustration of a semiconductor flip-chip package according to a fourth aspect is shown. Figure 6 The semiconductor flip chip package 20 includes: a lead frame 21, wherein the lead frame 21 includes a die pad 21.1 and one or more leads 21.2, and one or more conductive pillars 22 arranged on the die pad 21.1; a semiconductor die 23, wherein the semiconductor die 23 includes one or more contact pads 23.1 on its main surface, wherein the semiconductor die 23 is connected to the lead frame 21 so that at least one of the contact pads 23.1 is connected to one of the conductive pillars 22; and an encapsulant 24, wherein the encapsulant 24 is arranged on the lead frame 21 and the semiconductor die 23.

[0079] according to Figure 6In an example of a semiconductor flip chip package 20, the semiconductor flip chip package 20 further includes a bonding layer or connecting layer 25, each of which is disposed between one of the conductive pillars 22 and one of the contact pads 23.1. The bonding layer 25 is used for a stable connection between the conductive pillars 22 and the contact pads 23.1. According to another example thereof, the distance between the bonding layer 25 and the surface of the semiconductor die 23 is less than the distance between the bonding layer 25 and the surface of the die pad 21.1.

[0080] according to Figure 6 In another example of the semiconductor flip chip package 20, each of the bonding layers 25 may include a solder connection layer, ie, a layer produced by a soldering process. In particular, the solder connection layer may include Sn or SnAg, and may additionally include an intermediate Ni layer.

[0081] according to Figure 6 In another example of the semiconductor flip chip package 20, each of the bonding layers 25 may include a layer produced by a Cu-Cu diffusion bonding process. According to another example thereof, in the Cu-Cu diffusion bonding process, one or both of the surfaces of the contact pad and the conductive pillar include one or more of copper nanograss, copper nanowires, or porous copper.

[0082] according to Figure 6 In another example of the semiconductor flip chip package 20 , each of the bonding layers 25 may include a layer produced by an ultrasonic bonding process.

[0083] according to Figure 6 As another example of the semiconductor flip chip package 20 , the semiconductor flip chip package may be configured as a VQFN (Very Thin Quad Flat No-Lead) package.

[0084] Further examples of the semiconductor flip chip package of the fourth aspect may be formed according to the examples or features described above in conjunction with the method according to the second aspect.

[0085] Figure 7 A schematic cross-sectional side view illustration of two adjacent posts disposed on a lead of a lead frame is shown together with the plotted spatial dimensions (in μm) of the conductive posts. The left post comprises a Cu post of 40.5 μm in height and 65.5 μm in width. The solder layer applied on top of the Cu post comprises a height of 31.5 μm and a width of 65 μm. The distance between the post and the adjacent line is 13.5 μm. The width of the horizontal boss on top of the solder layer is 29.0 μm, and the distance between the boss and the line is 36.5 μm. The center-to-center distance between the two posts is 121.0 μm.

[0086] Figure 8 A schematic cross-sectional side view illustration of another example of a column is shown. Figure 8The column 80 includes a base pillar 81, a silicone pillar 82 deposited on the upper surface of the base pillar 81, and a metal spiral portion 83, for example made of copper, deposited on the surface of the silicone pillar 82. The silicone pillar 82 may include an elastic state and may also include a hemispherical form, and the spiral portion 83 may be deposited so that it contacts the base pillar 81 and is at least partially exposed on the upper surface of the silicone pillar 82 so that it can contact any conductive material that contacts the upper surface of the silicone pillar 82. The base pillar 81 may be a pillar such as that described in one of the aforementioned examples and may be made, for example, of copper or a copper alloy. One advantage of the silicone pillar 81 is that the base pillar 81 does not need to have the height of the pillar as described in the previous example. The metal spiral portion 83 may act like a spring that can compensate for tolerances. It may be manufactured, for example, by electroplating or electroless plating.

[0087] Example

[0088] Example 1 is a method for manufacturing a semiconductor flip chip package, the method comprising: providing an interconnect substrate, the interconnect substrate comprising a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures arranged on the first main surface; forming one or more pillars on at least one of the conductive structures; providing a semiconductor die comprising one or more contact pads on its main surface; attaching the semiconductor die to the substrate so that at least one of the contact pads is connected to one of the pillars; and applying an encapsulant to the substrate and the semiconductor die.

[0089] Example 2 is a method for manufacturing a semiconductor flip chip package, the method comprising: providing a lead frame, the lead frame comprising a die pad and one or more leads; forming one or more columns above the die pad and / or above one or more of the leads; providing a semiconductor die comprising one or more contact pads on a major surface thereof; attaching the semiconductor die to the die pad so that at least one of the contact pads is connected to one of the columns; and applying an encapsulant to the die pad, the leads and the semiconductor die.

[0090] Example 3 is the method of example 1 or 2, wherein the pillar is formed by galvanic plating.

[0091] Example 4 is a method according to any of the preceding examples, wherein the column is made of Cu, Al, an alloy thereof or a Cu / Zn alloy, and may include a solder layer on the upper surface, the solder layer comprising one or more of Sn, SnAg, Ag, NiAu or Pd.

[0092] Example 5 is a method according to any of the preceding examples, wherein the column comprises a base pillar, a silicone pillar deposited onto an upper surface of the base pillar, and a metal layer (particularly a metal spiral portion, particularly a copper spiral portion) deposited onto a surface of the silicone pillar.

[0093] Example 6 is a method according to any of the preceding examples, wherein the height of the pillars ranges from 20 μm to 120 μm, more specifically from 40 μm to 100 μm, more specifically from 40 μm to 80 μm, more specifically from 40 μm to 60 μm.

[0094] Example 7 is a method according to any of the preceding examples, wherein the width of the pillar is in a range from 40 μm to 120 μm, or from 80 μm to 120 μm, or from 40 μm to 80 μm, more specifically from 50 μm to 70 μm.

[0095] Example 8 is the method of Example 2, wherein a width of the pillar is greater than a width of the lead.

[0096] Example 9 is the method of any of the preceding examples, further comprising applying a solder material on top of the conductive pillar, and connecting a contact pad of the semiconductor die to the conductive pillar by a soldering process.

[0097] Example 10 is the method of any of Examples 1 to 8, further comprising connecting a contact pad of the semiconductor die to the pillar by Cu-Cu diffusion bonding or ultrasonic bonding.

[0098] Example 11 is a method according to any of the preceding examples, wherein forming one or more conductive pillars is performed additively by placing a mask over a substrate or lead, the mask including mask openings defining the locations of the pillars to be formed, and then depositing material for the pillars into the mask openings.

[0099] Example 12 is a method according to any of the preceding examples, wherein forming one or more conductive pillars is performed subtractively by depositing the material of the pillars to be formed in a continuous layer and then removing portions of the layer so that only the pillars remain.

[0100] Example 13 is a method according to any of the preceding examples, further comprising manufacturing a plurality of semiconductor flip chip packages by providing a panel comprising a plurality of substrates or lead frames, providing a plurality of semiconductor dies, attaching the semiconductor dies to the panel, applying an encapsulant to the panel and the semiconductor dies, and singulating the panel into a plurality of semiconductor flip chip packages.

[0101] Example 14 is the method according to Example 13, wherein the size of the panel is from 100x100mm 2Up to 1000x1000mm 2 within the range.

[0102] Example 15 is a semiconductor flip chip package, which includes: a substrate, the substrate including a first main surface, a second main surface opposite to the first main surface, and one or more conductive structures arranged on the first main surface; one or more pillars, the one or more pillars are arranged on at least one of the conductive structures; a semiconductor die, the semiconductor die including one or more contact pads on its main surface, wherein the semiconductor die is connected to the substrate so that at least one of the contact pads is connected to one of the pillars; and an encapsulant, the encapsulant is arranged on the substrate and the semiconductor die.

[0103] Example 16 is a semiconductor flip chip package, which includes: a lead frame, which includes a die pad and / or one or more leads; one or more columns, which are arranged on the die pad and / or on one or more of the leads; a semiconductor die, which includes one or more contact pads on its main surface, wherein the semiconductor die is connected to the lead frame so that at least one of the contact pads is connected to one of the columns; and an encapsulant, which is arranged on the lead frame and the semiconductor die.

[0104] Example 17 is a semiconductor flip chip package according to Example 15 or 16, wherein the semiconductor flip chip package also includes a bonding layer arranged between the column and the contact pad, wherein the distance between the bonding layer and the semiconductor tube core is smaller than the distance between the bonding layer and the conductive structure on the first main surface of the substrate or the tube core pad or lead.

[0105] Example 18 is a semiconductor flip chip package according to Example 17, wherein the bonding layer is a solder layer.

[0106] Example 19 is a semiconductor flip chip package according to any one of Examples 15 to 18, wherein the height of the column is in the range from 20 μm to 120 μm, more specifically from 40 μm to 100 μm, more specifically from 40 μm to 80 μm, more specifically from 40 μm to 60 μm.

[0107] Example 20 is a semiconductor flip chip package according to any one of Examples 15 to 19, wherein a width of the pillar is in a range from 40 μm to 120 μm, from 80 μm to 120 μm, or from 40 μm to 80 μm, more specifically from 50 μm to 70 μm.

[0108] Example 21 is a semiconductor flip chip package according to any one of Examples 15 to 20, wherein the pillar is made of Cu, Al or an alloy thereof, and may include a silicone pillar on the top, the silicone pillar including a metal layer on its upper surface.

[0109] In addition, although a particular feature or aspect of an embodiment of the present invention may have been disclosed with respect to only one of several embodiments, such a feature or aspect may be combined with one or more other features or aspects of other embodiments as desired and is advantageous for any given or specific application. In addition, to the extent that the terms "including," "having," "with," or other variations thereof are used in a specific embodiment or in the claims, these terms are intended to be inclusive in a manner similar to the term "including." In addition, it should be understood that embodiments of the present invention may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming devices. Likewise, the term "exemplary" is meant only as an example, not the best or optimal. It should also be understood that, for the purpose of simplicity and ease of understanding, the features and / or elements depicted herein are shown at specific sizes relative to each other, and the actual sizes may be substantially different from those shown herein.

[0110] Although specific embodiments are illustrated and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent embodiments may be used to replace the specific embodiments shown and described without departing from the scope of the present invention. The present application is intended to cover any adjustments and modifications of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A method (200) for manufacturing a semiconductor flip chip package, the method comprising: providing a semiconductor die comprising one or more contact pads (230) on a major surface thereof; providing a lead frame, the lead frame comprising a die pad and / or one or more leads (210); forming one or more posts on the lead frame, wherein each of the one or more posts has a first end and a second end attached to the die pad and / or one or more of the leads (220); After forming the one or more pillars on the lead frame, attaching the semiconductor die to the die pad includes connecting at least one of the contact pads to the first end of at least one of the one or more pillars (240); and An encapsulant is applied to the die pad, the leads, and the semiconductor die (250).

2. The method according to claim 1, wherein The pillars are formed by galvanic plating.

3. A method according to any one of the preceding claims, wherein The pillar is made of Cu, Al, an alloy thereof, or a Cu / Zn alloy, and includes a solder layer on an upper surface, the solder layer including one or more of Sn, SnAg, Ag, NiAu, or Pd.

4. A method according to any one of the preceding claims, wherein The column comprises a base pillar, a silicone pillar deposited onto an upper surface of the base pillar, and a metal layer, in particular a metal spiral, in particular a copper spiral, deposited onto a surface of the silicone pillar.

5. A method according to any one of the preceding claims, wherein The height of the pillars ranges from 20 μm to 120 μm, more specifically from 40 μm to 100 μm, more specifically from 40 μm to 80 μm, more specifically from 40 μm to 60 μm.

6. A method according to any one of the preceding claims, wherein The width of the pillars ranges from 40 μm to 120 μm, from 80 μm to 120 μm, or from 40 μm to 80 μm, more specifically from 50 μm to 70 μm.

7. A method according to any one of the preceding claims, wherein The width of the pillar is greater than the width of the lead.

8. The method according to any one of the preceding claims, further comprising: A solder material is applied on top of the pillars, and the contact pads of the semiconductor die are connected to the pillars by a soldering process.

9. The method according to any one of claims 1 to 7, further comprising: The contact pads of the semiconductor die are connected to the pillars by Cu-Cu diffusion bonding or ultrasonic bonding.

10. A method according to any one of the preceding claims, wherein Forming the one or more pillars is performed additively by placing a mask over the substrate or the leads, the mask including mask openings defining the locations of the pillars to be formed, and then depositing material for the pillars into the mask openings.

11. The method according to claim 10, wherein Forming the one or more pillars is performed subtractively by depositing the material of the pillars to be formed in the form of a continuous layer and then removing parts of the layer so that only the pillars remain.

12. The method according to any one of the preceding claims, further comprising: Multiple semiconductor flip chip packages are manufactured as follows: providing a panel including a plurality of substrates or lead frames; providing a plurality of semiconductor dies; attaching the semiconductor die to the panel; applying an encapsulant to the panel and the semiconductor die; as well as The panel is singulated into a plurality of semiconductor flip chip packages.

13. The method according to claim 12, wherein The panel size ranges from 100 x 100 mm 2 Up to 1000 x 1000 mm 2 within the range.

14. A semiconductor flip chip package (20), comprising: A lead frame (21), the lead frame (21) comprising a die pad (21.1) and / or one or more leads (21.2); One or more pillars (22), the one or more pillars (22) being arranged on the die pad (21.1) and / or on one or more of the leads (21.2); A semiconductor die (23), the semiconductor die (23) comprising one or more contact pads (23.1) on a main face thereof, wherein the semiconductor die (23) is connected to the lead frame (21) such that at least one of the contact pads (23.1) is connected to one of the pillars (22), and wherein the connection of the semiconductor die (23) to the lead frame (21) is achieved after the one or more pillars (22) are arranged on the die pads (21.1) and / or on one or more of the leads (21.2); and An encapsulant (24) is disposed on the lead frame (21) and the semiconductor die (23).

15. The semiconductor flip chip package (20) according to claim 14, further comprising: A bonding layer (25) is arranged between the column (22) and the contact pad (23.1), wherein the distance between the bonding layer (25) and the semiconductor die (23) is smaller than the distance between the bonding layer (25) and the die pad (21.1) or the lead (21.2).

16. The semiconductor flip chip package (20) according to claim 15, wherein The bonding layer (25) is a solder layer (25).

17. The semiconductor flip chip package (20) according to any one of claims 14 to 16, wherein The height of the pillars (22) ranges from 20 μm to 120 μm, more specifically from 40 μm to 100 μm, more specifically from 40 μm to 80 μm, more specifically from 40 μm to 60 μm.

18. The semiconductor flip chip package (20) according to any one of claims 14 to 17, wherein The pillars are made of Cu, Al or alloys thereof and include a silicone support on top that includes a metal layer on its upper surface.

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