Semiconductor Devices

Abstract

The present invention discloses a semiconductor device, comprising: a semiconductor body, comprising a first surface and a second surface opposite to the first surface in a vertical direction; and a plurality of transistor units, which are at least partially integrated in the semiconductor body. Each of the plurality of transistor units comprises: at least two source regions; a first gate electrode and a second gate electrode, which are spaced apart from each other in a first horizontal direction, each of the first gate electrode and the second gate electrode being arranged adjacent to a continuous body region and dielectrically insulated from the continuous body region; a drift region, which is separated from the at least two source regions by the body region; and at least three contact plugs, which extend from the body region toward the source electrode in a vertical direction, wherein the at least three contact plugs are arranged successively between the first gate electrode and the second gate electrode, and wherein only the two outermost contact plugs arranged closest to the first gate electrode and the second gate electrode, respectively, directly adjoin at least one of the source regions.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and in particular to super junction semiconductor devices. Background Art

[0002] Semiconductor devices such as insulated gate power transistor devices, for example power MOSFETs (metal oxide semiconductor field effect transistors) or IGBTs (insulated gate bipolar transistors), are widely used as electronic switches in various types of electronic applications. In many applications, the ruggedness (robustness) of such semiconductor devices is a critical aspect. Many applications require switching unclamped inductive loads, which may cause high stresses in the transistor device due to high currents inducing high device temperatures. In some semiconductor devices, there is a risk that activation of an undesired parasitic bipolar transistor will reduce the breakdown voltage of the semiconductor device.

[0003] It is desirable to provide a robust semiconductor device with a reduced risk of activating undesired parasitic bipolar transistors and with an increased breakdown voltage. Summary of the invention

[0004] An example relates to a semiconductor device, comprising: a semiconductor body, the semiconductor body comprising a first surface and a second surface opposite to the first surface in a vertical direction; and a plurality of transistor units at least partially integrated in the semiconductor body, each of the plurality of transistor units comprising: at least two source regions; a first gate electrode and a second gate electrode spaced apart from each other in a first horizontal direction, each of the first gate electrode and the second gate electrode being arranged adjacent to a continuous body region and dielectrically insulated from the continuous body region; a drift region, the drift region being separated from the at least two source regions by the body region; and at least three contact plugs, the at least three contact plugs extending in a vertical direction from the body region toward the source electrode, wherein the at least three contact plugs are arranged successively between the first gate electrode and the second gate electrode, and wherein only the two outermost contact plugs arranged closest to the first gate electrode and the second gate electrode directly adjoin at least one of the source regions.

[0005] Another example relates to a semiconductor device, comprising: a semiconductor body, the semiconductor body including a first surface and a second surface opposite to the first surface in a vertical direction; a plurality of transistor units at least partially integrated in the semiconductor body, each of the plurality of transistor units including: a single source region; a first gate electrode and a second gate electrode spaced apart from each other in a first horizontal direction, each of the first gate electrode and the second gate electrode being arranged adjacent to a continuous body region and dielectrically insulated from the continuous body region; a drift region, the drift region being separated from the single source region by the body region; and at least two contact plugs, the at least two contact plugs extending in a vertical direction from the body region toward the source electrode, wherein the at least two contact plugs are arranged successively between the first gate electrode and the second gate electrode, and wherein at least one of the at least two contact plugs is not directly adjacent to the source region.

[0006] The following is an explanation of the examples with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and therefore only illustrate aspects necessary for understanding these principles. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent similar features. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A cross-sectional view of a semiconductor body is schematically shown.

[0008] Figure 2 A cross-sectional view of another semiconductor body is schematically shown.

[0009] Figure 3 A cross-sectional view of a semiconductor device according to an example is schematically shown.

[0010] Figure 4 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0011] Figure 5 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0012] Figure 6 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0013] Figure 7 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0014] Figure 8 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0015] include Fig.9A and Fig. 9B FIG. 9 schematically shows a top view of a semiconductor device according to various examples.

[0016] Fig.10 A top view of a semiconductor device according to another example is schematically shown.

[0017] Fig.11 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0018] Fig.12 A cross-sectional view of a semiconductor device according to another example is schematically shown.

[0019] Fig.13 A cross-sectional view of a semiconductor device according to another example is schematically shown. DETAILED DESCRIPTION

[0020] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of the specification and, for illustrative purposes, show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0021] refer to Figure 1 , schematically shows a cross-sectional view of a semiconductor device including a semiconductor body 100. The semiconductor body 100 may include conventional semiconductor materials, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), etc. A transistor device is formed in the semiconductor body 100, and the transistor device is arranged in an active region 220 of the semiconductor body 100. Figure 1 In FIG. 1 , only a small section of the transistor device is shown. In its active region 220, the semiconductor body 100 comprises at least one operating transistor cell 30 having a first gate electrode 331 and a second gate electrode 332, which are dielectrically insulated from the body region 32 by a gate dielectric 34. The body region 32 is a doped semiconductor region in the active region 220 of the semiconductor body 100. Figure 1 In the example shown in FIG, body region 32 extends from first surface 101 into semiconductor body 100 and gate electrodes 331, 332 are arranged above first surface 101 of semiconductor body 100. Each of transistor cells 30 further comprises two source regions 311, 312 extending from first surface 101 into body region 32.

[0022] Figure 1The transistor device shown in also includes a drift region 35 formed in the semiconductor body 100. The drift region 35 is adjacent to the body region 32 of at least one transistor cell 30 and forms a pn junction with the body region 32. The drift region 35 is arranged between the body region 32 and the drain region 36 of at least one transistor cell 30. The drain region 36 may be adjacent to the drift region 35 (as shown in the figure). The drain region 36 may form a semiconductor layer 110 arranged between the second surface 102 of the semiconductor body 100 and the drift region 35. The second surface 102 is arranged opposite to the first surface 101 in the vertical direction y of the semiconductor body 100. The drain region 36 is generally a continuous region that is common to all of the plurality of transistor cells 30.

[0023] According to another example, Figure 2 As shown, a vertical field stop region or buffer region 111 having the same doping type as the drift region 35 but not as high doping as the drift region 35 is arranged between the drift region 35 and the drain region 36. However, according to another example, such a buffer region 111 can also be more highly doped than the drift region 35. Figure 2 As shown by way of example, in a semiconductor body 100 including such a field stop zone 111, the semiconductor layer 110 between the second surface 102 and the drift region 35 may be formed by the drain region 36 and the adjacent field stop zone 111. The vertical field stop zone 111 may be formed by a single layer or a plurality of independent sublayers (e.g., at least two sublayers 111a, 111b). The doping of the sublayer 111n arranged closer to the drift region 35 may not be as high as the sublayer 111n arranged further away from the drift region 35. For example, the doping concentration of the sublayer 111a arranged adjacent to the drift region 35 may be between 1E15 and 1E16 cm -3 The doping concentration of the sublayer 111b arranged adjacent to the drain region 36 may be higher than the doping concentration of the sublayer 111a arranged horizontally above the drain region 36. However, the doping concentration of the sublayer 111b arranged adjacent to the drain region 36 may be lower than the doping concentration of the drain region 36. In general, the doping concentrations of the different sublayers 111n may increase from the drift region 35 toward the drain region 36.

[0024] Figure 2 The transistor device shown in FIG. 1 comprises a plurality of trenches extending into the semiconductor body 100, wherein each of the plurality of gate electrodes 331, 332 is arranged in one of the trenches. Figure 1 The transistor unit 30 of the transistor device is opposite, Figure 2 The transistor cell 30 of the transistor device shown in is a trench transistor cell. Figure 2 The overall structure of the trench transistor cell 30 is similar to that described above for Figure 1The structure of the planar transistor cell 30 has been described.

[0025] The vertical field stop region 111 has been described for a transistor device including a trench transistor cell 30. However, this is merely an example. Figure 2 In the exemplary transistor device of FIG. 1 , the vertical field stop region 111 may also be omitted. Figure 1 The drain region 36 and the drift region 35 of the planar transistor device are arranged as shown in FIG. Figure 2 The vertical field stop zone 111.

[0026] refer to Figure 1 and Figure 2 , the transistor device includes at least one compensation region 38 of a doping type complementary to a doping type of the drift region 35. According to an example, the transistor device includes a plurality of transistor cells 30, and each transistor cell 30 includes a compensation region 38 adjacent to a body region 32 of the corresponding transistor cell 30. In a vertical direction y of the semiconductor body 100 (a direction perpendicular to the first surface 101), the at least one compensation region 38 extends from the body region 32 toward the semiconductor layer 110 into the semiconductor body 100.

[0027] Still reference Figure 1 and Figure 2 , the transistor device also includes a source electrode 41. The source electrode 41 is electrically connected to the source regions 311, 312 and the body region 32 of at least one transistor unit 30 through a contact plug 42. For example, the contact plug 42 may include at least one of tungsten, aluminum, copper, highly doped polysilicon, and a Ti / TiN barrier liner. The source electrode 41 forms a source node S or is electrically connected to a source node S of the transistor device. The contact plug 42 arranged below the source electrode 41 extends from the source region and the body region 31, 32 to the source electrode 41 through an insulating layer 51 formed on the top surface 101 of the semiconductor body 100. The transistor device also includes a drain node D electrically connected to the drain region 36. The drain electrode electrically connected to the drain region 36 may form a drain node D. However, such a drain electrode may be Figure 1 and Figure 2 Not explicitly shown.

[0028] The transistor device can be an n-type transistor device or a p-type transistor device. The device type is defined by the doping type of the source region 31. In an n-type transistor device, the source region 31 is an n-type region, the body region 32 is a p-type region, the drift region 35 having a doping type complementary to the doping type of the body region 32 is an n-type region, and at least one compensation region 38 is a p-type region. In a p-type transistor device, the source region 31 is a p-type region, the body region 32 is an n-type region, the drift region 35 is a p-type region, and at least one compensation region 38 is an n-type region. For example, the transistor device can be implemented as a MOSFET or an IGBT. In a MOSFET, the drain region 36 has the same doping type as the drift region 35, and in an IGBT, the drain region 36 (also called the collector region) has a doping type complementary to the doping type of the drift region 35. For example, from 1E18 and 1E19 cm -3 , 1E18 and 1E20cm -3 or 1E18 and 1E21cm -3 The doping concentration of the drain region 36 is selected in the range from 1E15 to 5E16 cm -3 The doping concentration of the drift region 35 and the compensation region 38 is selected in the range between 5E16 cm -3 and 5E17cm -3 The doping concentration of the body region 32 is selected between .

[0029] In the transistor device explained above, a plurality of transistor cells 30 are connected in parallel. That is, the source regions 311, 312 of these transistor cells 30 are connected to the source node S, the common drain region 36 is connected to the drain node D, and at least one gate electrode 331, 332 is connected to the gate node (at Figure 1 and Figure 2 not shown).

[0030] Figure 1 and Figure 2 The source electrode 41 in the example of FIG. 1 is not a continuous layer that completely covers the semiconductor body 100. Figure 1 As shown, for example, the gate runner 43 can be arranged adjacent to the source electrode 41 in the first horizontal direction x of the semiconductor body 100. The source electrode 41 and the gate runner 43 are separated from each other by a gap formed between the source electrode 41 and the gate runner 43. For example, the gate runner 43 can be electrically connected to the gate electrodes 331, 332 ( Figure 1 The electrical connection between the gate runner 43 and the gate electrodes 331, 332 is not specifically shown in the figure. The gate runner 43 generally couples the gate electrodes 331, 332 of the plurality of transistor cells 30 to the gate pad ( Figure 1 For example, the gate runner 43 may be arranged in the edge termination region 210 .

[0031] exist Figure 1 and Figure 2 In the example shown, a termination field plate electrode 44 is arranged adjacent to an outer edge of the edge termination region 210 . The edge termination region 210 will be described in more detail below. For example, the termination field plate electrode 44 may be electrically connected to the farthest edge of the drift region 35 . Figure 2 The example schematically shown in FIG. 4 also includes a floating field plate electrode 400. For example, such a floating field plate electrode 400 may be formed of a polycrystalline semiconductor material and may be electrically connected to the end field plate electrode 44. Figure 2 In the example shown in FIG. 1 , the contact plug 42 is used to connect the source electrode 41 to the body region 32, and more contact plugs ( Figure 2 (not specifically shown) can be used to connect the field plate electrode 400 to the end field plate electrode 44. The end field plate electrode 44 can also be electrically connected to the semiconductor body 100. Figure 1 and Figure 2 Many different alternative embodiments of the field plate arrangement as well as of the field plates are generally known and will not be described in detail herein.

[0032] Figure 2 A gate runner 45 is also shown. For example, the gate runner 45 may be electrically connected to the gate electrodes 331 , 332 of the transistor device. The gate runner 45 generally couples the gate electrodes 331 , 332 of the plurality of transistor cells 30 to the gate pad. The gate runner 45 may be arranged in the edge termination region 210 .

[0033] The semiconductor body 100 typically includes not only an active region 220 but also an inactive region, which is also referred to as an edge termination region 210. A semiconductor device, i.e. a plurality of transistor cells 30, may be implemented within the active region 220 of the semiconductor body 100. For example, the edge termination region 210 may be a region adjacent to a horizontal edge of the semiconductor body 100 (edge ​​region). According to one example, the active region 220 is horizontally surrounded by the edge termination region 210. The edge termination region 210 typically does not include any working transistor cells 30. In particular, the edge termination region 210 may be a region that does not include all active components necessary to form a functional (working) transistor cell 30. For example, the active components are a gate oxide, a source region 311, 312, a body region 32, a gate electrode 331, 332 or a drain region 36. According to another example, the edge termination region 210 may also be formed between two sections of the active region 220, for example in order to provide a so-called gate finger.

[0034] The source electrode 41 may be arranged on the active region 220 of the semiconductor body 100. For example, the (optional) field plate electrode 43, 44, 400 may be arranged on the edge termination region 210 of the semiconductor body 100. Generally speaking, a conductive field plate may be used in the edge termination region 210 of the semiconductor body 100 in order to spread the electric field more uniformly in the edge termination region 210.

[0035] In some semiconductor devices, the width s1 of a single transistor cell 30 in the first horizontal direction x may be larger than the width s3 of the contact plug 42 in the same direction x. This results in a distance s between two adjacent gate electrodes 331 and 332 in the first horizontal direction x. 11 It is also larger than the width s3 of the contact plug 42 in the same direction x. According to an example, the width s1 of a single transistor cell 30 may be 7 μm or less, and the distance s between two adjacent gate electrodes 331 , 332 may be 1 μm or less. 11 However, the width s3 of the contact plug 42 may be only 500 nm or less, or even only 300 nm or less, which is significantly smaller than the distance s between two adjacent gate electrodes 331 , 332 . 11 This is because the contact plug 42 often includes tungsten or polysilicon. When tungsten or polysilicon is used for the contact plug 42, its width s3 is generally limited to a maximum width s3 of several 100 nm (e.g., 500 nm or less, or 300 nm or less). However, the distance s between two adjacent gate electrodes 331, 332 is 11 When larger than the width s3 of the contact plug 42 , this may result in activation of an undesired parasitic bipolar transistor, resulting in a reduction in the breakdown voltage or ruggedness (robustness) of the semiconductor device.

[0036] Reference now Figure 3 In order to avoid undesired activation of the parasitic bipolar transistor, a transistor unit 30 may include at least three contact plugs 421, 422, 423, instead of the above-mentioned contact plugs 421, 422, 423. Figure 1 and Figure 2 The single contact plug 42. According to an example, the semiconductor device includes a semiconductor body 100 having a first surface 101 and a second surface 102 opposite to the first surface 101 in a vertical direction y. The semiconductor device also includes a plurality of transistor units 30 at least partially integrated in the semiconductor body 100. Figure 3In the cross-sectional view of , only one of the multiple transistor cells 30 is schematically shown. Each transistor cell 30 includes at least two source regions 311, 312, and a first gate electrode 331 and a second gate electrode 332 spaced apart from each other in a first horizontal direction x. Each of the first gate electrode 331 and the second gate electrode 332 is arranged adjacent to the continuous body region 32 and is dielectrically insulated from the continuous body region 32. That is, the body region 32 extends continuously from the first gate electrode 331 to the second gate electrode 332. The semiconductor device also includes a drift region 35 separated from the at least two source regions 311, 312 by the body region 32. At least three contact plugs 421, 422, 423 are arranged between the first gate electrode 331 and the second gate electrode 332, and extend from the body region 32 toward the source electrode 41 in the vertical direction y. At least three contact plugs 421, 422, 423 are arranged in sequence between the first gate electrode 331 and the second gate electrode 332. However, as Figure 3 As shown, only the two outermost contact plugs 421 , 423 arranged closest to the first gate electrode 331 and the second gate electrode 332 , respectively, directly adjoin the source regions 311 , 312 .

[0037] exist Figure 1 and Figure 2 In the illustrated example, the contact plug 42 is shown to extend to some extent into the semiconductor body 100 (into the body region 32). However, this is merely an example. Figure 3 As exemplarily shown in FIG. 1 , the contact plugs 421, 422, 423 may also be so-called flat contact plugs, which do not extend into the semiconductor body 100. In this case, the lower ends of the contact plugs 421, 422, 423 may be arranged adjacent to the first surface 101 of the semiconductor body 100. However, in this way, the contact plugs 421, 422, 423 may still contact the body region 32 without actually extending into the body region 32 in the vertical direction y. However, similar to Figure 1 and Figure 2 The contact plug, Figure 3 The at least three contact plugs 421 , 422 , 423 in the example of EMBODIMENT 4 may alternatively also extend into the semiconductor body 100 .

[0038] exist Figure 3, two source regions 311, 312 are schematically shown. Each of the two source regions 311, 312 is arranged between one of the two outermost contact plugs 421, 423 and the nearest gate electrode 331, 332. There is no source region 31 between the outermost contact plugs 421, 423 and the at least one intermediate contact plug 422. The two source regions 311, 312 are not directly coupled to each other. The source regions 311, 312 are electrically coupled to each other via the two outermost contact plugs 421, 423 and the source electrode 41. At least one intermediate contact plug 422 arranged between the two outermost contact plugs 421, 423 does not directly adjoin any source region 311, 312. At least one intermediate contact plug 422 adjoins only the body region 32. For example, if the contact plugs are implemented as planar contact plugs, the source regions 311, 312 may partially or completely extend under the respective outermost contact plugs 421, 423. Figure 3 In the example shown in , the source regions 311, 312 partially extend under the respective outermost contact plugs 421, 423. That is, each of the outermost contact plugs 421, 423 directly contacts one of the source regions 311, 312 and the body region 32. If the source regions 311, 312 extend completely under the outermost contact plugs 421, 423 (not specifically shown), the outermost contact plugs 421, 423 may not directly contact the body region 32 but directly contact only the respective source regions 311, 312. In such a case, the intermediate contact plugs 422, which directly contact the body region 32 but do not directly contact the source regions 311, 312, serve to electrically couple the source electrode to the body region 32.

[0039] Optionally, the transistor cell 30 may further include at least one or more body contact regions 322 of the same doping type as the body region 32 but with a higher doping than the body region 32. If the corresponding contact plugs 421, 422, 423 at least partially contact the body region 32, the body contact region 322 is arranged between the contact plugs 421, 422, 423 and the body region 32. Contact plugs that do not directly contact the body region 32 (the source region extends completely below the contact plug) may not include the body contact region 322. Figure 3 In the example of FIG. 4 , such body contact regions 322 are shown in dotted lines. Each of the body contact regions 322 is arranged between one of the contact plugs 421 , 422 , 423 and the body region 32 .

[0040] By providing at least three contact plugs 421, 422, 423 for each transistor cell 30, an avalanche current that may occur during the operation of the semiconductor device is conducted away through at least one intermediate contact plug 422. That is, the current flows in the middle portion of the transistor cell toward the at least one intermediate contact plug 422. In this way, the hole current along the body region 32 directly adjacent to the source region 31 can be greatly reduced. As a result, the base voltage of the parasitic npn transistor is kept closer to the corresponding emitter voltage, thereby avoiding undesirable parasitic turn-on of the semiconductor device.

[0041] Figure 3 A planar transistor cell is schematically shown, wherein Figure 4 A trench transistor cell is schematically shown. Mutually, the above has been described with respect to Figure 3 The general principles described apply to Figure 4 The trench transistor cell. Figure 3 compared to, Figure 4 4. Contact plugs 421, 422, 423 extending into the semiconductor body 100 are shown. However, such contact plugs 421, 422, 423 can also be implemented as flat contact plugs, as has been described above for Figure 3 On the other hand, it can also be implemented in Figure 3 The contact plugs 421, 422, 423 extending into the semiconductor body 100 in the device (see Figure 4 ).

[0042] Still reference Figure 3 and Figure 4 , similar to the above Figure 1 and Figure 2 As described above, each transistor unit cell 30 of the plurality of transistor units 30 may further include a compensation region 38 having a doping type complementary to that of the drift region 35. The compensation region 38 extends from the body region 32 into the drift region 35 in the vertical direction y.

[0043] In the first horizontal direction x, the distance s2 between two adjacent contact plugs 421, 422, 423 may be respectively greater than the distance s4 between each of the outermost contact plugs 421, 423 and the closest gate electrode 331, 332. According to an example, the distance s2 between two adjacent contact plugs 421, 422, 423 may be between 100nm and 500nm. For example, the distance s4 between each of the outermost contact plugs 421, 423 and the closest gate electrode 331, 332 may be between 100nm and 400nm.

[0044] exist Figure 3 and Figure 4In FIG. 1 , only one transistor unit 30 is shown completely. Two adjacent transistor units 30 are only shown partially. Figure 3 and Figure 4 As can be seen in FIG. 1 , two directly consecutive transistor cells 30 can share a common gate electrode 331, 332. That is, half of a gate electrode 331 can be part of one of the transistor cells 30, and the other half of the same gate electrode 332 can be part of the next directly consecutive transistor cell 30. This applies to planar gate electrodes 33 ( Figure 3 ) and the trench gate electrode 33 ( Figure 4 ).

[0045] Reference now Figure 5 (planar transistor cell) and Figure 6 (trench transistor unit), each transistor unit 30 may also include at least two source extension regions 31a1, 31a2. For example, for process-related reasons, the source extension regions 31a1, 31a2 may be formed non-artificially. The source regions 311, 312 may generally be formed by implanting and subsequently diffusing ions of the first type or the second type. During the diffusion process, the ions may diffuse non-artificially in the first horizontal direction x. That is, the width of the source regions 311, 312 in the first horizontal direction x may be larger than the desired value. When forming contact plugs 421, 422, 423 extending into the semiconductor body 100, the source extension regions 31a1, 31a2 may be separated from the source regions 311, 312. The source extension regions 31a1, 31a2 may not be formed in a device including flat contact plugs 421, 422, 423 (for example, see Figure 3 ). However, unintended diffusion of ions in the first horizontal direction x is only one possible cause of the process-related formation of the source extensions 31a1, 31a2. Other causes may be inaccuracies, misalignments or size deviations of the mask openings used during the step of implanting ions in the semiconductor body 100. Figure 5 and Figure 6 The exemplary embodiments shown in FIG. 1 generally correspond to Figure 3 and Figure 4 In an embodiment, additional source extension regions 31a1, 31a2 are formed adjacent to the outermost contact plugs 421, 423. Such source extension regions may introduce more parasitic npn transistors, which may reduce the avalanche robustness of the semiconductor device.

[0046] The first source extension region 31a1 is disposed adjacent to the first outermost contact plug 421 that is closest to the first gate electrode 331. The first source extension region 31a1 extends away from the first gate electrode 331 from the first outermost contact plug 421 in the first horizontal direction x. The second source extension region 31a2 extends away from the second gate electrode 332 from the second outermost contact plug 423 in the first horizontal direction x. The width s5 in the first horizontal direction x of each of the at least two source extension regions 31a1, 31a2 may be less than twice the distance s4 between the outermost contact plugs 421, 423 and the corresponding gate electrodes 331, 332 (s5 < 2*s4). According to another example, the width s5 in the first horizontal direction x of each of the at least two source extension regions 31a1, 31a2 may be less than the distance s4 between the outermost contact plugs 421, 423 and the corresponding gate electrodes 331, 332 (s5 < s4, or even s5 < 0.5*s4).

[0047] The semiconductor device may include a plurality (at least two) of transistor units 30 as described above. The plurality of transistor units 30 may be disposed in the active region 220 of the semiconductor body 100. As described above, in its active region 220, the semiconductor body 100 includes at least one working transistor unit 30 having first and second gate electrodes 331, 332 that are dielectrically insulated from the body region 32 by a gate dielectric 34.

[0048] Now referring to Figure 7 and Figure 8 , the semiconductor device may further include at least one boundary transistor unit 301 that forms a transition between the active region 220 and the edge region 210. For example, the semiconductor device may include two boundary transistor units 301, and each of the boundary transistor units 301 abuts the active region 220 on each side in the first horizontal direction x toward the edge region 210. The structure of the boundary transistor unit 301 may be different from the structure of the transistor unit 30 in the active region 220 of the semiconductor body 100.

[0049] According to one example, as Figure 7 and Figure 8As shown, the boundary transistor cell 301 may include only one gate electrode 331 and one source region 311. The source region 311 of the boundary transistor cell 301 may extend from the first surface 101 into a base region 321 formed in the semiconductor body 100. The base region 321 may have the same doping type as the body region 32 of the transistor cell 30 in the active area 220. The base region 321 may extend from the first surface 101 into the semiconductor body 100 and may have a larger width in the horizontal direction x than the body region 32 of the transistor cell 30 in the active area 220. The base region 321 is dielectrically insulated from the gate electrode 331 by the gate dielectric 34.

[0050] The gate electrode 331 of the boundary transistor unit 301 may be arranged adjacent to the second gate electrode 332 of the adjacent transistor unit 30 in the active area 220. In other words, the outermost transistor unit 30 of the active area 220 may share the gate electrodes 331, 332 with the boundary transistor unit 301. The boundary transistor unit 301 does not include the second gate electrode 332 in the transition area toward the edge area 210. The boundary transistor unit 301 may also not include the second source region 312 in the transition area toward the edge area 210. Figure 7 and Figure 8 As further shown in the dashed line in FIG. 3 , the boundary transistor cell 301 may also include a single optional source extension region 31 a 1. The boundary transistor cell 301 may not include a second source extension region 31 a 2 in the transition region toward the edge region 210. In other embodiments, the boundary transistor cell 301 may not include any source region 31 at all.

[0051] exist Figure 7 and Figure 8 In the example shown in , the boundary transistor cell 301 includes a first contact plug 421 and a second contact plug 422. In other words, the boundary transistor cell 301 may substantially correspond to half of the transistor cell 30 in the active area 220. The second contact plug 422 of the boundary transistor cell 301 may have the same function as the second contact plug 422 (and any optional additional intermediate contact plugs), as described above for Figures 3 to 6 That is, the risk of the parasitic bipolar transistor being undesirably activated can also be reduced in each of the at least one boundary transistor cells 301 .

[0052] However, the boundary transistor cell 301 including two contact plugs 421, 422 is only an example. Typically, the boundary transistor cell 301 may also include only the first contact plug 421, which is adjacent to the first source region 311, the body region 321 and the optional source extension region 31a1. That is, the second or any other contact plug may be omitted in the boundary transistor cell 301. However, according to another example, the boundary transistor cell 301 may also include more than two contact plugs. For example, the number of contact plugs in the boundary transistor cell 301 may be equal to the number of contact plugs of the transistor cell 30 in the active area 220. Because a more uniform layout can be used for the transistor cell 30 in the active area 220 and the boundary transistor cell 301, this can provide advantages during the production of semiconductor devices.

[0053] Regardless of whether at least one boundary transistor cell 301 includes only one contact plug or more than one contact plug, only one contact plug 421 can abut a single source region 311 and an optional single source extension region 31a1. That is, only the first contact plug 421 arranged closest to the single gate electrode 331 can abut a single source region 311 and a single optional source extension region 31a1. The contact plugs in the boundary transistor cell 301 that are not arranged closest to the first gate electrode 331 abut only the base region 321.

[0054] like Figure 7 and Figure 8 As further shown, the boundary transistor unit 301 may also include at least one body contact region 322 of the same doping type as the base region 321 but with a higher doping level. Figure 7 and Figure 8 In the example of , such body contact regions 322 are shown in dotted lines. The number of body contact regions 322 may be equal to the number of contact plugs of the boundary transistor unit 301. Each of the body contact regions 322 is arranged between one of the contact plugs 421, 422 and the base region 321.

[0055] In the above use Figures 3 to 8 In the described example, each transistor unit 30 includes two source regions 311, 312 and at least three contact plugs 421, 422, 423. However, this is only an example. According to another example, the transistor unit 30 may also include only one source region 311 and one optional source extension region 31a1. Figure 7 and Figure 8In FIG, this situation is indicated by illustrating the second source region 312 (and the second optional source extension region 31a2) with dotted lines. In such a case, it may also be sufficient to provide only two contact plugs 421, 422, wherein one of the two outermost contact plugs 421 directly adjoins the single source region 311 and the single optional source extension region 31a1. If a transistor cell 30 having a single source region 311 (in the present context a single having the meaning of one but not more than one source region 311) comprises two or more than two contact plugs, there may be at least one contact plug that does not directly adjoin the source region 311. In Figure 7 and Figure 8 In the example of FIG. 1 , if the second source region 312 is omitted, only the first contact plug 421 directly adjoins the single source region 311, while the other contact plugs 422 (and optionally any additional contact plugs 423) do not directly adjoin the single source region 311. That is, according to an example, only the first contact plug 421 arranged closest to one of the gate electrodes 331 directly adjoins the single source region 311. Providing only one source region 311 for each transistor cell 30 can further increase the short-circuit resistance of the device.

[0056] Referring now to FIG. 9 , which shows a top view of a semiconductor device according to several examples, the contact plugs 421 , 422 , 423 may be elongated contact plugs having a length w5 in the second horizontal direction z that is significantly greater than its maximum width s3 in the first horizontal direction x. According to one example, the length w5 of the contact plugs 421 , 422 , 423 in the second horizontal direction z may be several 100 μm, or even several millimeters. This may cause problems during the step of forming the contact plugs 421 , 422 , 423 , especially when a resist mask is formed on the semiconductor body 100 while etching the trenches for the contact plugs 421 , 422 , 423 .

[0057] Therefore, according to one example, at least one of the contact plugs (eg, Fig.9A The contact plug 422 in the second horizontal direction z is divided into at least two independent sections. Each of the independent sections may have a maximum length w1 in the second horizontal direction z, for example, 200 μm or less. Fig.9A (three contact plugs 421, 422, 423) and Fig. 9B In the example of (four contact plugs 421, 422, 423, 424), only the middle contact plug ( Fig.9A 422, and Fig. 9B 422, 423) are divided into a plurality of different sections. The two outermost contact plugs ( Fig.9A 421, 423 and Fig. 9B421, 424) are continuous contact plugs. However, this is only an example. One or two of the outermost contact plugs can also be divided into several independent sections. For example, the distance w2 between two adjacent sections of the same contact plug 421, 422, 423, 424 in the second horizontal direction z can be several μm.

[0058] exist Fig.9A In the example of FIG. 3 , a first gate electrode 331 and a second gate electrode 332 are schematically shown, wherein three contact plugs 421 , 422 , 423 are arranged between the first and second gate electrodes 331 , 332 . In addition, Fig.9A Also schematically shown are outermost contact plugs 421, 423 of corresponding adjacent transistor cells (only partially shown in the figure). Fig. 9B The first gate electrode 331 and the second gate electrode 332 are schematically shown, wherein four contact plugs 421 , 422 , 423 , 424 are arranged between the first gate electrode 331 and the second gate electrode 332 . Fig.9A and Fig. 9B The source regions 311, 312 and the source extension regions 31a1, 31a2 are not specifically shown.

[0059] Reference now Fig.10 The source regions 311, 312 and source extension regions 31a1, 31a2 schematically indicated by dashed lines show Fig.9A In the second horizontal direction z, each source region 311, 312 may be divided into two or more independent sections. Different sections of the source regions 311, 312 may not have direct connections to each other and may be connected to each other only via corresponding contact plugs (e.g., Fig.10 However, different sections of the source regions 311, 312 may also have direct connections to each other. Fig.10 4 shows this situation by means of the second source region 312 arranged adjacent to the third contact plug 423. In this example, different sections of the second source region 312 are connected to each other by means of a narrow bridge section 31b. The width s7 of the bridge section 31b in the first horizontal direction x may be smaller than the width s6 of the independent section of the corresponding source region 312 in the first horizontal direction x, for example, the width s7 of the bridge section 31b in the first horizontal direction x may be less than 50% or less than 25% of the width s6 of the corresponding source region 312 in the first horizontal direction x.

[0060] Each of the individual segments of the source regions 311 , 312 may have a maximum length w3 in the second horizontal direction z of, for example, 200 μm or less. For example, a distance w4 between two adjacent segments of the same source region 311 , 312 in the second horizontal direction z may be several μm.

[0061] As described above Figure 5 and Figure 6 Schematically shows Fig.10 A cross-sectional view of a semiconductor device in a cross-sectional plane BB'.

[0062] The above is for Figure 9 and Fig.10 The contents described above also apply mutatis mutandis to semiconductor devices, wherein each transistor cell 30 includes only a single source region 311 and at least two contact plugs 421 , 422 .

[0063] Reference now Fig.11 , a single extended contact plug 421 may also be arranged between two adjacent gate electrodes 331, 332 instead of at least three (or at least two if the transistor cell comprises only one source region 311) consecutive narrow contact plugs 421, 422, 423. The width s1 of a single transistor cell 30 in the first horizontal direction x may be 7 μm or less, and the distance s between two adjacent gate electrodes 331, 332 in the first horizontal direction x may be 1 μm or less. 11 It can be 6.5 μm or less, as described above for Figure 3 and Figure 4 Depends on the distance s between two adjacent gate electrodes 331 and 332 11 , the width s8 of the single extended contact plug 421 in the first horizontal direction x may be, for example, at least 5 μm or at least 6 μm. That is, the width s8 of the single extended contact plug 421 may be only slightly smaller than the distance s between two adjacent gate electrodes 331 , 332 11 In this way, the single extended contact plug 421 extends substantially along almost the entire distance s between two adjacent gate electrodes 331 , 332 . 11 For example, the width s8 of the single extended contact plug 421 may be equal to the width s 13 , or even greater than the width s of the compensation zone 38 13 .

[0064] For example, a single extended contact plug 421 may include different layers. Fig.11As schematically shown in , a single extended contact plug 421 may include three layers, namely a first layer 411, a second layer 412 and a metal layer. The metal layer may form or may be connected to a source electrode. The metal layer may be the uppermost layer. The first layer 411 may be the lowermost layer. That is, the first layer 411 may be in direct contact with the source regions 311, 312 and the body region 32. The second layer 412 may be arranged between the first layer 411 and the metal layer. For example, the first layer 411 may be a barrier layer including titanium nitride (TiN). For example, the second layer 412 may include tungsten (W). For example, the metal layer may include aluminum (Al). However, these are merely examples. Any other suitable material may be used to form the first layer 411, the second layer 412 and the metal layer. Fig.11 The remaining structure of the transistor cell 30 shown in FIG. 1 is similar to that already described above for Figure 1 and Figure 2 Optionally, the transistor unit 30 may further include a body contact region 322 having the same doping type as the body region 32 but with a higher doping level. Fig.11 In the example of FIG. 4 , such a body contact region 322 is shown in dotted lines. The (optional) body contact region 322 is arranged between the single extended contact plug 421 and the body region 32 .

[0065] like Fig.11 , the metal layer extends toward the main region 32 in the vertical direction y. The metal layer may partially extend into the semiconductor body 100 in the vertical direction y. That is, the lowermost end of the metal layer may extend into the semiconductor body 100 to be below the first surface 101. However, this is only an example. The lowermost end of the metal layer may also terminate far above the first surface 101 in the vertical direction y (not shown).

[0066] The gate electrodes 331, 332 may be narrower than the single extended contact plug 421. That is, the width s9 of the gate electrodes 331, 332 in the first horizontal direction x may be significantly smaller than the width s8 of the single extended contact plug 421. According to one example, the width s9 of the gate electrode 33 in the first horizontal direction x may be 2 μm or less. Fig.11 In the example of , the width s9 of the gate electrode refers to the width of the common gate electrodes 331 , 332 , that is, the first gate electrode 331 of one transistor unit 30 and the adjacent second gate electrode 332 of the directly consecutive transistor unit 30 .

[0067] In the vertical direction y, the single extended contact plug 421 may extend to a deeper depth d1 in the semiconductor body 100 than to a deeper depth d2 in the source regions 311, 312. That is, the depth d1 of the lowermost end of the first layer 411 may be deeper than the depth d2 of the lowermost end of the source regions 311, 312.

[0068] Reference now Fig.12 , schematically showing a gate contact plug 430, which electrically couples the gate electrode 33 to the gate runner 45. The semiconductor device typically includes a gate pad (not shown) that forms or can be coupled to the gate node G. The gate runner 45 typically connects multiple gate electrodes 33 to the gate pad. The gate runner 45 may include a metal layer arranged above the first surface 101. For example, the gate runner 45 may be a circumferential layer extending along the outer edge of the semiconductor body 100. Each of the gate electrodes 33 is typically coupled to the gate runner 45 by means of a gate contact plug 430. Compared to the single extended contact plug 421 of the transistor cell 30, Fig.12 4 shows that one of the gate contact plugs 430 may be narrow. That is, compared with the width s8 of the single extended contact plug 421 in the first horizontal direction x, the width s of the gate contact plug 430 in the first horizontal direction x is s. 10 According to an example, the width s of the gate contact plug 430 in the first horizontal direction x is 10 The width s9 of the gate contact plug 430 in the first horizontal direction x may be smaller than the width s9 of the common gate electrode 33 in the first horizontal direction x. That is, the width s9 of the gate contact plug 430 in the first horizontal direction x 10 It may be smaller than 1 μm or even smaller than 0.5 μm.

[0069] The gate contact plug 430 may include two or more layers. For example, the gate contact plug 430 may include a barrier layer 451 and an intermediate layer 452. The barrier layer 451 may be the lowest layer. That is, the barrier layer 451 may directly adjoin the common gate electrode 33 and the insulating layer 51 formed on the top surface 101 of the semiconductor body 100. For example, the barrier layer 451 may include titanium nitride (TiN). The intermediate layer 452 may be arranged on the barrier layer 451. That is, the barrier layer 451 may be arranged between the intermediate layer 452 and the gate electrode 33 and between the intermediate layer 452 and the insulating layer 51, respectively. The gate runner 45 may be arranged on top of the intermediate layer 452. That is, the intermediate layer 452 may be arranged between the gate runner 45 and the barrier layer 451.

[0070] Since the width s of the gate contact plug 430 in the first horizontal direction x 10 The intermediate layer 452 is relatively small and may only partially extend into the trench extending through the insulating layer 51 toward the gate electrode 33. For process-related reasons, such a trench usually tapers to some extent toward the gate electrode 33. Therefore, when the barrier layer 451 is formed in the trench, the bottom of the trench will be completely filled with the material of the barrier layer 451, leaving only a relatively small remaining trench to be filled with the material of the intermediate layer 452.

[0071] For example, you can Fig.12 The narrow gate contact plug 430 and Fig.11 A single extended contact plug 421 is combined.

[0072] As mentioned above Fig.12 As described above, the narrow contact plug may additionally or alternatively be used to contact other elements of the semiconductor device. Fig.12 As exemplarily shown in , the additional field plate electrode 39 may be arranged below the gate electrode 33. In this context, "below" means that the gate electrode 33 is arranged between the additional field plate electrode 39 and the first surface 101 of the semiconductor body 100 in the vertical direction y. The (optional) field plate electrode 39 may include a layer of conductive material. According to one example, the (optional) additional field plate electrode 39 may be formed by a polysilicon layer. For example, the additional field plate electrode 39 may be electrically connected to the source node S or the gate node G of the semiconductor device. As described above with respect to the gate contact plug 430, a narrow contact plug may also be used to electrically contact the additional field plate electrode 39. Such a narrow contact plug for electrically contacting the additional field plate electrode 39 is Fig.12 4. The gate contact plug 430 is not specifically shown in the figure, but basically corresponds to the gate contact plug 430 described above. That is, the gate contact plug 430 is connected to the gate contact plug 430 by the gate contact plug 430. Fig.11 ), the width of the contact plug for contacting the additional field plate electrode 39 may be small compared to the width s8 of the gate electrode 33. According to an example, the width of the contact plug for contacting the additional field plate electrode 39 in the first horizontal direction x may be smaller than the width s9 of the common gate electrode 33 in the first horizontal direction x (see Fig.11 ). That is, the width of the contact plug for contacting the additional field plate electrode 39 in the first horizontal direction x may be less than 2 μm or even less than 1 μm.

[0073] Reference now Fig.13 , one or more narrow contact plugs 601 may be used to electrically contact a conductive layer 61 arranged in or on the semiconductor body 100. For example, the conductive layer 61 may be a polysilicon layer. According to one example, the semiconductor device may further include at least one diode integrated in the conductive layer 61. For example, the at least one diode may be an ESD protection diode. Fig.13, a single continuous conductive layer 61 is schematically shown. However, for example, at least one pn junction may be formed in the conductive layer 61 to form at least one diode. According to one example, two or more diodes may be formed in the conductive layer 61 so that they are electrically coupled in series between two contact plugs 601. Each of the contact plugs 601 electrically couples the conductive layer 61 to a corresponding metal layer 62 formed on the semiconductor body 100. According to one example, the conductive layer 61 may be electrically insulated from other components of the semiconductor device by at least one oxide layer 60.

[0074] The single extended contact plug 421 (see Fig.11 ) compared to Fig.13 FIG. 4 shows that two of the additional contact plugs 601 may be narrow. That is, compared with the width s8 of the single extended contact plug 421 in the first horizontal direction x, the width s of the additional contact plug 601 in the first horizontal direction x is s. 12 According to an example, the width s of the additional contact plug 601 in the first horizontal direction x is 12 The width s9 of the additional contact plug 601 in the first horizontal direction x may be smaller than the width s9 of the shared gate electrode 33 in the first horizontal direction x. That is, for example, the width s9 of the additional contact plug 601 in the first horizontal direction x may be smaller than the width s9 of the shared gate electrode 33 in the first horizontal direction x. 12 It may be smaller than 2 μm or even smaller than 1 μm.

[0075] Each of the additional contact plugs 601 may include two or more layers. For example, the additional contact plug 601 may include a barrier layer 621 and an intermediate layer 622. The barrier layer 621 may be the lowermost layer. That is, the barrier layer 621 may directly adjoin the conductive layer 61. For example, the barrier layer 621 may include titanium nitride (TiN). The intermediate layer 622 may be arranged on the barrier layer 621. That is, the barrier layer 621 may be arranged between the intermediate layer 622 and the conductive layer 61. The metal layer 62 may be arranged on top of the corresponding intermediate layer 622. That is, the intermediate layer 622 may be arranged between the metal layer 62 and the barrier layer 621.

[0076] Since the width s of the additional contact plug 601 in the first horizontal direction x 12 The intermediate layer 622 may be relatively small and may only partially extend into the trench extending from the metal layer 62 toward the conductive layer 61. For process-related reasons, such a trench usually tapers to some extent toward the conductive layer 61. Therefore, when the barrier layer 621 is formed in the trench, the bottom of the trench will be completely filled with the material of the barrier layer 621, leaving only a relatively small remaining trench to be filled with the material of the intermediate layer 622.

[0077] For example, you can Fig.13The narrow additional contact plug 601 and Fig.11 The single extended contact plug 421 and Fig.12 The narrow gate contact plug 430 can be further combined with Fig.12 and Fig.13 The plug is the same as the one described above for Figure 3-Figure 8 The device combination.

Claims

1. A semiconductor device, comprising: A semiconductor body (100), the semiconductor body (100) comprising a first surface (101) and a second surface (102) opposite to the first surface (101) in a vertical direction (y); A plurality of transistor cells (30), the plurality of transistor cells (30) being at least partially integrated in the semiconductor body (100), each of the plurality of transistor cells (30) comprising: at least two source regions (311, 312), a first gate electrode (331) and a second gate electrode (332), the first gate electrode (331) and the second gate electrode (332) being spaced apart from each other in a first horizontal direction (x), each of the first gate electrode (331) and the second gate electrode (332) being arranged adjacent to the continuous body region (32) and being dielectrically insulated from the continuous body region (32), a drift region (35), the drift region (35) being separated from the at least two source regions (311, 312) by the body region (32), and at least three contact plugs (421, 422, 423), the at least three contact plugs (421, 422, 423) extending from the body region (32) toward the source electrode (41) in the vertical direction (y), wherein the at least three contact plugs (421, 422, 423) are arranged successively between the first gate electrode (331) and the second gate electrode (332), and wherein only the two outermost contact plugs (421, 423) arranged closest to the first gate electrode (331) and the second gate electrode (332), respectively, directly adjoin at least one of the source regions (311, 312), Each of the at least three contact plugs (421, 422, 423) is an elongated contact plug, and at least one of the contact plugs (421, 422, 423) is divided into at least two independent sections in the second horizontal direction (z).

2. The semiconductor device according to claim 1, wherein Each of the plurality of transistor cells (30) further comprises a compensation region (38) having a doping type complementary to that of the drift region (35) and extending from the corresponding body region (32) into the drift region (35) in the vertical direction (y).

3. The semiconductor device according to claim 1 or 2, wherein: Each of the plurality of transistor cells (30) has a first width (s1) in the first horizontal direction (x), wherein the first width (s1) is 7 μm or less.

4. The semiconductor device according to any one of claims 1 to 3, wherein: Each of the at least three contact plugs (421, 422, 423) has a maximum width (s3) of 500 nm or less in the first horizontal direction (x).

5. The semiconductor device according to any one of claims 1 to 4, wherein: The distance (s2) between two directly consecutive contact plugs (421, 422, 423) is greater than the distance (s4) between the outermost contact plug (421, 423) and the corresponding gate electrode (331, 332).

6. The semiconductor device according to claim 5, wherein: The distance (s4) between the outermost contact plug (421, 423) and the corresponding gate electrode (331, 332) is between 100 nm and 400 nm.

7. The semiconductor device according to any one of claims 1 to 6, wherein: Each of the plurality of transistor cells (30) further comprises at least three body contact regions (322) of the same doping type as the body region (32) but with a higher doping, wherein each of the body contact regions (322) is arranged between one of the contact plugs (421, 422, 423) and the body region (32).

8. The semiconductor device according to any one of claims 1 to 7, wherein: The elongated contact plug has a length (w5) in the second horizontal direction (z) that is significantly greater than its maximum width (s3) in the first horizontal direction (x).

9. The semiconductor device according to claim 8, wherein: Each of the independent segments has a maximum length ( w1 ) of 200 μm or less in the second horizontal direction (z).

10. A semiconductor device according to any one of the preceding claims, wherein: Two directly successive transistor cells (30) have a common gate electrode (331, 332).

11. A semiconductor device according to any one of the preceding claims, wherein Each of the plurality of transistor units (30) further includes a first source extension region (31a1), the first source extension region (31a1) being arranged adjacent to a first outermost contact plug (421) arranged closest to the first gate electrode (331), and extending from the first outermost contact plug (421) away from the first gate electrode (331) in the first horizontal direction (x); as well as A second source extension region (31a2), wherein the second source extension region (31a2) is arranged adjacent to a second outermost contact plug (423) arranged closest to the second gate electrode (332), and extends from the second outermost contact plug (423) away from the second gate electrode (332) in the first horizontal direction (x).

12. The semiconductor device according to claim 11, wherein A width (s5) of each of the first source extension region and the second source extension region (31a1, 31a2) in the first horizontal direction (x) is less than twice a distance (s4) between the outermost contact plug (421, 423) and the corresponding gate electrode (331, 332).

13. The semiconductor device according to claim 12, wherein: The width (s5) of each of the first source extension region and the second source extension region (31a1, 31a2) in the first horizontal direction (x) is smaller than the distance (s4) between the outermost contact plug (421, 423) and the corresponding gate electrode (331, 332).

14. The semiconductor device according to any of the preceding claims, further comprising at least one boundary transistor cell (301), the at least one boundary transistor cell (301) forming a transition between an active region (220) and an edge region (210) of the semiconductor body (100) and being at least partially integrated in the semiconductor body (100), each of the at least one boundary transistor cell (301) comprising a single source region (311), a single first gate electrode (331), the single first gate electrode (331) being arranged adjacent to the continuous base region (321) and being dielectrically insulated from the continuous base region (321), a drift region (35), the drift region (35) being separated from the single source region (311) by the base region (321), and At least one contact plug (421, 422, 423), the at least one contact plug (421, 422, 423) extending from the base region (321) toward the source electrode (41) in the vertical direction (y), wherein: Only the first contact plug (421) arranged closest to the first gate electrode (331) directly adjoins the single source region (311).

15. A semiconductor device comprising: A semiconductor body (100), the semiconductor body (100) comprising a first surface (101) and a second surface (102) opposite to the first surface (101) in a vertical direction (y); A plurality of transistor cells (30), the plurality of transistor cells (30) being at least partially integrated in the semiconductor body (100), each of the plurality of transistor cells (30) comprising: a single source region (311), a first gate electrode (331) and a second gate electrode (332), the first gate electrode (331) and the second gate electrode (332) being spaced apart from each other in a first horizontal direction (x), each of the first gate electrode (331) and the second gate electrode (332) being arranged adjacent to the continuous body region (32) and being dielectrically insulated from the continuous body region (32), a drift region (35), the drift region (35) being separated from the source regions (311, 312) by the body region (32), and at least two contact plugs (421, 422, 423), the at least two contact plugs (421, 422, 423) extending from the body region (32) toward the source electrode (41) in the vertical direction (y), wherein the at least two contact plugs (421, 422, 423) are arranged successively between the first gate electrode (331) and the second gate electrode (332), and wherein at least one of the at least two contact plugs (421, 422, 423) does not directly adjoin the source region (311), Each of the at least two contact plugs (421, 422, 423) is an elongated contact plug, and at least one of the contact plugs (421, 422, 423) is divided into at least two independent sections in the second horizontal direction (z).

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