Image sensor

Abstract

This disclosure provides an image sensor comprising a photoelectric conversion layer, an integrated circuit layer, and a charge storage layer. The photoelectric conversion layer includes a pixel separation structure defining pixel regions, each pixel region including a photoelectric conversion region. The integrated circuit layer reads charge from the photoelectric conversion region. The charge storage layer includes stacked capacitors for each of the plurality of pixel regions. The stacked capacitors include: a lower pad electrode; a middle pad electrode; an upper pad electrode; a contact plug connecting the upper pad electrode to the lower pad electrode; a lower capacitor structure connected between the lower pad electrode and the middle pad electrode; and an upper capacitor structure connected between the middle pad electrode and the upper pad electrode. The upper capacitor structure is stacked on the lower capacitor structure to partially overlap with the lower capacitor structure when viewed in a plan view.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority to Korean Patent Application No. 10-2019-0066959, filed on June 5, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to an image sensor, and more specifically, to an image sensor capable of performing global shutter operation. Background Technology

[0004] An image sensor is an electronic device used to convert optical images into electrical signals. Due to the development of the computer and communications industries, high-performance image sensors are increasingly required to be integrated into various devices, such as digital cameras, camcorders, personal communication systems (PCS), game consoles, security cameras, and medical microcameras. Furthermore, image sensors for realizing three-dimensional (3D) and color images have been developed. Summary of the Invention

[0005] One or more exemplary embodiments provide an image sensor with improved shutter efficiency.

[0006] According to one aspect of an embodiment, an image sensor is provided, the image sensor including a photoelectric conversion layer, an integrated circuit layer, and a charge storage layer. The photoelectric conversion layer includes a pixel separation structure defining a plurality of pixel regions, each of the plurality of pixel regions including a photoelectric conversion region. The integrated circuit layer is disposed on the photoelectric conversion layer and includes a readout circuit for reading charge from the photoelectric conversion region of the pixel region. The charge storage layer is disposed on the integrated circuit layer and includes a stacked capacitor for each of the plurality of pixel regions, the stacked capacitor including: a first lower pad electrode; a middle pad electrode; and a first upper pad electrode. A contact plug connecting the first upper pad electrode to the first lower pad electrode; a first lower capacitor structure connected between the first lower pad electrode and the intermediate pad electrode and including a plurality of first lower storage electrodes for storing the charge read from the photoelectric conversion region of the pixel region; and an upper capacitor structure connected between the intermediate pad electrode and the first upper pad electrode and including a plurality of upper storage electrodes for storing the charge read from the photoelectric conversion region of the pixel region, the upper capacitor structure being stacked on the first lower capacitor structure to partially overlap the first lower capacitor structure when viewed in a plan view.

[0007] According to another aspect of the embodiments, an image sensor is provided, the image sensor including a photoelectric conversion layer, an integrated circuit layer, a first charge storage layer, and a second charge storage layer, the photoelectric conversion layer having a pixel separation structure defining a photoelectric conversion region, the integrated circuit layer disposed on the photoelectric conversion layer and including a readout circuit for reading charge from the photoelectric conversion region, the first charge storage layer including: a first capacitor structure including a plurality of first storage electrodes for storing the charge read from the photoelectric conversion region; and a first warpage control layer, the second charge storage layer being coupled to the first charge storage layer, the second charge storage layer including: a second capacitor structure including a plurality of second storage electrodes for storing the charge read from the photoelectric conversion region, the second capacitor structure being stacked on the first capacitor structure to partially overlap the first capacitor structure when viewed in a plan view; and a second warpage control layer formed on the surface of the second charge storage layer opposite to the first charge storage layer.

[0008] According to another aspect of the embodiments, an image sensor is provided, the image sensor including a pixel array, the pixel array including a plurality of pixels, each of the plurality of pixels including a stacked capacitor, the stacked capacitor including: a lower pad electrode; a first intermediate pad electrode; a second intermediate pad electrode; an upper pad electrode; a lower capacitor structure connected between the lower pad electrode and the first intermediate pad electrode; an intermediate capacitor structure connected between the first intermediate pad electrode and the second intermediate pad electrode, the intermediate capacitor structure being stacked on the lower capacitor structure to partially overlap with the lower capacitor structure when viewed in a plan view; a lower contact plug connecting the second intermediate pad electrode to the lower pad electrode; an upper capacitor structure connected between the second intermediate pad electrode and the upper pad electrode, the upper capacitor structure being stacked on the intermediate capacitor structure; and an upper contact plug connecting the second intermediate pad electrode to the upper pad electrode. Attached Figure Description

[0009] These and other aspects will become more apparent in conjunction with the accompanying drawings and detailed description, in which:

[0010] Figure 1 This is a schematic block diagram illustrating an image sensor according to some embodiments.

[0011] Figure 2 This is a schematic diagram illustrating a pixel array of an image sensor according to some embodiments.

[0012] Figure 3A , Figure 3B and Figure 3C This is a circuit diagram illustrating a unit pixel of a pixel array according to some embodiments.

[0013] Figure 4A , Figure 4B and Figure 4C This is a circuit diagram illustrating a capacitor disposed in a unit pixel according to some embodiments.

[0014] Figure 5 This is a schematic plan view illustrating an image sensor according to some embodiments.

[0015] Figure 6A and Figure 6B They are respectively along Figure 5 The images taken along lines I-I' and II-II' show cross-sectional views of an image sensor according to some embodiments.

[0016] Figures 7 to 18 This is a cross-sectional view showing an image sensor according to some embodiments. Detailed Implementation

[0017] The image sensor according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In this specification, unless otherwise specifically indicated, the structure of a feature having a reference indicator with a letter is the same as the structure of a feature having a reference indicator without a letter. For example, unless otherwise specifically mentioned, the lower electrode structures 231a and 231b have the same structure as the lower electrode structure 231.

[0018] Figure 1 This is a schematic block diagram illustrating an image sensor according to some embodiments.

[0019] Reference Figure 1 The image sensor 110 may include a pixel array 10, a row decoder 20, a row driver 30, a column decoder 40, a timing generator 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output (I / O) buffer 80.

[0020] Pixel array 10 may include a plurality of unit pixels arranged along rows and columns and may convert light incident on the unit pixels into electrical signals. Row decoder 20 may provide drive signals to unit pixels row by row. The electrical signals converted in pixel array 10 may be provided to associated double sampler 60 in response to the drive signals. Row driver 30 may provide drive signals to pixel array 10 for driving unit pixels in response to the result decoded in row decoder 20. When unit pixels are arranged in a matrix, drive signals may be provided row by row.

[0021] The timing generator 50 controls the row decoder 20 and column decoder 40, the correlated double sampler 60, the analog-to-digital converter 70, and the I / O buffer 80, and can supply control signals (e.g., clock signals and timing control signals) to the row decoder 20 and column decoder 40, the correlated double sampler 60, the analog-to-digital converter 70, and the I / O buffer 80 during operation. The timing generator 50 may include logic control circuitry, phase-locked loop (PLL) circuitry, timing control circuitry, and communication interface circuitry.

[0022] The correlated dual sampler 60 can receive electrical signals generated from the pixel array 10, and can hold and sample the received electrical signals. The correlated dual sampler 60 can sample specific noise levels and signal levels of the electrical signals, and can output a difference level corresponding to the difference between the noise level and the signal level.

[0023] The analog-to-digital converter 70 converts an analog signal corresponding to the difference level output from the correlated dual sampler 60 into a digital signal. The analog-to-digital converter 70 can output a digital signal. The I / O buffer 80 can latch the digital signal output from the analog-to-digital converter 70 and can sequentially output the latched digital signal to the image signal processing unit (not shown) in response to the decoding result in the column decoder 40.

[0024] Figure 2 This is a schematic diagram illustrating a pixel array of an image sensor according to some embodiments.

[0025] Reference Figure 2 The pixel array 10 may include multiple drive signal lines SL and output lines Vout, as well as multiple unit pixels P arranged in two dimensions along multiple rows and multiple columns.

[0026] In each unit pixel P, an electrical signal can be generated by incident light. The unit pixel P can be driven by a drive signal transmitted via a drive signal line SL connected to the unit pixel P. Each of the drive signal lines SL can extend in a row direction (e.g., horizontal direction) to simultaneously drive the unit pixels P included in the same row.

[0027] Each unit pixel P may include a photoelectric conversion element and a plurality of metal oxide semiconductor (MOS) transistors. The plurality of MOS transistors may constitute a readout circuit and a sampling circuit. The photoelectric conversion element of unit pixel P can generate photocharge (or charge) proportional to the amount of light incident from the outside, and can store a voltage proportional to the amount of photocharge generated. In other words, in each unit pixel P, incident light can be converted into a voltage proportional to the amount of photocharge generated, and the voltage can be stored.

[0028] Each unit pixel P may include sampling circuitry for holding and sampling the charge generated from the photoelectric conversion element, and thus, according to some embodiments, the image sensor can perform global shutter operation. In other words, in the operation of the image sensor, all unit pixels P can be exposed simultaneously to store charge in all unit pixels P simultaneously, and pixel signals can be output sequentially unit by unit. In some embodiments, unit pixels P may have the same circuit configuration, and reference will be made to... Figure 3A , Figure 3B and Figure 3C Let me explain the circuit configuration in detail.

[0029] Figure 3A , Figure 3B and Figure 3C This is a circuit diagram illustrating a unit pixel of a pixel array according to some embodiments.

[0030] Reference Figure 3A According to some embodiments, the image sensor may have an intra-pixel correlated double sampling (CDS) structure.

[0031] Each unit pixel P may include a photoelectric conversion element PD, a transfer transistor TX, a reset transistor RX, a first source follower transistor SF1, a precharge transistor PC, a sampling transistor SAM, a calibration transistor CAL, a second source follower transistor SF2, a selection transistor SEL, a first capacitor C1, and a second capacitor C2. In some embodiments, the plurality of MOS transistors described above may include a transfer transistor TX, a reset transistor RX, a first source follower transistor SF1, a precharge transistor PC, a sampling transistor SAM, a calibration transistor CAL, a second source follower transistor SF2, and a selection transistor SEL.

[0032] A transfer transistor TX can be connected between a photoelectric conversion element PD and a charge detection node (e.g., a floating diffusion region) FD. The transfer transistor TX transfers the charge accumulated in the photoelectric conversion element PD to the charge detection node FD. The transfer transistor TX can be controlled by a charge transfer signal input to the transfer gate electrode.

[0033] A photoelectric conversion element (PD) can generate photocharge (or charge) proportional to the amount of light incident from the outside and can accumulate the generated photocharge. In some embodiments, the photoelectric conversion element (PD) may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or any combination thereof.

[0034] The charge detection node FD can receive the charge generated in the photoelectric conversion element PD and can accumulate and store the received charge. The potential of the gate electrode of the first source follower transistor SF1 can be changed according to the amount of photocharge accumulated in the charge detection node FD.

[0035] The reset transistor RX periodically resets the charge accumulated in the charge detection node FD. The reset transistor RX is controlled by a reset signal input to its gate electrode. The drain of the reset transistor RX is connected to the charge detection node FD, and the source of the reset transistor RX is connected to the power supply voltage Vpix. When the reset transistor RX is turned on by the reset signal, the power supply voltage Vpix connected to the source of the reset transistor RX can be transferred to the charge detection node FD. In other words, when the reset transistor RX is turned on, the photocharge accumulated in the charge detection node FD can be discharged to reset the charge detection node FD.

[0036] The first source follower transistor SF1 can be a source follower buffer amplifier that generates a source-drain current proportional to the amount of photocharge supplied to its gate electrode. The drain of the first source follower transistor SF1 can be connected to the power supply voltage Vpix, and the source of the first source follower transistor SF1 can be connected to the source of the precharge transistor PC and the source of the sampling transistor SAM.

[0037] A sampling transistor SAM can be connected between the source of the first source follower transistor SF1 and the first node n1. The first electrode of each of the first capacitor C1 and the second capacitor C2 can be connected to the first node n1. A capacitor voltage VC can be applied to the second electrode of the first capacitor C1, and the second electrode of the second capacitor C2 can be connected to the second node n2.

[0038] The drain of the calibration transistor CAL can be connected to the power supply voltage Vpix, and the source of the calibration transistor CAL can be connected to the second node n2. The second node n2 can be calibrated by the calibration transistor CAL.

[0039] The gate electrode of the second source follower transistor SF2 can be connected to the second node n2. The drain of the second source follower transistor SF2 can be connected to the power supply voltage Vpix, and the source of the second source follower transistor SF2 can be connected to the drain of the select transistor SEL. The second source follower transistor SF2 can amplify the potential change in the second node n2, and can output a pixel signal to the output line Vout through the select transistor SEL.

[0040] Methods for manipulating a unit pixel P may include a reset operation to reset the photoelectric conversion element PD and the charge detection node FD, a photoaccumulation operation to accumulate photocharge in the photoelectric conversion element PD, and a sampling operation to output the accumulated photocharge as a pixel signal. The sampling operation may include a reset signal sampling operation and an image signal sampling operation.

[0041] During the reset operation, the reset transistor RX and the transfer transistor TX can be turned on. Therefore, the power supply voltage Vpix can be supplied to the charge detection node FD. This allows the charge in the photoelectric conversion element PD and the charge detection node FD to be discharged, thereby resetting the photoelectric conversion element PD and the charge detection node FD.

[0042] After resetting the photoelectric conversion element PD and the charge detection node FD, photocharge can be generated and accumulated in the photoelectric conversion element PD until the transfer transistor TX is turned on again after it is turned off (i.e., the continuous photoelectric conversion time).

[0043] After the light accumulation operation, the charge detection node FD can be reset by the power supply voltage Vpix. Here, the reset signal may contain a noise component. The reset signal containing the noise component can be amplified in the first source follower transistor SF1.

[0044] During the reset signal sampling operation, the sampling transistor SAM can be turned on, and the first capacitor C1 and the second capacitor C2 can sample the reset signal. When the reset signal sampling operation begins, the first capacitor C1 and the second capacitor C2 can be pre-charged to remove their previously sampled voltages, allowing the first source follower transistor SF1 to sample the new voltage. This pre-charging operation can be performed using the pre-charge transistor PC. During the reset signal sampling operation, the calibration transistor CAL can be turned off. After the reset signal sampling operation, the transfer transistor TX can be turned on again, and the image signal detected at the charge detection node FD can be free of noise.

[0045] During image signal sampling, the sampling transistor SAM can be turned on, and the first capacitor C1 and the second capacitor C2 can sample the image signal. Here, the voltage of the first capacitor C1 can have a value proportional to the amount of charge transferred by the transfer transistor TX. Therefore, the voltage value in the first capacitor C1 can be a new voltage value different from the voltage value of the previous reset signal. During image signal sampling, the second node n2 of the second capacitor C2 can be floated, and the amount of charge in the second capacitor C2 can be maintained at the amount of charge in the previous reset signal sampling operation. Here, the voltage of the second node n2 of the second capacitor C2 can be reduced to the voltage of the first node n1 of the second capacitor C2, instead of the calibration voltage (e.g., Vpix).

[0046] During the reset signal sampling operation, the second node n2 of the second capacitor C2 can be continuously calibrated according to the calibration voltage (e.g., Vpix), and therefore the second node n2 of the second capacitor C2 may not contain noise components. Thus, the pixel signal without noise components can be transmitted to the analog-to-digital converter.

[0047] In the image signal sampling operation, the second capacitor C2 can be charged with a voltage that corresponds to the difference between the voltage charged in the reset signal sampling operation (e.g., the reset signal) and the image signal generated from the unit pixel P.

[0048] A specific noise level and an image signal level can be double-sampled in each unit pixel P within a unit pixel P, and a pixel signal corresponding to the difference between the noise level and the image signal level can be output from each unit pixel P within a unit pixel P. In other words, each unit pixel P within a unit pixel P can generate a voltage proportional to the difference between the potential of the charge detection node FD in the reset state and the potential of the charge detection node FD formed by the photocharge generated by the image signal.

[0049] according to Figure 3B In the embodiments illustrated, a unit pixel P may include a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2, as well as a first transfer transistor TX1 and a second transfer transistor TX2. The first transfer transistor TX1 and the second transfer transistor TX2 may share a charge detection node FD. The first transfer transistor TX1 and the second transfer transistor TX2 may be independently controlled by a charge transfer signal. Therefore, in some embodiments, the plurality of MOS transistors described above may include the first transfer transistor TX1 and the second transfer transistor TX2, a reset transistor RX, a first source follower transistor SF1, a precharge transistor PC, a sampling transistor SAM, a calibration transistor CAL, a second source follower transistor SF2, and a selection transistor SEL.

[0050] according to Figure 3CIn the embodiments illustrated, a unit pixel P may include a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a third photoelectric conversion element PD3, and a fourth photoelectric conversion element PD4, as well as a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, and a fourth transfer transistor TX4. The first transfer transistors TX1 to the fourth transfer transistors TX4 may share a charge detection node FD. The first transfer transistors TX1 to the fourth transfer transistors TX4 may be independently controlled by a charge transfer signal. Therefore, in some embodiments, the plurality of MOS transistors described above may include the first transfer transistors TX1 to the fourth transfer transistors TX4, a reset transistor RX, a first source follower transistor SF1, a precharge transistor PC, a sampling transistor SAM, a calibration transistor CAL, a second source follower transistor SF2, and a selection transistor SEL.

[0051] Figure 4A , Figure 4B and Figure 4C This is a circuit diagram illustrating a capacitor disposed in a unit pixel according to some embodiments.

[0052] Reference Figure 4A Each of the first capacitor C1 and the second capacitor C2 may include a first sub-capacitor C a and the second sub-capacitor C b First sub-capacitor C a and the second sub-capacitor C b Each of these may include a first electrode and a second electrode. Bottom voltage V b It can be applied together to the first sub-capacitor C a and the second sub-capacitor C b The first electrode. Top voltage V t It can be applied together to the first sub-capacitor C a and the second sub-capacitor C b The second electrode. In other words, the first sub-capacitor C a With the second sub-capacitor C b They can be connected to each other in parallel, thus increasing the capacitance of each of the first capacitor C1 and the second capacitor C2.

[0053] Reference Figure 4B Each of the first capacitor C1 and the second capacitor C2 may include a first sub-capacitor C a Second sub-capacitor C b and the third sub-capacitor C c First sub-capacitor C a Second sub-capacitor C b and the third sub-capacitor C cEach of these may include a first electrode and a second electrode. Bottom voltage V b It can be applied together to the first sub-capacitor C a Second sub-capacitor C b and the third sub-capacitor C c The first electrode, and the top voltage V t It can be applied together to the first sub-capacitor C a Second sub-capacitor C b and the third sub-capacitor C c The second electrode. In other words, the first sub-capacitor C a Second sub-capacitor C b and the third sub-capacitor C c They can be connected in parallel to each other, and therefore the capacitance of each of the first capacitor C1 and the second capacitor C2 is comparable. Figure 4A The capacitance of each of the first capacitor C1 and the second capacitor C2 in the configuration shown is increased significantly.

[0054] Reference Figure 4C Each of the first capacitor C1 and the second capacitor C2 may include a first sub-capacitor C a Second sub-capacitor C b Third sub-capacitor C c and the fourth sub-capacitor C d First sub-capacitor C a Second sub-capacitor C b Third sub-capacitor C c and the fourth sub-capacitor C d Each of these may include a first electrode and a second electrode. Bottom voltage V b It can be applied together to the first sub-capacitor C a Second sub-capacitor C b Third sub-capacitor C c and the fourth sub-capacitor C d The first electrode, and the top voltage V t It can be applied together to the first sub-capacitor C a Second sub-capacitor C b Third sub-capacitor C c and the fourth sub-capacitor C d The second electrode. In other words, the first sub-capacitor C a Second sub-capacitor C b Third sub-capacitor C c and the fourth sub-capacitor C d They can be connected in parallel. Therefore, the capacitance of each of the first capacitor C1 and the second capacitor C2 is comparable. Figure 4BThe capacitance of each of the first capacitor C1 and the second capacitor C2 in the configuration shown is increased significantly. According to some embodiments, the capacitance of each of the first capacitor C1 and the second capacitor C2 may be increased proportionally to the number of sub-capacitors constituting each of the first capacitor C1 and the second capacitor C2 and connected to each other in parallel.

[0055] Figure 5 This is a schematic plan view illustrating an image sensor according to some embodiments. Figure 6A and Figure 6B They are along Figure 5 The images taken along lines I-I' and II-II' show cross-sectional views of an image sensor according to some embodiments.

[0056] Reference Figure 5 , Figure 6A and Figure 6B An image sensor according to some embodiments may include a photoelectric conversion layer 100, an integrated circuit layer 200, a charge storage layer 300, an interconnect layer 400, and a light transmission layer 500. When viewed in a top view, the photoelectric conversion layer 100 may be disposed between the integrated circuit layer 200 and the light transmission layer 500. The charge storage layer 300 may be disposed between the interconnect layer 400 and the integrated circuit layer 200.

[0057] The photoelectric conversion layer 100 may include a semiconductor substrate 101, a pixel separation structure 103 defining a pixel region PR, and a photoelectric conversion region 111 disposed in the semiconductor substrate 101. An integrated circuit layer 200 may be disposed on a first surface 101a of the semiconductor substrate 101. The integrated circuit layer 200 may include a readout circuit and a sampling circuit electrically connected to the photoelectric conversion region 111.

[0058] Integrated circuit layer 200 may include the above references Figures 3A to 3C The described transistors are the reset transistor RX, the first source follower transistor SF1 and the second source follower transistor SF2, the sampling transistor SAM, the precharge transistor PC, the calibration transistor CAL, and the selection transistor SEL.

[0059] The charge storage layer 300 may be disposed on the integrated circuit layer 200 and may include a first capacitor C1 and a second capacitor C2 in each pixel region PR. The first capacitor C1 and the second capacitor C2 may be connected to the readout circuit and the sampling circuit of the integrated circuit layer 200, as shown in the figure. Figure 3AAs described above, in the charge storage layer 300, each of the first capacitor C1 and the second capacitor C2 may include a lower capacitor structure LC1 or LC2 located between the lower pad electrode 222a or 222b and the intermediate pad electrode 237, and an upper capacitor structure UC1 or UC2 located between the intermediate pad electrode 237 and the upper pad electrode 247a or 247b. That is, for example, the first capacitor C1 may include a lower capacitor structure LC1 located between the lower pad electrode 222a and the intermediate pad electrode 237, and an upper capacitor structure UC1 located between the intermediate pad electrode 237 and the upper pad electrode 247a.

[0060] Interconnect layer 400 may be disposed on charge storage layer 300 and may include interconnect lines 351, 361 and 371, which are connected to transistors of integrated circuit layer 200 and first capacitor C1 and second capacitor C2 of charge storage layer 300.

[0061] The light-transmitting layer 500 may be disposed on the second surface 101b of the semiconductor substrate 101. The light-transmitting layer 500 may include a planarization insulating layer 510, a light-blocking pattern 515, a filter layer 520, and a microlens ML.

[0062] More specifically, the semiconductor substrate 101 may have a first surface (or front surface) 101a and a second surface (or rear surface) 101b opposite to each other. The semiconductor substrate 101 may be a bulk silicon substrate having a first conductivity type (e.g., P-type).

[0063] Pixel separator structure 103 may be disposed in semiconductor substrate 101 and may define a plurality of pixel regions PR arranged in a matrix along a first direction D1 and a second direction D2. When viewed in a plan view, pixel separator structure 103 may surround each pixel region PR. In detail, pixel separator structure 103 may include a first portion extending parallel to each other in the first direction D1, and a second portion extending parallel to each other in the second direction D2 and intersecting with the first portion.

[0064] The pixel separator structure 103 may be formed of an insulating material having a lower refractive index than the semiconductor substrate 101 (e.g., silicon) and may include one or more insulating layers. The pixel separator structure 103 may penetrate the semiconductor substrate 101. In other words, the vertical thickness of the pixel separator structure 103 may be substantially equal to the vertical thickness of the semiconductor substrate 101. Alternatively, the vertical thickness of the pixel separator structure 103 may be less than the vertical thickness of the semiconductor substrate 101.

[0065] The isolation structure 105 can penetrate the semiconductor substrate 101 of each pixel region PR and can define a light-receiving region R1 and a light-blocking region R2. In other words, each pixel region PR can include a light-receiving region R1 and a light-blocking region R2. The isolation structure 105 can extend in a first direction D1 or a second direction D2.

[0066] The isolation structure 105 may have a substantially the same structure as the pixel separation structure 103. Like the pixel separation structure 103, the isolation structure 105 may be formed of an insulating material having a refractive index lower than that of the semiconductor substrate 101 (e.g., silicon) and may include one or more insulating layers.

[0067] A photoelectric conversion region 111 can be disposed in the light receiving region R1 of each pixel region PR. The photoelectric conversion region 111 can be formed by implanting dopant ions of a second conductivity type into the semiconductor substrate 101. The second conductivity type can be opposite to the first conductivity type of the semiconductor substrate 101. A photodiode can be formed by junction of a semiconductor substrate 101 having a first conductivity type and a photoelectric conversion region 111 having a second conductivity type. Externally incident light can be converted into an electrical signal in the photoelectric conversion region 111.

[0068] A device isolation layer 107 may be disposed on the first surface 101a adjacent to the semiconductor substrate 101. The device isolation layer 107 may define the active region.

[0069] Reference Figure 3A The transfer transistor TX, reset transistor RX, and first source follower transistor SF1 described herein can be disposed on the first surface 101a of the semiconductor substrate 101 of the light receiving region R1. (Refer to...) Figure 3A The sampling transistor SAM, precharge transistor PC, calibration transistor CAL, selection transistor SEL, and second source follower transistor SF2 described herein can be disposed on the first surface 101a of the semiconductor substrate 101 of the light blocking region R2.

[0070] In each pixel region PR, a reference may be provided on the first surface 101a of the semiconductor substrate 101. Figures 3A to 3C The transfer gate electrode TG and gate electrode GE of the transistor are described.

[0071] A portion of the transfer gate electrode TG may be disposed in the semiconductor substrate 101, and a gate insulating layer may be disposed between the transfer gate electrode TG and the semiconductor substrate 101.

[0072] A floating diffusion region FD may be provided on one side of the transfer gate electrode TG in the semiconductor substrate 101. In addition to the floating diffusion region FD, a reference region may also be provided in the semiconductor substrate 101. Figures 3A to 3C The source / drain doped region of the transistor is described as 101sd.

[0073] The floating diffusion region FD and the source / drain doped region 101sd can be formed by ion implantation of a dopant with a conductivity type opposite to that of the semiconductor substrate 101. For example, the floating diffusion region FD and the source / drain doped region 101sd can be N-type doped regions.

[0074] The first interlayer insulating layer 210 may cover the first surface 101a of the semiconductor substrate 101 and the transistor. A first interconnect 211 may be disposed on the first interlayer insulating layer 210. The first interconnect 211 may be electrically connected to the transistor through a first contact plug CP1.

[0075] A second interlayer insulating layer 220 may be disposed on the first interlayer insulating layer 210, and the second interlayer insulating layer 220 may cover the first interconnect 211. For example, each of the first interlayer insulating layer 210 and the second interlayer insulating layer 220 may contain at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0076] A second interconnect 221, a first lower pad electrode 222a, and a second lower pad electrode 222b may be disposed on the second interlayer insulating layer 220. The second interconnect 221 may be selectively connected to some of the first interconnects 211 via second contact plugs CP2. The second lower pad electrode 222b may be connected to at least one of the first interconnects 211 via one of the second contact plugs CP2. The second lower pad electrode 222b may be electrically connected to the gate electrode of the second source follower transistor and the source / drain doped region of the calibration transistor via first contact plugs CP1 and CP2 and the first interconnect 211.

[0077] The first lower pad electrode 222a and the second lower pad electrode 222b can be spaced apart from each other in each pixel area PR (see [reference]). Figure 6B The first lower pad electrode 222a and the second lower pad electrode 222b may have a plate shape. When viewed in a plan view, the first lower pad electrode 222a and the second lower pad electrode 222b may overlap with the photoelectric conversion region 111. The plate-shaped first lower pad electrode 222a and the second lower pad electrode 222b may reflect light provided through the semiconductor substrate 101 toward the photoelectric conversion region 111.

[0078] The second interconnect 221 and the first lower pad electrode 222a and the second lower pad electrode 222b may contain a first metallic material, such as a metal (e.g., tungsten, titanium and / or tantalum) and / or a conductive metal nitride (e.g., titanium nitride, tantalum nitride and / or tungsten nitride).

[0079] A lower molded insulating layer 230 may be provided on the second interlayer insulating layer 220. The lower molded insulating layer 230 may cover the second interconnect 221 and the first lower pad electrode 222a and the second lower pad electrode 222b.

[0080] The lower molded insulating layer 230 may have multiple openings exposing the first lower pad electrode 222a and the second lower pad electrode 222b. The lower molded insulating layer 230 may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0081] A first lower capacitor structure LC1 and a second lower capacitor structure LC2 may be provided in the lower molded insulating layer 230 (see...). Figure 6B The first lower capacitor structure LC1 may include a first lower storage electrode 231a, a lower dielectric layer pattern 233, and a lower plate electrode 235. The second lower capacitor structure LC2 may include a second lower storage electrode 231b, a lower dielectric layer pattern 233, and a lower plate electrode 235.

[0082] More specifically, the lower storage electrodes 231a and 231b may be disposed in the openings of the lower molded insulating layer 230. In some embodiments, the lower storage electrodes 231a and 231b may include a plurality of first lower storage electrodes 231a disposed on the first lower pad electrode 222a, and a plurality of second lower storage electrodes 231b disposed on the second lower pad electrode 222b.

[0083] The first lower storage electrode 231a may be arranged on the first lower pad electrode 222a in the first direction D1 and the second direction D2, and the first lower storage electrodes 231a adjacent to each other may be arranged offset from each other. In other words, the first lower storage electrode 231a may be arranged in a zigzag or honeycomb pattern (see, for example, Figure 5The adjacent second lower storage electrodes 231b can be arranged offset from each other. The second lower storage electrodes 231b can be arranged on the second lower pad electrodes 222b in a zigzag or honeycomb pattern, similar to the first lower storage electrode 231a. For example, the centers of at least two of the first lower storage electrodes 231a or the second lower storage electrodes 231b can be spaced apart by substantially the same distance. Since the first lower storage electrodes 231a and the second lower storage electrodes 231b are arranged in a zigzag or honeycomb pattern as described above, the diameters of the first lower storage electrode 231a and the second lower storage electrode 231b can be increased, and the integration density of the first lower storage electrodes 231a and the second lower storage electrodes 231b can be improved. In some embodiments, the first lower storage electrodes 231a and the second lower storage electrodes 231b can be arranged in a matrix pattern with equal distances in the first direction D1 and the second direction D2.

[0084] For example, each of the first lower storage electrode 231a and the second lower storage electrode 231b may have a cup shape that conformally covers the inner surface of each of the openings in the lower molded insulating layer 230. More specifically, each of the lower storage electrodes 231a and 231b may have a cylindrical shape having a bottom portion and sidewall portions extending vertically from the edge of the bottom portion to define an empty space. The top surfaces of the lower storage electrodes 231a and 231b may be located at substantially the same level as the top surface of the lower molded insulating layer 230.

[0085] A lower dielectric layer pattern 233 and a lower planar electrode 235 conformally covering each of the first lower storage electrode 231a and the second lower storage electrode 231b may be sequentially stacked on the lower molded insulating layer 230. The lower dielectric layer pattern 233 may have a uniform thickness and conformally cover the inner surface of each of the first lower storage electrode 231a and the second lower storage electrode 231b. The lower planar electrode 235 may be disposed on the lower dielectric layer pattern 233 and may cover each of the first lower storage electrode 231a and the second lower storage electrode 231b. In other words, each of the lower dielectric layer pattern 233 and the lower planar electrode 235 may extend into the lower storage electrodes 231a and 231b in a finger-like arrangement. For example, portions of the lower dielectric layer pattern 223 may extend between adjacent first lower storage electrodes 231a in the first lower storage electrode 231a, and portions of the lower planar electrode 235 may extend between adjacent first lower storage electrodes 231a in the first lower storage electrode 231a.

[0086] The lower planar electrode 235 can uniformly cover the surface of the lower dielectric layer pattern 233. For example, the lower planar electrode 235 can fill the opening in which the first lower storage electrode 231a and the second lower storage electrode 231b and the lower dielectric layer pattern 233 are formed. In another embodiment, the lower planar electrode 235 can define a gap region in the opening of the lower molded insulating layer 230.

[0087] The first lower storage electrode 231a, the second lower storage electrode 231b, and the lower plate electrode 235 may include a refractory metal layer (e.g., cobalt, titanium, nickel, tungsten, and / or molybdenum) and / or a metal nitride layer (e.g., titanium nitride (TiN) layer, titanium-silicon nitride (TiSiN) layer, titanium-aluminum nitride (TiAlN) layer, tantalum nitride (TaN) layer, tantalum-silicon nitride (TaSiN) layer, tantalum-aluminum nitride (TaAlN) layer, and / or tungsten nitride (WN) layer).

[0088] For example, the lower dielectric layer pattern 233 may include a single layer or multiple layers comprising metal oxides (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and / or TiO2) and / or perovskite dielectric materials (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and / or PLZT).

[0089] The intermediate pad electrode 237 may be disposed on the lower plate electrode 235. The intermediate pad electrode 237 may contain a doped semiconductor material or conductive material different from the doped semiconductor material or conductive material of the lower plate electrode 235. For example, the intermediate pad electrode 237 may contain polycrystalline silicon or silicon germanium doped with dopants, and / or metals (e.g., tungsten, copper, aluminum, titanium, and / or tantalum).

[0090] When viewed in a plan view, the intermediate pad electrode 237 may overlap with the first lower pad electrode 222a and the second lower pad electrode 222b. In some embodiments, the thickness of the intermediate pad electrode 237 may be greater than the thickness of the first lower pad electrode 222a and the second lower pad electrode 222b. In some embodiments, the intermediate pad electrode 237 may be in direct contact with the top surface of the lower flat electrode 235 disposed on the top surface of the lower molded insulating layer 230.

[0091] An upper molding insulating layer 240 may be disposed on the lower molding insulating layer 230 and may cover the intermediate pad electrode 237. The upper molding insulating layer 240 may have multiple openings exposing the intermediate pad electrode 237. The upper molding insulating layer 240 may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The thickness of the upper molding insulating layer 240 may be equal to or different from the thickness of the lower molding insulating layer 230.

[0092] A first upper capacitor structure UC1 and a second upper capacitor structure UC2 may be provided in the upper molded insulating layer 240 (see...). Figure 6B The first upper capacitor structure UC1 may include a first upper storage electrode 241a, a first upper dielectric layer pattern 243a, and a first upper planar electrode 245a. The second upper capacitor structure UC2 may include a second upper storage electrode 241b, a second upper dielectric layer pattern 243b, and a second upper planar electrode 245b.

[0093] More specifically, the upper storage electrodes 241a and 241b may be disposed in the openings of the upper molded insulating layer 240. In some embodiments, the upper storage electrodes 241a and 241b may include a first upper storage electrode 241a disposed on the first lower storage electrode 231a and a second upper storage electrode 241b disposed on the second lower storage electrode 231b.

[0094] The first upper storage electrode 241a and the second upper storage electrode 241b can be electrically connected to the lower plate electrode 235 via the intermediate pad electrode 237. The first upper storage electrode 241a and the second upper storage electrode 241b can be arranged in a zigzag or honeycomb pattern, similar to the first lower storage electrode 231a and the second lower storage electrode 231b (see, for example,...). Figure 5Additionally, each of the first upper storage electrode 241a and the second upper storage electrode 241b may have a cup-shaped or cylindrical shape, conformally covering the inner surface of each of the openings in the upper molded insulating layer 240, just like the first lower storage electrode 231a and the second lower storage electrode 231b. The top surfaces of the first upper storage electrode 241a and the second upper storage electrode 241b may be located at substantially the same level as the top surface of the upper molded insulating layer 240. In some embodiments, the first upper storage electrode 241a and the second upper storage electrode 241b may comprise the same conductive material as the first lower storage electrode 231a and the second lower storage electrode 231b.

[0095] A first upper dielectric layer pattern 243a and a first upper planar electrode 245a conformally covering a plurality of first upper storage electrodes 241a may be sequentially stacked on an upper molded insulating layer 240. In other words, each of the first upper dielectric layer pattern 243a and the first upper planar electrode 245a may extend into the first upper storage electrode 241a in a finger-like arrangement. For example, portions of the first upper dielectric layer pattern 243a may extend between adjacent first upper storage electrodes 241a, and portions of the first upper planar electrode 245a may extend between adjacent first upper storage electrodes 241a. A second upper dielectric layer pattern 243b and a second upper planar electrode 245b conformally covering a plurality of second upper storage electrodes 241b may be sequentially stacked on an upper molded insulating layer 240. In other words, each of the second upper dielectric layer pattern 243b and the second upper planar electrode 245b can extend into the second upper storage electrode 241b in a finger-like arrangement. For example, portions of the second upper dielectric layer pattern 243b can extend between adjacent second upper storage electrodes 241b, and portions of the second upper planar electrode 245b can extend between adjacent second upper storage electrodes 241b.

[0096] The first upper dielectric layer pattern 243a and the second upper dielectric layer pattern 243b may have a uniform thickness and may respectively cover the inner surface of the first upper memory electrode 241a and the inner surface of the second upper memory electrode 241b. The first upper planar electrode 245a and the second upper planar electrode 245b may be respectively disposed on the first upper dielectric layer pattern 243a and the second upper dielectric layer pattern 243b, and may respectively cover the first upper memory electrode 241a and the second upper memory electrode 241b. The first upper planar electrode 245a and the second upper planar electrode 245b may be spaced apart from each other, just like the first lower pad electrode 222a and the second lower pad electrode 222b.

[0097] In some embodiments, the first upper dielectric layer pattern 243a and the second upper dielectric layer pattern 243b may contain the same dielectric material as the lower dielectric layer pattern 233. In other embodiments, the first upper dielectric layer pattern 243a and the second upper dielectric layer pattern 243b may contain a dielectric material different from the dielectric material of the lower dielectric layer pattern 233.

[0098] The first upper plate electrode 245a and the second upper plate electrode 245b can respectively cover the surfaces of the first upper dielectric layer pattern 243a and the second upper dielectric layer pattern 243b, which have uniform thicknesses. The first upper plate electrode 245a and the second upper plate electrode 245b can respectively fill the openings in which the first upper storage electrode 241a and the second upper storage electrode 241b, as well as the first upper dielectric layer pattern 243a and the second upper dielectric layer pattern 243b are formed. In some embodiments, the first upper plate electrode 245a and the second upper plate electrode 245b can contain the same conductive material as the lower plate electrode 235.

[0099] The first upper pad electrode 247a and the second upper pad electrode 247b may be respectively disposed on the first upper plate electrode 245a and the second upper plate electrode 245b. In some embodiments, the first upper pad electrode 247a and the second upper pad electrode 247b may contain a doped semiconductor material or conductive material different from the doped semiconductor material or conductive material of the first upper plate electrode 245a and the second upper plate electrode 245b. For example, the first upper pad electrode 247a and the second upper pad electrode 247b may contain polycrystalline silicon or silicon germanium doped with dopants, and / or metals (e.g., tungsten, copper, aluminum, titanium, and / or tantalum).

[0100] When viewed in a plan view, the first upper pad electrode 247a and the second upper pad electrode 247b can overlap with the first lower pad electrode 222a and the second lower pad electrode 222b, respectively (see example). Figure 6B In some embodiments, the thickness of the first upper pad electrode 247a and the thickness of the second upper pad electrode 247b may be greater than the thickness of the first lower pad electrode 222a and the thickness of the second lower pad electrode 222b. A third interlayer insulating layer 310 may be provided on the upper molded insulating layer 240, and the third interlayer insulating layer 310 may cover the first upper pad electrode 247a and the second upper pad electrode 247b.

[0101] The first lower contact plug BCP1 can penetrate the lower molded insulating layer 230 and the upper molded insulating layer 240 to connect to the first lower pad electrode 222a. The second lower contact plug BCP2 can penetrate the lower molded insulating layer 230 and the upper molded insulating layer 240 to connect to the second lower pad electrode 222b.

[0102] The first upper pad electrode 247a can be connected to the first lower contact plug BCP1, and the second upper pad electrode 247b can be connected to the second lower contact plug BCP2. In other words, the first lower storage electrode 231a can be electrically connected to the first upper plate electrode 245a, and the second lower storage electrode 231b can be electrically connected to the second upper plate electrode 245b.

[0103] In some embodiments, the first lower pad electrode 222a, the middle pad electrode 237, the first upper pad electrode 247a, the first lower capacitor structure LC1, and the first upper capacitor structure UC1 may constitute a reference. Figure 3A The first capacitor C1 is described. The second lower capacitor structure LC2 located between the second lower pad electrode 222b and the middle pad electrode 237, and the second upper capacitor structure UC2 located between the middle pad electrode 237 and the second upper pad electrode 247b, can constitute a reference. Figure 3A The second capacitor C2 is described. Here, the intermediate pad electrode 237 can be connected to both the first capacitor C1 and the second capacitor C2.

[0104] The upper contact plug TCP can penetrate the third interlayer insulation layer 310 and the upper molded insulation layer 240 to connect to the intermediate pad electrode 237. The third contact plug CP3 can penetrate the third interlayer insulation layer 310, the upper molded insulation layer 230, and the lower molded insulation layer 240 to connect to at least one of the second interconnects 221.

[0105] In some embodiments, the upper contact plug TCP, the first lower contact plug BCP1, the second lower contact plug BCP2, and the third contact plug CP3 may comprise the same metallic material. In some embodiments, the upper contact plug TCP, the first lower contact plug BCP1, the second lower contact plug BCP2, and the third contact plug CP3 may comprise the same metallic material as the first interconnect 211 and the second interconnect 221 (i.e., the first metallic material). For example, the first metallic material may comprise a metal (e.g., tungsten, titanium, and / or tantalum) and / or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride).

[0106] A third interconnect 351 may be disposed on a third interlayer insulating layer 310. At least one of the third interconnects 351 may be electrically connected to at least one of the second interconnects 221 via a third contact plug CP3. Another of the third interconnects 351 may be connected to a first upper pad electrode 247a via a fourth contact plug CP4. At least one of the third interconnects 351 may have a linear shape extending in one direction and may be connected to an intermediate pad electrode 237 via an upper contact plug TCP.

[0107] In some embodiments, the third interconnect 351 and the fourth interconnect 361, disposed at a height level above the top surface of the third interlayer insulating layer 310, may contain a second metal material different from the first metal material of the first interconnect 211 and the second interconnect 221 disposed below the top surface of the third interlayer insulating layer 310. The resistivity of the second metal material may be less than that of the first metal material. For example, the second metal material may include copper or a copper alloy.

[0108] Some of the third interconnects 351 may intersect with multiple pixel regions PR and may include power lines to which power supply voltage and capacitor voltage are applied. Since the third interconnects 351 are formed of a second metallic material with low resistivity, signal delay can be reduced. A fourth interlayer insulating layer 320 may cover the third interlayer insulating layer 310 and the third interconnects 351. A fourth interconnect 361 may be disposed on the fourth interlayer insulating layer 320, and a fifth interlayer insulating layer 330 covering the fourth interconnect 361 may be disposed on the fourth interlayer insulating layer 320. A fifth interconnect 371 may be disposed on the fifth interlayer insulating layer 330. In some embodiments, the fifth interconnect 371 may have a plate shape covering each pixel region PR. A sixth interlayer insulating layer 340 covering the fifth interconnect 371 may be disposed on the fifth interlayer insulating layer 330.

[0109] A planarization insulating layer 510 may cover the second surface 101b of the semiconductor substrate 101. The planarization insulating layer 510 may be formed of an insulating material having a refractive index different from that of the semiconductor substrate 101. A light-blocking pattern 515 may be disposed on the planarization insulating layer 510 in the light-blocking region R2. The light-blocking pattern 515 may reflect and block light incident on the second surface 101b of the semiconductor substrate 101. In other words, light incident on the light-blocking region R2 of each pixel region PR in the pixel region PR may be blocked by the light-blocking pattern 515, and therefore the light-blocking pattern 515 may prevent the generation of photocharge in the semiconductor substrate 101 of the light-blocking region R2 and may also prevent light from incident on the sampling circuit formed on the first surface 101a of the semiconductor substrate 101 in the light-blocking region R2. For example, the light-blocking pattern 515 may be formed of a metallic material such as tungsten or aluminum. A buffer insulating layer 517 covering the light-blocking pattern 515 may be disposed on the planarization insulating layer 510 of the light-blocking region R2.

[0110] A filter layer 520 may be disposed on the second surface 101b of the semiconductor substrate 101 in the light receiving region R1. The filter layer 520 may transmit light of a specific wavelength band from the incident light provided from the outside. The filter layer 520 may include a color filter and / or an infrared filter.

[0111] Microlenses ML, each corresponding to the photoelectric conversion region 111, can be disposed on the filter layer 520. The microlenses ML can be arranged in two dimensions along intersecting first directions D1 and second directions D2. Each of the microlenses ML can have a convex shape and a specific radius of curvature.

[0112] In some embodiments, the photoelectric conversion layer 100, integrated circuit layer 200, charge storage layer 300, and interconnect layer 400 may together form the upper layer of an image sensor, and the image sensor may further include a lower layer, which includes a substrate containing multiple logic gates and one or more additional layers, wherein the upper layer and the lower layer are combined. Alternatively, in other embodiments, the photoelectric conversion layer 100, integrated circuit layer 200, charge storage layer 300, and interconnect layer 400 may together form the lower layer of an image sensor, and the image sensor may further include an upper layer, which includes a substrate containing multiple logic gates and one or more additional layers, wherein the upper layer and the lower layer are combined. That is, Figure 5 , Figure 6A and Figure 6B The stacked capacitors shown may be included in the lower layer of the image sensor or in the upper layer of the image sensor.

[0113] Figures 7 to 11 This is a cross-sectional view illustrating an image sensor according to some embodiments. In the following text, for ease of explanation and illustrative purposes, [the image sensor is referred to as an image sensor]. Figure 6A and Figure 6B The same components shown in the above embodiments will be represented by the same reference numbers or indicators, and their descriptions will be omitted.

[0114] Reference Figure 7 The lower pad electrode 222, the first intermediate pad electrode 237, the second intermediate pad electrode 247, and the upper pad electrode 257 can be vertically stacked on the semiconductor substrate 101 of each pixel region PR. A lower capacitor structure LC can be provided between the lower pad electrode 222 and the first intermediate pad electrode 237, and an intermediate capacitor structure MC can be provided between the first intermediate pad electrode 237 and the second intermediate pad electrode 247. In addition, an upper capacitor structure UC can be provided between the second intermediate pad electrode 247 and the upper pad electrode 257.

[0115] Each of the lower capacitor structure LC, the intermediate capacitor structure MC, and the upper capacitor structure UC may include multiple storage electrodes 231, 241, or 251, dielectric layer patterns 233, 243, or 253, and planar electrodes 235, 245, or 255. The multiple storage electrodes 251, dielectric layer patterns 253, and planar electrodes 255 may each have a configuration similar to that of the multiple storage electrodes 231 or 241, dielectric layer patterns 233 or 243, and planar electrodes 235 or 245. The lower pad electrode 222, the first intermediate pad electrode 237, the second intermediate pad electrode 247, the upper pad electrode 257, and the lower capacitor structure LC, the intermediate capacitor structure MC, and the upper capacitor structure UC may form a reference. Figure 3A The first capacitor C1 and the second capacitor C2 are described.

[0116] In some embodiments, the lower contact plug BCP can electrically connect the lower pad electrode 222 to the second intermediate pad electrode 247, and the upper contact plug TCP can electrically connect the first intermediate pad electrode 237 to the upper pad electrode 257. In other words, the storage electrode 231 of the lower capacitor structure LC, the planar electrode 245 of the intermediate capacitor structure MC, and the storage electrode 251 of the upper capacitor structure UC can be electrically connected to each other. Additionally, the planar electrode 235 of the lower capacitor structure LC, the storage electrode 241 of the intermediate capacitor structure MC, and the planar electrode 255 of the upper capacitor structure UC can be electrically connected to each other.

[0117] exist Figure 7In the illustrated embodiment, three capacitor structures LC, MC, and UC are stacked. However, in some embodiments, the number of stacked capacitor structures may be four or more, and pad electrodes may be provided between the capacitor structures. In embodiments where four or more stacked capacitor structures are provided, an odd number of pad electrodes may be electrically connected to each other, and an even number of pad electrodes may be electrically connected to each other. As described above, the number of stacked capacitor structures can be increased, and the capacitor structures can be electrically connected to each other in parallel, thus increasing... Figure 3A The capacitance of the first capacitor C1 and / or the second capacitor C2.

[0118] Reference Figure 8 Each of the lower capacitor structure LC1 and the upper capacitor structure UC1 may include a storage electrode 231a or 241a, a dielectric layer pattern 233 or 243a, and a planar electrode 235 or 245a.

[0119] The width W1 of the lower storage electrode 231a of the lower capacitor structure LC1 may differ from the width W2 of the upper storage electrode 241a of the upper capacitor structure UC1. For example, the width W1 of the lower storage electrode 231a may be smaller than the width W2 of the upper storage electrode 241a. In some embodiments, additionally or alternatively, the distance between adjacent lower storage electrodes 231a may differ from the distance between adjacent upper storage electrodes 241a. In some embodiments, alternatively or additionally, the height (in direction D3) of the lower storage electrode 231a may differ from the height of the upper storage electrode 241a.

[0120] Reference Figure 9 Each of the lower capacitor structure LC1 and the upper capacitor structure UC1 may include a storage electrode 231a or 241a, a dielectric layer pattern 233 or 243a, and a planar electrode 235 or 245a.

[0121] The lower storage electrode 231a and the upper storage electrode 241a may have a columnar shape. For example, in some embodiments, the width of each of the storage electrodes 231a may be greater than the width of each of the portions of the planar electrodes 235 extending between the storage electrodes 231a, and the width of each of the storage electrodes 241a may be greater than the width of each of the portions of the planar electrodes 245a extending between the storage electrodes 241a. In some embodiments, the width and / or height of the lower storage electrode 231a and the upper storage electrode 241a may be equal to or different from each other. As described above, the columnar lower storage electrode 231a and the upper storage electrode 241a may be arranged in a zigzag or honeycomb pattern.

[0122] The lower dielectric layer pattern 233 and the upper dielectric layer pattern 243a may have uniform thickness and may cover the outer surfaces of the lower memory electrode 231a and the upper memory electrode 241a. The lower dielectric layer pattern 233 may cover the lower pad electrode 222a between the lower memory electrodes 231a. The upper dielectric layer pattern 243a may cover the intermediate pad electrode 237 between the upper memory electrodes 241a.

[0123] The lower plate electrode 235 can be disposed on the lower dielectric layer pattern 233 to cover multiple lower storage electrodes 231a and fill the space between the lower storage electrodes 231a. The upper plate electrode 245a can be disposed on the upper dielectric layer pattern 243a to cover multiple upper storage electrodes 241a and fill the space between the upper storage electrodes 241a.

[0124] exist Figure 9 In this embodiment, both the lower storage electrode 231a and the upper storage electrode 241a have a columnar shape. However, the embodiments are not limited to this. In some embodiments, one of the lower storage electrode 231a and the upper storage electrode 241a may have a columnar shape, and the other of the lower storage electrode 231a and the upper storage electrode 241a may have a reference shape. Figure 6A The cylindrical shape described.

[0125] Reference Figure 10 The image sensor may further include a lower barrier insulating layer BLK1 located between the integrated circuit layer 200 and the charge storage layer 300, and an upper barrier insulating layer BLK2 located between the charge storage layer 300 and the interconnect layer 400. For example, the lower barrier insulating layer BLK1 and the upper barrier insulating layer BLK2 may comprise insulating materials such as SiN, SiON, SiC, SiCN, SiOCH, SiOC, and / or SiOF. In some embodiments, the lower barrier insulating layer BLK1 and the upper barrier insulating layer BLK2 may have the same insulating material. In other embodiments, the material of the lower barrier insulating layer BLK1 may be different from the material of the upper barrier insulating layer BLK2.

[0126] The lower barrier insulating layer BLK1 and the upper barrier insulating layer BLK2 prevent hydrogen or deuterium from permeating into the lower capacitor structure LC1 and the upper capacitor structure UC1 during the hydrogen (H2) or deuterium annealing process performed during the manufacture of the image sensor. Therefore, interface degradation between the dielectric layer pattern 233 or 243a in each of the lower capacitor structure LC1 and the upper capacitor structure UC1 and the storage electrode 231a or 241a (or the planar electrode 235 or 245a) can be prevented.

[0127] Reference Figure 11An etch stop layer (ESL) may be provided on the top surface of the intermediate pad electrode 237. The etch stop layer (ESL) may include an insulating layer that has etch selectivity for the upper molded insulating layer 240. When the upper molded insulating layer 240 is formed of silicon oxide, the etch stop layer (ESL) may include silicon nitride or silicon oxynitride.

[0128] In some embodiments, the upper storage electrode 241a of the upper capacitor structure UC1 can penetrate the etch stop layer ESL to connect to the intermediate pad electrode 237. In this configuration, the lower portion of the upper storage electrode 241a may be located within the intermediate pad electrode 237. In other words, the bottom surface of the upper storage electrode 241a may be lower than the top surface of the intermediate pad electrode 237.

[0129] Reference Figure 12 According to some embodiments, the image sensor may include a lower electronics EC1 and an upper electronics EC2.

[0130] The lower electronic device EC1 may include a photoelectric conversion layer 100, an integrated circuit layer 200, a first charge storage layer 300-1, a lower interconnect layer 400-1, and a light transmission layer 500. The photoelectric conversion layer 100 and integrated circuit layer 200 of the lower electronic device EC1 may be related to the above-mentioned... Figure 6A and Figure 6B The photoelectric conversion layer 100 and the integrated circuit layer 200 described herein are essentially the same, and therefore their description will be omitted.

[0131] The first charge storage layer 300-1 may include a first molding layer 230, a first interlayer insulating layer 310 stacked above the first molding layer 230, and a lower capacitor structure LC located between the first pad electrode 222 and the second pad electrode 237. A first lower contact plug BCPa may be connected to the first pad electrode 222, and a first upper contact plug TCPa may be connected to the second pad electrode 237. In this embodiment, the first pad electrode 222, the second pad electrode 237, and the lower capacitor structure LC may be compared with a reference. Figure 6A and Figure 6B The lower pad electrode, middle pad electrode, and lower capacitor structures described are essentially the same, and their descriptions will be omitted.

[0132] The lower interconnect layer 400-1 may include first interlayer insulating layers 320 and 330 and a lower conductor LCL located in the first interlayer insulating layers 320 and 330. In addition, the lower interconnect layer 400-1 may include a lower conductive pad PAD1 electrically connected to the lower conductor LCL.

[0133] The upper electronic device EC2 may include a semiconductor device layer 100-2, a second charge storage layer 300-2, and an upper interconnect layer 400-2.

[0134] Semiconductor device layer 100-2 may include an upper semiconductor substrate 601, a transistor TR formed on the upper semiconductor substrate 601, and a wire 711 connected to the transistor TR. Semiconductor device layer 100-2 may be electrically connected to the integrated circuit layer 100 of the lower electronic device EC1. Semiconductor device layer 100-2 may include, for example, logic elements for processing data. In another example, semiconductor device layer 100-2 may include memory elements for storing data. Lower interlayer insulating layers 710 and 720 covering the transistor TR may be stacked on the upper semiconductor substrate 601 (i.e., between the upper semiconductor substrate 601 and the second charge storage layer 300-2).

[0135] The second charge storage layer 300-2 may include a second molding layer 730, a second interlayer insulating layer 810 stacked below the second molding layer 730, and an upper capacitor structure UC located between the third pad electrode 722 and the fourth pad electrode 737. A second lower contact plug BCPb may be connected to the third pad electrode 722, and a second upper contact plug TCPb may be connected to the fourth pad electrode 737. The upper capacitor structure UC may include a storage electrode 731, a dielectric layer pattern 733, and a planar electrode 735, and may be similar to that shown in the reference. Figure 6A The storage electrode 231, dielectric layer pattern 233, and planar electrode 235 are described.

[0136] The upper interconnect layer 400-2 may include second interlayer insulating layers 820 and 830 and upper conductors UCL located in the second interlayer insulating layers 820 and 830. In addition, the upper interconnect layer 400-2 may include upper conductive pads PAD2 electrically connected to the upper conductors UCL.

[0137] The upper conductive pad PAD2 can be configured to correspond to the lower conductive pad PAD1. The size and arrangement of the upper conductive pad PAD2 can be substantially the same as the size and arrangement of the lower conductive pad PAD1. The upper conductive pad PAD2 of the upper electronic device EC2 can be directly connected to the lower conductive pad PAD1 of the lower electronic device EC1. In other words, the lower electronic device EC1 and the upper electronic device EC2 can be bonded to each other by means that the lower conductive pad PAD1 and the upper conductive pad PAD2 are in contact with each other. The lower conductive pad PAD1 and the upper conductive pad PAD2 can contain metals (e.g., copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), or tin (Sn)) and / or any alloy thereof. For example, in some embodiments, the lower electronic device EC1 and the upper electronic device EC2 can be bonded to each other by copper-to-copper bonding.

[0138] In some embodiments, the first pad electrode 222 and the third pad electrode 722 can be electrically connected to each other via a first lower contact plug BCPa and a second lower contact plug BCPb, as well as corresponding lower conductive pads PAD1 and upper conductive pads PAD2. The second pad electrode 237 and the fourth pad electrode 737 can be electrically connected to each other via a first upper contact plug TCPa and a second upper contact plug TCPb, as well as corresponding lower conductive pads PAD1 and upper conductive pads PAD2.

[0139] Figures 13 to 16 This is a cross-sectional view illustrating an image sensor according to some embodiments. In the following text, for ease of explanation and illustrative purposes, [the image sensor is referred to as an image sensor]. Figure 12 In the above embodiments, the same components will be represented by the same reference numbers or indicators, and their descriptions will be omitted.

[0140] Reference Figure 13 The lower interconnect layer 400-1 of the lower electronic device EC1 may include a lower warp control layer WCL1 disposed at the uppermost layer of the lower interconnect layer 400-1, and the upper interconnect layer 400-2 of the upper electronic device EC2 may include an upper warp control layer WCL2 disposed at the lowermost layer of the upper interconnect layer 400-2.

[0141] The lower electronic device EC1 and the upper electronic device EC2 can be bonded to each other by means of contact between the lower warp control layer WCL1 and the upper warp control layer WCL2. Each of the lower warp control layer WCL1 and the upper warp control layer WCL2 can be formed of an insulating material resistant to tensile or compressive forces. For example, the lower warp control layer WCL1 can be formed of a tensile-resistant insulating material, and the upper warp control layer WCL2 can be formed of a compressive-resistant insulating material. In some embodiments, the lower warp control layer WCL1 and the upper warp control layer WCL2 can contain the same material, but can have different thicknesses. The lower warp control layer WCL1 and the upper warp control layer WCL2 can contain, for example, silicon oxide or silicon nitride.

[0142] Reference Figure 14 The shape of the lower storage electrode 231 of the lower capacitor structure LC1 may differ from the shape of the upper storage electrode 731 of the upper capacitor structure UC. For example, the lower storage electrode 231 may be cylindrical, and the upper storage electrode 731 may be columnar, or vice versa.

[0143] Reference Figure 15 The number of lower storage electrodes 231 in the lower capacitor structure LC1 may differ from the number of upper storage electrodes 731 in the upper capacitor structure UC. Therefore, the capacitance of the lower capacitor structure LC1 may differ from the capacitance of the upper capacitor structure UC.

[0144] Reference Figure 16 The first pad electrode 222 of the lower electronic device EC1 can be electrically connected to the third pad electrode 722 of the upper electronic device EC2 via a through-conductive plug (TSV). For example, the through-conductive plug (TSV) can extend vertically from the second surface 101b of the lower semiconductor substrate 101 to the third pad electrode 722 of the upper electronic device EC2. The through-conductive plug (TSV) can penetrate the lower semiconductor substrate 101, the first molding layer 230, and the second molding layer 730, and can directly contact the first pad electrode 222 and the third pad electrode 722. In other words, the through-conductive plug (TSV) can be electrically connected to both the first pad electrode 222 and the third pad electrode 722. The through-conductive plug (TSV) can be connected to the conductive pad 525 disposed on the second surface 101b of the lower semiconductor substrate 101.

[0145] Figure 17 and Figure 18 This is a cross-sectional view showing an image sensor according to some embodiments.

[0146] Reference Figure 17 The photoelectric conversion layer 100 may include a first pixel region PR1 and a second pixel region PR2 defined by the pixel separation structure 103. The first pixel region PR1 and the second pixel region PR2 may be arranged alternately in one direction. Each of the first pixel region PR1 and the second pixel region PR2 may have the same characteristics as described above. Figure 5 , Figure 6A and Figure 6B The pixel regions described are essentially the same structure as PR.

[0147] The first charge storage layer 300-1 and the second charge storage layer 300-2 can be stacked sequentially on the integrated circuit layer 200. An intermediate insulating layer 260 can be disposed between the first charge storage layer 300-1 and the second charge storage layer 300-2.

[0148] The first charge storage layer 300-1 may include a first pad electrode 222, a second pad electrode 237, and a lower capacitor structure LC disposed between the first pad electrode 222 and the second pad electrode 237. In some embodiments, each of the first pad electrode 222 and the second pad electrode 237 may be disposed on the first pixel region PR1 and the second pixel region PR2. In other words, each of the first pad electrode 222 and the second pad electrode 237 may overlap with a portion of the photoelectric conversion region 111 of the first pixel region PR1 and the second pixel region PR2. Each of the lower capacitor structures LC may include a lower storage electrode 231, a lower dielectric layer pattern 233, and a lower planar electrode 235. The lower capacitor structure LC may be electrically connected to the transistor of the first pixel region PR1. For example, the first pad electrode 222 may be electrically connected to the transistor of the first pixel region PR1 through a first lower contact plug BCP1.

[0149] The second charge storage layer 300-2 may include a third pad electrode 262, a fourth pad electrode 247, and an upper capacitor structure UC disposed between the third pad electrode 262 and the fourth pad electrode 247. Each of the upper capacitor structures UC may partially overlap with and adjacent to a lower capacitor structure LC. Each of the upper capacitor structures UC may include an upper storage electrode 241, an upper dielectric layer pattern 243, and an upper planar electrode 245. The upper capacitor structure UC may be electrically connected to a transistor in the second pixel region PR2. For example, the third pad electrode 262 may be electrically connected to the transistor in the second pixel region PR2 via a second lower contact plug BCP2. For example, each of the second lower contact plugs BCP2 may penetrate a lower molded insulating layer 230 located between adjacent lower capacitor structures LC.

[0150] An interconnect layer 400 may be disposed on the second charge storage layer 300-2. The interconnect layer 400 may include interlayer insulating layers 310 to 340 vertically stacked on the upper molded insulating layer 240, and interconnect lines 351, 361 and 371 located between the interlayer insulating layers 310 to 340.

[0151] The first upper contact plug TCP1 can penetrate the interlayer insulation layer 310 and the upper molded insulation layer 240 respectively to connect to the second pad electrode 237. Each of the first upper contact plugs TCP1 can penetrate the upper molded insulation layer 240 located between two adjacent upper capacitor structures UC in the upper capacitor structure UC. The second upper contact plug TCP2 can penetrate the interlayer insulation layer 310 respectively to connect to the fourth pad electrode 247.

[0152] exist Figure 17In the embodiment shown, a first charge storage layer 300-1 and a second charge storage layer 300-2 are stacked. However, the embodiments are not limited to this. In some embodiments, like the first charge storage layer 300-1 and the second charge storage layer 300-2, three or more charge storage layers may be sequentially stacked on the integrated circuit layer 200.

[0153] Reference Figure 18 The photoelectric conversion layer 100 may include a first pixel region PR1 and a second pixel region PR2 defined by the pixel separation structure 103. The first pixel region PR1 and the second pixel region PR2 may be arranged alternately in one direction. Each of the first pixel region PR1 and the second pixel region PR2 may have a reference [missing information]. Figure 5 , Figure 6A and Figure 6B The pixel regions PR are described as having essentially the same structure. However, the area of ​​the first pixel region PR1 may differ from the area of ​​the second pixel region PR2. For example, the width of the first pixel region PR1 in one direction may be smaller than the width of the second pixel region PR2 in one direction, while the height of the first pixel region PR1 is the same as the height of the second pixel region PR2. Alternatively, in some embodiments, the height of the first pixel region PR1 in one direction may be smaller than the height of the second pixel region PR2, while the width of the first pixel region PR1 is the same as the width of the second pixel region PR2. In some embodiments, each of the first pixel regions PR1 may correspond to a high-illumination pixel, and each of the second pixel regions PR2 may correspond to a low-illumination pixel. A first photoelectric conversion region 111a may be provided in the semiconductor substrate 101 of each of the first pixel regions PR1, and a second photoelectric conversion region 111b may be provided in the semiconductor substrate 101 of each of the second pixel regions PR2. Here, the area of ​​the first photoelectric conversion region 111a may be smaller than the area of ​​the second photoelectric conversion region 111b.

[0154] An integrated circuit layer 200 may be disposed on the first surface 101a of the semiconductor substrate 101. The integrated circuit layer 200 may include a first interlayer insulating layer 210 and a second interlayer insulating layer 220, as shown in the figure. Figure 3A The transistor, first contact CP1, first interconnect 211, and second contact CP2 are described. The first contact CP1, first interconnect 211, and second contact CP2 are electrically connected to the transistor.

[0155] The charge storage layer 300 may include a first pixel charge storage component corresponding to a first pixel region PR1 and a second pixel charge storage component corresponding to a second pixel region PR2. Here, the charge storage capacity of the first pixel charge storage component may be greater than the charge storage capacity of the second pixel charge storage component.

[0156] Each of the first pixel charge storage components may include a first lower capacitor structure LC1 located between a first lower pad electrode 222a and an intermediate pad electrode 237a, and an upper capacitor structure UC located between the intermediate pad electrode 237a and a first upper pad electrode 247. Here, the first lower capacitor structure LC1 and the upper capacitor structure UC may be electrically connected to each other in parallel. The first lower capacitor structure LC1 may be disposed in the lower molded insulating layer 230 and may include a first lower storage electrode, a first lower dielectric layer pattern, and a first lower planar electrode. The upper capacitor structure UC may be disposed in the upper molded insulating layer 240 and may include an upper storage electrode 241, an upper dielectric layer pattern 243, and an upper planar electrode 245. Here, the first lower pad electrode 222a and the first upper pad electrode 247 may be electrically connected to each other via a lower contact plug BCP. The first lower pad electrode 222a may be electrically connected to the transistor of the first pixel region PR1 via a second contact plug CP2. The intermediate pad electrode 237a can be electrically connected to at least one of the interconnects in the interconnect layer 400 via the first upper contact plug TCP1.

[0157] Each of the second pixel charge storage components may include a second lower capacitor structure LC2 located between a second lower pad electrode 222b and a second upper pad electrode 237b. The second lower capacitor structure LC2 may include a second lower storage electrode 231, a second lower dielectric layer pattern 233, and a second lower planar electrode 235. The second lower pad electrode 222b may be electrically connected to a transistor in the second pixel region PR2 via a second contact plug CP2. The second upper pad electrode 237b may be electrically connected to at least one of the interconnects in the interconnect layer 400 via a second upper contact plug TCP2.

[0158] According to an embodiment, each of the first capacitor and the second capacitor disposed in each pixel area may include a lower capacitor structure and an upper capacitor structure that can be vertically stacked and connected in parallel to each other. Therefore, the capacitance of the first capacitor and the capacitance of the second capacitor can be increased. Thus, in global shutter operation, charge loss and noise can be reduced, and shutter efficiency can be improved.

[0159] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but merely illustrative. Consequently, the scope of the inventive concept will be determined by the widest interpretation permitted by the foregoing claims and their equivalents, and should not be construed as limited or restricted by the foregoing description.

Claims

1. An image sensor, comprising: The photoelectric conversion layer includes a pixel separation structure, which defines multiple pixel regions, each pixel region including a photoelectric conversion region. An integrated circuit layer is disposed on the photoelectric conversion layer and includes a readout circuit for reading charge from the photoelectric conversion region of the pixel region; A charge storage layer, disposed on the integrated circuit layer and including a stacked capacitor for each of the plurality of pixel regions, the stacked capacitor comprising: First lower pad electrode; Intermediate pad electrode; First upper pad electrode; A contact plug connects the first upper pad electrode to the first lower pad electrode; A first lower capacitor structure, connected between the first lower pad electrode and the intermediate pad electrode, includes a plurality of first lower storage electrodes for storing the charge read from the photoelectric conversion region of the pixel region; and An upper capacitor structure, connected between the intermediate pad electrode and the first upper pad electrode, includes a plurality of upper storage electrodes for storing the charge read from the photoelectric conversion region of the pixel region, the upper capacitor structure being stacked on the first lower capacitor structure to partially overlap the first lower capacitor structure when viewed in a plan view.

2. The image sensor according to claim 1, wherein the first lower capacitor structure has a first storage capacity, and The upper capacitor structure has a second storage capacity that is different from the first storage capacity.

3. The image sensor according to claim 1, wherein the first lower capacitor structure has a first storage capacity, and The upper capacitor structure has a second storage capacity that is the same as the first storage capacity.

4. The image sensor according to claim 1, wherein the first lower storage electrode and the upper storage electrode have a cylindrical shape.

5. The image sensor according to claim 1, further comprising: An insulating layer is disposed on the surface of the intermediate pad electrode that faces the first upper pad electrode. The upper capacitor structure includes an upper molded insulating layer, and the plurality of upper storage electrodes are disposed within the upper molded insulating layer. The insulating layer is an etch stop layer that has etch selectivity for the upper molded insulating layer.

6. The image sensor of claim 5, wherein the upper capacitor structure penetrates the etch stop layer to connect to the intermediate pad electrode.

7. The image sensor of claim 6, wherein the lower portion of the upper storage electrode is located in the intermediate pad electrode such that the bottom surface of the upper storage electrode is lower than the top surface of the intermediate pad electrode.

8. The image sensor of claim 1, wherein the plurality of pixel regions are first pixel regions, and the stacked capacitor is provided to each of the plurality of first pixel regions, and The pixel separation structure further defines a plurality of second pixel regions that are alternately arranged with the plurality of first pixel regions in a first direction, each of the plurality of second pixel regions including a photoelectric conversion region, and The charge storage layer includes a capacitor for each of the plurality of second pixel regions, the capacitor comprising: Second lower pad electrode; Second upper pad electrode; as well as The second lower capacitor structure is connected between the second lower pad electrode and the second upper pad electrode and includes a plurality of second lower storage electrodes for storing the charge read from the photoelectric conversion region of the second pixel region.

9. The image sensor of claim 8, wherein the area of ​​the photoelectric conversion region of each second pixel region in the second pixel region is greater than the area of ​​the photoelectric conversion region of each first pixel region in the first pixel region.

10. The image sensor according to claim 1, further comprising: The upper layer includes a first substrate, a photoelectric conversion layer formed in the first substrate, and an integrated circuit layer and a charge storage layer formed on the first substrate; as well as The lower layer includes a second substrate, the second substrate including a plurality of logic circuits formed on the second substrate. The upper layer is bonded to the lower layer.

11. The image sensor according to claim 1, further comprising: The lower layer includes a first substrate, a photoelectric conversion layer formed in the first substrate, and an integrated circuit layer and a charge storage layer formed on the first substrate; as well as The upper layer includes a second substrate, the second substrate including a plurality of logic circuits formed on the second substrate. The upper layer is bonded to the lower layer.

12. An image sensor, comprising: The photoelectric conversion layer has a pixel separation structure, wherein the pixel separation structure defines the photoelectric conversion region; An integrated circuit layer is disposed on the photoelectric conversion layer and includes a readout circuit for reading charge from the photoelectric conversion region; A first charge storage layer includes a first capacitor structure, the first capacitor structure including a plurality of first storage electrodes for storing the charge read from the photoelectric conversion region; First warp control layer; A second charge storage layer is incorporated into the first charge storage layer. The second charge storage layer includes a second capacitor structure, which includes a plurality of second storage electrodes for storing the charge read from the photoelectric conversion region. The second capacitor structure is stacked on the first capacitor structure to partially overlap with the first capacitor structure when viewed in a plan view. as well as A second warping control layer is formed on the surface of the second charge storage layer opposite to the first charge storage layer.

13. The image sensor of claim 12, wherein the first capacitor structure has a first storage capacity, and The second capacitor structure has a second storage capacity that is different from the first storage capacity.

14. The image sensor of claim 12, wherein the first capacitor structure has a first storage capacity, and The second capacitor structure has the same second storage capacity as the first storage capacity.

15. The image sensor of claim 12, wherein the first warpage control layer is formed of an insulating material that resists either tension or compression, and the second warpage control layer is formed of an insulating material that resists the other of said tension or said compression.

16. The image sensor of claim 12, wherein the second charge storage layer is bonded to the first charge storage layer by copper-to-copper bonding.

17. The image sensor according to claim 16, The first capacitor structure includes: The plurality of first storage electrodes are connected to the first pad electrodes; A first dielectric layer pattern covers the plurality of first storage electrodes; as well as A first plate electrode is connected to a second pad electrode, and portions of the first plate electrode extend between adjacent first memory electrodes. The second capacitor structure includes: The plurality of second storage electrodes are connected to the third pad electrode; A second dielectric layer pattern covers the plurality of second storage electrodes; and A second planar electrode is connected to a fourth pad electrode, and portions of the second planar electrode extend between adjacent second memory electrodes. The second pad electrode is electrically connected to the fourth pad electrode via the first connecting pad and the second connecting pad, and The image sensor further includes a through-conductive plug connected to the first pad electrode, the third pad electrode, and the conductive pad disposed in the light-transmitting layer.

18. An image sensor, comprising: A pixel array comprising multiple pixels, each pixel comprising a stacked capacitor, the stacked capacitor comprising: Lower pad electrode; First intermediate pad electrode; Second intermediate pad electrode; Upper pad electrode; The lower capacitor structure is connected between the lower pad electrode and the first intermediate pad electrode; An intermediate capacitor structure is connected between the first intermediate pad electrode and the second intermediate pad electrode, and the intermediate capacitor structure is stacked on the lower capacitor structure so as to partially overlap the lower capacitor structure when viewed in a plan view; The lower contact plug connects the second intermediate pad electrode to the lower pad electrode; An upper capacitor structure is connected between the second intermediate pad electrode and the upper pad electrode, the upper capacitor structure being stacked on the intermediate capacitor structure; and The upper contact plug connects the first intermediate pad electrode to the upper pad electrode.

19. The image sensor of claim 18, wherein the lower capacitor structure comprises: Multiple lower storage electrodes are connected to the lower pad electrodes; The lower dielectric layer pattern covers the plurality of lower storage electrodes; as well as A lower planar electrode is connected to the first intermediate pad electrode, and portions of the lower planar electrode extend between adjacent lower memory electrodes in the lower memory electrode configuration. The intermediate capacitor structure includes: Multiple intermediate storage electrodes are connected to the first intermediate pad electrode; Intermediate dielectric layer pattern covering the plurality of intermediate storage electrodes; and An intermediate planar electrode is connected to the second intermediate pad electrode, portions of which extend between adjacent intermediate memory electrodes in the intermediate memory electrode configuration. The upper capacitor structure includes: Multiple upper storage electrodes are connected to the second intermediate pad electrode; The upper dielectric layer pattern covers the plurality of upper storage electrodes; and An upper plate electrode is connected to the upper pad electrode, and portions of the upper plate electrode extend between adjacent upper storage electrodes in the upper storage electrode.

20. The image sensor of claim 18, further comprising: The photoelectric conversion layer includes a pixel separation structure, wherein the pixel separation structure defines pixel regions corresponding to the plurality of pixels respectively, and each pixel region includes a photoelectric conversion region. An integrated circuit layer is disposed on the photoelectric conversion layer and includes a readout circuit for reading charge from the photoelectric conversion region; A charge storage layer is disposed on the integrated circuit layer, the charge storage layer including the stacked capacitor; An interconnect layer is disposed on the charge storage layer; A light-transmitting layer is disposed on the photoelectric conversion layer to transmit light into the photoelectric conversion region.

Images