Low latency interrupt alerts for artificial neural network systems and methods

Abstract

Various techniques are provided to provide higher efficiency for neural networks. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream, and to process the first data input after a first delay to generate a first reasoning output. The second ANN is configured to receive a second plurality of data inputs associated with the data stream, and to process the second data input after a second delay less than the first delay to generate a second reasoning output. The logic device is configured to receive the second reasoning output before the first reasoning output is generated. Other systems and methods are also provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation of U.S. Patent Application No. 16 / 290,811 filed on March 1, 2019, which in turn claims the benefit of U.S. Provisional Patent Application No. 62 / 640,741 filed on March 9, 2018, all of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to artificial neural networks, and more particularly to such networks with reduced latency. Background Art

[0004] Artificial neural networks (ANNs) are typically implemented as trainable systems for performing complex data analysis. ANNs typically include multiple nodes (e.g., also referred to as neurons). Nodes are configured to receive data, weight the received data, process the weighted data (e.g., by applying transfer functions, biases, activation functions, setting thresholds, and / or other processes), and pass the processed data to other nodes. Nodes can be arranged in layers including: an input layer, which receives data provided to the ANN; a hidden layer, which performs most of the ANN data processing; and an output layer, which provides results from the ANN (e.g., also referred to as inference).

[0005] In some cases, ANNs are used for complex image analysis, such as performing object characterization (e.g., object recognition) on image data (e.g., video frames or single images). The resulting inferences generated by such ANNs can be characterizations of the data, such as the identification of specific objects appearing in an image.

[0006] Unfortunately, in order to perform such an analysis, a conventional ANN may include many hidden layers of nodes. Because any data input may affect the processing of any node in a hidden layer, the input data (e.g., an entire video frame) must typically be fully processed by all layers of the ANN before an inference can be generated. This causes such an ANN to exhibit significant delays from the time the input layer receives data to the time the output layer provides an inference. Unfortunately, such delays may be problematic for systems that may need to respond quickly to various types of inferences. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram of a system providing multiple artificial neural networks (ANNs) according to an embodiment of the present disclosure is shown.

[0008] Figure 2 A block diagram of an example hardware implementation according to an embodiment of the present disclosure is shown.

[0009] Figure 3 Block diagrams of a master ANN, a low-latency ANN, and associated timing diagrams are shown according to embodiments of the present disclosure.

[0010] Figure 4 A block diagram of a main ANN and a low-latency ANN in sequential operation is shown according to an embodiment of the present disclosure.

[0011] Figure 5 A block diagram of a main ANN and a low-latency ANN in parallel operation according to an embodiment of the present disclosure is shown.

[0012] Figure 6 A block diagram of a main ANN and a low-latency ANN with pre-processing operations according to an embodiment of the present disclosure is shown.

[0013] Figure 7 A process of operating a main ANN and a low-latency ANN according to an embodiment of the present disclosure is shown.

[0014] Figure 8 Other timing diagrams of the main ANN and the low-latency ANN according to embodiments of the present disclosure are shown.

[0015] Embodiments of the present disclosure and their advantages will be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements shown in one or more of the accompanying drawings. DETAILED DESCRIPTION

[0016] According to the embodiments disclosed herein, various systems and methods are provided for utilizing a main artificial neural network (ANN) and a low-latency ANN to facilitate different processing requirements. For example, Figure 1 1 shows a block diagram of a system 100 for providing multiple ANNs according to an embodiment of the present disclosure. Figure 1 As shown, the main ANN 110 (e.g., the first ANN) and the low-latency ANN 120 (e.g., the second ANN) receive data input 140 and generate associated inferences 150 and 160 in response thereto, respectively. The inferences 150 and 160 are provided to the application 130, and the application 130 can selectively adjust its operation in response to the inferences 150 and / or the inferences 160.

[0017] Notably, low-latency ANN 120 exhibits reduced latency compared to primary ANN 110. In this regard, even if ANNs 110 and 120 are both receiving data input 140 at the same time, low-latency ANN 120 generates inference 160 before primary ANN 110 generates inference 150. As discussed further, this reduced latency may be associated with, for example, fewer layers and / or nodes included in low-latency ANN 120, and / or fewer data inputs 140 (e.g., or different data inputs) being processed by low-latency ANN 120.

[0018] The data input 140 may be any type of data that is desired to be analyzed by the system 100. Although the data input 140 and the reasoning 150 and 160 are generally discussed herein with respect to image data, any appropriate type of data input and reasoning may be used for the various embodiments provided herein. In some embodiments, both ANNs 110 and 120 may process the same data input 140. In other embodiments, the low-latency ANN 120 may process a reduced number of data inputs 140 (e.g., a subset thereof) compared to the main ANN 110. In some embodiments, fewer data inputs 140 may be provided to the low-latency ANN 120, and / or the data inputs 140 may be pre-processed to reduce their number, reduce their resolution (e.g., reduce pixel resolution in the case of image processing), and / or reduce their bit depth (e.g., reduce pixel depth in the case of image processing) before being processed by the low-latency ANN 120.

[0019] In some embodiments, data input 140 may include image data such as a data stream of video frames, where each frame constitutes a set of data input 140 to be processed by ANNs 110 and 120. For example, data input 140 may be provided by a video file, a real-time video feed, and / or other suitable source. In this example, master ANN 110 may be configured to perform feature analysis on data input 140 to generate inferences identifying objects identified in data input 140.

[0020] Likewise, in this example, the low-latency ANN 120 may be configured to perform a less complex analysis on the data input 140 to generate an inference identifying an occurrence of an event identified in the data input 140. In this regard, the analysis performed by the low-latency ANN 120 may be less complex than the analysis performed by the main ANN 110 (e.g., due to reduced processing performed by the low-latency ANN 120). For example, the detection of an event (e.g., the sudden appearance of an object in a scene of a video image) provided by the example inference 160 of the low-latency ANN 120 may require less processing than further characterization of the event (e.g., identification of a type of object appearing in a scene of a video image) provided by the example inference 150 of the main ANN 110.

[0021] For example, the reasoning 160 provided by the low-latency ANN 120 may correspond to the detection of an event that requires a quick response from the application 130 (e.g., a sudden change in the imaged video scene, the appearance of a new object in the scene, and / or other events). If the reasoning 160 is associated with such a high-priority event, the low-latency ANN 120 and / or the application 130 may identify it as an interruption alarm that triggers the application 130 to adjust its operation. Such an interruption alarm may constitute a higher priority for the application 130 than the complex characterization provided by the reasoning 150 from the main ANN 110. For example, in the case of video image processing, if the low-latency ANN 120 detects the sudden appearance of an object, it may be preferred that the application 130 perform one or more quick actions (e.g., instruct the guidance system of the vehicle including the system 100 to maneuver the vehicle to avoid hitting the detected object) in response to the reasoning 160 (e.g., in this case, the interruption alarm) rather than waiting for an additional period of time to pass until the main ANN 110 performs a more specific identification of a particular type of object and ultimately provides the reasoning 150.

[0022] The various features of system 100 may be implemented in appropriate hardware. For example, Figure 2 1 is a block diagram of an example hardware implementation that can be used to provide one or more of the main ANN 110, the low-latency ANN 120, the application 130, and the data input 140 according to an embodiment of the present disclosure. As shown in the figure, Figure 2 The illustrated implementation provides a hardware system including logic 210 , memory 220 , communication interface 230 , display 240 , user controls 250 , and other components 260 .

[0023] Logic device 210 may be implemented as any suitable device for data processing, such as a processor (e.g., a microprocessor, a single-core processor, and / or a multi-core processor), a microcontroller, a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a field programmable system on a chip (FPSC), or other types of programmable devices), a graphics processing unit (GPU), and / or other devices. Memory 220 may be implemented by one or more memory devices that provide machine-readable media, such as volatile memory (e.g., random access memory), non-volatile non-transitory memory (e.g., read-only memory, electrically erasable read-only memory, flash memory), or other types of memory. In various embodiments, memory 220 may store software instructions to be executed by logic device 120 (e.g., or used to configure logic device 120) according to various operations discussed herein, data corresponding to data input 140, data corresponding to inferences 150 and 160, and / or other appropriate information.

[0024] The communication interface 230 may be implemented with appropriate hardware to provide wired and / or wireless data communications between the various components of the system 100 and / or between the system 100 and other devices. For example, in some embodiments, the communication interface 230 may be a network interface (e.g., an Ethernet interface, a Wi-Fi interface, and / or other network interface), a serial interface, a parallel interface, and / or other appropriate types. For example, one or more communication interfaces 230 may be provided to receive data input 140 from an external device (e.g., from a networked camera or file system), pass communications between the various components of the system 100, and / or provide data output to an external device.

[0025] The display 140 may be implemented with appropriate hardware to present information to a user of the system 100. For example, in some embodiments, the display 140 may be implemented with a screen, a touch screen, and / or other appropriate hardware. The user controls 250 may be implemented with appropriate hardware to allow a user to interact with the system 100 and / or operate the system 100. For example, in some embodiments, the user controls may be implemented with various components such as a keyboard, a mouse, a trackpad, a touch screen (e.g., in some cases integrated with the display 140), buttons, slide bars, knobs, and / or other appropriate hardware. Other components 260 may be provided to implement any other hardware features suitable for a particular implementation.

[0026] Figure 3A block diagram of the master ANN 110, the low-latency ANN 120, and associated timing diagrams 310 and 320 are shown in accordance with an embodiment of the present disclosure. As previously discussed, the master ANN 110 and the low-latency ANN 120 receive data input 140 and provide inferences 150 and 160 in response thereto.

[0027] As shown, the main ANN 110 includes various nodes 300 arranged in multiple layers including an input layer 112, a hidden layer 114, and an output layer 116. The low-latency ANN 120 includes various nodes 301 arranged in multiple layers including an input layer 122, a hidden layer 124, and an output layer 126. However, compared to the main ANN 110, the low-latency ANN 120 may include a reduced number of hidden layers 124, and a reduced number of nodes 301 in the input layer 122, the hidden layer 124, and the output layer 126. Compared to the nodes 300 of the main ANN 110, the processing associated with the nodes 301 of the low-latency ANN 120 may be reduced. For example, in some embodiments, the nodes 301 of the low-latency ANN 120 may be implemented with binary weights (e.g., the low-latency ANN 120 may be implemented as a binary ANN and / or a ternary ANN), while the nodes 300 of the main ANN 110 may be implemented as non-binary weights.

[0028] Although a specific number of hidden layers 114 and 124 are shown, in various embodiments, any desired number of hidden layers may be provided. Also, although a specific number of nodes 300 / 301 are shown in layers 112, 114, 116, 122, 124, and 126, in various embodiments, any desired number of nodes 300 / 301 may be provided.

[0029] In some embodiments, the main ANN 110 and the low-latency ANN 120 may be implemented to run in parallel on separate hardware devices of different complexity and / or processing power to accommodate the different processing characteristics of the ANNs 110 and 120. For example, in some embodiments, the main ANN 110 may be implemented in a high-performance logic device (e.g., a GPU or other processor), while the low-latency ANN 120 may be implemented in a low-power logic device (e.g., a PLD). In other embodiments, the main ANN 110 and the low-latency ANN 120 may be implemented to run sequentially (e.g., using a single processing core) or in parallel (e.g., using multiple processing cores) on the same logic device. In various embodiments, the application 130 may run on the same logic device as one or both of the main ANN 110 and the low-latency ANN 120, or on a separate logic device.

[0030] In the case of the master ANN 110, all data inputs 140 are processed by all layers 112, 114, and 116 before providing inference 150. In the case of the low-latency ANN 110, a reduced number of data inputs 140 may be processed by all layers 122, 124, and 126 before providing inference 160. However, the master ANN 110 is implemented using a greater number of nodes 300 than the number of nodes 301 of the low-latency ANN 120 (e.g., due to a greater number of hidden layers 114 than hidden layers 124 and / or a greater number of nodes 300 than nodes 301). As a result, the master ANN 110 will exhibit greater latency than the low-latency ANN 120. Therefore, before the master ANN 110 generates inference 150, the inference 160 will be generated by the low-latency ANN 120.

[0031] These different delays are further illustrated in timing diagrams 310 and 320 associated with the main ANN 110 and the low-latency ANN 120, respectively. In the case of the timing diagrams 310 and 320, the data input 140 corresponds to a data stream of multiple video frames. In this regard, the first video frame f0 can be provided as the data input 140 to the main ANN 110 and the low-latency ANN 120 at time 330.

[0032] In response to the received data input 140, the low-latency ANN 120 processes the video frame f0 during a time period 332 that lasts from time 330 to time 340 at which inference 160 is generated. Also in response to the received data input 140, the main ANN 110 processes the video frame f0 during a time period 334 that lasts from time 330 to time 350 at which inference 150 is generated.

[0033] As shown, low-latency ANN 120 exhibits a delay corresponding to time period 332 extending from time 330 to time 340. Master ANN 110 exhibits a delay corresponding to time period 334 extending from time 330 to time 350. Therefore, it should be understood that low-latency ANN 120 and master ANN 110 exhibit a delay difference corresponding to time period 336 lasting from time 340 to time 350. As a result, inference 160 will be available to application 130 earlier than inference 150.

[0034] As discussed, the application 130 may selectively adjust its operation in response to the inferences 150 and / or the inferences 160. Advantageously, by implementing a low-latency ANN 120 with reduced latency compared to the main ANN 110, the application 130 will promptly receive any inferences 160 corresponding to the outage alert and may adjust its operation in response thereto without having to wait for the main ANN 110 to generate its inferences 150.

[0035] like Figure 3 As further shown, successive video frames (e.g., video frame f0, then video frame f1, and so on) may be provided and processed by ANNs 110 and 120. In addition, in some embodiments, due to the greatly reduced latency provided by low-latency ANN 120, application 130 may adjust its operation in response to an interruption alert during processing of the current video frame (e.g., f0) and even before receiving the next video frame (e.g., f1) at data input 140.

[0036] Various configurations are contemplated for the main ANN 110 and the low-latency ANN 120. For example, Figure 4 FIG. 1 shows a block diagram of a master ANN 110 and a low-latency ANN 120 in sequential operation according to an embodiment of the present disclosure. Figure 4 , the master ANN 110 and the low-latency ANN 120 are implemented on a shared logic device 400 and are configured for the sequential operation discussed. In this regard, after receiving the data input 140 at time t0, the low-latency ANN 120 begins processing the data input 140 and provides reasoning 160 at time t1 (e.g., exhibiting a delay from time t0 to time t1). The master ANN 110 receives and begins processing the data input 140 at time t1, and provides reasoning 150 at time t2 (e.g., exhibiting a delay from time t1 to time t2). Thus, at Figure 4 In the sequential processing example shown, inference 160 arrives earlier at time t1, while inference 150 arrives later at time t2.

[0037] Figure 5 FIG. 1 shows a block diagram of a main ANN 110 and a low-latency ANN 120 in parallel operation according to an embodiment of the present disclosure. Figure 5 In , the main ANN 110 and the low-latency ANN 120 operate in parallel and may be implemented on a shared logic device 500 (e.g., having different processor cores associated with each of the ANNs 110 and 120) and / or on separate logic devices, as discussed. Figure 5 , both the master ANN 110 and the low-latency ANN receive data input 140 at time t0 and begin processing. The low-latency ANN 120 provides reasoning 160 at time t1, and the master ANN 110 subsequently provides reasoning 150 at time t2 because of its longer latency.

[0038] Figure 6A block diagram of a main ANN 110 and a low-latency ANN 120 implemented with preprocessing operations according to an embodiment of the present disclosure is shown. As discussed, in some embodiments, the data input 140 can be preprocessed before providing the data input 140 to the low-latency ANN 120. For example, the data input 140 can be preprocessed to reduce its number, reduce its resolution, reduce its bit depth, and / or otherwise appropriately modified to provide processed data input 630 to be further processed by the low-latency ANN 120.

[0039] exist Figure 6 , the main ANN 110 is implemented by logic device 600, and the low latency ANN 120 is implemented by logic device 610. In addition, pre-processing operations are performed by logic device 620. Although various logic devices 600, 610, and 620 are shown, any desired number of shared and / or separate logic devices may be used to implement the present invention as appropriate. Figure 6 various characteristics.

[0040] As shown, data input 140 is initially provided to logic device 620, which pre-processes it to provide processed data input 630 for use by low-latency ANN 120, as discussed. In some embodiments, as shown, processed data input 630 can also be provided to main ANN 110 for processing if necessary.

[0041] In some embodiments, the pre-processing operations of the logic device 620 may be performed prior to the processing performed by the main ANN 110, such that the data input 140 and the processed data input 630 are provided to the main ANN 110 and the low-latency ANN 120, respectively, at time t0. As discussed with respect to various embodiments, the low-latency ANN 120 may then process the data input 630 at time t1 to provide the inference 160, and the main ANN 110 may process the data input 630 at a later time t2 to provide the inference 150. In other embodiments, the data input 140 may be provided to the pre-processing operations of the main ANN 110 and the logic device 620 simultaneously, such that the main ANN 110 may begin processing the data input 140 while the pre-processing operations are being performed by the logic device 620.

[0042] Figure 7A process for operating a main ANN 110 and a low-latency ANN 120 according to an embodiment of the present disclosure is shown. In box 701, the main ANN 110 and the low-latency ANN 120 are trained on an appropriate data set. In this regard, a known data set can be provided to the main ANN 110 and the low-latency ANN 120 as a data input 140. The weights, transfer functions, and other processing associated with its various nodes 300 / 301 can be adjusted in an iterative manner (e.g., through appropriate feedback, back-propagation, and / or other techniques) until the main ANN 110 and the low-latency ANN 120 generate appropriate inferences 150 and 160. For example, in some embodiments where video frames are to be analyzed, the main ANN 110 can be trained on a data set including video frames with full resolution and full bit depth, and the low-latency ANN 120 can be trained on a data set including video frames with reduced resolution and reduced bit depth (e.g., a pre-processed version of the video frames provided to the main ANN 110, such as Figure 6 ). After training is complete, the main ANN 110 and the low-latency ANN 120 can begin normal operation. Thus, in block 702, the system 100 receives a data input 140, such as a video frame to be analyzed by the main ANN 110 and the low-latency ANN 120.

[0043] As discussed, in various embodiments, the main ANN 110 and the low-latency ANN 120 may operate in parallel or sequentially. Figure 7 , parallel operation is shown, where the blocks of group 710 are generally associated with the low-latency ANN 120, and the blocks of group 730 are generally associated with the main ANN 110. However, sequential operation may also be provided, where some of all the blocks of group 710 are executed before the blocks of group 730.

[0044] Figure 8 Additional timing diagrams of various operations of groups 710 and 730 associated with the master ANN 110 and the low-latency ANN 120 according to embodiments of the present disclosure are shown. In particular, Figure 8 Operations associated with analyzing sequential video frames f0 and f1 received in a data stream provided to data input 140 are shown.

[0045] Referring to the blocks of group 710, in block 712, pre-processing is optionally performed on the data input 140 to generate the processed data input 630. In block 714, the data input 140 (or the processed data input 630) is provided to and received by the low-latency ANN 120. In block 716, the low-latency ANN 120 processes the data input 140 / 630. In block 718, the low-latency ANN 120 generates the inference 160 and provides it to the application 130.

[0046] As discussed, in some cases, the low latency ANN 120 and / or the application 130 may identify the inference 160 as an outage alarm for triggering the application 130 to adjust its operation. Thus, in block 720, if the low latency ANN 120 and / or the application 130 determines that the inference 160 is associated with an outage alarm, the process proceeds to block 722. Otherwise, the process proceeds to block 736, as shown, where the main ANN 110 continues its processing.

[0047] In block 722, the application 130 adjusts its operation in response to the interruption alert. In some embodiments, the application 130 may not need to receive the additional reasoning 150 subsequently provided by the main ANN 120, and may therefore ignore the reasoning 150 when the reasoning 150 is finally generated. In other embodiments, the application 130 may utilize the reasoning 150 in further processing.

[0048] Referring now to the blocks of group 730, in block 732, data input 140 is provided to and received by master ANN 110. As shown, in some embodiments, master ANN 110 may receive data input 140 while pre-processing block 712 is being executed, such that master ANN 110 does not need to wait to begin processing data input 140. In block 734, master ANN 110 begins processing data input 140. In this regard, as previously described, low latency ANN 120 may provide inference 160 (block 718) before master ANN 110 provides inference 150, such as Figure 7 and 8 Thus, even after the blocks of group 710 have been completed, the master ANN 110 may continue to process the data input 140 in block 736 .

[0049] In block 738, the master ANN 110 generates inferences 150 and provides them to the application 130. In block 740, the application 130 adjusts its operation in response to the inferences 150.

[0050] For additional data input, such as Figure 8 Blocks 702 through 740 may be repeated for additional video frames f1 as shown, and thus, the system 100 may continue to process the data stream providing a collection of new data inputs 140 as needed, such as for processing video data.

[0051] Where applicable, the various embodiments provided by the present disclosure may be implemented using hardware, software, or a combination of hardware and software. Likewise, where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components set forth herein may be combined into composite components comprising software, hardware, and / or both. Where applicable, without departing from the spirit of the present disclosure, the various hardware components and / or software components set forth herein may be divided into subcomponents comprising software, hardware, or both. In addition, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0052] Software (such as program code and / or data) according to the present disclosure may be stored on one or more computer-readable media. It is also contemplated that the software identified herein may be implemented using one or more general or special-purpose computers and / or computer systems networked and / or otherwise. Where applicable, the order of the various steps described herein may be changed, combined into composite steps and / or divided into sub-steps to provide the features described herein.

[0053] The embodiments described above illustrate but do not limit the present invention. It should also be understood that various modifications and variations may be made based on the principles of the present invention. Therefore, the scope of the present invention is limited only by the appended claims.

Claims

1. A method, include: receiving a plurality of first data inputs at a first artificial neural network and a plurality of second data inputs at a second artificial neural network, wherein the first data inputs and the second data inputs are associated with a data stream, wherein the data stream includes image data; processing, by the first artificial neural network, the first data input to perform feature analysis on the first data input to generate a first inference output after a first delay, wherein the first inference output includes a representation identifying a type of object in the image data; performing a detection analysis on the second data input by the second artificial neural network independently of the first artificial neural network to generate a second inference output after a second delay, wherein the second inference output comprises detecting an occurrence of an event, the event comprising a sudden appearance of the object in the image data, wherein the second delay is less than the first delay due to the first artificial neural network comprising a greater number of hidden layers and a greater number of nodes than the second artificial neural network, wherein the second inference output comprises an interrupt alert associated with the event; providing the second inference output to a logic device before the first inference output is generated; triggering an application implemented on the logic device to adjust operation of the application in response to the interrupt alert before the first inference output is generated, thereby allowing the operation of the application to be adjusted without waiting for the representation to be provided by the first artificial neural network and causing the application to exhibit a reduced response time to the image data; and Wherein the processing performed by the first artificial neural network and the second artificial neural network are performed simultaneously during at least an overlapping time period until the second inference output is generated.

2. The method according to claim 1, further comprising: include: The first inference output is ignored by the application in response to the interruption alert.

3. The method according to claim 1, further comprising: include: The first data input is preprocessed to generate the second data input.

4. The method according to claim 3, in: The first data input comprises video frames of the data stream; The second data input comprises reduced resolution video frames; and The pre-processing includes processing the video frames of the data stream to generate the reduced resolution video frames.

5. The method of claim 1, wherein the outage alert provided by the second artificial neural network constitutes a higher priority for the application than the characterization provided by the first artificial neural network.

6. The method according to claim 1, further comprising: include: training the first artificial neural network using the first set of video frames; training the second artificial neural network using a second set of video frames generated from the first set of video frames; and Wherein the second set of video frames has a reduced pixel resolution and / or a reduced pixel depth relative to the first set of video frames. The method of claim 5 , wherein the regulated operation of the application includes instructing a guidance system of a vehicle.

8. The method according to claim 1, in: The first data input is greater than the second data input; and The hidden layer of the second artificial neural network includes nodes with binary weights.

9. The method according to claim 1, in: said processing performed by said first artificial neural network and said second artificial neural network is performed in parallel; The first artificial neural network is implemented by a graphics processing unit; and The second artificial neural network is implemented by a programmable logic device.

10. The method of claim 1, wherein the processing performed by the first artificial neural network and the second artificial neural network is performed sequentially by the logic device.

11. A system, include: The first artificial neural network is configured as: receiving a plurality of first data inputs associated with a data stream, wherein the data stream includes image data, and processing the first data input to perform feature analysis on the first data input to generate a first reasoning output after a first delay, wherein the first reasoning output includes a representation identifying a type of object in the image data; The second artificial neural network is configured as: receiving a plurality of second data inputs associated with the data stream, and performing a detection analysis on the second data input independently of processing the second data input by the first artificial neural network to generate a second inference output after a second delay, wherein the second inference output comprises detecting an occurrence of an event, the event comprising a sudden appearance of the object in the image data, wherein the second delay is less than the first delay due to the first artificial neural network comprising a greater number of hidden layers and a greater number of nodes than the second artificial neural network, wherein the second inference output comprises an interrupt alert associated with the event; a logic device configured to receive the second inference output before the first inference output is generated, wherein an application implemented by the logic device is configured to be triggered to adjust operation of the application in response to the interruption alert before the first inference output is generated, thereby allowing the operation of the application to be adjusted without waiting for the representation to be provided by the first artificial neural network and causing the application to exhibit a reduced response time to the image data; and Wherein the processing performed by the first artificial neural network and the second artificial neural network are performed simultaneously during at least an overlapping time period until the second inference output is generated. 12 . The system of claim 11 , wherein the application is configured to ignore the first reasoning output in response to the outage alert.

13. The system of claim 11, wherein the second data input is generated from the first data input.

14. The system according to claim 13, in: The first data input comprises video frames of the data stream; and The second data input comprises reduced resolution video frames.

15. The system of claim 11, wherein the outage alert provided by the second artificial neural network constitutes a higher priority for the application than the characterization provided by the first artificial neural network.

16. The system according to claim 11, in: The first artificial neural network is configured to be trained using a first set of video frames; The second artificial neural network is configured to be trained using a second set of video frames generated from the first set of video frames; and The second set of video frames has a reduced pixel resolution and / or a reduced pixel depth relative to the first set of video frames.

17. The system of claim 15, wherein the regulated operation of the application includes instructions to a guidance system of a vehicle.

18. The system according to claim 11, in: The first data input is greater than the second data input; The hidden layer of the second artificial neural network includes nodes with binary weights.

19. The system according to claim 11, in: said processing performed by said first artificial neural network and said second artificial neural network is performed in parallel; The first artificial neural network is implemented by a graphics processing unit; and The second artificial neural network is implemented by a programmable logic device.

20. The system of claim 11, wherein the processing performed by the first artificial neural network and the second artificial neural network is performed sequentially by the logic device.

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