Main control chip and memory chip compatibility test circuit

Abstract

The present application provides a test circuit for the compatibility of a main control chip and a memory chip, which is applied to the field of memory chip testing technology. An XU4 platform, a main control chip and a memory chip are all installed in the same circuit to test the internal wiring. The test circuit includes an XU4 platform module and a test platform module. Current and data are conducted through the XU4 platform module and the test platform module to solve the technical problem of too slow rate when the XU4 platform transmits signals to the main control chip and NAND Flash through external wiring, eliminate the use of external signal lines, and improve the data transmission rate.

Description

Technical Field

[0001] The present application relates to the technical field of memory chip testing, and in particular to a test circuit for compatibility between a main control chip and a memory chip. Background Art

[0002] For the compatibility verification between the main control chip and NAND Flash (non-volatile flash memory chip), the verification method is to input instructions to the main control chip through the XU4 platform, and then control the NAND Flash through the main control chip. Under the current conditions, the XU4 platform can only be connected to the main control chip and NAND Flash by external wiring, but the external wiring has great interference on the signal, and the data transmission rate can only reach about 50MHz.

[0003] There are several reasons for the problem of large external wiring signal interference:

[0004] 1. If the DuPont line is too long, the signal will be attenuated;

[0005] 2. The length and impedance of DuPont lines are different, which will affect the transmission rate of the signal;

[0006] 3. The quality of DuPont cables is poor and will affect the signal. Summary of the invention

[0007] The present application provides a test circuit for the compatibility of a main control chip and a storage chip, which solves the technical problem of slow transmission rate when the XU4 platform transmits signals to the main control chip and NAND Flash through external wiring, eliminates the use of external signal lines, and improves the data transmission rate.

[0008] This application adopts the following technical means to solve the technical problem:

[0009] The present application provides a test circuit for the compatibility of a main control chip and a memory chip, wherein an XU4 platform, a main control chip and a memory chip are installed in the same circuit to test internal wiring, and the test circuit comprises:

[0010] XU4 platform module, including a CPU processor, a data transmission circuit, a storage medium, a power module, a first connection socket and a second connection socket, wherein the data transmission circuit is connected in series with the storage medium and connected to the CPU processor, the first pin of the power module is connected to the CPU processor, the second pin of the power module is connected to the first connection socket, and the CPU processor is connected to the second connection socket;

[0011] The test platform module includes a power conversion circuit, a main control chip, a socket for an object to be tested, a third connection socket and a fourth connection socket, wherein the third connection socket is connected to the first connection socket through an I / O line and a power line, the fourth connection socket is connected to the second connection socket through an I / O line, the third connection socket is connected to the power conversion circuit through the I / O line and the power line, the power conversion circuit is respectively connected to the main control chip and the socket for the object to be tested, the fourth connection socket is connected to the main control chip, and the main control chip is connected to the socket for the object to be tested.

[0012] Furthermore, the data transmission circuit is connected to an external PC terminal.

[0013] Furthermore, the storage medium includes a burning circuit and a storage device, and the burning circuit and the storage device are respectively connected to the CPU processor, the data transmission circuit and the power module.

[0014] Furthermore, the burning circuit is connected to an external PC terminal.

[0015] Further, the power conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit;

[0016] The first voltage-to-digital conversion circuit includes a first transformer U2 and a plurality of capacitors, wherein the first pin of the first transformer U2 is connected to the third connection socket to receive a 5V voltage load current, the fifth pin of the first transformer U2 is connected in series to the main control chip and the socket of the object to be tested to output a 3.3V load current, and the plurality of capacitors are connected in parallel to the first pin or the fifth pin of the first transformer U2 respectively;

[0017] The second voltage-to-digital conversion circuit includes a second transformer U3 and a plurality of capacitors. The first pin of the second transformer U3 is connected to the third connection socket to receive a load current of 5V voltage. The fifth pin of the second transformer U3 is connected in series to the main control chip to output a load current of 1.8V. The plurality of capacitors are connected in parallel to the first pin or the fifth pin of the second transformer U3 respectively.

[0018] Furthermore, the test platform module also includes a reset button, and the reset button is connected to the main control chip.

[0019] The present application also provides a method for testing the compatibility of a main control chip and a storage chip, and the test method is performed using the above-mentioned test circuit. The test method includes a power supply test method and a data interaction test method, wherein:

[0020] The power supply test method is as follows: the power module outputs a first load current corresponding to a 5V voltage to a first connection socket, and the first connection socket transmits the first load current from the XU4 platform part to the third connection socket of the test platform part through a power line and an I / O line; the third connection socket outputs the first load current to a power conversion module correspondingly, and the power conversion module converts the first load current into a second load current of 3.3V and a third load current of 1.8V, and outputs the second load current and the third load current to the main control chip, and outputs the second load current to the socket of the object to be tested;

[0021] The data interaction test method is: the CPU processor outputs the test instructions in the emmc protocol to the second connection socket, the second connection socket outputs the test instructions from the XU4 platform part to the fourth connection socket of the test platform part through the I / O line, and the fourth connection socket outputs the test instructions to the main control chip.

[0022] Further, the power conversion module converts the first load current into a second load current of 3.3V and a third load current of 1.8V, and outputs the second load current and the third load current to the main control chip, and the step of outputting the second load current to the socket of the object to be tested includes:

[0023] The first voltage-to-number conversion circuit is used to convert the first load current into a second load current, and the second load current is output to the main control chip and the socket of the object to be tested respectively, so as to be used for powering the main control chip and the socket of the object to be tested;

[0024] The second volt-to-digital conversion circuit is used to convert the first load current into a third load current, and the third load current is output to the main control chip. After the main control chip obtains the test instruction and the third load current, the test instruction is output to the socket of the object to be tested through the third load current, and the compatibility signal corresponding to the feedback of the socket of the object to be tested is obtained to determine whether the main control chip and the socket of the object to be tested are compatible.

[0025] The present application provides a test circuit for the compatibility of a main control chip and a storage chip, which has the following beneficial effects:

[0026] The present application provides a test circuit for the compatibility of a main control chip and a memory chip. The XU4 platform, the main control chip and the memory chip are all installed in the same circuit to test the internal wiring. The test circuit includes:

[0027] XU4 platform module, including a CPU processor, a data transmission circuit, a storage medium, a power module, a first connection socket and a second connection socket, wherein the data transmission circuit is connected in series with the storage medium and connected to the CPU processor, the first pin of the power module is connected to the CPU processor, the second pin of the power module is connected to the first connection socket, and the CPU processor is connected to the second connection socket;

[0028] The test platform module includes a power conversion circuit, a main control chip, a socket for an object to be tested, a third connection socket and a fourth connection socket, wherein the third connection socket is connected to the first connection socket through an I / O line and a power line, the fourth connection socket is connected to the second connection socket through an I / O line, the third connection socket is connected to the power conversion circuit through the I / O line and the power line, the power conversion circuit is respectively connected to the main control chip and the socket for the object to be tested, the fourth connection socket is connected to the main control chip, and the main control chip is connected to the socket for the object to be tested.

[0029] In order to solve the technical problem that the rate of signal transmission from the XU4 platform to the main control chip and NAND Flash through external wiring is too slow, the use of external signal lines is eliminated and the data transmission rate is improved; in addition, the main control chip and the NAND Flash to be tested are combined into the same circuit, and the line length is reduced by internal routing when drawing the PCB. At the same time, the data transmission lines and clock signal lines of various channels are treated with equal length and width, thereby improving the signal transmission quality; the NAND Flash is loaded with Socket instead of direct welding, so that the test board can be used multiple times, which improves the use value; a connector that can be directly connected to the XU4 platform is adopted, which avoids the signal transmission by external wiring and improves the signal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a circuit module of an embodiment of a test circuit for compatibility between a main control chip and a storage chip of the present application;

[0031] Figure 2 A circuit diagram of a power conversion circuit of an embodiment of a test circuit for compatibility between a main control chip and a memory chip of the present application.

[0032] The implementation, functional features and advantages of the present application will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0033] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] It should be noted that the terms "include", "comprises" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In the claims, specification and drawings of the present application, relational terms such as "first" and "second" are merely used to distinguish one entity / operation / object from another entity / operation / object, and do not necessarily require or imply any such actual relationship or order between these entities / operations / objects.

[0036] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] Reference Figure 1 , is a circuit diagram of a test circuit for compatibility between the main control chip 115 and the storage chip in one embodiment of the present application;

[0038] The test circuit for compatibility between the main control chip 115 and the memory chip provided in the present application installs the XU4 platform, the main control chip 115 and the memory chip in the same circuit to test the internal wiring;

[0039] The test circuit includes:

[0040] XU4 platform module, including a CPU processor 106, a data transmission circuit 109, a storage medium, a power module 103, a first connection socket 107 and a second connection socket 110, wherein the data transmission circuit 109 is connected in series with the storage medium and connected to the CPU processor 106, a first pin of the power module 103 is connected to the CPU processor 106, a second pin of the power module 103 is connected to the first connection socket 107, and the CPU processor 106 is connected to the second connection socket 110;

[0041] The test platform module includes a power conversion circuit, a main control chip 115, a socket 116 for an object to be tested, a third connection socket 111 and a fourth connection socket 113, wherein the third connection socket 111 is connected to the first connection socket 107 through an I / O line and a power line, the fourth connection socket 113 is connected to the second connection socket 110 through an I / O line, the third connection socket 111 is connected to the power conversion circuit through the I / O line and the power line, the power conversion circuit is respectively connected to the main control chip 115 and the socket 116 for the object to be tested, the fourth connection socket 113 is connected to the main control chip 115, and the main control chip 115 is connected to the socket 116 for the object to be tested.

[0042] The data transmission circuit 109 is connected to the external PC terminal 108 to monitor the interactive device externally.

[0043] The above-mentioned storage medium includes a burning circuit 105 and a storage device 104, and the burning circuit 105 and the storage device 104 are respectively connected to the CPU processor 106, the data transmission circuit 109 and the power module 103, and the burning circuit 105 is connected to the external PC terminal 108 to burn the test script to the storage device 104 for storage and filing of the test process.

[0044] Reference Figure 2 , the power conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit;

[0045] The first voltage-to-digital conversion circuit includes a first transformer U2 and a plurality of capacitors. The first pin of the first transformer U2 is connected to the third connection socket 111 to receive a 5V voltage load current. The fifth pin of the first transformer U2 is connected in series to the main control chip and the socket of the object to be tested to output a 3.3V load current. The plurality of capacitors are connected in parallel to the first pin or the fifth pin of the first transformer U2 respectively.

[0046] The second volt-to-digital conversion circuit includes a second transformer U3 and a plurality of capacitors. The first pin of the second transformer U3 is connected to the third connection socket 111 to receive a load current of 5V voltage. The fifth pin of the second transformer U3 is connected in series to the main control chip to output a load current of 1.8V. The plurality of capacitors are connected in parallel to the first pin or the fifth pin of the second transformer U3 respectively.

[0047] In one embodiment, the test platform module further includes a reset button, which is connected to the main control chip 115. When the TO0 pin of the main control chip 115 is set to a low potential, the system will enter the test mode. In the test mode, pressing the reset button 114 resets the system.

[0048] The present invention also provides a method for testing the compatibility of the main control chip 115 and the storage chip. The test method is performed using the above-mentioned test circuit. The test method includes a power supply test method and a data interaction test method, wherein:

[0049] The power supply test method is as follows: the power module 103 outputs a first load current corresponding to a 5V voltage to the first connection socket 107, and the first connection socket 107 transmits the first load current from the XU4 platform part 101 to the third connection socket 111 of the test platform part 102 through a power line and an I / O line; the third connection socket 111 outputs the first load current to the power conversion module 112 correspondingly, and the power conversion module 112 converts the first load current into a second load current of 3.3V and a third load current of 1.8V, and outputs the second load current and the third load current to the main control chip 115, and outputs the second load current to the test object socket 116;

[0050] The data interaction test method is: the CPU processor 106 outputs the test instructions in the emmc protocol to the second connection socket 110, the second connection socket 110 outputs the test instructions from the XU4 platform part 101 to the fourth connection socket 113 of the test platform part 102 through the I / O line, and the fourth connection socket 113 outputs the test instructions to the main control chip 115.

[0051] In one embodiment, the power conversion module 112 converts the first load current into a second load current of 3.3V and a third load current of 1.8V, and outputs the second load current and the third load current to the main control chip 115, and the step of outputting the second load current to the DUT socket 116 includes:

[0052] A first voltage conversion circuit is used to convert the first load current into a second load current, and the second load current is output to the main control chip 115 and the DUT socket 116 respectively, so as to be used for powering the main control chip 115 and the DUT socket 116;

[0053] A second volt-to-number conversion circuit is used to convert the first load current into a third load current, and the third load current is output to the main control chip 115. After the main control chip 115 obtains the test instruction and the third load current, the test instruction is output to the socket 116 of the object to be tested through the third load current, and the compatibility signal corresponding to the feedback of the socket 116 of the object to be tested is obtained to determine whether the main control chip 115 and the socket 116 of the object to be tested are compatible.

[0054] In summary, the present application provides a test circuit for the compatibility of the main control chip 115 and the memory chip. The XU4 platform, the main control chip 115 and the memory chip are all installed on the same circuit board to test the internal wiring. The test circuit includes:

[0055] XU4 platform module, including a CPU processor 106, a data transmission circuit 109, a storage medium, a power module 103, a first connection socket 107 and a second connection socket 110, wherein the data transmission circuit 109 is connected in series with the storage medium and connected to the CPU processor 106, a first pin of the power module 103 is connected to the CPU processor 106, a second pin of the power module 103 is connected to the first connection socket 107, and the CPU processor 106 is connected to the second connection socket 110;

[0056] The test platform module includes a power conversion circuit, a main control chip 115, a socket 116 for an object to be tested, a third connection socket 111 and a fourth connection socket 113, wherein the third connection socket 111 is connected to the first connection socket 107 through an I / O line and a power line, the fourth connection socket 113 is connected to the second connection socket 110 through an I / O line, the third connection socket 111 is connected to the power conversion circuit through the I / O line and the power line, the power conversion circuit is respectively connected to the main control chip 115 and the socket 116 for the object to be tested, the fourth connection socket 113 is connected to the main control chip 115, and the main control chip 115 is connected to the socket 116 for the object to be tested.

[0057] In order to solve the technical problem that the rate is too slow when the XU4 platform transmits signals to the main control chip 115 and NAND Flash through external wiring, the use of external signal lines is eliminated and the data transmission rate is improved; in addition, the main control chip 115 and the NAND Flash to be tested are combined into the same circuit, and the line length is reduced by internal routing when drawing the PCB, and the data transmission lines and clock signal lines of various channels are treated with equal length and width, thereby improving the signal transmission quality; the NAND Flash is loaded with a socket instead of direct welding, so that the test board can be used multiple times, and the use value is improved; a connection socket that can be directly connected to the XU4 platform is adopted, so that the signal transmission by external wiring is avoided, and the signal quality is improved.

[0058] Although the embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A test circuit for compatibility between a main control chip and a storage chip, characterized in that: The XU4 platform, the main control chip and the storage chip are all installed in the same circuit to test the internal wiring. The test circuit includes: XU4 platform module, including a CPU processor, a data transmission circuit, a storage medium, a power module, a first connection socket and a second connection socket, wherein the data transmission circuit is connected in series with the storage medium and connected to the CPU processor, the first pin of the power module is connected to the CPU processor, the second pin of the power module is connected to the first connection socket, and the CPU processor is connected to the second connection socket; A test platform module, comprising a power conversion circuit, a main control chip, a socket for an object to be tested, a third connection socket and a fourth connection socket, wherein the third connection socket is connected to the first connection socket via an I / O line and a power line, the fourth connection socket is connected to the second connection socket via an I / O line, the third connection socket is connected to the power conversion circuit via an I / O line and a power line, the power conversion circuit is respectively connected to the main control chip and the socket for the object to be tested, the fourth connection socket is connected to the main control chip, and the main control chip is connected to the socket for the object to be tested; The test circuit executes a test method, which includes a power supply test method and a data interaction test method, wherein: The power supply test method is as follows: the power module outputs a first load current corresponding to a 5V voltage to a first connection socket, and the first connection socket transmits the first load current from the XU4 platform module to the third connection socket of the test platform module through a power line and an I / O line; the third connection socket outputs the first load current to a power conversion module correspondingly, and the power conversion module converts the first load current into a second load current of 3.3V and a third load current of 1.8V, and outputs the second load current and the third load current to the main control chip, and outputs the second load current to the socket of the object to be tested; The data interaction test method is as follows: the CPU processor outputs the test instruction in the emmc protocol to the second connection socket, the second connection socket outputs the test instruction from the XU4 platform module to the fourth connection socket of the test platform module through the I / O line, and the fourth connection socket outputs the test instruction to the main control chip; After the main control chip obtains the test instruction and the third load current, it outputs the test instruction to the DUT socket through the third load current, and obtains the compatibility signal fed back by the DUT socket to determine whether the main control chip and the DUT socket are compatible.

2. The test circuit for compatibility between the main control chip and the memory chip according to claim 1, characterized in that: The data transmission circuit is connected to an external PC terminal.

3. The test circuit for compatibility between the main control chip and the storage chip according to claim 1, characterized in that: The storage medium comprises a burning circuit and a storage device, and the burning circuit and the storage device are respectively connected to a CPU processor, a data transmission circuit and a power supply module.

4. The test circuit for compatibility between the main control chip and the storage chip according to claim 3, characterized in that: The burning circuit is connected to an external PC terminal.

5. The test circuit for compatibility between the main control chip and the storage chip according to claim 1, characterized in that: The power conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit; The first voltage-to-digital conversion circuit includes a first transformer U2 and a plurality of capacitors, wherein the first pin of the first transformer U2 is connected to the third connection socket to receive a 5V voltage load current, the fifth pin of the first transformer U2 is connected in series to the main control chip and the socket of the object to be tested to output a 3.3V load current, and the plurality of capacitors are connected in parallel to the first pin or the fifth pin of the first transformer U2 respectively; The second voltage-to-digital conversion circuit includes a second transformer U3 and a plurality of capacitors. The first pin of the second transformer U3 is connected to the third connection socket to receive a load current of 5V voltage. The fifth pin of the second transformer U3 is connected in series to the main control chip to output a load current of 1.8V. The plurality of capacitors are connected in parallel to the first pin or the fifth pin of the second transformer U3 respectively. 6 . The test circuit for compatibility between a main control chip and a storage chip according to claim 1 , wherein the test platform module further comprises a reset button, and the reset button is connected to the main control chip.

7. The test circuit for compatibility between the main control chip and the memory chip according to claim 5, characterized in that: The first voltage-to-number conversion circuit is used to convert the first load current into a second load current, and the second load current is output to the main control chip and the socket of the object to be tested respectively, so as to be used for powering the main control chip and the socket of the object to be tested; The second voltage-to-number conversion circuit is used to convert the first load current into a third load current, and the third load current is output to the main control chip.

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