System and method for managing cache hierarchy

Abstract

The present invention relates to a system and method for managing a cache hierarchy. A processor core is disclosed; one or more low-level caches accessible by the processor core; a high-level cache accessible by the processor core and the one or more low-level caches; and a controller for: counting low-level cache victims evicted from the one or more low-level caches; when the count of the low-level cache victims is not greater than a threshold number, storing each of the low-level cache victims in a system memory; and when the count of the low-level cache victims is greater than the threshold number, storing one or more low-level cache victims evicted after exceeding the threshold number in the high-level cache.

Description

[0001] This application is a divisional application of the application with application number 201780054334.9, application date September 1, 2017, and invention name “System and method for delayed cache utilization”. Technical Field

[0002] The present application relates to memory systems, and more particularly to a system and method for delayed cache utilization. Background Art

[0003] Processing systems often use memory subsystems with multiple levels of cache. It is often advantageous to disable such caches when not in use (i.e., "power off"). In order to disable the cache, the cache is flushed and any valid lines are sent to the system memory. However, power is consumed when searching the high-level cache to obtain valid cache lines sent to the memory. Some traditional memory subsystems use tracking hardware outside the cache to track a set of validity bits indicating the approximate occupied area of ​​the cache (i.e., where the valid cache lines are located within the cache), sometimes referred to as "way valid" or "sector valid" bits, to help search for the speed of valid lines. If the valid lines are not widely distributed on the cache, the use of such validity bits can speed up the flushing. However, the process of searching for valid lines and flushing the cache in preparation for disabling the cache utilizes a large amount of power or a large number of clock cycles. Summary of the invention

[0004] In one aspect, the present application provides a method for managing cache utilization in a processing system (100), the method comprising: in response to enabling a higher level cache (140), counting lower level cache victims (250) evicted from one or more lower level caches (131 to 134); when the count (110) of the lower level cache victims is not greater than a threshold number, storing each of the lower level cache victims to a memory (116) without storing the lower level cache victims to the higher level cache; and when the count of the lower level cache victims is greater than the threshold number, storing each lower level cache victim evicted after exceeding the threshold number to the higher level cache.

[0005] In another aspect, the present application provides a system (100), comprising: a processor core (111 to 114); one or more lower level caches (131 to 134) accessible by the processor core; a higher level cache (140) accessible by the processor core and the one or more lower level caches; and a controller (142) for accessing the one or more lower level caches and the higher level cache, wherein the controller is configured to: count (110) lower level cache victims evicted from the one or more lower level caches in response to enabling the higher level cache; store each of the lower level cache victims in a system memory (116) without storing the lower level cache victims in the higher level cache when the count of the lower level cache victims is not greater than a threshold number; and store each lower level cache victim evicted after exceeding the threshold number in the higher level cache when the count of the lower level cache victims is greater than the threshold number.

[0006] The present application provides, in yet another aspect, a method for managing cache utilization, the method comprising: storing a cache victim history, the cache victim history associating a number of cache victims with each time period in a set of active time periods of a lower-level cache; determining a threshold number of lower-level cache victims to be sent to memory without being stored in a higher-level cache; and in response to enabling the higher-level cache, storing the threshold number of lower-level cache victims to system memory without writing to the higher-level cache after enabling the higher-level cache.

[0007] In yet another aspect, the present application provides a method for managing cache utilization, the method comprising: in response to enabling a higher-level cache, counting lower-level cache victims sent to the higher-level cache; and when the count (110) of the lower-level cache victims is not greater than a threshold number, storing each of the lower-level cache victims in the higher-level cache, and storing the location of the higher-level cache storing the lower-level cache victims in a dump flush table. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0009] Figure 1 Included is an illustration of an example system for memory management utilizing lazy caching techniques in accordance with some embodiments.

[0010] Figure 2Including according to some embodiments Figure 1 Illustration of an example delayed caching process in a system of FIG.

[0011] Figure 3 Included is a flow chart illustrating an example method for managing cache utilization based on lazy caching after cache enablement in accordance with some embodiments.

[0012] Figure 4 Included is a flow chart illustrating an example method for training threshold parameters for a delay caching process for memory management in accordance with some embodiments.

[0013] Figure 5 A flow chart illustrating an example method for cache flushing of a cache subject to delays is included according to some embodiments.

[0014] Figure 6 Including according to some embodiments Figure 1 An illustration of another example of a delay caching process in a system of FIG.

[0015] Figure 7 A flow chart illustrating an example method of memory management based on a lazy cache process utilizing a flush table according to some embodiments is included.

[0016] Figure 8 A flow chart illustrating an example method for flushing a cache using a flush table according to some embodiments is included.

[0017] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0018] Figures 1 to 8An example system and method for cache management using a delayed cache process after cache enablement is shown to reduce the power and cycle costs caused by flushing the cache when the cache is subsequently disabled. In an example embodiment, a system includes one or more processor cores and a memory subsystem, the memory subsystem including at least a low-level cache and a high-level cache, as well as a memory controller and a system memory. The high-level cache is enabled (that is, changes from a low-power state to a high-power state) in response to activity at one or more associated processor cores. In response to enabling the high-level cache, the system counts cache lines transferred from or removed from the low-level cache. Such transferred or removed cache lines are referred to herein as "low-level cache victims." When the count of low-level cache victims does not exceed a specified threshold number, the low-level cache victims are sent to the system memory and, for example, are not written to the high-level cache. When the count reaches the threshold number, any subsequent low-level cache victims are permitted to be stored in the high-level cache. Therefore, caching the low-level cache victims at the high-level cache is delayed until the threshold number of low-level cache victims is reached. Therefore, the higher level cache remains empty for a longer time after it is enabled, and therefore, if the higher level cache is disabled soon after being enabled, it is easier for the higher level cache to transition to the disabled state without expending time and energy searching for and transferring valid cache lines from the higher level cache to system memory.

[0019] In an alternative embodiment, when the higher-level cache is enabled, the system counts the lower-level cache victims issued after the higher-level cache is enabled. When the count does not exceed a threshold number, the lower-level cache victims are stored in the higher-level cache and a list of cache line addresses or other locations in the higher-level cache storing cache level victims (this list is referred to herein as a "dump-purge table") is stored at the system. Optionally, the memory controller also stores an indicator indicating whether the count exceeds a threshold. If the higher-level cache is disabled and the count does not exceed the threshold, the system implements a deactivation process that accesses the dump-purge table and dumps the cache lines of the higher-level cache associated with the specific cache line addresses stored in the dump-purge table. Alternatively, when the count exceeds a threshold number with the higher level cache disabled, the memory is disabled according to a different deactivation process, such as a process based on tracking valid bits, identifying ways or other areas used to store cache victims or otherwise occupied by cache victims, flushing those identified ways of the higher level cache used to store lower level cache victims, and disabling the higher level cache. Thus, after a short period of time in a high power state, valid cache lines can be more easily identified and transferred before transitioning to a low power state, thereby reducing the time and power consumption associated with transitioning between power states.

[0020] Figure 1 A processing system 100 is shown in accordance with at least some embodiments. In the example shown, the processing system 100 includes a computing complex 102, a cache hierarchy 104, a memory controller 106, and a south bridge 108. The computing complex 102 includes a plurality of processor cores, such as four processor cores 111, 112, 113, 114. The processor cores include, for example, central processing unit (CPU) cores, graphics processing unit (GPU) cores, digital signal processor (DSP) cores, or combinations thereof. It will be appreciated that the number of processor cores of the computing complex 102 can be less than or greater than four.

[0021] The memory controller 106 operates as an interface between the cache hierarchy 104 and the system memory 116. Thus, data to be cached in the cache hierarchy 104 is typically manipulated as blocks of data, referred to as cache lines, and addressed using physical addresses of the system memory 116 or otherwise located in the memory hierarchy. Cache lines are accessed from the system memory 116 by the memory controller 106 in response to memory requests from the cache hierarchy 104. Likewise, when a cache line containing modified data is evicted from the cache hierarchy 104 and therefore needs to be updated in the system memory 116, the system controller 106 manages this write-back process. The south bridge 108 operates as an interface between the cache hierarchy 104, the memory controller 106, and one or more peripherals 118 of the processing system 100 (e.g., a network interface, keyboard, mouse, display, and other input / output devices).

[0022] The cache hierarchy 104 includes two or more levels of cache. In the example shown, the cache hierarchy 104 includes three cache levels: Level 1 (L1); Level 2 (L2) and Level 3 (L3). For L1, the core complex 102 implements a small private cache for each processing core, which is shown as L1 caches 121, 122, 123, 124, each associated with a corresponding one of the processor cores 111 to 114. For L2, the core complex 102 implements a larger private cache for each processor core, which is shown as L2 caches 131, 132, 133, 134 corresponding to the processor cores 111 to 114, respectively. Each of the L2 caches 131 to 134 is private to its corresponding processor core, but the cache hierarchy 104 operates to maintain coherency between the L2 caches 131 to 134. In some embodiments, L2 caches 131 - 134 include, for example, direct-mapped caches or n-way set associative caches.

[0023] For the L3 cache level, the cache hierarchy 104 implements an L3 cache 140 that is shared by the processor cores of the compute complex 102 and, therefore, at least the L2 caches 131-134. The L3 cache 140 implements an L3 controller 142 and an L3 data array that includes a plurality of indices and a plurality of corresponding ways, each way being used to store a corresponding cache line at a corresponding index, and an L3 tag array for storing tag information associated with each index / way. The L3 data array and the L3 tag array are shown collectively and are referred to herein as L3 data / tag array 144. For purposes hereinafter, the L3 cache 140 is considered a high-level cache, while the L1 caches 121-124 and the L2 caches 131-134 are considered low-level caches (relative to the L3 cache 140).

[0024] As described in more detail below, when a higher level cache such as L3 cache 140 is enabled (i.e., transitions from a low power state to a high power state) in response to activity at one or more of the associated processor cores 111-114, counter 110 begins counting cache lines evicted from one or more of the lower level caches (i.e., "lower level cache victims") after the start of the enabling of L3 cache 140. For example, the count includes a count of L2 cache victims or a count of L1 and L2 cache victims to be removed from L1 caches 121-124 or L2 caches 131-134. Counter 110 may be implemented, for example, in L3 cache 140 (e.g., in L3 controller 142, such as Figure 1 ) or implemented in hardware external to L3 cache 140 (e.g., in memory controller 106).

[0025] While the count of lower level cache victims does not exceed a threshold number, in some embodiments, the cache hierarchy 104 prevents any lower level cache victims from being cached in the L3 cache 140, and thus each lower level cache victim is instead transferred to the system memory 116, for example, using the L3 controller 142. However, once the count of lower level cache victims meets or exceeds this threshold number, the cache hierarchy 104 permits any subsequent lower level cache victims to be cached in the L3 cache 140. Thus, in this approach, the L3 cache 140 remains "empty" (i.e., has no valid cache lines) for the first threshold number of lower level cache victims issued from the lower level cache. Thus, if the L3 cache 140 is disabled again before the threshold number of lower level cache victims are evicted from the lower level cache, the L3 cache 140 can be disabled without having to flush the L3 cache 140.

[0026] For illustration, now refer to Figure 2 In the specific example shown in FIG. 1 , a low-level cache victim 250 is evicted from a low-level cache (e.g., L2 caches 131 to 134) after L3 cache 140 is enabled. As shown, L3 cache 140 is shared by a group of low-level caches (e.g., L2 caches 131 to 134). Therefore, in some cases, this set of low-level cache victims 250 is a cumulative set of low-level cache victims from each of the low-level caches associated with the shared high-level cache. Alternatively, the set of low-level cache victims 250 is generated by a single low-level cache and provided to a dedicated high-level cache. As shown, after the L3 cache 140 is enabled, an initial subset 252 of the lower level cache victims 250 numbered no greater than a threshold number “N” are sent to the system memory 116 without being cached in the L3 cache 140, while any subsequent lower level cache victims 250 after this threshold number N (such as those in the subset 254 shown) are permitted to be cached in the L3 cache 140.

[0027] In systems where a higher level cache (e.g., an L3 cache) is disabled when the associated processor core is in a power-gated state and enabled when one or more of the associated processor cores are active, the higher level cache can be disabled more quickly when the cache is empty (i.e., contains no valid cache lines). In systems where processor cores and associated higher level caches frequently wake up and shut down, bypassing the higher level cache during such short activity periods as described herein can reduce power consumption and reduce the time associated with disabling the higher level cache. Thus, in Figure 2 In the illustrated example of , if the deactivation of the L3 cache 140 occurs before issuing the N lower level cache victims 250, the L3 cache 140 will be empty and therefore ready for deactivation without first flushing the valid cache lines of the L3 cache 140, thereby reducing the power consumed when deactivating the L3 cache 140.

[0028] Figure 3 1 is a diagram showing a method 300 for implementing a delayed cache after a higher level cache is enabled according to some embodiments. The method 300 is based on a higher level cache (e.g., L3 cache 140, Figure 1), as shown at block 302. In an example, the higher level cache is enabled in response to activity at an associated processor core or at an associated lower level cache. In response to enabling the higher level cache, the counter 110 begins counting lower level cache victims issued by the lower level caches (e.g., L2 caches 131 to 134), as shown at block 304.

[0029] As the lower level cache victims are transferred from the lower level cache (as shown at block 306), the L3 controller 142 increments the current count by one (count=count+1) for each lower level cache victim issued, as shown at block 308, and then compares the current count of the lower level cache victim to a threshold number, as shown at block 310. If the current count does not exceed the threshold number, access to the higher level cache is not granted, and thus the lower level cache victim bypasses storage in the higher level cache and is sent to system memory or a cache other than the higher level cache, as shown at block 312. However, when the current count associated with the lower level cache victim exceeds the threshold number (that is, when N lower level cache victims have been issued since the higher level cache was enabled), access to the higher level cache is granted, and thus the lower level cache victim is stored to the higher level cache, as shown at block 314. For example, the lower level cache victim is written to the higher level cache using a conventional protocol, such as using a way valid bit to identify a valid cache line.

[0030] Therefore, by preventing the first N (N=threshold number) lower level victims from being stored to the higher level cache after the higher level cache is powered on, the higher level cache remains empty for an initial period of time and for an initial number of lower level cache victims as shown by method 300. Thus, when the higher level cache is disabled after a short period of activity, the higher level cache is more likely to be empty and thus avoid a flush process prior to disabling the higher level cache.

[0031] In some implementations, the threshold number is a static number over multiple activations of the higher-level cache. In some embodiments, this static number can be established based on expected usage of the system or determined through modeling or simulation. Alternatively, the threshold number can be dynamically determined, for example, based at least in part on historical usage of the higher-level cache or counts of lower-level cache victims. For example, Figure 4As shown, method 400 includes L3 controller 142 tracking high-level cache usage, as shown at block 402. Alternatively, memory controller 106 tracks high-level cache usage and implements aspects of method 400. In an example, L3 controller 142 tracks a history of way valid bits to determine a usage history of the high-level cache. In an example, the valid bit history associates valid bit usage with a previous active time period of the high-level cache. In another example, the number or count of low-level cache victims transferred during the active period is tracked. For example, the cache victim count history associates low-level victim counts with previous active time periods.

[0032] As shown at block 404, the L3 controller 142 stores such high-level cache victim history (such as a valid bit history or a victim count history) in a table or other data structure of the L3 controller 142 or the memory controller 106. As shown at block 406, the L3 controller 142 or the memory controller 106 determines the threshold number based at least in part on the cache victim history. For example, the threshold number is determined based at least in part on the count of low-level cache victims transferred from the low-level cache during the previous active time period. In another example, the threshold number is determined using a high-level cache usage history based on the number of way valid bits or sector valid bits. In yet another example, the threshold number is also affected by an upper limit constraint on the threshold number or a lower limit constraint on the threshold number. For example, when the threshold number is dynamically determined based on the usage history, the L3 controller 142 prevents the threshold number from being set to a number greater than the upper limit constraint or prevents the threshold number from being set to a number less than the lower limit constraint. In some embodiments, determining the threshold number also includes determining the threshold number based on an algorithm that associates the number of clock cycles of power consumption or power failure with the high-level cache usage history.

[0033] Thus, the threshold number is determined using, for example, a lookup table, algorithm, heuristic, or histogram that relies on usage history data, such as a history of way valid or sector valid bits or a history of low level cache victim counts bounded by upper and lower constraints associated with previous activity time periods. Such a lookup table, algorithm, heuristic, or histogram is informed by, for example, power consumption or the number of powered off clock cycles.

[0034] To deactivate the higher-level cache, the system selects a particular deactivation procedure to implement based on whether a lower-level cache victim writes to the higher-level cache, or selects a deactivation procedure for the higher-level cache based at least in part on whether a count of lower-level cache victims exceeds a threshold number. Figure 5As shown, method 500 includes initiating deactivation of a higher level cache of system 100, as shown at block 502. Such deactivation is initiated, for example, in response to an associated core entering a power gated state.

[0035] The system 100 determines whether the higher level cache contains any valid cache lines, as shown at block 504. In the event that the higher level cache contains valid cache lines, the system selects to utilize the deactivation protocol of the cache flush process, and thus flushes the higher level cache according to this deactivation protocol, as shown at block 506. In an example, the system searches the tag array (e.g., L3 data / tag array 144) of the higher level cache for the way valid bit to identify the cache line of the higher level cache to be flushed, and may transfer the identified cache line victim to the system memory 116. Once the higher level cache is flushed, the system 100 places the higher level cache in a low power state, as shown at block 508.

[0036] Referring again to block 504, when the lower level cache victim is not writing to the higher level cache, the system 100 may select a deactivation protocol that does not include a flushing process, and thus the system 100 may bypass flushing of the higher level cache and instead directly power down the higher level cache without flushing, as shown at block 510. Thus, by preventing the first N lower level victims from storing to the higher level cache, the system may periodically bypass the time intensive and power consuming flushing process when the higher level cache is deactivated before the N+1th lower level victim is evicted from the lower level cache.

[0037] The above description describes an example implementation whereby a threshold number of initial lower level victims are prevented from being stored in the higher level cache after the higher level cache is enabled. Figure 6 In an alternative implementation shown by the example in , an initial set of lower level cache victims whose number is no greater than a threshold number ("N") is permitted to be stored in a higher level cache, such as the L3 cache 140. The L3 controller 142 or other component of the cache hierarchy 104 stores one or more flush tables 670 that store the locations of the corresponding lower level cache victims in the L3 cache 140 where the initial set is stored. Furthermore, as described below, in some implementations, this initial set of lower level cache victims is limited to a subset of the ways of the higher level cache (in Figure 6672 in the way), and lower level cache victims issued after this initial set may be stored in any of the entire set of ways (represented by block 674), subject to other way-based constraints. In addition, the L3 controller 142 stores an identifier 680 (e.g., a control bit or register value) to identify whether the number of lower level cache victims transferred to the higher level cache exceeds a threshold number. As described in more detail below, the flush table 670 may be utilized during the deactivation process to reduce the amount of time, clock cycles, or power usage used to deactivate the higher level cache.

[0038] Figure 7 A method 700 for populating the flush table 670 after enabling a higher level cache is shown according to some embodiments. The method 700 includes enabling a higher level cache (e.g., the L3 cache 140), as shown at block 702. As described above, the higher level cache is enabled, for example, in response to activity at one or more associated processor cores. As shown at block 704, the counter 110 begins counting lower level cache victims evicted from the lower level cache. As lower level cache victims are transferred from the lower level cache (as shown at block 706), the memory controller 106 increases the current count by one (count=count+1) for each lower level cache victim issued, as shown at block 708, and then compares the current count of the lower level cache victims to a threshold number, as shown at block 710. When the count does not exceed the threshold number, each lower level victim is written to the higher level cache, as shown at block 712. Optionally, the lower level cache victims are written to locations within the higher level cache that are constrained by way constraints that identify areas where a finite set of lower level cache victims are written. The locations within the higher level cache where the initial set of lower level cache victims are written may also be stored in the flush table 670, as shown at 714. Alternatively, the initial set of lower level cache victims may be written as a contiguous set, written to locations stored in the flush table 670.

[0039] Referring again to block 710, when the count of the lower level cache victims exceeds the threshold number, the system 100 writes any subsequent lower level cache victims to the higher level cache without a location-based restriction for writing the initial set of N lower level victims, as shown at block 716. Various algorithms and heuristics for determining the location of writing lower level cache victims on the higher level cache may be used to write such lower level cache victims. In each case, writing the lower level cache victims to the higher level cache may use the way valid bits of the tag array of the higher level cache to identify the used region.

[0040] In an alternative example, aspects of the above method may be implemented in the L3 controller 142. In addition, Figure 3 Method 300 and Figure 7 The method 700 may be combined with a first threshold number of lower level cache victims being sent to system memory without being written to the higher level cache and a second threshold number of lower level cache victims being stored at the higher level cache while the addresses are stored in the flush table.

[0041] When disabling the higher level cache, the system 100 can determine based on the count whether to utilize the flush table 670 to speed up flushing of the higher level cache before disabling, or whether to use other mechanisms, such as monitoring the valid bit or tracking the way valid bit. Figure 8 As shown, method 800 includes starting a power-off process for a higher level cache, as shown at block 802. A count of lower level cache victims transferred from lower level caches to higher level caches while the higher level cache is active is compared to a threshold number, as shown at block 804. Note that this threshold number is the same as the threshold number in Figure 7 The same threshold number is used at block 706 of .

[0042] If the count does not exceed the threshold number (i.e., if no more than the threshold number of lower level victims have been stored in the higher level cache), the system 100 may flush the higher level cache using the flush table 670. Thus, as shown at block 806, the system accesses the flush table 670 stored in the memory controller or other storage location. As described above with reference to Figure 7 As described, the flush table 670 stores an identifier of each location within the higher-level cache for each of the initial set of N lower-level victims. Using the flush table 670, the system 100 may flush the locations indicated in the flush table 670, as shown at 808, and then power off the higher-level cache, as shown at block 810.

[0043] Referring again to block 804, if the count of lower level cache victims does not exceed the threshold number, the system 100 is unable to flush the higher level cache using only the flush table 670. Therefore, the system 100 searches the valid bits associated with each cache line in the tag array of the higher level cache to identify a valid cache line, or accesses the way valid bits to identify a region within the higher level cache storing a valid cache line to be flushed, as shown at block 812. The identified valid cache line is flushed to the system memory 116 (or higher cache level), as shown at block 814, and the higher level cache may be deactivated, as shown at block 818. Given that searching the higher level cache to obtain a valid cache line or valid region of the higher level cache to be flushed may take more time than utilizing the flush table 670 that identifies a limited number of physical locations on the higher level cache, the deactivation process utilizing valid bits or table walking may be slower than the process utilizing the flush table 670.

[0044] In some embodiments, the above-described apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as those described above with reference to Figures 1 to 8 Processing system described. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used to design and manufacture these IC devices. These design tools are generally represented as one or more software programs. The one or more software programs include codes executable by a computer system to manipulate the computer system to operate on the code representing the circuit of one or more IC devices so as to execute at least a part of the process for designing or adapting a manufacturing system to manufacture the circuit. This code may include instructions, data, or a combination of instructions and data. Software instructions representing design tools or manufacturing tools are generally stored in a computer-readable storage medium that can be accessed by a computing system. Similarly, codes representing one or more stages of the design or manufacture of an IC device can be stored in and accessed from the same computer-readable storage medium or different computer-readable storage media.

[0045] A non-transitory computer-readable storage medium may include any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact disks (CDs), digital versatile disks (DVDs), Blu-ray disks), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical system (MEMS)-based storage media. A computer-readable storage medium may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or flash memory based on a universal serial bus (USB)), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0046] In some embodiments, certain aspects of the above-mentioned technology can be implemented by executing software by one or more processors of a processing system. The software includes one or more executable instruction sets stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data, which manipulate the one or more processors to perform one or more aspects of the above-mentioned technology when executed by one or more processors. Non-transitory computer-readable storage media may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, caches, random access memories (RAM), or one or more other non-volatile memory devices, etc. The executable instructions stored on the non-transitory computer-readable storage medium may be in source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0047] It should be noted that not all of the above-mentioned activities or elements are necessary, a part of a specific activity or device may not be necessary, and in addition to those activities and elements described above, one or more other activities may be performed or other elements may be included. In addition, the order in which the activities are listed is not necessarily the order in which the activities are performed. Moreover, the concepts have been described with reference to specific embodiments. However, it should be understood by those skilled in the art that various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0048] The benefits, other advantages and solutions to the problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to the problems and any features that may cause any benefit, advantage or solution to appear or become more apparent should not be interpreted as decisive, necessary or essential features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, because it is obvious to those skilled in the art who benefit from the teachings herein that the disclosed subject matter can be modified and practiced in different but equivalent ways. Except as described in the appended claims, it is not intended to limit the details of the construction or design shown in this article. It is therefore obvious that the specific embodiments disclosed above can be changed or modified and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is set forth in the appended claims.

Claims

1. A method for managing a cache hierarchy having a high-level cache and one or more low-level caches, the method comprising: counting low level cache victims evicted from one or more low level caches; storing each of the low level cache victims to a system memory when the count of the low level cache victims is not greater than a threshold number; as well as When the count of the lower level cache victims is greater than the threshold number, one or more lower level cache victims evicted after exceeding the threshold number are stored in a higher level cache.

2. The method of claim 1, wherein the threshold amount is static across multiple activations of the higher level cache.

3. The method of claim 1, further comprising: The threshold number is dynamically determined based at least in part on at least one of: a cache victim count history of the one or more lower-level caches; a valid bit history of the higher-level cache; an upper bound constraint on the threshold number; a lower bound constraint on the threshold number; power usage of the higher-level cache; or a power-off time of the higher-level cache.

4. The method of claim 1, further comprising: storing a cache victim history associating a number of cache victims with each time period in a set of one or more activity time periods of the one or more low-level caches; as well as The threshold number is determined based at least in part on the cache victim history. The method of claim 4 , wherein determining the threshold number comprises determining the threshold number based at least in part on an upper limit constraint on the threshold number.

6. The method of claim 1, further comprising: Tracking occupied regions of the higher level cache using valid bits; storing a valid bit history that associates usage of valid bits with one or more activity time periods of the higher level cache; and The threshold number is determined based at least in part on the valid bit history.

7. The method of claim 1 , wherein storing the one or more lower level cache victims evicted after exceeding the threshold number to the higher level cache comprises: A region of the higher level cache for storing lower level cache victims is selected based on a way constraint.

8. The method of claim 1, further comprising: In response to an indication that the higher level cache is to be disabled, a power off procedure for the higher level cache is selected based at least in part on whether the count of the lower level cache victims exceeds the threshold number.

9. The method of claim 8, wherein: The selective power-off process includes one of the following: When the count of the lower level cache victims does not exceed the threshold number, selecting a power off procedure in which the higher level cache is disabled without flushing the higher level cache; or When the count of the lower level cache victims exceeds the threshold number, a power off procedure is selected in which the higher level cache is disabled with the higher level cache flushed.

10. A system comprising: Processor core; one or more low-level caches accessible by the processor core; a high-level cache accessible by the processor core and the one or more low-level caches; as well as Controller for: counting low level cache victims evicted from the one or more low level caches; storing each of the low level cache victims to a system memory when the count of the low level cache victims is not greater than a threshold number; as well as When the count of the lower level cache victims is greater than the threshold number, one or more lower level cache victims evicted after exceeding the threshold number are stored in the higher level cache.

11. The system of claim 10, wherein the controller is further configured to dynamically determine the threshold number based at least in part on at least one of: a cache victim count history of the one or more lower level caches; a valid bit history of the one or more lower level caches; an upper bound constraint on the threshold number; a lower bound constraint on the threshold number; power usage of the higher level cache; or a power off time of the higher level cache.

12. The system of claim 10, wherein the controller is configured to: storing a cache victim history associating a number of cache victims with each time period in a set of one or more activity time periods of the one or more low-level caches; and The threshold number is determined based at least in part on the cache victim history.

13. The system of claim 10, wherein the controller is configured to: The occupied regions of the higher level cache are tracked using valid bits in a tag array of the higher level cache.

14. The system of claim 13, wherein the controller is configured to: storing a valid bit history that associates usage of the valid bit with one or more activity time periods of the higher level cache; and The threshold number is determined based at least in part on the valid bit history.

15. The system of claim 10, wherein the controller is to power off the higher level cache without flushing the higher level cache when the count of the lower level cache victims does not exceed the threshold number.

16. The system of claim 10, wherein the controller is to select a region of the higher level cache for storing lower level victims based on a way constraint when the count is not greater than the threshold number.

17. A method for managing a cache hierarchy having a high-level cache and at least one low-level cache, the method comprising: storing a cache victim history associating a number of cache victims with each time period in a set of one or more activity time periods of the low-level cache; Determine threshold quantity; as well as After enabling the higher level cache, a threshold number of lower level cache victims are stored to system memory without writing the lower level cache victims to the higher level cache.

18. The method of claim 17, wherein storing reaching the threshold number of lower level cache victims comprises determining a count of the lower level cache victims.

19. The method of claim 18, wherein storing reaching the threshold number of low level cache victims further comprises: When the count of the lower level cache victims is not greater than the threshold number, each of the lower level cache victims is stored to system memory without storing the lower level cache victims to the higher level cache.

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