Semiconductor device

Abstract

A semiconductor device includes a substrate, a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, both of which include a semiconductor material, a molded structure on the lower structure and including alternately stacked interlayer insulating films and conductive films, a channel hole penetrating the molded structure, a channel structure extending along a side wall of the channel hole, an isolation trench penetrating the molded structure and extending into the lower structure, and a polysilicon liner extending along a side wall of the isolation trench, the polysilicon liner being connected to the lower structure and including a semiconductor material.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2019-0067686, entitled "Semiconductor Device and Method of Fabricating the Same", filed on June 10, 2019 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0004] Semiconductor memory devices are memory devices that use semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices can be mainly divided into volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that lose stored data when power is interrupted. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM, etc. Non-volatile memory devices are memory devices that retain their data even when power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), resistive memory devices (e.g., phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), or resistive random access memory (RRAM)), etc. Summary of the Invention

[0006] An embodiment can be implemented by providing a semiconductor device comprising: a substrate; a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, both the sealing layer and the support layer comprising a semiconductor material; a molded structure located on the lower structure and including alternately stacked interlayer insulating films and conductive films; a channel via penetrating the molded structure; a channel structure extending along the sidewalls of the channel via; an isolation trench penetrating the molded structure and extending into the lower structure; and a polysilicon liner extending along the sidewalls of the isolation trench, the polysilicon liner being connected to the lower structure and comprising a semiconductor material.

[0007] Embodiments can be realized by providing a semiconductor device including a substrate, a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer each including a semiconductor material, a molded structure on the lower structure, the molded structure including alternately stacked interlayer insulating films and conductive films, a first isolation trench penetrating the molded structure and extending into the lower structure, a second isolation trench penetrating the molded structure and contacting the substrate, a first polysilicon liner and a second polysilicon liner extending along sidewalls of the first isolation trench and the second isolation trench, respectively, and each including a semiconductor material, a channel hole penetrating the molded structure between the first isolation trench and the second isolation trench, and a semiconductor pattern extending along sidewalls of the channel hole, wherein the second polysilicon liner is connected to the lower structure.

[0008] Embodiments can be realized by providing a semiconductor device including a substrate, a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer each including a semiconductor material, a molded structure on the lower structure, the molded structure including alternately stacked interlayer insulating films and conductive films, a first isolation trench penetrating the molded structure, a second isolation trench penetrating the molded structure, a first polysilicon liner and a second polysilicon liner extending along sidewalls of the first isolation trench and the second isolation trench, respectively, and including a semiconductor material, a channel hole penetrating the molded structure between the first isolation trench and the second isolation trench, and a semiconductor pattern extending along sidewalls of the channel hole, wherein a bottom surface of the first polysilicon liner contacts the substrate, and a bottom surface of the second polysilicon liner is in the lower structure. BRIEF DESCRIPTION OF DRAWINGS

[0009] Features will become apparent to those of ordinary skill in the art upon examination of the following details. It is also intended that any conclusions drawn be indicative of the preferred embodiments only and by no means a limitation of the scope of the application.

[0010] Figure 1 A circuit diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0011] Figure 2 A layout diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0012] Figure 3 shows a cross-sectional view taken along line A-A' of Figure 2

[0013] Figure 4 shows a layout view of a semiconductor device according to some embodiments of the disclosure.

[0014] Figure 5 shows a cross-sectional view taken along line B-B' of Figure 4

[0015] Figures 6 to 15 shows cross-sectional views of stages in a method of manufacturing a semiconductor device according to some embodiments of the disclosure. Figure 3 DETAILED DESCRIPTION

[0016] Figure 1 shows a circuit diagram of a semiconductor device according to some embodiments of the disclosure.

[0017] With reference to Figure 1 , the semiconductor device can include a plurality of common source lines CSL, a plurality of bit lines BL, a plurality of cell strings CSTR, a ground select transistor GST, and a gate induced drain leakage (GIDL) transistor GDT.

[0018] The bit lines BL can be arranged two-dimensionally. For example, the bit lines BL can be spaced apart from each other and can extend in a first direction X (e.g., longitudinally). The plurality of cell strings CSTR can be connected in parallel to each bit line BL. The cell strings CSTR can be connected to the common source lines CSL. For example, the cell strings CSTR can be between a bit line B1 and a common source line CSL.

[0019] In an embodiment, the common source lines CSL can be arranged two-dimensionally. For example, the common source lines CSL can be spaced apart from each other and can extend in a second direction Y (e.g., longitudinally). The same voltage can be applied to the common source lines CSL, or different voltages can be applied to the common source lines CSL and can be controlled individually.

[0020] Each cell string CSTR can include the GIDL transistor GDT connected to one of the common source lines CSL, the string select transistor SST connected to one of the bit lines BL, the ground select transistor GST connected to the GIDL transistor GDT, and a plurality of memory cell transistors MCT between the ground select transistor GST and the string select transistor SST. Each memory cell transistor MCT can include a data storage element. The GIDL transistor GDT, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT can be connected in series to each other.

[0021] ​​​A common source line CSL can be commonly connected to a source of the GIDL transistor GDT. A GIDL selection line GDSL, a ground selection line GSL, a plurality of word lines WL0 to WLn, and a string selection line SSL can be disposed between the common source line GSL and the bit line BL. The GIDL selection line GDSL can be connected to a gate electrode of the GIDL transistor GDT to turn on or turn off the GIDL transistor GDT, the ground selection line GSL can be connected to a gate electrode of the ground selection transistor GST to turn on or turn off the ground selection transistor GST, the word lines WL0 to WLn can be connected to gate electrodes of the storage cell transistors MCT to turn on or turn off the storage cell transistors MCT, and the string selection line SSL can be connected to a gate electrode of the string selection transistor SST to turn on or turn off the string selection transistor SST.

[0022] Figure 2 A layout view of a semiconductor device according to some embodiments of the disclosure is shown. Figure 3 A cross-sectional view taken along line A-A' of Figure 2 is shown.

[0023] Referring to Figure 2 and Figure 3 , the semiconductor device can include a substrate 100, a first channel structure CS1, a second channel structure CS2, a dummy channel structure DCS, a first isolation trench SH1, a second isolation trench SH2, and a lower structure 230. The first channel structure CS1 and the second channel structure CS2 can be collectively referred to as channel structures (CS1 and CS2), and the first isolation trench SH1 and the second isolation trench SH2 can be collectively referred to as isolation trenches (SH1 and SH2).

[0024] The substrate 100 can include a semiconductor substrate, such as a Si substrate, a Ge substrate, or a Si-Ge substrate. As used herein, the term "or" is not an exclusive term, for example, "A or B" includes A, B, or both A and B. In embodiments, the substrate 100 can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0025] The molded structure MS can include conductive films (GDSL, GSL, WL0 to WLn, and SSL) and an interlayer insulating film 400. The conductive films (GDSL, GSL, WL0 to WLn, and SSL) and the interlayer insulating film 400 can extend in a first direction X parallel to a top surface of the substrate 100.

[0026] The conductive films (GDSL, GSL, WL0 to WLn, and SSL) and the interlayer insulating film 400 can be alternately stacked in a third direction Z perpendicular to the top surface of the substrate 100. For example, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can be sequentially stacked on the substrate 100 along the third direction Z to be spaced apart from each other, and the interlayer insulating film 400 can be between the conductive films (GDSL, GSL, WL0 to WLn, and SSL) and between the conductive films (GDSL, GSL, WL0 to WLn, and SSL) and the lower structure 230. For example, as shown in Figure 3 FIG. 1, the molded structure MS can include the interlayer insulating film 400 and the conductive films (GDSL, GSL, WL0 to WLn, and SSL) stacked on the substrate 100.

[0027] The interlayer insulating film 400 can be stacked between the conductive films (GDSL, GSL, WL0 to WLn, and SSL) and can be formed along the sidewalls of each isolation trench (SH1 and SH2) and between the isolation trench (SH1 and SH2) and the support layer 210.

[0028] In an embodiment, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can have the same thickness. In an embodiment, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can have different thicknesses.

[0029] In an embodiment, a lowermost (e.g., closest to the substrate 100 in the third direction Z) of the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can be a GIDL select line GDSL. In an embodiment, an uppermost (e.g., farthest from the substrate 100 in the third direction Z) of the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can be a string select line SSL. Figure 1 In an embodiment, an intermediate conductive film between the lowermost conductive film and the uppermost conductive film of the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can be a ground select line GSL and / or a word line WL0 to WLn. Figure 1 Figure 1 The conductive films (GDSL, GSL, WL0 to WLn, and SSL) can include a conductive material. In an embodiment, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can include, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni) or a semiconductor material such as Si.

[0030] The conductive films (GDSL, GSL, WL0 to WLn, and SSL) can include a conductive material. In an embodiment, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can include, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni) or a semiconductor material such as Si.

[0031] ​The interlayer insulating film 400 can include an insulating material. In embodiments, the interlayer insulating film 400 can include, for example, silicon oxide, such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate glass (TEOS), or high-density plasma chemical vapor deposition (HDP-CVD) silicon oxide.

[0032] The channel structures (CS1 and CS2) and the dummy channel structure DCS can be formed along sidewalls of each channel hole extending in the third direction Z to penetrate the mold structure MS. For example, the channel structures (CS1 and CS2) and the dummy channel structure DCS can penetrate the conductive films (GDSL, GSL, WL0 to WLn, and SSL) and the interlayer insulating film 400 on the substrate 100. In embodiments, the channel structures (CS1 and CS2) and the dummy channel structure DCS can be formed, for example, as a column. For example, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can intersect the channel structures (CS1 and CS2) and the dummy channel structure DCS.

[0033] A plurality of first channel structures CS1, a plurality of second channel structures CS2, and a plurality of dummy channel structures DCS can be formed. For example, as shown in FIG. 1A, the plurality of first channel structures CS1, the plurality of second channel structures CS2, and the plurality of dummy channel structures DCS can be arranged along the second direction Y and along the third direction Z. The channel structures (CS1 and CS2) and the dummy channel structure DCS can be between the first isolation trench SH1 and the second isolation trench SH2. Figure 2

[0034] The channel structures (CS1 and CS2) and the dummy channel structure DCS can include a semiconductor pattern 108. The semiconductor pattern 108 can be connected to the substrate 100 through the mold structure MS. For example, the semiconductor pattern 108 can extend in the third direction Z. In embodiments, the semiconductor pattern 108 can be formed, for example, in the shape of a cup. For example, the channel structures (CS1 and CS2) and the dummy channel structure DCS can include a fill insulating pattern 112 and a semiconductor pattern 108 extending conformally along a bottom surface and sidewalls of the respective fill insulating pattern 112. In embodiments, the fill insulating pattern 112 can include, for example, silicon oxide. In embodiments, the semiconductor pattern 108 can be formed in various other shapes, such as a cylindrical shape, a rectangular container, or a non-hollow column shape.

[0035] ​In an embodiment, the semiconductor pattern 108 can be formed of, for example, polysilicon. The semiconductor pattern 108 can completely fill the channel structures (CS1 and CS2) and the dummy channel structure DCS. In an embodiment, the filling insulating pattern 112 can not be formed. In an embodiment, the semiconductor pattern 108 can be formed along a surface of the filling insulating pattern 112, so as not to fill the channel structures (CS1 and CS2) and the dummy channel structure DCS.

[0036] The cover film 110 can be formed on the channel structures (CS1 and CS2) and the dummy channel structure DCS. For example, the cover film 110 can be on the filling insulating pattern 112. In an embodiment, as shown, a top surface of the cover film 110 can be on a same plane as a top surface of the semiconductor pattern 108. In an embodiment, the top surface of the semiconductor pattern 108 can be on a same plane as a top surface of the filling insulating pattern 112. In an embodiment, the cover film 110 can be on the top surface of the filling insulating pattern 112 and on the top surface of the semiconductor pattern 108.

[0037] The cover film 110 can be formed of a same material as the semiconductor pattern 108. In an embodiment, the cover film 110 can be formed of, for example, polysilicon.

[0038] The tunnel insulating film 106 can be formed along a sidewall of each of the channel structures (CS1 and CS2) and the dummy channel structure (DCS). For example, the tunnel insulating film 106 can be formed to partially surround the sidewall of each semiconductor pattern 108. The tunnel insulating film 106 can extend in the third direction Z.

[0039] The tunnel insulating film 106 can include, for example, silicon oxide or silicon oxynitride. In an embodiment, the tunnel insulating film 106 can be formed to include a double layer of a silicon oxide film and a silicon nitride film. For convenience, the tunnel insulating film 106 will be described below as including silicon oxide.

[0040] The charge storage film 104 can be formed on the tunnel insulating film 106. For example, the tunnel insulating film 106 can be between the semiconductor pattern 108 and the charge storage film 104. The charge storage film 104 can extend in the third direction Z.

[0041] Charges that tunnel through the tunnel insulating film 106 from the semiconductor pattern 108 can be stored in the charge storage film 104. The charges stored in the charge storage film 104 can be changed by, for example, Fowler-Nordheim tunneling caused by a voltage difference between the semiconductor pattern 108 and the conductive films (GDSL, GSL, WL0 to WLn, and SSL).

[0042] The charge storage film 104 can include, for example, silicon nitride, silicon oxynitride, silicon-rich nitride, or nanocrystal silicon. For convenience, the charge storage film 104 will be described hereinafter as including silicon nitride.

[0043] The blocking insulating film 102 can be on the charge storage film 104. For example, the charge storage film 104 can be between the tunnel insulating film 106 and the blocking insulating film 102.

[0044] In embodiments, the blocking insulating film 102 can be, for example, between the charge storage film 104 and the conductive films (GDSL, GSL, WL0 to WLn, and SSL). In embodiments, the blocking insulating film 102 can, for example, surround the conductive films (GDSL, GSL, WL0 to WLn, and SSL).

[0045] The blocking insulating film 102 can include, for example, silicon oxide or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material can include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or a combination thereof. For convenience, the blocking insulating film 102 will be described hereinafter as including silicon oxide.

[0046] The lower structure 230 can be below the molded structure MS (e.g., closer to the substrate 100 in the third direction Z than the molded structure MS). The lower structure 230 can include the support layer 210 and the sealing layer 220. The sealing layer 220 can include the docking layer 224 in the channel structure (CS1 and CS2) and the sub-docking layer 222 outside of each channel structure (CS1 and CS2).

[0047] The support layer 210 and the sealing layer 220 can be formed of the same material as the semiconductor pattern 108. In embodiments, the support layer 210 and the sealing layer 220 can be formed of, for example, polysilicon. In embodiments, the support layer 210 and the sealing layer 220 can include, for example, the same material.

[0048] The support layer 210 can help prevent, for example, collapse of the semiconductor device as the semiconductor device becomes taller in the third direction Z.

[0049] The sealing layer 220 can transport current to or receive current from the second isolation trench SH2 (e.g., the structure in the second isolation trench SH2) that functions as a common source line through the low resistance and through the docking layer 224 in the channel structure (CS1 and CS2) and the sub-docking layer 222 connected to the docking layer 224. The sealing layer 220 can be formed by forming a sidewall profile of the second isolation trench SH2, and any defects that can be generated in, for example, the substrate 100 when etching the sealing layer 220 can be reduced.

[0050] The isolation trenches (SH1 and SH2) (e.g., structures in the isolation trenches SH1 and SH2) can be connected to the substrate 100 through the molded structure MS. For example, the first isolation trench SH1 can isolate the channel structures adjacent to each other. For example, the second isolation trench SH2 can be a common source line GSL or can accommodate a common source line GSL.

[0051] In embodiments, the first polysilicon liner 302 can be on sidewalls of the first isolation trench SH1, and the second polysilicon liner 306 can be on sidewalls of the second isolation trench SH2. The first sub-polysilicon liner 304 can fill an interior (e.g., a remaining portion) of the first isolation trench SH1, and the second sub-polysilicon liner 308 can fill an interior (e.g., a remaining portion) of the second isolation trench SH2.

[0052] In embodiments, the first polysilicon liner 302 and the second polysilicon liner 306 can comprise the same material, such as polysilicon. In embodiments, the first sub-polysilicon liner 304 and the second sub-polysilicon liner 308 can comprise the same material, such as polysilicon. In embodiments, the first polysilicon liner 302 and the first sub-polysilicon liner 304 can comprise the same material. In embodiments, the second polysilicon liner 306 and the second sub-polysilicon liner 308 can comprise the same material. The first polysilicon liner 302 and the second polysilicon liner 306 can be collectively referred to as polysilicon liners (302 and 306), and the first sub-polysilicon liner 304 and the second sub-polysilicon liner 308 can be collectively referred to as sub-polysilicon liners (302 and 306).

[0053] The second polysilicon liner 306 can extend along sidewalls of the second isolation trench SH2 and can be connected to the seal layer 220 of the lower structure 230 underneath the second channel structure CS2. For example, a bottom surface 303 of the first polysilicon liner 302 can be in contact with the substrate 100, and a bottom surface 307 of the second polysilicon liner 306 can be in the lower structure 230, such that the second polysilicon liner 306 can be connected to the lower structure 230.

[0054] For example, the seal layer 220 can transport current to or receive current from the second polysilicon liner 306 of the second isolation trench SH2 through the docking layer 224 formed inside the second channel structure CS2 and the sub-docking layer 222 connected to the docking layer 224, and through low resistance. The seal layer 220 can be formed by the formation of the second polysilicon liner 306 that forms the sidewall profile polysilicon liner of the second isolation trench SH2, and any defects that can be generated in the substrate 100 when etching the seal layer 220 are reduced.

[0055] In one embodiment, a highly doped region, including a portion of the bottom surface 307 of the second polysilicon liner 306 including the second isolation trench SH2, may be present in the substrate 100.

[0056] Figure 4 A layout diagram of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 5 It shows along Figure 4 The cross-sectional view taken by line B-B'. The following will describe... Figure 4 and Figure 5 Semiconductor devices, mainly concentrated in and Figure 2 and Figure 3 Differences in semiconductor devices.

[0057] refer to Figure 4 and Figure 5 The electrode substrate 600 (which serves as a common source electrode) can be formed on the bottom surface 303 of the first isolation trench SH1, the bottom surface 307 of the second isolation trench SH2, the bottom surface of the channel structure (CS1 and CS2), the bottom surface of the dummy channel structure DCS, the bottom surface of the lower structure 230, and the bottom surface of the interlayer insulating film 400.

[0058] A highly doped region 610 (which includes a portion of the bottom surface 307 of the second polysilicon liner 306 of the second isolation trench SH2) may be present in the electrode substrate 600. The concentration of the highly doped region 610 is higher than that of the electrode substrate 600.

[0059] For example, the isolation trenches (SH1 and SH2) can be floating.

[0060] A peripheral circuit region 500 (in which peripheral circuitry is disposed) may be formed on the bottom of the electrode substrate 600. The peripheral circuitry may include logic circuitry for selecting and controlling cells storing data. In some embodiments, the peripheral circuitry may include, for example, a row decoder, a column decoder, a sense amplifier, and control circuitry.

[0061] The first sub-polysilicon substrate 304 and the second sub-polysilicon substrate 308 may include an insulating material. In an embodiment, the first sub-polysilicon substrate 304 and the second sub-polysilicon substrate 308 may include the same material.

[0062] Figures 6 to 15 Manufacturing processes according to some embodiments of this disclosure are illustrated. Figure 3 Cross-sectional views of each stage in the process of developing semiconductor devices. Figure 5 Semiconductor devices are almost the same as Figure 3 The semiconductor device is the same, except that it includes a peripheral circuit region 500 and an electrode substrate 600 instead of a substrate 100. Therefore, the following will describe how to fabricate only the substrate 100. Figure 3semiconductor device. The description of the above materials for manufacturing Figure 3 the semiconductor device will be omitted.

[0063] Referring to Figure 6 A sealing layer sacrificial film 226 can be formed on the substrate 100. The substrate 100 can be a silicon substrate. After a portion of the sealing layer sacrificial film 226 is removed from the substrate 100, a support layer 210 can be formed on the sealing layer sacrificial film 226.

[0064] Referring to Figure 7 A preliminary molding structure MSP (which includes first sacrificial films 700 and second sacrificial films 710) can be formed on the support layer 210.

[0065] In an embodiment, the first sacrificial films 700 and the second sacrificial films 710 can be alternately stacked. For example, the first sacrificial films 700 and the second sacrificial films 710 can be sequentially and alternately stacked on the sealing layer sacrificial film 226 and the support layer 210 sequentially stacked on the substrate 100 to form the preliminary molding structure MSP.

[0066] In an embodiment, the first sacrificial films 700 and the second sacrificial films 710 can have the same thickness, as shown. In an embodiment, the thickness of the lowermost first sacrificial film 700 can be different from the thickness of the other first sacrificial films 700, or the second sacrificial films 710 can have different thicknesses. The first sacrificial films 700 can include, for example, silicon nitride, silicon oxynitride, silicon-rich nitride, or nanocrystalline silicon. For convenience, the first sacrificial films 310 will be described hereinafter as including silicon nitride.

[0067] The second sacrificial films 710 can define regions in which conductive films (GDSL, GSL, WL0 to WLn, and SSL) are to be formed. In an embodiment, the second sacrificial films 710 can include, for example, polysilicon.

[0068] Referring to Figure 8 Channel holes and dummy channel holes (which expose the substrate 100) can be formed by removing a portion of the preliminary molding structure MSP. For convenience, the channel holes and the dummy channel holes are not shown.

[0069] Thereafter, a barrier insulating film 102, a charge storage film 104, a tunnel insulating film 106, a semiconductor pattern 108, and a filling insulating pattern 112 can be formed in the channel holes and the dummy channel holes to cover sidewalls and bottoms of each of the channel holes and each of the dummy channel holes. The barrier insulating film 102, the charge storage film 104, the tunnel insulating film 106, the semiconductor pattern 108, and the filling insulating pattern 112 can be formed by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0070] In embodiments, the semiconductor pattern 108 may be formed in, for example, a cup shape. For example, the channel structures (CS1 and CS2) and the dummy channel structure DCS may include a fill insulating pattern 112 and a semiconductor pattern 108 conformally extending along the bottom and sidewalls of the respective fill insulating pattern 112. In embodiments, the fill insulating pattern 112 may include, for example, silicon oxide. In embodiments, the semiconductor pattern 108 may be formed in various other shapes, such as cylindrical, rectangular containers, or non-hollow cylinders.

[0071] The first channel structure CS1 and the second channel structure CS2 can be formed by depositing a barrier insulating film 102, a charge storage film 104, a tunnel insulating film 106, a semiconductor pattern 108, and a filling insulating pattern 112 in the channel vias, and the dummy channel structure DCS can be formed by depositing a barrier insulating film 102, a charge storage film 104, a tunnel insulating film 106, a semiconductor pattern 108, and a filling insulating pattern 112 in the dummy channel vias.

[0072] In one embodiment, the semiconductor pattern 108 may be formed of, for example, polysilicon. The semiconductor pattern 108 may completely fill the channel structures (CS1 and CS2) and the dummy channel structure DCS. In another embodiment, the filling insulating pattern 112 may not be provided. In yet another embodiment, the semiconductor pattern 108 may be formed along the surface of the filling insulating pattern 112, thereby not filling the channel structures (CS1 and CS2) and the dummy channel structure DCS.

[0073] The barrier insulating film 102 may include, for example, silicon oxide or a high-k material with a dielectric constant greater than that of silicon oxide. High-k materials may include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, or combinations thereof.

[0074] The charge storage film 104 may include, for example, silicon nitride, silicon oxynitride, silicon-rich nitride, or nanocrystalline silicon.

[0075] The tunnel insulating film 106 may include, for example, silicon oxide or silicon oxynitride. In an embodiment, the tunnel insulating film 106 may be formed as a bilayer comprising a silicon oxide film and a silicon oxynitride film.

[0076] refer to Figure 9 A cover film 110 can be formed on the filled insulating pattern 112. In an embodiment, such as Figure 9 As shown, the top surface of the cover film 110 may be on the same plane as the top surface of the semiconductor pattern 108. In an embodiment, the top surface of the semiconductor pattern 108 may be on the same plane as the top surface of the filling insulating pattern 112. In an embodiment, the cover film 110 may be formed on the top surface of both the filling insulating pattern 112 and the top surface of the semiconductor pattern 108.

[0077] Thereafter, referring to Figure 10 A first preliminary isolation hole SHp1 can be formed by removing a portion of the preliminary molding structure MSP adjacent to the first trench structure CS1 to expose the top surface of the substrate 100. In addition, a second preliminary isolation hole SHp2 can be formed by removing a portion of the preliminary molding structure MSP adjacent to the second trench structure CS2 to expose the sealing layer sacrificial film 226.

[0078] Thereafter, referring to Figure 11 The second sacrificial film 710 can be removed. The second sacrificial film 710 can be removed using the first preliminary isolation hole SHp1 and the second preliminary isolation hole SHp2 and using a pullback process. A first recess RC1 can be formed in the region where the second sacrificial film 710 has been removed. For example, the second sacrificial film 710 can include a material having etch selectivity with respect to the first sacrificial film 700. The barrier insulating film 102 can be partially removed when the second sacrificial film 710 is removed. For example, to compensate for any reduction in the thickness of the barrier insulating film 102, a portion of the barrier insulating film 102 exposed between the first sacrificial film 700 after the second sacrificial film 710 is removed can be removed, and a deposition process can be performed using the same material as that of the barrier insulating film 102.

[0079] Referring to Figure 11 and Figure 12 A diffusion barrier film can be conformally formed in the first recess RC1 between the first sacrificial film 700. The diffusion barrier film can be formed by CVD or ALD. The diffusion barrier film can include, for example, a nitride such as silicon nitride (SiN), silicon oxynitride (SiON), or a high-k nitride film. The high-k nitride film can include, for example, aluminum silicon oxynitride (AlSiON), aluminum oxynitride (AlON), HfSiON, or HfON. In an embodiment, the diffusion barrier film can include a material having low etch selectivity with respect to hydrogen fluoride (HF) gas. The conductive films (GDSL, GSL, WL0 to WLn, and SSL) can be formed on the diffusion barrier film.

[0080] The conductive films (GDSL, GSL, WL0 to WLn, and SSL) can include a conductive material. In an embodiment, the conductive films (GDSL, GSL, WL0 to WLn, and SSL) can include, for example, a metal such as W, Co, or Ni or a semiconductor material such as Si.

[0081] Referring to Figure 12 and Figure 13By performing a back-etching process on the first sacrificial film 700, a recess can be formed in the portion of the first sacrificial film 700 exposed by the first preliminary isolation hole SHp1 and the second preliminary isolation hole SHp2, and then the interlayer insulating film 400 can be deposited. The interlayer insulating film 400 can be formed by CVD or ALD.

[0082] The interlayer insulating film 400 can include an insulating material. In an embodiment, the interlayer insulating film 400 can include, for example, silicon oxide, such as BSG, PSG, BPSG, USG, TEOS, or HDP-CVD silicon oxide.

[0083] Referring to Figure 14 A portion of the interlayer insulating film 400 adjacent to the first channel structure CS1 can be removed to form a first isolation trench SH1 that exposes a top surface of the substrate 100, and a portion of the interlayer insulating film 400 adjacent to the second channel structure CS2 can be removed to form a second isolation trench SH2 that exposes a top surface of the sealing layer sacrificial film 226.

[0084] Thereafter, referring to Figure 3 and Figure 15 The sealing layer sacrificial film 226 can be removed. The sealing layer sacrificial film 226 can be removed using the second isolation trench SH2 and using a pull-back process. For example, the sealing layer sacrificial film 226 can include a material having etch selectivity with respect to the materials of other layers. Thereafter, the second polysilicon liner 306 can be implanted into the sealing layer contact region 228 exposed by the removal of the sealing layer sacrificial film 226 and into the second isolation trench SH2, the first polysilicon liner 302 can be implanted into the first isolation trench SH1, the first sub-polysilicon liner 304 can be implanted into the first isolation trench SH1, and the second sub-polysilicon liner 308 can be implanted into the second isolation trench SH2, thereby obtaining a semiconductor device of Figure 3

[0085] For example, the second polysilicon liner 306 can be formed on the sidewall of the second isolation trench SH2, while the second polysilicon liner 306 can be implanted into the sealing layer contact region 228. In this way, defects that can be generated in the lower structure 230 including the sealing layer 220 and the support layer 210 when the second isolation trench SH2 is formed by etching the lower structure 230 can be reduced. In addition, any increase in resistance that can be caused by defects in the substrate 100 when the second isolation trench SH2 is formed by etching the lower structure 230 can be prevented.

[0086] ​Accordingly, the seal layer 220 can transmit or receive current to or from the second polysilicon liner 306 of the second isolation trench SH2 through a low resistance and through the docking layer 224 formed in the second channel structure CS2 and the sub-docking layer 222 connected to the docking layer 224. The seal layer 220 can be formed by forming a sidewall profile of the second isolation trench SH2, and any defects that can be generated in the substrate 100 when etching the seal layer 220 can be reduced.

[0087] By summarizing and reviewing, the integration density of a nonvolatile memory device can be increased to meet user demands, such as excellent performance and low price. The integration density of a two-dimensional (2D) or planar memory device can be determined by the area occupied by each unit storage cell. For example, a three-dimensional (3D) memory device in which unit storage cells are arranged vertically has been considered.

[0088] One or more embodiments can provide a semiconductor device having a seal layer and an isolation trench, wherein the seal layer and a polysilicon liner filling the isolation trench contain the same material.

[0089] One or more embodiments can provide a semiconductor device having an isolation trench and a seal layer, wherein the seal layer and a polysilicon liner filling the isolation trench contain the same material, so that the semiconductor device has improved reliability.

[0090] One or more embodiments can provide a method of manufacturing a semiconductor device having an isolation trench and a seal layer, wherein the seal layer and a polysilicon liner filling the isolation trench contain the same material, so that the semiconductor device has improved reliability.

[0091] Example embodiments have been disclosed herein and, although a specific terminology is employed, they are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, attributes and / or benefits described in connection with a particular embodiment can be used separate from or in combination with features, attributes and / or benefits described in connection with other embodiments, and vice versa. Thus, various changes and modifications can be made to the teachings described herein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device comprising: a substrate; an understructure comprising a sealing layer on the substrate and a support layer on the sealing layer, both the sealing layer and the support layer comprising a semiconductor material; a molded structure on the understructure, the molded structure comprising interlaidly stacked interlayer insulating films and conductive films; a channel hole penetrating the molded structure; a channel structure extending along a sidewall of the channel hole; an isolation trench penetrating the molded structure and extending into the understructure; and a polysilicon liner extending along a sidewall of the isolation trench to completely cover the sidewall of the isolation trench, the polysilicon liner being connected to the understructure and comprising the semiconductor material.

2. The semiconductor device according to claim 1, further comprising a butt layer formed to penetrate a portion of the channel structure, the butt layer comprising the polysilicon liner. wherein, the substrate comprising the semiconductor material.

3. The semiconductor device of claim 1, wherein, 4. The semiconductor device according to claim 3, further comprising a peripheral circuit on the substrate, wherein: the understructure and the molded structure are sequentially on a first surface of the substrate, and the peripheral circuit is on a second surface of the substrate opposite the first surface of the substrate. the isolation trench is in an insulating material.

5. The semiconductor device of claim 4, wherein, 6. The semiconductor device according to claim 4, wherein: the substrate comprises a high concentration doped region in which the semiconductor material is doped to a high concentration, and a portion of a top surface of the high concentration doped region is in contact with the polysilicon liner. a sub-polysilicon liner is included in the isolation trench, the sub-polysilicon liner comprising the semiconductor material.

7. The semiconductor device of claim 1, wherein, the sealing layer and the support layer comprise the same semiconductor material.

8. The semiconductor device of claim 1, wherein, 9. A semiconductor device comprising: a substrate; an understructure comprising a sealing layer on the substrate and a support layer on the sealing layer, both the sealing layer and the support layer comprising a semiconductor material; a molded structure on the understructure, the molded structure comprising interlaidly stacked interlayer insulating films and conductive films; a first isolation trench penetrating the molded structure and extending into the understructure; a second isolation trench penetrating the molded structure and contacting the substrate; first and second polysilicon liners extending along sidewalls of the first and second isolation trenches, respectively, to completely cover the sidewalls of the first and second isolation trenches, respectively, and both comprising the semiconductor material; a channel hole penetrating the molded structure between the first and second isolation trenches; and a semiconductor pattern extending along a sidewall of the channel hole, ​ ​ The first polysilicon liner is connected to the lower structure.

10. The semiconductor device of claim 9, wherein, The substrate includes the semiconductor material.

11. The semiconductor device of claim 10, further comprising a peripheral circuit on the substrate, wherein: the lower structure and the molded structure are sequentially on a first surface of the substrate, and the peripheral circuit is on a second surface of the substrate opposite the first surface of the substrate.

12. The semiconductor device of claim 11, wherein, The first isolation trench and the second isolation trench are each in an insulating material.

13. The semiconductor device of claim 11, wherein: the substrate includes a high concentration doped region in which the semiconductor material is doped to a high concentration, and a portion of a top surface of the high concentration doped region is in contact with the second polysilicon liner.

14. The semiconductor device of claim 9, wherein, The first isolation trench and the second isolation trench each include a sub-polysilicon liner including the semiconductor material.

15. A semiconductor device, comprising: a substrate; a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer each including a semiconductor material; a molded structure on the lower structure, the molded structure including alternately stacked interlayer insulating films and conductive films; a first isolation trench penetrating the molded structure; a second isolation trench penetrating the molded structure; a first polysilicon liner and a second polysilicon liner extending along sidewalls of the first isolation trench and the second isolation trench, respectively, to completely cover the sidewalls of the first isolation trench and the second isolation trench, respectively, and including the semiconductor material; a channel hole penetrating the molded structure between the first isolation trench and the second isolation trench; and a semiconductor pattern extending along a sidewall of the channel hole, wherein: a bottom surface of the first polysilicon liner is in contact with the substrate, and a bottom surface of the second polysilicon liner is in the lower structure. The substrate includes the semiconductor material.

16. The semiconductor device of claim 15, wherein, 17. The semiconductor device of claim 16, further comprising a peripheral circuit on the substrate, wherein: the lower structure and the molded structure are sequentially on a first surface of the substrate, and the peripheral circuit is on a second surface of the substrate opposite the first surface of the substrate. The first isolation trench and the second isolation trench are each in an insulating material.

18. The semiconductor device of claim 17, wherein, 19. The semiconductor device of claim 17, wherein: the substrate includes a high concentration doped region in which the semiconductor material is doped to a high concentration, and a portion of a top surface of the high concentration doped region is in contact with the second polysilicon liner. The first isolation trench and the second isolation trench each include a sub-polysilicon liner including the semiconductor material.

20. The semiconductor device of claim 15, wherein, ​

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