Integrated circuit device including vertical memory

Abstract

An integrated circuit device is provided that includes a plurality of word lines, a string select line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string select line structure. The string select line structure includes a string select jog line that includes a lower horizontal extension extending in a horizontal direction at a first horizontal level that is higher than a horizontal level of the plurality of word lines, an upper horizontal extension extending in the horizontal direction at a second horizontal level that is higher than the first horizontal level, and a vertical extension connected between the lower horizontal extension and the upper horizontal extension.

Description

[0001] Priority is claimed on Korean Patent Application No. 10-2019-0068802, filed on June 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device including a vertical memory. BACKGROUND

[0003] As information communication devices become multifunctional, there is an increasing demand for higher memory capacity and higher integration. In addition, as memory cell sizes decrease, the operation and electrical connection of memory circuits and line structures are becoming increasingly complex. SUMMARY

[0004] According to an aspect of the inventive concept, there is provided an integrated circuit device including a substrate including a main surface, a plurality of word lines extending in a horizontal direction parallel to the main surface of the substrate over the substrate and stacked on each other in a vertical direction, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in the vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection jog line including a lower horizontal extension extending in the horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension extending in the horizontal direction at a second level higher than the first level, and a vertical extension connected between the lower horizontal extension and the upper horizontal extension.

[0005] According to another aspect of the inventive concept, there is provided an integrated circuit device including a substrate including a main surface, and a pair of word line cut regions extending longitudinally in a first horizontal direction over the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, a cell block region located between the pair of word line cut regions, wherein the first horizontal direction and the second horizontal direction are parallel to the main surface of the substrate. The integrated circuit device further includes a plurality of word lines extending in a third horizontal direction parallel to the main surface of the substrate in the cell block region and stacked on each other in a vertical direction, a string selection line structure stacked on the plurality of word lines in the cell block region, and a plurality of channel structures extending in the vertical direction through the plurality of word lines and the string selection line structure in the cell block region. The string selection line structure includes a string selection jog line including a lower horizontal extension extending in the horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension extending in the horizontal direction at a second level higher than the first level, and a vertical extension connected between the lower horizontal extension and the upper horizontal extension.

[0006] According to another aspect of the inventive concept, there is provided an integrated circuit device, the integrated circuit device comprising: a substrate; a plurality of word line cut regions arranged over the substrate; and a plurality of cell block regions each arranged individually between the plurality of word line cut regions and each comprising a string select line structure. In each of the plurality of cell block regions, the string select line structure comprises a string select jog line comprising a lower horizontal extension extending in a horizontal direction at a first level over the substrate, an upper horizontal extension extending in the horizontal direction at a second level higher than the first level, and a vertical extension connected between the lower horizontal extension and the upper horizontal extension. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the inventive concept will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the present inventive concept, and wherein:

[0008] FIG. 1 is a plan view showing some components of an integrated circuit device according to an embodiment of the inventive concept;

[0009] FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1 , FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1 , FIG. 2C is a cross-sectional view of FIG. 2A , FIG. 2D is a magnified cross-sectional view of a region CYA in FIG. 2B ,

[0010] FIG. 3A to FIG. 3D is a cross-sectional view showing a gate dielectric layer of an integrated circuit device according to an embodiment of the inventive concept in more detail;

[0011] FIG. 4A and FIG. 4B are cross-sectional views showing an integrated circuit device according to other embodiments of the inventive concept;

[0012] FIG. 5A and FIG. 5B are cross-sectional views showing an integrated circuit device according to other embodiments of the inventive concept, FIG. 5C is a magnified cross-sectional view of a region CYA in FIG. 5A , FIG. 5D is a magnified cross-sectional view of a region CYB in FIG. 5B ;

[0013] FIG. 6 is a cross-sectional view showing an integrated circuit device according to other embodiments of the inventive concept;

[0014] FIG. 7This is a schematic cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concept;

[0015] FIG. 8 This is a schematic cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concept;

[0016] FIG. 9A to FIG. 9J It is a sequential cross-sectional view used for reference when describing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0017] FIG. 10A and 10B This is a sequential cross-sectional view used for reference when describing a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept;

[0018] FIG. 11A to FIG. 11C These are sequential cross-sectional views used for reference when describing methods of manufacturing integrated circuit devices according to other embodiments of the inventive concept; and

[0019] FIG. 12A to FIG. 12G This is a sequential cross-sectional view used for reference when describing a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept. Specific Implementation

[0020] In the following description, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Here, the same reference numerals will denote the same elements, and redundant descriptions will be omitted for brevity. Throughout the description, terms such as “vertical,” “horizontal,” “above,” and “higher” are used to describe the relative positions of components. These terms are for descriptive purposes only and are intended only to describe the relative positions of components assuming the overall orientation of the device is the same as that shown in the drawings. However, the embodiments are not limited to the orientation of the device shown.

[0021] FIG. 1 This is a plan view illustrating some components of an integrated circuit device according to an embodiment of the inventive concept. FIG. 2A It is along FIG. 1 The sectional view taken by line A-A'. FIG. 2B It is along FIG. 1 The sectional view taken by line B-B'. FIG. 2C yes FIG. 2A An enlarged sectional view of region CYA in the middle. FIG. 2D yes FIG. 2B An enlarged sectional view of region CYB in the diagram.

[0022] Reference FIG. 1 as well as FIG. 2A to FIG. 2DThe integrated circuit device 100 can include a substrate 102 including a memory cell region MEC and a connection region CON. The substrate 102 can include a main surface 102M extending in a horizontal direction along an X-Y plane. The substrate 102 can include Si, Ge, or SiGe. A memory cell array MCA can be formed over an active region AC of the memory cell region MEC.

[0023] The connection region CON can be disposed adjacent to an edge side of the memory cell region MEC. Although FIG. 1 Only the connection region CON disposed on one side of the memory cell region MEC is illustrated, but the connection region CON can be disposed on each of two sides of the memory cell region MEC in a first horizontal direction (X direction).

[0024] The memory cell array MCA can include a memory stack STA1. The memory stack STA1 can include a ground select line GSL, a plurality of word lines WL1, WL2, …, WLn-1, and WLn, and a string select line structure SL1.

[0025] The plurality of word lines WL1, WL2, …, WLn-1, and WLn can extend over the memory cell region MEC in a horizontal direction parallel to the main surface 102M of the substrate 102, and are stacked on each other in a vertical direction (Z direction). The memory stack STA1 can include 48, 64, or 96 word lines WL1, WL2, …, WLn-1, and WLn, but is not limited thereto.

[0026] A plurality of word line cut regions WLC can extend in a first horizontal direction (X direction) parallel to the main surface 102M of the substrate 102. A unit block region UB can be defined by a pair of adjacent word line cut regions WLC among the plurality of word line cut regions WLC. The plurality of word line cut regions WLC can define a width of the plurality of word lines WL1, WL2, …, WLn-1, and WLn in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) in the unit block region UB.

[0027] Multiple common-source regions 172 may extend longitudinally in a first horizontal direction (X direction) within the substrate 102. In an example embodiment, the multiple common-source regions 172 may be doped regions heavily doped with n-type dopant. The multiple common-source regions 172 may serve as source regions for supplying current to vertical memory cells. Multiple common-source patterns CSP may extend longitudinally over the multiple common-source regions 172 in the first horizontal direction (X direction). The multiple common-source patterns CSP may be formed as part of a word line cut region WLC filling one side of each of multiple word lines WL1, WL2, ..., WLn-1 and WLn. The two sidewalls of the common-source pattern CSP may be surrounded by insulating spacers 192 in the word line cut region WLC.

[0028] In the memory cell array MCA, multiple channel structures 180 and multiple dummy channel structures D180 can extend longitudinally through the memory stack STA1 in a vertical direction (Z direction) perpendicular to the main surface 102M of the substrate 102.

[0029] The string select line structure SL1 can be arranged at a level higher than the level (height) of the multiple word lines WL1, WL2, ..., WLn-1 and WLn. As used herein, the term "level (height)" can refer to the distance from the main surface 102M of the substrate 102 in the vertical direction (Z direction or -Z direction). The cell block region UB in the memory stack STA1 may include a first string select region STR1, a second string select region STR2, and a third string select region STR3 arranged sequentially in the second horizontal direction (Y direction).

[0030] In the memory stack STA1, the serial select line structure SL1 may include a lower serial select line SSL1, an intermediate serial select line SSM2, an upper serial select line SSU3, and a serial select bend line SSMB.

[0031] like FIG. 2C and FIG. 2D As shown, the string selection bend line SSMB may include a lower horizontal extension HM1 extending horizontally at a first level LV1, an upper horizontal extension HM2 extending horizontally at a second level LV2 higher than the first level LV1, and a vertical extension VM connecting the lower horizontal extension HM1 and the upper horizontal extension HM2. The lower horizontal extension HM1, the upper horizontal extension HM2, and the vertical extension VM may be integrally connected.

[0032] The string selection bend line SSMB can be disposed only in the second and third string selection areas STR2 and STR3 among the first, second, and third string selection areas STR1, STR2, and STR3, the lower horizontal extension HM1 can be disposed in the third string selection area STR3, and the upper horizontal extension HM2 can be disposed in the second string selection area STR2. The vertical extension VM can be disposed between the second and third string selection areas STR2 and STR3.

[0033] The lower string selection line SSL1 can be disposed only in the first and second string selection areas STR1 and STR2 among the first, second, and third string selection areas STR1, STR2, and STR3. The lower string selection line SSL1 can extend in the horizontal direction at the first horizontal LV1 and can be spaced apart from the lower horizontal extension HM1 of the string selection bend line SSMB in the second horizontal direction (Y direction). The lower string selection line SSL1 can overlap the upper horizontal extension HM2 of the string selection bend line SSMB in the vertical direction (Z direction) in the second string selection area STR2.

[0034] The middle string selection line SSM2 can be disposed only in the first string selection area STR1 among the first, second, and third string selection areas STR1, STR2, and STR3. The middle string selection line SSM2 can extend in the horizontal direction at the second horizontal LV2 and can be spaced apart from the upper horizontal extension HM2 of the string selection bend line SSMB in the second horizontal direction (Y direction).

[0035] The lower string selection line SSL1 and the middle string selection line SSM2 can overlap in the vertical direction (Z direction) in the first string selection area STR1.

[0036] The upper string selection line SSU3 can be disposed only in the third string selection region STR3 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3. The upper string selection line SSU3 can extend in the horizontal direction at the second level LV2 and can be spaced apart from the upper horizontal extension HM2 of the string selection bend line SSMB in the second horizontal direction (Y direction). Each of a bottom surface of the middle string selection line SSM2, a bottom surface of the upper string selection line SSU3, and a bottom surface of the upper horizontal extension HM2 of the string selection bend line SSMB can extend at the second level LV2. At the second level LV2, the upper string selection line SSU3 can be spaced apart from the middle string selection line SSM2 in the second horizontal direction (Y direction) with the upper horizontal extension HM2 of the string selection bend line SSMB located between the upper string selection line SSU3 and the middle string selection line SSM2. The upper string selection line SSU3 can be stacked with the plurality of word lines WL1, WL2, …, WLn-1, and WLn in the vertical direction (Z direction) with the lower horizontal extension HM1 of the string selection bend line SSMB located between the upper string selection line SSU3 and the plurality of word lines WL1, WL2, …, WLn-1, and WLn.

[0037] The upper string selection line SSU3 can further include a protrusion SSUP extending from the second level LV2 to a level higher than the second level LV2 in a direction away from the base 102 at an end facing the upper horizontal extension HM2 of the string selection bend line SSMB.

[0038] At the second level LV2, the middle string selection line SSM2 and the upper horizontal extension HM2 of the string selection bend line SSMB can be spaced apart from each other with the string selection line cut region SSLC located between the middle string selection line SSM2 and the upper horizontal extension HM2 of the string selection bend line SSMB. The string selection line cut region SSLC can be filled with an isolation insulating layer 178. The isolation insulating layer 178 can be disposed between the middle string selection line SSM2 and the upper horizontal extension HM2 of the string selection bend line SSMB at the second level LV2. A level of a bottom surface of the isolation insulating layer 178 closest to the base 102 can be higher than the first level LV1. The isolation insulating layer 178 can be stacked with the lower string selection line SSL1 in the vertical direction (Z direction).

[0039] As shown in FIG. 18B, the isolation insulating layer 178 can include a plurality of isolation insulating portions 178P extending in a straight line in the first horizontal direction (X direction) between the first string selection region STR1 and the second string selection region STR2. The dummy channel structure D180 can extend longitudinally in the vertical direction (Z direction) between the respective isolation insulating portions 178P. The isolation insulating layer 178 can include an oxide layer. At least a portion of the string selection line cut region SSLC can be filled with an air gap. FIG. 1 As shown in FIG. 18B, the isolation insulating layer 178 can include a plurality of isolation insulating portions 178P extending in a straight line in the first horizontal direction (X direction) between the first string selection region STR1 and the second string selection region STR2. The dummy channel structure D180 can extend longitudinally in the vertical direction (Z direction) between the respective isolation insulating portions 178P. The isolation insulating layer 178 can include an oxide layer. At least a portion of the string selection line cut region SSLC can be filled with an air gap.

[0040] A first minimum separation distance D1 can be maintained between the lower string selection line SSL1 and the lower horizontal extension HM1 of the string selection bend line SSMB at the first level LV1. A second minimum separation distance D2 can be maintained between the middle string selection line SSM2 and the upper horizontal extension HM2 of the string selection bend line SSMB at the second level LV2. A third minimum separation distance D3 in the second horizontal direction (Y direction) between the lower string selection line SSL1 and the upper string selection line SSU3 can be greater than the first minimum separation distance D1.

[0041] The plurality of channel structures 180 can include a plurality of first channel structures 180A arranged in the first string selection region STR1, a plurality of second channel structures 180B arranged in the second string selection region STR2, and a plurality of third channel structures 180C arranged in the third string selection region STR3. The plurality of first channel structures 180A can pass through the ground selection line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, the lower string selection line SSL1, and the middle string selection line SSM2. The plurality of second channel structures 180B can pass through the ground selection line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, the lower string selection line SSL1, and the upper horizontal extension HM2 of the string selection bend line SSMB. The plurality of third channel structures 180C can pass through the ground selection line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, the lower horizontal extension HM1 and the upper string selection line SSU3 of the string selection bend line SSMB.

[0042] The plurality of dummy channel structures D180 can include a plurality of first dummy channel structures D180A arranged (i.e., aligned) in a line in the first horizontal direction (X direction) between the first string selection region STR1 and the second string selection region STR2, and a plurality of second dummy channel structures D180B arranged in a line in the first horizontal direction (X direction) between the second string selection region STR2 and the third string selection region STR3. The plurality of first dummy channel structures D180A can be arranged in a line in the first horizontal direction (X direction) between the middle string selection line SSM2 and the upper horizontal extension HM2 of the string selection bend line SSMB, and can be arranged individually between the plurality of isolation insulating portions 178P, respectively. Likewise, the plurality of second dummy channel structures D180B can be arranged in a line in the first horizontal direction between the lower string selection line SSL1 and the upper string selection line SSU3. In addition, the plurality of second dummy channel structures D180B can pass through the string selection bend line SSMB between the lower string selection line SSL1 and the upper string selection line SSU3.

[0043] Each of the ground select line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, and the string select line structure SL1 can include a metal, a metal silicide, a doped semiconductor, or a combination thereof. The metal can include tungsten, nickel, cobalt, or tantalum. The metal silicide can include tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide. The doped semiconductor can include polysilicon.

[0044] The insulating layer 176 can be disposed between the substrate 102 and the ground select line GSL, between the ground select line GSL and the word line WL1, and between adjacent word lines of the plurality of word lines WL1, WL2, …, WLn-1, and WLn. The first insulating layer 176A can be disposed between the word line WLn and the string select line structure SL1. The second insulating layer 176B can be disposed between the lower string select line SSL1 and the middle string select line SSM2, between the lower string select line SSL1 and the string select bend line SSMB, and between the first insulating layer 176A and the string select bend line SSMB. The third insulating layer 176C can be disposed between the string select bend line SSMB and the upper string select line SSU3. The third insulating layer 176C can include a portion that covers an upper surface of the middle string select line SSM2 and an upper surface of the string select bend line SSMB. An upper surface of the upper string select line SSU3 can be covered by the fourth insulating layer 176D. The third insulating layer 176C and the fourth insulating layer 176D can be covered by the fifth insulating layer 176E.

[0045] The insulating layer 176 and the first insulating layer 176A, the second insulating layer 176B, the third insulating layer 176C, the fourth insulating layer 176D, and the fifth insulating layer 176E can respectively surround the plurality of channel structures 180 and the plurality of dummy channel structures D180. Each of the insulating layer 176 and the first insulating layer 176A, the second insulating layer 176B, the third insulating layer 176C, the fourth insulating layer 176D, and the fifth insulating layer 176E can include silicon oxide, silicon nitride, or silicon oxynitride.

[0046] The plurality of channel structures 180 and the plurality of dummy channel structures D180 can be disposed to be spaced apart from each other at intervals in the X direction and the Y direction. Each of the plurality of channel structures 180 and the plurality of dummy channel structures D180 can include a gate dielectric layer 182, a channel region 184, a buried insulating layer 186, and a drain region 188.

[0047] The channel region 184 can include doped polysilicon and / or undoped polysilicon. The channel region 184 can have a cylindrical shape. An inner space of the channel region 184 can be filled with a buried insulating layer 186. The buried insulating layer 186 can include an insulating material. For example, the buried insulating layer 186 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an example embodiment, the buried insulating layer 186 can be omitted, and in this case, the channel region 184 can have a pillar structure in which there is no insulating space. The plurality of drain regions 188 of the plurality of channel structures 180 can be insulated from each other by an upper insulating layer 187. The plurality of drain regions 188 can include doped polysilicon, metal, conductive metal nitride, or a combination thereof. Examples of the metal that can constitute the plurality of drain regions 188 can include tungsten, nickel, cobalt, tantalum, etc. The upper insulating layer 187 can include an oxide layer, a nitride layer, or a combination thereof.

[0048] The plurality of word line cut regions WLC, the plurality of channel structures 180, the plurality of dummy channel structures D180, and the upper insulating layer 187 can be covered by an interlayer insulating layer 193. In the memory cell region MEC, a plurality of bit lines BL can extend in parallel to each other along a second horizontal direction (Y direction) on the interlayer insulating layer 193. A plurality of contact plugs 194 can be disposed between the plurality of channel structures 180 and the plurality of bit lines BL. The drain region 188 of each of the plurality of channel structures 180 can be connected to a corresponding bit line BL among the plurality of bit lines BL through the contact plug 194. The plurality of contact plugs 194 can fill a plurality of contact holes 193H formed in the interlayer insulating layer 193. The plurality of contact plugs 194 can be insulated from each other by the interlayer insulating layer 193. The interlayer insulating layer 193 can include an oxide layer, a nitride layer, or a combination thereof.

[0049] Each of the plurality of channel structures 180 can be a normal channel structure connected to any one of the plurality of bit lines BL to constitute a memory cell string of the memory cell array MCA. On the other hand, each of the plurality of dummy channel structures D180 can be a dummy channel structure not connected to the bit line BL and not contributing to the operation of the memory cell array MCA.

[0050] Although FIG. 2A to FIG. 2D It is shown that the plurality of channel structures 180 and the plurality of dummy channel structures D180 include the gate dielectric layer 182 and the gate dielectric layer 182 has a shape extending longitudinally in a vertical direction (Z direction) along the channel region 184, but the inventive concept is not limited thereto.

[0051] FIG. 3A is more specifically shown FIG. 2A to FIG. 2D a cross-sectional view of the gate dielectric layer 182 shown in FIG. 3A is shown FIG. 2A an enlarged view of the region CZ in

[0052] Referring to FIG. 3A , the gate dielectric layer 182 can have a structure including a tunneling dielectric layer TD, a charge storage layer CS, and a blocking dielectric layer BD formed in order from the channel region 184. The relative thicknesses of the tunneling dielectric layer TD, the charge storage layer CS, and the blocking dielectric layer BD are not limited to FIG. 3A the case shown in FIG. 1, and various modifications can be made.

[0053] The tunneling dielectric layer TD can include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. The charge storage layer CS can be a region in which electrons passing through the tunneling dielectric layer TD from the channel region 184 can be stored, and can include silicon nitride, boron nitride, silicon boron nitride, or doped polysilicon. The blocking dielectric layer BD can include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant higher than that of silicon oxide. The metal oxide can include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0054] FIG. 3B to FIG. 3D is a cross-sectional view illustrating example structures of gate dielectric layers 182A, 182B, and 182C that can be used instead of the gate dielectric layer 182 shown in FIG. 1. FIG. 3A

[0055] In an example embodiment, the integrated circuit device 100 can include the gate dielectric layer 182A shown in FIG. 2 instead of the gate dielectric layer 182. The gate dielectric layer 182A can have substantially the same configuration as that of the gate dielectric layer 182 shown in FIG. 1. However, the gate dielectric layer 182A can include a first blocking dielectric layer BD1 and a second blocking dielectric layer BD2 instead of the blocking dielectric layer BD. The first blocking dielectric layer BD1 can extend in parallel with the tunneling dielectric layer TD and the charge storage layer CS together with the channel region 184, and the second blocking dielectric layer BD2 can be disposed to surround the word line WL2. Each of the first blocking dielectric layer BD1 and the second blocking dielectric layer BD2 can include silicon oxide, silicon nitride, or a metal oxide. For example, the first blocking dielectric layer BD1 can include a silicon oxide layer, and the second blocking dielectric layer BD2 can include a metal oxide layer having a dielectric constant higher than that of the silicon oxide layer. FIG. 3B FIG. 3A In other example embodiments, the integrated circuit device 100 can include the gate dielectric layer 182B shown in FIG. 3 instead of the gate dielectric layer 182. The gate dielectric layer 182B can have substantially the same configuration as that of the gate dielectric layer 182 shown in FIG. 1. However, the gate dielectric layer 182B can include a first blocking dielectric layer BD1 and a second blocking dielectric layer BD2 instead of the blocking dielectric layer BD. The first blocking dielectric layer BD1 can extend in parallel with the tunneling dielectric layer TD and the charge storage layer CS together with the channel region 184, and the second blocking dielectric layer BD2 can be disposed to surround the word line WL2. Each of the first blocking dielectric layer BD1 and the second blocking dielectric layer BD2 can include silicon oxide, silicon nitride, or a metal oxide. For example, the first blocking dielectric layer BD1 can include a silicon oxide layer, and the second blocking dielectric layer BD2 can include a metal oxide layer having a dielectric constant higher than that of the silicon oxide layer.

[0056] In other example embodiments, the integrated circuit device 100 can include the gate dielectric layer 182B shown in FIG. 3 instead of the gate dielectric layer 182. The gate dielectric layer 182B can have substantially the same configuration as that of the gate dielectric layer 182 shown in FIG. 1. However, the gate dielectric layer 182B can include a first blocking dielectric layer BD1 and a second blocking dielectric layer BD2 instead of the blocking dielectric layer BD. The first blocking dielectric layer BD1 can extend in parallel with the tunneling dielectric layer TD and the charge storage layer CS together with the channel region 184, and the second blocking dielectric layer BD2 can be disposed to surround the word line WL2. Each of the first blocking dielectric layer BD1 and the second blocking dielectric layer BD2 can include silicon oxide, silicon nitride, or a metal oxide. For example, the first blocking dielectric layer BD1 can include a silicon oxide layer, and the second blocking dielectric layer BD2 can include a metal oxide layer having a dielectric constant higher than that of the silicon oxide layer. FIG. 3C ​​The gate dielectric layer 182B can have a surface facing the channel region 184 and a surface facing the insulating layer 176, and can be formed to cover the bottom surface, the top surface, and the sidewall of the word line WL2. The gate dielectric layer 182B can include a tunneling dielectric layer TD, a charge storage layer CS, and a blocking dielectric layer BD sequentially formed from the channel region 184.

[0057] In other example embodiments, the integrated circuit device 100 can include FIG. 3D The gate dielectric layer 182C can be arranged only between the word line WL2 and the channel region 184, and can be formed to cover only the sidewall of the word line WL2 without covering the bottom surface and the top surface of the word line WL2. The gate dielectric layer 182C can include a tunneling dielectric layer TD, a charge storage layer CS, and a blocking dielectric layer BD sequentially formed from the channel region 184.

[0058] As FIG. 1 As shown in FIG. 1C, in the connection region CON, the plurality of contact members 132 can be formed at the stepped connection unit 122 of the ground select line GSL and the stepped connection unit 124 of each of the plurality of word lines WL1, WL2, …, WLn-1, and WLn. In addition, in the connection region CON, the first contact member 134A, the second contact member 134B, the third contact member 134C, and the fourth contact member 134D can be formed at the string select line structure SL1. The first contact member 134A can be connected to the connection region S1 of the lower string select line SSL1. The second contact member 134B can be connected to the connection region S2 of the middle string select line SSM2. The third contact member 134C can be connected to the connection region S3 of the upper string select line SSU3. The fourth contact member 134D can be connected to the connection region S4 of the string select bend line SSMB.

[0059] The turn-on or turn-off of each of the lower string selection line SSL1, the middle string selection line SSM2, the upper string selection line SSU3, and the string selection meander line SSMB can be determined in accordance with the voltage applied through the first contact 134A, the second contact 134B, the third contact 134C, and the fourth contact 134D. Any one of the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3 can be selected in accordance with the voltage applied to the first contact 134A, the second contact 134B, the third contact 134C, and the fourth contact 134D. For example, in order to select only the first string selection region STR1 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3, the lower string selection line SSL1 and the middle string selection line SSM2 can be turned on, and the upper string selection line SSU3 and the string selection meander line SSMB can be turned off. In order to select only the second string selection region STR2 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3, the lower string selection line SSL1 and the string selection meander line SSMB can be turned on, and the middle string selection line SSM2 and the upper string selection line SSU3 can be turned off. In order to select only the third string selection region STR3 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3, the string selection meander line SSMB and the upper string selection line SSU3 can be turned on, and the lower string selection line SSL1 and the middle string selection line SSM2 can be turned off.

[0060] According to the integrated circuit device 100 described with reference to FIG. 1 and FIG. 2A to FIG. 2D Because the three string selection regions including the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3 are included in one cell block region UB, the width of one cell block region UB in the second horizontal direction (Y direction) can be increased compared to the case where two string selection regions are included in one cell block region UB. Therefore, even when the number of the stack of the word lines WL1, WL2, …, WLn-1, and WLn stacked in the vertical direction (Z direction) in the memory cell region MEC is increased in order to improve the integration, the undesirable physical change such as the falling or tilting of the memory stack STA1 can be prevented. In addition, because the three string selection regions including the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3 are included in one cell block region UB, the number of the channel structures per unit area in the memory cell region MEC can be increased. Therefore, even when the chip size of the integrated circuit device 100 is not increased, the integration of the integrated circuit device 100 can be effectively improved.

[0061] FIG. 4Aand FIG. 4B This is a cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concept, wherein, FIG. 4A Is along FIG. 1 A sectional view of the portion corresponding to the section cut by line A-A'. FIG. 4B Is along FIG. 1 A sectional view of the portion corresponding to the section cut by line B-B'. FIG. 4A and FIG. 4B In, with FIG. 2A to FIG. 2D The same reference numerals in the figures denote the same elements, and for the sake of brevity, their redundant descriptions will be omitted.

[0062] Reference FIG. 4A and FIG. 4B The integrated circuit device 200 may include a memory stack STA2 comprising a serial select line structure SL2. The serial select line structure SL2 may have a... FIG. 1 and FIG. 2A to FIG. 2D The serial select line structure SL1 of the integrated circuit device 100 shown in the figure has a substantially the same construction. However, the serial select line structure SL2 may include an upper serial select line SSU23 instead of an upper serial select line SSU3. Unlike the upper serial select line SSU3, the upper serial select line SSU23 may have a flat upper surface and may not include the protrusion SSUP.

[0063] The integrated circuit device 200 may include a fifth insulating layer 276E covering the string select line structure SL2. The fifth insulating layer 276E may include an insulating protrusion 276P that protrudes downward toward the substrate 102 in the vertical direction (Z direction) and contacts the upper surface of the string select line SSU23. The insulating protrusion 276P may be disposed between a third insulating layer 176C and a fourth insulating layer 176D.

[0064] More detailed construction information regarding the upper selection line SSU23 and the fifth insulation layer 276E can be found in the relevant section. FIG. 2A and FIG. 2B The upper selection line SSU3 and the fifth insulating layer 176E shown in the figure have essentially the same construction.

[0065] FIG. 5A to FIG. 5D This is a cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concept, wherein, FIG. 5A Is along FIG. 1 A sectional view of the portion corresponding to the section cut by line A-A'. FIG. 5B Is along FIG. 1 A sectional view of the portion corresponding to the section cut by line B-B'. FIG. 5C yes FIG. 5A An enlarged sectional view of region CYA in the middle. FIG. 5C yesFIG. 5A is an enlarged cross-sectional view of the region CYA in FIG. 5D is FIG. 5B is an enlarged cross-sectional view of the region CYB in FIG. 5A to FIG. 5D is FIG. 2A to FIG. 2D In the same reference numerals are used for the same elements, and redundant description thereof will be omitted for the sake of brevity.

[0066] Referring to FIG. 5A and FIG. 5B The integrated circuit device 300 can include a memory stack STA3 including a string selection line structure SL3. The string selection line structure SL3 can have substantially the same configuration as that of the string selection line structure SL2 shown in FIG. 4A and FIG. 4B However, the string selection line structure SL3 can include an upper string selection line SSU33 instead of the upper string selection line SSU23. The bottom level of the upper string selection line SSU33 can be a third level LV3 higher than the second level LV2. The upper string selection line SSU33 can extend in the horizontal direction at the third level LV3. The bottom level of the upper string selection line SSU33 can be higher than the bottom level of the upper horizontal extension HM2 of the string selection bend line SSMB.

[0067] In the integrated circuit device 300, a third insulating layer 376C can be disposed between the string selection bend line SSMB and the upper string selection line SSU33. The thickness DA2 of the third insulating layer 376C can be greater than the thickness DA1 of the second insulating layer 176B.

[0068] The more detailed configuration of the upper string selection line SSU33 and the third insulating layer 376C can be substantially the same as that described with respect to the upper string selection line SSU3 and the third insulating layer 176C shown in FIG. 2A and FIG. 2B

[0069] FIG. 6 is a cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concept. In FIG. 6 the same reference numerals are used for the same elements, and redundant description thereof will be omitted for the sake of brevity. FIG. 2A to FIG. 2D Referring to

[0070] and FIG. 6 The integrated circuit device 400 can include a memory stack STA4 including a string selection line structure SL4. The string selection line structure SL4 can include first and second lower string selection lines SL1A and SL1B, first and second intermediate string selection lines SM2A and SM2B, first and second upper string selection lines SU3A and SU3B, and first and second string selection bend lines SMBA and SMBB.

[0071] The first lower string select line SL1A and the second lower string select line SL1B, the first middle string select line SM2A and the second middle string select line SM2B, the first upper string select line SU3A and the second upper string select line SU3B, and the first string select meander line SMBA and the second string select meander line SMBB can receive voltages through string select contacts having the same or similar configuration as the configuration of the first contact 134A, the second contact 134B, the third contact 134C, and the fourth contact 134D shown in FIG. 13. The turn-on or turn-off of each of the first lower string select line SL1A and the second lower string select line SL1B, the first middle string select line SM2A and the second middle string select line SM2B, the first upper string select line SU3A and the second upper string select line SU3B, and the first string select meander line SMBA and the second string select meander line SMBB can be determined according to the voltages applied through the string select contacts. In an example embodiment, the first lower string select line SL1A and the second lower string select line SL1B can be turned on together or turned off together. The first middle string select line SM2A and the second middle string select line SM2B can be turned on together or turned off together. The first upper string select line SU3A and the second upper string select line SU3B can be turned on together or turned off together. The first string select meander line SMBA and the second string select meander line SMBB can be turned on together or turned off together. FIG. 1

[0072] Similar to the method of selecting any one of the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3 of the integrated circuit device 400, in the integrated circuit device 400, any one of the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3 can be selected by using the voltages applied through the string select contacts. FIG. 1 FIG. 2A to FIG. 2D

[0073] ​​​To select only the first string selection region STR1 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3, the first lower string selection line SL1A and the second lower string selection line SL1B and the first intermediate string selection line SM2A and the second intermediate string selection line SM2B can be turned on, and the first upper string selection line SU3A and the second upper string selection line SU3B and the first string selection meander line SMBA and the second string selection meander line SMBB can be turned off. To select only the second string selection region STR2 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3, the first string selection meander line SMBA and the second string selection meander line SMBB and the first upper string selection line SU3A and the second upper string selection line SU3B can be turned on, and the first lower string selection line SL1A and the second lower string selection line SL1B and the first intermediate string selection line SM2A and the second intermediate string selection line SM2B can be turned off. To select only the third string selection region STR3 among the first string selection region STR1, the second string selection region STR2, and the third string selection region STR3, the first upper string selection line SU3A and the second upper string selection line SU3B and the first string selection meander line SMBA and the second string selection meander line SMBB can be turned on, and the first lower string selection line SL1A and the second lower string selection line SL1B and the first intermediate string selection line SM2A and the second intermediate string selection line SM2B can be turned off.

[0074] More detailed configurations of the first lower string selection line SL1A and the second lower string selection line SL1B, the first intermediate string selection line SM2A and the second intermediate string selection line SM2B, the first upper string selection line SU3A and the second upper string selection line SU3B, and the first string selection meander line SMBA and the second string selection meander line SMBB can be the same as those described with reference to FIGS. 6A and 6B. FIG. 1 and FIG. 2A to FIG. 2D The configurations described with respect to the lower string selection line SSL1, the intermediate string selection line SSM2, the upper string selection line SSU3, and the string selection meander line SSMB are substantially the same.

[0075] The first intermediate string selection line SM2A and the second intermediate string selection line SM2B and the first string selection meander line SMBA and the second string selection meander line SMBB can be spaced apart from each other with a string selection line cut region SSLC4 located between the first intermediate string selection line SM2A and the second intermediate string selection line SM2B and the first string selection meander line SMBA and the second string selection meander line SMBB. The string selection line cut region SSLC4 can be filled with an isolation insulating layer 478. The isolation insulating layer 478 can be overlaid with the first lower string selection line SL1A and the second lower string selection line SL1B in a vertical direction (Z direction). The isolation insulating layer 478 can include a silicon oxide layer.

[0076] The second insulating layer 476B can be disposed between the first lower string selection line SL1A and the second lower string selection line SL1B. The third insulating layer 476C can be disposed between the second lower string selection line SL1B and the first middle string selection line SM2A and between the second lower string selection line SL1B and the first string selection bend line SMBA. The fourth insulating layer 476D can be disposed between the first middle string selection line SM2A and the second middle string selection line SM2B and between the first string selection bend line SMBA and the second string selection bend line SMBB. The fifth insulating layer 476E can be disposed between the second string selection bend line SMBB and the first upper string selection line SU3A. The sixth insulating layer 476F can be disposed between the first upper string selection line SU3A and the second upper string selection line SU3B. The second upper string selection line SU3B can be covered by the seventh insulating layer 476G. The string selection line structure SL4 can be covered by the eighth insulating layer 476H. Each of the second insulating layer 476B, the third insulating layer 476C, the fourth insulating layer 476D, the fifth insulating layer 476E, the sixth insulating layer 476F, the seventh insulating layer 476G, and the eighth insulating layer 476H can include a silicon oxide layer.

[0077] FIG. 7 is a schematic cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concepts.

[0078] Referring to FIG. 7 , the integrated circuit device 500 can include a plurality of word line cut regions WC51, WC52, WC53, and WC54 and a plurality of cell block regions UB5A, UB5B, and UB5C disposed between the plurality of word line cut regions WC51, WC52, WC53, and WC54, respectively.

[0079] Each of the plurality of cell block regions UB5A, UB5B, and UB5C can have substantially the same configuration as that of the cell block region UB of the integrated circuit device 100 described with reference to FIG. 1 and FIG. 2A to FIG. 2D . However, the plurality of cell block regions UB5A, UB5B, and UB5C can include string selection line structures SL5A, SL5B, and SL5C instead of the string selection line structure SL1. In FIG. 7 , other configurations than the string selection line structures SL5A, SL5B, and SL5C among the configurations of the plurality of cell block regions UB5A, UB5B, and UB5C are not illustrated. Each of the plurality of word line cut regions WC51, WC52, WC53, and WC54 can have the same or similar configuration as that of the word line cut region WLC of the integrated circuit device 100 described with reference to FIG. 1 and FIG. 2A to FIG. 2D .

[0080] Each of the string selection line structures SL5A, SL5B, and SL5C can include a lower string selection line L1, an intermediate string selection line M2, an upper string selection line U3, and a string selection jog line MB. The lower string selection line L1, the intermediate string selection line M2, and the string selection jog line MB can have the same or similar configuration as described with respect to the lower string selection line SSL1, the intermediate string selection line SSM2, and the string selection jog line SSMB illustrated in FIG. 2A to FIG. 2D The upper string selection line U3 can have the same or similar configuration as described with respect to the upper string selection line SSU3, FIG. 2A to FIG. 2D the upper string selection line SSU23 illustrated in FIG. 4A and FIG. 4B the upper string selection line SSU33 illustrated in FIG. 5A to FIG. 5D .

[0081] The cross-sectional configuration of the string selection line structures SL5A, SL5B, and SL5C in two adjacent cell block regions among the plurality of cell block regions UB5A, UB5B, and UB5C can have a mirror-symmetrical configuration with respect to the word line cut regions WC52 and WC53 located between the plurality of cell block regions UB5A, UB5B, and UB5C. For example, the cell block region UB5A and the cell block region UB5B can be adjacent to each other with the word line cut region WC52 located between the cell block region UB5A and the cell block region UB5B, and the string selection line structure SL5A of the cell block region UB5A and the string selection line structure SL5B of the cell block region UB5B can have a mirror-symmetrical configuration with respect to the word line cut region WC52. In addition, the cell block region UB5B and the cell block region UB5C can be adjacent to each other with the word line cut region WC53 located between the cell block region UB5B and the cell block region UB5C, and the string selection line structure SL5B of the cell block region UB5B and the string selection line structure SL5C of the cell block region UB5C can have a mirror-symmetrical configuration with respect to the word line cut region WC53.

[0082] FIG. 8 is a schematic cross-sectional view illustrating an integrated circuit device according to other embodiments of the inventive concept.

[0083] Referring to FIG. 8 , the integrated circuit device 600 can include a plurality of word line cut regions WC61, WC62, WC63, and WC64 and a plurality of cell block regions UB6A, UB6B, and UB6C arranged one by one between the plurality of word line cut regions WC61, WC62, WC63, and WC64, respectively.

[0084] Each of the plurality of cell block regions UB6A, UB6B, and UB6C can have the same or similar configuration as described with respect to the cell block region UB1 illustrated in FIG. 6The configuration of the unit block region UB of the integrated circuit device 400 described is substantially the same configuration. However, the plurality of unit block regions UB6A, UB6B, and UB6C can include string selection line structures SL6A, SL6B, and SL6C instead of the string selection line structure SL4 of the integrated circuit device 400. In FIG. 8 Among the configurations of the plurality of unit block regions UB6A, UB6B, and UB6C, other configurations than the string selection line structures SL6A, SL6B, and SL6C are not shown.

[0085] Each of the plurality of word line cut regions WC61, WC62, WC63, and WC64 can have the same or similar configuration as the word line cut region WLC of the integrated circuit device 100 described. FIG. 1 and FIG. 2A to FIG. 2D The configuration of the word line cut region WLC of the integrated circuit device 100 described is the same or similar configuration.

[0086] Each of the string selection line structures SL6A, SL6B, and SL6C can include first lower string selection lines L1A and second lower string selection lines L1B, first intermediate string selection lines M2A and second intermediate string selection lines M2B, first upper string selection lines U3A and second upper string selection lines U3B, and first string selection jog lines MBA and second string selection jog lines MBB. The first lower string selection lines L1A and the second lower string selection lines L1B, the first intermediate string selection lines M2A and the second intermediate string selection lines M2B, the first upper string selection lines U3A and the second upper string selection lines U3B, and the first string selection jog lines MBA and the second string selection jog lines MBB can have the same or similar configuration as the configuration described with respect to the first lower string selection lines SL1A and the second lower string selection lines SL1B, the first intermediate string selection lines SM2A and the second intermediate string selection lines SM2B, the first upper string selection lines SU3A and the second upper string selection lines SU3B, and the first string selection jog lines SMBA and the second string selection jog lines SMBB shown in FIG. 6

[0087] ​The cross-sectional configuration of the string selection line structures SL6A, SL6B, and SL6C in two adjacent cell block regions among the plurality of cell block regions UB6A, UB6B, and UB6C can have a mirror-symmetrical configuration with respect to the word line cut regions WC62 and WC63 located between the plurality of cell block regions UB6A, UB6B, and UB6C, respectively. For example, the cell block region UB6A and the cell block region UB6B can be adjacent to each other with the word line cut region WC62 located between the cell block region UB6A and the cell block region UB6B, and the string selection line structure SL6A of the cell block region UB6A and the string selection line structure SL6B of the cell block region UB6B can have a mirror-symmetrical configuration with respect to the word line cut region WC62. In addition, the cell block region UB6B and the cell block region UB6C can be adjacent to each other with the word line cut region WC63 located between the cell block region UB6B and the cell block region UB6C, and the string selection line structure SL6B of the cell block region UB6B and the string selection line structure SL6C of the cell block region UB6C can have a mirror-symmetrical configuration with respect to the word line cut region WC63.

[0088] Similar to the integrated circuit device 100 described with reference to FIG. 1 and FIG. 2A to FIG. 2D the integrated circuit devices 200, 300, 400, 500, and 600 described with reference to FIG. 4A and FIG. 4B , FIG. 5A to FIG. 5D and FIG. 6 to FIG. 8 can prevent undesired physical deformation such as a memory stack falling off or tilting, and can increase the number of channel structures per unit area in a memory cell region, thereby improving the integration of the integrated circuit devices 200, 300, 400, 500, and 600.

[0089] FIG. 9A to FIG. 9J is a sequential cross-sectional view for describing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. In this example, the method of manufacturing the integrated circuit device 100 shown in FIG. 1 and FIG. 2A to FIG. 2D will be described as an example. FIG. 9A to FIG. 9J Some configurations of the manufacturing process in regions corresponding to cross-sections taken along the line A-A' of the integrated circuit device 200 are schematically shown. FIG. 1

[0090] Referring to FIG. 9A , an active area AC can be defined in the substrate 102, and then a plurality of insulating layers 176 and a plurality of sacrificial layers PW can be alternately stacked one by one on the active area AC of the substrate 102. In an example embodiment, the plurality of insulating layers 176 can include silicon oxide, and the plurality of sacrificial layers PW can include silicon nitride or polysilicon. ​

[0091] Referring to FIG. 9B A first insulating layer 176A covering the uppermost one of the plurality of sacrificial layers PW can be formed, and then a lower sacrificial layer PSL can be formed on the first insulating layer 176A. The first insulating layer 176A can have the same configuration as that of the insulating layer 176 described with reference to FIG. 9A The first insulating layer 176A can have a thickness greater than that of the insulating layer 176; however, the inventive concept is not limited thereto. The lower sacrificial layer PSL can include the same material as that of the plurality of sacrificial layers PW.

[0092] Referring to FIG. 9C A portion of the lower sacrificial layer PSL can be removed by using a selective etching process that utilizes a difference in etching selectivity between the lower sacrificial layer PSL and the first insulating layer 176A.

[0093] In the process of etching the lower sacrificial layer PSL for forming the lower sacrificial pattern PSL1, the first insulating layer 176A exposed around the lower sacrificial pattern PSL1 by over-etching can be consumed in part thickness from its upper surface, as a result, a step portion ST1 can be formed at a top surface of the first insulating layer 176A near the edge portion E1 of the lower sacrificial pattern PSL1.

[0094] Referring to FIG. 9D A second insulating layer 176B, an intermediate sacrificial layer PSM, a third insulating layer 176C, an upper sacrificial layer PSU, and a fourth insulating layer 176D can be sequentially formed on the resultant structure of FIG. 9C

[0095] At a position adjacent to the edge portion E1 of the lower sacrificial pattern PSL1, the intermediate sacrificial layer PSM can include a vertical extension portion V1, and the upper sacrificial layer PSU can include a vertical extension portion V2. The second insulating layer 176B, the third insulating layer 176C, and the fourth insulating layer 176D can have the same configuration as that of the insulating layer 176 described with reference to FIG. 9A The intermediate sacrificial layer PSM and the upper sacrificial layer PSU can have the same configuration as that of the plurality of sacrificial layers PW described with reference to FIG. 9A

[0096] Referring to FIG. 9E A portion of the lower sacrificial layer PSL can be removed by using a selective etching process that utilizes a difference in etching selectivity between the lower sacrificial layer PSL and the first insulating layer 176A. FIG. 9D ​​The resulting structure was subjected to a chemical mechanical polishing (CMP) process to remove a portion of the fourth insulating layer 176D and a portion of the upper sacrificial layer PSU until a portion of the third insulating layer 176C covering the intermediate sacrificial layer PSM was exposed. As a result, an upper sacrificial pattern PSU3 comprising the remaining portion of the upper sacrificial layer PSU can be formed.

[0097] The upper sacrificial pattern PSU3 may not overlap with the lower sacrificial pattern PSL1 in the vertical direction (Z direction). At least a portion of the vertical extension V2 may be retained in the upper sacrificial pattern PSU3 in the portion near the edge portion E1 of the lower sacrificial pattern PSL1. A portion of the fourth insulating layer 176D may be retained on the upper sacrificial pattern PSU3.

[0098] Reference FIG. 9F , can FIG. 9E A fifth insulating layer 176E is formed on the resulting structure. Then, by etching a portion of each of the fifth insulating layer 176E, the third insulating layer 176C, and the intermediate sacrificial layer PSM using an etching mask (not shown), a string selection wire cut region SSLC can be formed, and an isolation insulating layer 178 filling the string selection wire cut region SSLC can be formed.

[0099] During the formation of the string select wire cut region SSLC, a portion of the second insulating layer 176B can be removed by over-etching the intermediate sacrificial layer PSM, and after the formation of the string select wire cut region SSLC, the second insulating layer 176B can be exposed through the string select wire cut region SSLC.

[0100] After forming the string selection wire cut region SSLC, the intermediate sacrificial layer PSM can be separated by the string selection wire cut region SSLC into intermediate sacrificial patterns PSM2 and bent sacrificial patterns PSMB that are spaced apart from each other. The bent sacrificial pattern PSMB may include a vertical extension V1.

[0101] Reference FIG. 9G , can FIG. 9Fa plurality of channel holes 180H formed in the resulting structure of the above, each of the plurality of channel holes 180H extending through the plurality of insulating layers 176, the first insulating layer 176A, the second insulating layer 176B, the third insulating layer 176C, the fourth insulating layer 176D, and the fifth insulating layer 176E, the plurality of sacrificial layers PW, and the lower sacrificial pattern PSL1, the intermediate sacrificial pattern PSM2, the upper sacrificial pattern PSU3, and the meander sacrificial pattern PSMB in the vertical direction (Z direction). Subsequently, an upper insulating layer 187 can be formed to cover upper surfaces of each of the gate dielectric layer 182, the channel region 184, and the buried insulating layer 186, and an upper surface of the fifth insulating layer 176E, and a plurality of contact holes 187H exposing top surfaces of the channel region 184 and the buried insulating layer 186 can be formed in the upper insulating layer 187, and then a plurality of drain regions 188 can be formed in the plurality of contact holes 187H to form a plurality of channel structures 180 and a plurality of dummy channel structures D180.

[0102] The plurality of channel structures 180 can include a plurality of first channel structures 180A passing through the lower sacrificial pattern PSL1 and the intermediate sacrificial pattern PSM2, a plurality of second channel structures 180B passing through the lower sacrificial pattern PSL1 and the meander sacrificial pattern PSMB, and a plurality of third channel structures 180C passing through the meander sacrificial pattern PSMB and the upper sacrificial pattern PSU3. The plurality of dummy channel structures D180 can include a plurality of first dummy channel structures D180A (see FIG. 1 and FIG. 2B ) passing through the isolation insulating layer 178 and arranged in a line in the first horizontal direction (X direction), and a plurality of second dummy channel structures D180B passing through the meander sacrificial pattern PSMB and arranged in a line in the first horizontal direction (X direction). A vertical extension V1 (see FIG. 9F ) of the meander sacrificial pattern PSMB can be reserved between the plurality of second dummy channel structures D180B.

[0103] The gate dielectric layer 182 can be formed to cover inner sidewalls of each of the plurality of channel holes 180H. Each of the gate dielectric layer 182, the channel region 184, and the buried insulating layer 186 can be formed by a chemical vapor deposition (CVD) process, a low pressure CVD (LPCVD) process, or an atomic layer deposition (ALD) process. In an example embodiment, the channel region 184 can be formed to contact the substrate 102 exposed to the bottom of the channel hole 180H. In other example embodiments, a semiconductor layer (not shown) can be formed on the substrate 102 exposed to the bottom of the channel hole 180H by a selective epitaxial growth process, and the channel region 184 can be formed on the semiconductor layer.

[0104] Referring to FIG. 9H , the plurality of channel structures 180 can be formed by removing the plurality of sacrificial layers PW and the plurality of sacrificial patterns PSL1, PSM2, PSU3, and PSMB in the plurality of channel holes 180H.FIG. 9G A plurality of word line cut regions WLC are formed in the resulting structure of the above, and then a plurality of common source regions 172 can be formed by implanting impurity ions into the substrate 102 through the plurality of word line cut regions WLC, which pass through the plurality of insulating layers 176, the first insulating layer 176A, the second insulating layer 176B, the third insulating layer 176C, the fourth insulating layer 176D, and the fifth insulating layer 176E, the upper insulating layer 187, the plurality of sacrificial layers PW, the lower sacrificial pattern PSL1, the middle sacrificial pattern PSM2, the upper sacrificial pattern PSU3, and the bent sacrificial pattern PSMB and extend in the vertical direction (Z direction), and have a bottom portion that exposes the substrate 102.

[0105] Thereafter, the plurality of sacrificial layers PW, the lower sacrificial pattern PSL1, the middle sacrificial pattern PSM2, the upper sacrificial pattern PSU3, and the bent sacrificial pattern PSMB (see FIG. 9G ) can be replaced with the ground select line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, and the string select line structure SL1 (see

[0106] In example embodiments, in order to form the ground select line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, and the string select line structure SL1, empty spaces can be formed by selectively removing the plurality of sacrificial layers PW, the lower sacrificial pattern PSL1, the middle sacrificial pattern PSM2, the upper sacrificial pattern PSU3, and the bent sacrificial pattern PSMB (see FIG. 9G ) exposed through the plurality of word line cut regions WLC, and the empty spaces can be filled with a conductive material.

[0107] In other example embodiments, when each of the plurality of sacrificial layers PW, the lower sacrificial pattern PSL1, the middle sacrificial pattern PSM2, the upper sacrificial pattern PSU3, and the bent sacrificial pattern PSMB (see FIG. 9G ) includes polysilicon, a polysilicon silicidation process can be performed to form the ground select line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, and the string select line structure SL1. In this case, each of the ground select line GSL, the plurality of word lines WL1, WL2, …, WLn-1, and WLn, and the string select line structure SL1 can include a metal silicide.

[0108] Referring to FIG. 9I , an insulating spacer 192 and a common source pattern CSP can be formed in each of the plurality of word line cut regions WLC.

[0109] In the example embodiment, to form the insulating spacers 192, an insulating layer covering inner walls of the plurality of word line cut regions WLC can be first formed. Thereafter, the insulating spacers 192 including portions of the insulating layer remaining on the inner walls of the plurality of word line cut regions WLC can be formed by etching back the insulating layer to expose the substrate 102 at bottom surfaces of the plurality of word line cut regions WLC. To form the common source patterns CSP in each of the plurality of word line cut regions WLC, spaces in the plurality of word line cut regions WLC defined by the insulating spacers 192 can be filled with a conductive layer. In the example embodiment, a metal silicide layer (not shown) can be disposed between the common source regions 172 and the common source patterns CSP to reduce contact resistance of the metal silicide layer. For example, the metal silicide layer can include cobalt silicide; however, the inventive concepts are not limited thereto.

[0110] Referring to FIG. 9J , an interlayer insulating layer 193 covering the plurality of common source patterns CSP, the plurality of channel structures 180, and the plurality of dummy channel structures D180 can be formed, then a plurality of contact holes 193H through some regions of the interlayer insulating layer 193 to expose the drain regions 188 of the plurality of channel structures 180 can be formed, and a plurality of contact plugs 194 can be formed by filling the plurality of contact holes 193H with a conductive material. Thereafter, a plurality of bit lines BL can be formed on the interlayer insulating layer 193 and the plurality of contact plugs 194 to fabricate the integrated circuit device 100.

[0111] FIG. 10A and FIG. 10B are sequential cross-sectional views for describing a method of manufacturing an integrated circuit device according to other embodiments of the inventive concepts. In this example, the method of manufacturing the integrated circuit device 200 shown in FIG. 4A and FIG. 4B will be described as an example. In FIG. 10A and FIG. 10B , the same reference numerals as those in FIG. 9A to FIG. 9J denote the same elements, and for the sake of brevity, redundant descriptions thereof will be omitted.

[0112] Referring to FIG. 10A , after performing the processes described with reference to FIG. 9A to FIG. 9D , in the same manner as described with reference to FIG. 9E , the integrated circuit device 200 can be manufactured. FIG. 9DThe resulting structure is subjected to a CMP process until a portion of the third insulating layer 176C covering the intermediate sacrificial layer PSM is exposed. However, in this example, during or after the CMP process, a portion of the fourth insulating layer 176D and a portion of the upper sacrificial layer PSU can be removed by utilizing an etch environment with a higher etch rate for the upper sacrificial layer PSU than for the fourth insulating layer 176D. As a result, a portion of the fourth insulating layer 176D and a portion of the upper sacrificial layer PSU can be removed to expose a portion of the third insulating layer 176C covering the intermediate sacrificial layer PSM, and an empty space VS can then be formed between the third insulating layer 176C and the fourth insulating layer 176D. The upper sacrificial pattern PSU3, which is the remaining portion of the upper sacrificial layer PSU, can be exposed through the empty space VS. The upper sacrificial pattern PSU3 may not include the vertical extension V2 (see FIG. 9E ).

[0113] Reference FIG. 10B It can be compared with the reference FIG. 9F The method described regarding the process of forming the fifth insulating layer 176E is similar to that described in the previous section. FIG. 10A A fifth insulating layer 276E is formed on the resulting structure. The fifth insulating layer 276E may include filling the empty space VS between the third insulating layer 176C and the fourth insulating layer 176D (see...). FIG. 10A The insulating protrusion 276P of the fifth insulating layer 276E may include a silicon oxide layer.

[0114] From then on, it can be referred to as follows FIG. 9F The described formation of the string selection wire cut region SSLC and the isolation insulation layer 178 can be performed as per reference. FIG. 9G to FIG. 9J The described process is for manufacturing FIG. 4A and FIG. 4B The integrated circuit device 200 shown in the figure.

[0115] FIG. 11A to FIG. 11C This is a sequential cross-sectional view used for reference when describing a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept. In this example, the manufacturing process will be... FIG. 5A and FIG. 5B The method of the integrated circuit device 300 shown in the figure is described as an example. FIG. 11A to FIG. 11C In, with FIG. 9A to FIG. 9J The same reference numerals in the figures denote the same elements, and for the sake of brevity, their redundant descriptions will be omitted.

[0116] Reference FIG. 11A In executing the reference FIG. 9A to FIG. 9C After describing the process, it is possible to FIG. 9CA second insulating layer 176B and an intermediate sacrificial layer PSM are formed on the resulting structure. Subsequently, a third insulating layer 376C and an upper sacrificial layer 378U can be sequentially formed on the intermediate sacrificial layer PSM. The thickness DA2 of the third insulating layer 376C can be greater than the thickness DA1 of the second insulating layer 176B, and the thickness DB2 of the upper sacrificial layer 378U can be greater than the thickness DB1 of the intermediate sacrificial layer PSM. In an example embodiment, the bottom level of the intermediate sacrificial layer PSM can be a second level LV2. The bottom level of the upper sacrificial layer 378U can be a third level LV3 higher than the second level LV2. The top level of the intermediate sacrificial layer PSM can be a fourth level LV4 equal to or higher than the third level LV3. A more detailed construction of the third insulating layer 376C and the upper sacrificial layer 378U can be found in reference [reference missing]. FIG. 9D The constructions of the third insulating layer 176C and the upper sacrificial layer PSU are basically the same.

[0117] Reference FIG. 11B It can be done by... FIG. 11A The resulting structure is subjected to a CMP process to remove a portion of the upper sacrificial layer 378U and a portion of the third insulating layer 376C until a portion of the third insulating layer 376C covering the lower sacrificial pattern PSL1 is exposed. An upper sacrificial pattern 378UP, which constitutes the remainder of the upper sacrificial layer 378U, can be formed after the CMP process.

[0118] The thickness DB3 of the upper sacrificial pattern 378UP can be substantially equal to or similar to the thickness DB1 of the intermediate sacrificial layer PSM, thereby minimizing the thickness variations in the lower sacrificial pattern PSL1, the intermediate sacrificial layer PSM, and the upper sacrificial pattern 378UP.

[0119] Reference FIG. 11C It can be compared with the reference FIG. 9F The method described is similar to the method used to form the fifth insulating layer 176E, the string selection wire cut region SSLC, and the isolation insulating layer 178.

[0120] After that, the reference can be executed. FIG. 9G to FIG. 9J The described process for manufacturing FIG. 5A and FIG. 5B The integrated circuit device 300 shown in the figure.

[0121] FIG. 12A to FIG. 12G This is a sequential cross-sectional view used for reference when describing a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept. In this example, the manufacturing process will be... FIG. 6 The method of the integrated circuit device 400 shown in the figure is described as an example. FIG. 12A to FIG. 12G In, with FIG. 9A to FIG. 9J The same reference numerals in the figures denote the same elements, and for the sake of brevity, their redundant descriptions will be omitted.

[0122] Referring to FIG. 12A , a plurality of insulating layers 176 and a plurality of sacrificial layers PW can be alternately stacked one by one on the base 102 in the same manner as described with reference to FIG. 9A , and then a first insulating layer 176A can be formed in the same manner as described with reference to FIG. 9B

[0123] Thereafter, a first lower sacrificial layer LA, a second insulating layer 476B, and a second lower sacrificial layer LB can be sequentially formed on the first insulating layer 176A. The first lower sacrificial layer LA and the second lower sacrificial layer LB and the second insulating layer 476B can have the same configuration as described with reference to FIG. 9A the configuration described with reference to the plurality of sacrificial layers PW and the insulating layer 176.

[0124] Referring to FIG. 12B , a portion of each of the first lower sacrificial layer LA, the second lower sacrificial layer LB, and the second insulating layer 476B can be removed to form a first lower sacrificial pattern LA1 and a second lower sacrificial pattern LB1. A portion of the second insulating layer 476B can be left between the first lower sacrificial pattern LA1 and the second lower sacrificial pattern LB1. In this case, a portion of the first insulating layer 176A can be consumed around the first lower sacrificial pattern LA1 as a result, a step portion ST4 can be formed at an upper surface of the first insulating layer 176A.

[0125] Referring to FIG. 12C , a third insulating layer 476C, a first intermediate sacrificial layer MDA, a fourth insulating layer 476D, a second intermediate sacrificial layer MDB, a fifth insulating layer 476E, a first upper sacrificial layer UDA, a sixth insulating layer 476F, a second upper sacrificial layer UDB, and a seventh insulating layer 476G can be sequentially formed on the resultant structure of FIG. 12B The third insulating layer 476C, the fourth insulating layer 476D, the fifth insulating layer 476E, the sixth insulating layer 476F, and the seventh insulating layer 476G can have the same configuration as described with reference to the insulating layer 176. The first intermediate sacrificial layer MDA, the second intermediate sacrificial layer MDB, the first upper sacrificial layer UDA, and the second upper sacrificial layer UDB can have the same configuration as described with reference to

[0126] the configuration described with reference to the plurality of sacrificial layers PW. FIG. 9A FIG. 9A

[0127] Referring to FIG. 12D , a portion of each of the first lower sacrificial layer LA, the second lower sacrificial layer LB, and the second insulating layer 476B can be removed to form a first lower sacrificial pattern LA1 and a second lower sacrificial pattern LB1. A portion of the second insulating layer 476B can be left between the first lower sacrificial pattern LA1 and the second lower sacrificial pattern LB1. In this case, a portion of the first insulating layer 176A can be consumed around the first lower sacrificial pattern LA1 as a result, a step portion ST4 can be formed at an upper surface of the first insulating layer 176A. FIG. 12C ​​​The resulting structure can be subjected to a CMP process to remove a portion of each of the sixth insulating layer 476F and the seventh insulating layer 476G and the first upper sacrificial layer UDA and the second upper sacrificial layer UDB until a portion of the fifth insulating layer 476E covering an upper surface of the second intermediate sacrificial layer MDB is exposed. As a result, a first upper sacrificial pattern UDA3 and a second upper sacrificial pattern UDB3 including remaining portions of the first upper sacrificial layer UDA and the second upper sacrificial layer UDB can be formed.

[0128] Referring to FIG. 12E , the resulting structure can be subjected to a CMP process to remove a portion of each of the sixth insulating layer 476F and the seventh insulating layer 476G and the first upper sacrificial layer UDA and the second upper sacrificial layer UDB until a portion of the fifth insulating layer 476E covering an upper surface of the second intermediate sacrificial layer MDB is exposed. As a result, a first upper sacrificial pattern UDA3 and a second upper sacrificial pattern UDB3 including remaining portions of the first upper sacrificial layer UDA and the second upper sacrificial layer UDB can be formed. FIG. 12D The resulting structure can be subjected to a CMP process to remove a portion of each of the sixth insulating layer 476F and the seventh insulating layer 476G and the first upper sacrificial layer UDA and the second upper sacrificial layer UDB until a portion of the fifth insulating layer 476E covering an upper surface of the second intermediate sacrificial layer MDB is exposed. As a result, a first upper sacrificial pattern UDA3 and a second upper sacrificial pattern UDB3 including remaining portions of the first upper sacrificial layer UDA and the second upper sacrificial layer UDB can be formed.

[0129] Through the string selection line cut region SSLC4, the first intermediate sacrificial layer MDA (see FIG. 12D ) can be separated into a first intermediate sacrificial pattern MDA2 and a first bend sacrificial pattern RMDA, and the second intermediate sacrificial layer MDB (see FIG. 12D ) can be separated into a second intermediate sacrificial pattern MDB2 and a second bend sacrificial pattern RMDB. The first bend sacrificial pattern RMDA can include a first vertically extending portion VA4, and the second bend sacrificial pattern RMDB can include a second vertically extending portion VB4.

[0130] Referring to FIG. 12F , the resulting structure can be subjected to a CMP process to remove a portion of each of the sixth insulating layer 476F and the seventh insulating layer 476G and the first upper sacrificial layer UDA and the second upper sacrificial layer UDB until a portion of the fifth insulating layer 476E covering an upper surface of the second intermediate sacrificial layer MDB is exposed. As a result, a first upper sacrificial pattern UDA3 and a second upper sacrificial pattern UDB3 including remaining portions of the first upper sacrificial layer UDA and the second upper sacrificial layer UDB can be formed. FIG. 9G FIG. 12E The resulting structure can be subjected to a CMP process to remove a portion of each of the sixth insulating layer 476F and the seventh insulating layer 476G and the first upper sacrificial layer UDA and the second upper sacrificial layer UDB until a portion of the fifth insulating layer 476E covering an upper surface of the second intermediate sacrificial layer MDB is exposed. As a result, a first upper sacrificial pattern UDA3 and a second upper sacrificial pattern UDB3 including remaining portions of the first upper sacrificial layer UDA and the second upper sacrificial layer UDB can be formed. FIG. 9H ​A plurality of word line cut regions WLC and a plurality of common source regions 172 are formed in the same manner as described above, and the plurality of sacrificial layers PW, the first and second lower sacrificial patterns LA1 and LB1, the first and second intermediate sacrificial patterns MDA2 and MDB2, the first and second upper sacrificial patterns UDA3 and UDB3, and the first and second bend sacrificial patterns RMDA and RMDB can be replaced with the ground select lines GSL, the plurality of word lines WL1, WL2, …, WLn-1, and the string select line structure SL4. The string select line structure SL4 can include the first and second lower string select lines SL1A and SL1B, the first and second intermediate string select lines SM2A and SM2B, the first and second upper string select lines SU3A and SU3B, and the first and second string select bend lines SMBA and SMBB.

[0131] Referring to FIG. 12G , the insulating spacers 192 and the common source pattern CSP can be formed in each of the plurality of word line cut regions WLC in the same manner as described above with reference to FIG. 9I . Thereafter, the interlayer insulating layer 193, the plurality of contact plugs 194, and the plurality of bit lines BL can be formed in the same manner as described above with reference to FIG. 9J to fabricate the integrated circuit device 400 shown in FIG. 6 .

[0132] Although the example methods of fabricating the integrated circuit devices 100, 200, 300, and 400 according to the inventive concepts have been described above with reference to FIG. 9A to FIG. 12G , it will be well understood by those of ordinary skill in the art that various modifications and changes can be made therein without departing from the scope of the inventive concepts to fabricate the integrated circuit devices 500 and 600 shown in FIG. 7 and FIG. 8 , and the integrated circuit devices within the scope of the inventive concepts with various modifications thereto.

[0133] While the inventive concepts have been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: The substrate, including the main surface; Multiple letter lines extend horizontally parallel to the main surface of the base and overlap each other vertically. Serial select line structure, stacked on the multiple word lines; and Multiple channel structures extend vertically through the multiple word lines and string select line structures. The string selection line structure includes a string selection bend line, which comprises a lower horizontal extension extending horizontally at a first height higher than the plurality of character lines, an upper horizontal extension extending horizontally at a second height higher than the first height, and a vertical extension connecting the lower horizontal extension and the upper horizontal extension. The string selection line structure also includes a lower string selection line, which extends horizontally at a first height at a position spaced apart from the lower horizontal extension of the string selection bend line, and includes a portion that overlaps with the upper horizontal extension of the string selection bend line in the vertical direction.

2. The integrated circuit device according to claim 1, wherein, The string selection line structure also includes an intermediate string selection line, which extends horizontally at a second height at a position spaced apart from the upper horizontal extension of the string selection bend.

3. The integrated circuit device according to claim 1, wherein, The string selection line structure also includes an upper string selection line, which extends horizontally at a second height at a position spaced apart from the upper horizontal extension of the string selection bend line, and includes a portion that overlaps with the lower horizontal extension of the string selection bend line in the vertical direction.

4. The integrated circuit device according to claim 1, wherein, Each of the multiple word lines extends above the base across three string selection regions arranged sequentially in the horizontal direction, and The string selection bend line is only placed in two of the three string selection areas.

5. The integrated circuit device according to claim 1, wherein, Each of the multiple word lines extends above the base across a first set of selection areas, a second set of selection areas, and a third set of selection areas arranged sequentially in the horizontal direction, and The plurality of channel structures include: Multiple first channel structures pass through the multiple word lines in the first string selection area but do not pass through the string selection bend line; Multiple second channel structures extend horizontally through the upper portion of the multiple word lines and the string selection bend in the second string selection area; and Multiple third channel structures extend horizontally through the lower horizontal extensions of the multiple word lines and string selection bends in the third string selection area.

6. An integrated circuit device, the integrated circuit device comprising: The substrate, including the main surface; A pair of character line-cut regions extend longitudinally over a base along a first horizontal direction and are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, such that a unit block region is located between the pair of character line-cut regions, the first horizontal direction and the second horizontal direction being parallel to the main surface of the base; Multiple letter lines extend in the unit block area along a third horizontal direction parallel to the main surface of the base, and overlap each other in the vertical direction; A serial select line structure, stacked on the multiple word lines in a cell block region; and Multiple channel structures extend vertically through the multiple word lines and string select line structures in the unit block region. The serial selection line structure includes a serial selection bend line, which comprises a lower horizontal extension extending in a third horizontal direction at a first height higher than the plurality of word lines, an upper horizontal extension extending in a third horizontal direction at a second height higher than the first height, and a vertical extension connecting the lower horizontal extension and the upper horizontal extension. The string selection line structure also includes a lower string selection line, which extends at a first height along a third horizontal direction at a position spaced apart from the lower horizontal extension of the string selection bend line, and includes a portion that overlaps with the upper horizontal extension of the string selection bend line in the vertical direction.

7. The integrated circuit device according to claim 6, wherein, The unit block region includes a first series of selection regions, a second series of selection regions, and a third series of selection regions arranged sequentially in the second horizontal direction, and The string selection bend line is only placed in the second and third string selection areas, which are the first, second, and third string selection areas.

8. The integrated circuit device according to claim 7, wherein, The next selection line is only placed in the first and second selection areas among the first, second, and third selection areas, and... The upper horizontal extensions of the lower selection line and the selection bend line overlap each other in the vertical direction in the second selection area.

9. The integrated circuit device according to claim 8, wherein, The string selection line structure also includes intermediate string selection lines, which are only arranged in the first string selection area among the first, second, and third string selection areas, and extend along the third horizontal direction at the second height. The intermediate string selection line is spaced apart from the upper horizontal extension of the string selection bend line in the second horizontal direction, and The lower selection line and the middle selection line are vertically overlapped in the first selection area.

10. The integrated circuit device according to claim 9, The integrated circuit device further includes an isolation insulating layer disposed at a second height between the upper horizontal extension of the intermediate string select line and the string select bend line. in, The insulating layer is stacked vertically with the lower selection line.

11. The integrated circuit device according to claim 9, wherein, The string selection line structure also includes an upper string selection line, which is only arranged in the third string selection area among the first, second, and third string selection areas, and extends along the third horizontal direction. The upper string selection line is spaced apart from the middle string selection line in the second horizontal direction, and the upper horizontal extension of the string selection bend line is located between the upper string selection line and the middle string selection line. The upper selection line overlaps with the multiple character lines in the vertical direction, and the lower horizontal extension of the selection line bend is located between the upper selection line and the multiple character lines.

12. The integrated circuit device according to claim 11, wherein, In the second horizontal direction, the minimum interval between the upper and lower string selection lines is greater than the minimum interval between the lower string selection line and the lower horizontal extension of the string selection bend line.

13. The integrated circuit device according to claim 11, wherein, The plurality of channel structures include: Multiple first channel structures pass through the multiple word lines, lower selection lines, and middle selection lines in the first selection area; Multiple second channel structures extend horizontally through the upper horizontal portions of the multiple word lines, lower string selection lines, and string selection bends in the second string selection area; and Multiple third channel structures pass through the lower horizontal extension of the multiple word lines, the string selection bend line, and the upper string selection line in the third string selection area.

14. The integrated circuit device of claim 11, further comprising: Multiple first dummy channel structures are arranged in a line in a first horizontal direction between the upper horizontal extension of the intermediate string selection line and the string selection bend line. as well as Multiple second dummy channel structures are arranged in a line in the first horizontal direction between the lower selection line and the upper selection line.

15. The integrated circuit device according to claim 11, wherein, The bottom surface of the upper selection line extends along the third horizontal direction at the second height.

16. The integrated circuit device according to claim 11, wherein, The bottom surface of the upper selection line extends along the third horizontal direction at a third height that is higher than the second height.

17. An integrated circuit device, the integrated circuit device comprising: Base; Multiple character line cutting areas are arranged on the base; as well as Multiple unit block regions are arranged one by one between the multiple word line cutting regions, and each includes a serial selection line structure. In each of the plurality of unit block regions, the string selection line structure includes a string selection bend line, which includes a lower horizontal extension extending horizontally at a first height above the base, an upper horizontal extension extending horizontally at a second height higher than the first height, and a vertical extension connecting the lower horizontal extension and the upper horizontal extension. The string selection line structure also includes a lower string selection line, which extends horizontally at a first height at a position spaced apart from the lower horizontal extension of the string selection bend line, and includes a portion that overlaps with the upper horizontal extension of the string selection bend line in the vertical direction.

18. The integrated circuit device according to claim 17, wherein, The plurality of unit block regions include first unit block regions and second unit block regions that are adjacent to each other, and a first character line cutting region selected from the plurality of character line cutting regions is located between the first unit block region and the second unit block region, and The serial selection line structure of the first unit block region and the serial selection line structure of the second unit block region have a mirror-symmetric structure relative to the first word line cutting region.

19. The integrated circuit device according to claim 17, wherein, In each of the plurality of unit block regions, the string selection line structure further includes: The intermediate string selection line extends horizontally at a second height and includes a portion that overlaps with the lower string selection line in the vertical direction; and The upper selection line extends horizontally at a second height and includes a portion that overlaps with the lower horizontal extension of the selection bend line in the vertical direction.

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