Use an adaptive coupling device to couple the bias circuit to the amplifier

Abstract

The present disclosure relates to coupling a bias circuit to an amplifier using an adaptive coupling device. An exemplary bias network includes: an adaptive bias circuit configured to generate a bias signal for the amplifier, and further includes a coupling circuit configured to couple the adaptive bias circuit to the amplifier. The coupling circuit is adaptive in that its impedance depends on the power level of the input signal to be amplified by the amplifier. By configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal, the coupling circuit can adapt to the input power level, so that the bias signal can be modified to reduce / optimize at least some of the nonlinearities that the adaptive bias circuit can introduce into the bias signal.

Description

Technical Field

[0001] The present disclosure relates generally to radio frequency (RF) systems and, more particularly, to conversion networks for amplifiers. Background Art

[0002] Radio systems are systems that send and receive signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems are commonly used for wireless communications, cellular / wireless mobile technology being a prominent example, but can also be used for cable communications such as cable television. In both types of systems, amplifiers play a vital role, such as power amplifiers used to amplify RF signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0004] Figure 1 A schematic diagram of an antenna device with a power amplifier according to some embodiments of the present disclosure is provided, which power amplifier can be biased by a bias network of a bias circuit and an adaptive coupling circuit.

[0005] Figure 2A A schematic diagram of a power amplifier with a bias circuit and no coupling circuit is provided.

[0006] Figure 2B A schematic diagram of a power amplifier having a bias circuit and a fixed coupling circuit according to some embodiments of the present disclosure is provided;

[0007] Figure 3 A schematic diagram is provided showing how the output of a third-order intercept point (OIP3) depends on the output power of an amplified RF signal generated by a power amplifier for different resistance values ​​of a resistor used to couple a bias circuit to a power amplifier, according to some embodiments of the present disclosure;

[0008] Figure 4A A schematic diagram of a power amplifier with a bias network including a bias circuit and an adaptive coupling circuit according to some embodiments of the present disclosure is provided.

[0009] Figure 4B A schematic diagram is provided of how the resistance of an adaptive coupling circuit depends on the input power of a power amplifier according to some embodiments of the present disclosure.

[0010] Figure 5 Provided is a schematic diagram of an adaptive coupling circuit implemented using a P-type metal oxide semiconductor (PMOS) transistor according to some embodiments of the present disclosure;

[0011] Figure 6 Provided is a schematic diagram of an adaptive coupling circuit implemented using an N-type metal oxide semiconductor (NMOS) transistor according to some embodiments of the present disclosure;

[0012] Figure 7 Provided is a schematic diagram of an adaptive coupling circuit implemented using a PMOS transistor and an NMOS transistor according to some embodiments of the present disclosure;

[0013] Figure 8 A block diagram is provided according to some embodiments of the present disclosure, the block diagram illustrating a method of amplifying an input signal using a power amplifier coupled to a bias circuit using an adaptive coupling circuit.

[0014] Fig. 9 A block diagram of an exemplary data processing system according to some embodiments of the present disclosure is provided, which exemplary data processing system can be configured to implement or control the use of a power amplifier to amplify or boost at least a portion of a signal, which power amplifier is coupled to a bias circuit using an adaptive coupling circuit. DETAILED DESCRIPTION

[0015] Overview

[0016] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0017] In order to illustrate the bias network for an amplifier in an RF system proposed herein, it may be useful to first understand the phenomena that may be at work in such a system. The following basic information may be considered as a basis for appropriately interpreting the present disclosure. This information is provided for the purpose of explanation only and, therefore, should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications. Although the following description may be provided for the example of an amplifier as a power amplifier, embodiments of the present disclosure are equally applicable to other types of amplifiers, such as low noise amplifiers, linear amplifiers, variable gain amplifiers, etc.

[0018] In the context of wireless radio systems, an antenna is a device that acts as an interface between radio waves that propagate wirelessly through space and electrical currents that move in metallic conductors used with a transmitter or receiver. During transmission, a radio transmitter can provide an electrical signal that is amplified by a power amplifier, which then provides an amplified version of the signal to the terminals of the antenna. The antenna can then radiate energy from the signal output by the power amplifier as radio waves. Similarly, in a wired radio system, the electrical signal is first amplified by a power amplifier before being transmitted over a wired cable connection.

[0019] Linear and efficient power amplifiers are critical to modern communication systems, both for wireless systems such as fifth generation cellular technology (5G) systems as well as cable wireless systems. A bias circuit that provides a bias signal to a power amplifier contributes to the linearity and efficiency of the power amplifier. For example, adaptive bias circuits have been developed in an attempt to optimize the efficiency of a power amplifier. Such circuits are "adaptive" because the bias signal provided to the power amplifier depends on the signal to be amplified by the power amplifier, which can be advantageous in terms of improving the efficiency of the power amplifier. However, the bias circuit itself may inadvertently add nonlinearity to the bias signal, thereby reducing the linearity of the power amplifier. In other words, one disadvantage of conventional bias circuits for power amplifiers, particularly adaptive bias circuits, is that the linearity of the power amplifier may be reduced due to the nonlinearity of the bias circuit.

[0020] A common conventional approach to providing adaptive biasing to a power amplifier while attempting to maintain the linearity of the power amplifier is to implement a biasing network that couples the adaptive biasing circuit to the power amplifier using a fixed coupling component (e.g., a fixed resistor). However, the inventors of the present invention have recognized that coupling the adaptive biasing circuit to the power amplifier using a fixed coupling component can reduce the power and / or efficiency of the power amplifier.

[0021] Various embodiments of the present disclosure provide systems and methods that are intended to improve one or more of the challenges described above in providing linear and efficient amplifiers (e.g., but not limited to, power amplifiers, linear amplifiers, low noise amplifiers, or variable gain amplifiers) for RF systems (e.g., but not limited to, phased antenna arrays for 5G cellular technology or cable communication systems). In one aspect of the present disclosure, an exemplary bias network for an amplifier includes an adaptive bias circuit / arrangement configured to generate a bias signal for the amplifier, and also includes a coupling circuit / arrangement configured to couple the adaptive bias circuit to the amplifier to provide a bias signal to the amplifier. In particular, the coupling circuit is configured so that the impedance of the coupling circuit depends on the power level of the input signal to be amplified by the amplifier (i.e., the coupling circuit is an adaptive coupling circuit). As described above, the operation of the adaptive bias circuit can introduce some nonlinearity into the bias signal, which can distort the input signal to be amplified by the amplifier. The adaptive coupling circuit described herein is configured to receive a bias signal generated by the adaptive bias circuit at its input. The adaptive coupling circuit is also configured to modify the received bias signal to generate a modified bias signal, wherein the modified bias signal is then provided to the amplifier. In particular, by configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal to the amplifier, the coupling circuit can adapt to the input power level and the bias signal can be modified in this way to reduce or optimize at least some of the nonlinearities introduced into the bias signal by the adaptive bias circuit.

[0022] Both the adaptive bias circuit and the adaptive coupling circuit can be viewed as "modifying" the bias signal used to bias the amplifier, but the modifications provided by each of the two circuits are different. In particular, while the adaptive bias circuit can be configured to ensure that the bias signal is based on the power level at which the amplifier is operating, the adaptive coupling circuit can be configured to reduce or eliminate at least some nonlinear components from the bias signal generated by the bias circuit, which nonlinear components may be introduced into the bias signal by the bias circuit itself, which may optimize the bias signal based on the bias signal, thereby reducing the linear performance of the amplifier. Embodiments of the present disclosure are based on the following recognition: the nonlinearity of the adaptive bias signal can be based on the input power level (i.e., the power level of the signal to be amplified by the amplifier) ​​and the degree of nonlinearity in the adaptive bias signal may depend on the impedance between the adaptive bias circuit and the amplifier input. Therefore, providing a bias network for an amplifier, wherein the adaptive coupling circuit can be configured to adapt the impedance between the amplifier input and the adaptive bias circuit based on the input power level, can improve (e.g., optimize) the overall linearity of the amplifier.

[0023] As will be appreciated by those skilled in the art, various aspects of the present disclosure, and in particular various aspects of the bias network for providing a modified bias signal to an amplifier using an adaptive coupling circuit, as described herein, can be implemented in various ways, such as as a method, a system, a computer program product, or a computer-readable storage medium. Thus, various aspects of the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which are generally referred to herein as "circuits," "arrangements," "modules," or "systems." At least some of the functions described in the present disclosure can be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of any method described herein can be performed by different processing units. In addition, various aspects of the present disclosure can take the form of a computer program product embodied in one or more computer-readable media, preferably non-transitory, having computer-readable program code embodied (e.g., stored) thereon. In various embodiments, such a computer program may, for example, be downloaded (updated) to existing devices and systems (eg, existing bias networks of power amplifiers and / or their controllers, etc.), or stored when these devices and systems are manufactured.

[0024] The following detailed description gives various descriptions of certain embodiments. However, the innovations described herein may be embodied in a variety of different ways, for example, as defined and covered by the claims or selected examples. In the following description, reference is made to the accompanying drawings in which similar reference numerals may indicate identical or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. In addition, it will be understood that some embodiments may include more elements than shown in the figures and / or a subset of the elements shown in the figures. In addition, some embodiments may combine any suitable combination of features from two or more of the accompanying drawings.

[0025] The description may use the phrase "in one embodiment" or "in an embodiment", which may refer to one or more of the same or different embodiments, respectively. Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc. to describe a common object only indicates that different instances of the same object are to be referenced, and is not intended to imply that the objects described in this way must be in a given order in time, space, level, or any other manner. The various aspects of the illustrative embodiments are described using terms commonly used by those skilled in the art to convey the essence of their work to other technicians in the field. The terms "substantially", "approximately", and "roughly" may be used to generally refer to within + / -20% of a target value based on the context of a specific value described herein or known in the art. For the purposes of this disclosure, the phrase "A and / or B" or the symbol "A / B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used with reference to a measurement range, the term "between..." includes the ends of the measurement range. As used herein, the notation "A / B / C" means (A, B and / or C).

[0026] Example antenna device with amplifier biased using adaptive coupling circuit

[0027] As described above, embodiments of the present disclosure relating to bias networks for amplifiers may be applied to wireless as well as cable communication systems. For illustrative purposes only, Figure 1 As shown in and described below, the exemplary communication system / device (particularly an example of a wireless communication system / device) may include one or more amplifiers biased by any of the bias networks described herein.

[0028] Figure 1 A schematic diagram of an antenna device 100 according to some embodiments of the present disclosure is provided, the antenna device 100 being, for example, a phased array system / device. Figure 1 As shown, the antenna device 100 may include an antenna array 110, a beamformer array 120, and an up / down converter (UDC) circuit 140. The antenna device 100 may further include one or more low noise amplifiers 142 and one or more power amplifiers 146, any of which may be biased by any bias network of the bias circuits and adaptive coupling circuits described herein.

[0029] Typically, antenna array 110 may include one or more, typically a plurality of, antenna elements 112 (in order not to clutter the drawing). Figure 1Only one of them is labeled with a reference number. In various embodiments, antenna element 112 can be a radiating element or a passive element. For example, antenna element 112 can include a dipole, an open waveguide, a slotted waveguide, a microstrip antenna, etc. In some embodiments, antenna element 112 can include any suitable element configured to wirelessly transmit and / or receive RF signals. Although Figure 1 A certain number of antenna elements 112 are shown, but it should be understood that various embodiments may be implemented using arrays of any number of two or more antenna elements. In addition, although the present disclosure may discuss certain embodiments as one type of antenna array, it should be understood that the embodiments disclosed herein may be implemented using different types of antenna arrays, such as time domain beamformers, frequency domain beamformers, dynamic antenna arrays, antenna arrays, passive antenna arrays, etc.

[0030] Similarly, the beamformer array 120 may include one or more, typically a plurality of, beamformers 122 (in order not to clutter the drawing). Figure 1 1 . The beamformers 122 may be viewed as transceivers (e.g., devices that can send and / or receive signals, in this case RF signals) that feed the antenna elements 112. In some embodiments, a single beamformer 122 of the beamformer array 120 is associated with a single antenna element 112 of the antenna array 110 in a one-to-one correspondence (i.e., different beamformers 122 are associated with different antenna elements 112). In other embodiments, more than one beamformer 122 may be associated with a single antenna element 112, e.g., two beamformers 122 may be associated with a single antenna element 112 if the antenna elements are dual-polarized antenna elements.

[0031] In some embodiments, each beamformer 122 may include a switch 124 to switch the path from the corresponding antenna element 112 to a receiver or transmitter path. Figure 1 Although not specifically shown in the figure, in some embodiments, each beamformer 122 may also include another switch to switch the path from the signal processor (also not shown) to the receiver or transmitter path. Figure 1As shown, in some embodiments, the transmitter path (TX path) of each beamformer 122 may include a phase shifter 126 and a variable (e.g., programmable) gain amplifier 128, while the receiver path (RX path) may include a phase adjuster 130 and a variable (e.g., programmable) gain amplifier 132. The phase shifter 126 may be configured to adjust the phase of the RF signal (TX signal) to be transmitted by the antenna element 112, and the variable gain amplifier 128 may be configured to adjust the amplitude of the TX signal to be transmitted by the antenna element 112. Similarly, the phase shifter 130 and the variable gain amplifier 132 may be configured to adjust the RF signal (RX signal) received by the antenna element 112 before providing the RX signal to other circuits, such as the UDC circuit 140, a signal processor (not shown), etc. The beamformer 122 can be considered to be "in the RF path" of the antenna device 100 because the signals passing through the beamformer 122 are RF signals (i.e., the TX signal that can pass through the beamformer 122 is an RF signal that has been up-converted from a low frequency signal, such as an intermediate frequency (IF) signal or a baseband signal, by the UDC circuit 140, and the RX signal that can pass through the beamformer 122 is an RF signal that has not yet been down-converted to a low frequency signal, such as an IF signal or a baseband signal, by the UDC circuit 140).

[0032] Despite Figure 1 1 shows a switch (i.e., switch 124) for switching from the transmitter path to the receive path, but in other embodiments of the beamformer 122, other components, such as a duplexer, may be used. Figure 1 An embodiment is shown in which the beamformer 122 includes phase shifters 126, 130 (also referred to as "phase adjusters") and variable gain amplifiers 128, 132, but in other embodiments, any beamformer 122 may include other components to adjust the amplitude and / or phase of the TX and / or RX signals. In yet another embodiment, one or more beamformers 122 may not include phase shifters 126 and / or phase shifters 130, as a phase shifting module in the LO path may alternatively be used to perform the desired phase adjustment. In other embodiments, the phase shifters of the beamformer 122 may be used to combine the phase adjustment performed in the LO path with the phase adjustment performed in the RF path.

[0033] Regarding the details of the UDC circuit, in general, the UDC circuit 140 may include an up-converter and / or a down-converter circuit, that is, in various embodiments, the UDC circuit 140 may include 1) an up-converter circuit but not a down-converter circuit, 2) a down-converter circuit but not an up-converter circuit, or 3) an up-converter circuit and a down-converter circuit. Figure 1As shown, the downconverter circuit of the UDC circuit 140 may include an amplifier 142 and a mixer 144, while the upconverter circuit of the UDC circuit 140 may include an amplifier 146 and a mixer 148. In addition, the UDC circuit 140 may further include a phase shift module 150 configured to provide a phase shift in the LO path.

[0034] In some embodiments, a single UDC circuit 140 can provide upconverted RF signals to any of the beamformers 122 and / or receive RF signals to be downconverted from these beamformers 122. Thus, a single UDC circuit 140 can be associated with multiple beamformers 122 of the beamformer array 120 (e.g., there may be 48 beamformers 122 in the beamformer array 120, associated with 48 antenna elements 112 of the antenna array 110). Figure 1 The dashed and dotted lines are schematically shown in FIG. 1 , which connect the various elements of the beamformer array 120 and the UDC circuit 140. That is, Figure 1 It is shown that a dashed line may connect the downconverter circuit (i.e., amplifier 142) of the UDC circuit 140 to the RX paths of two different beamformers 122, and a dashed line may connect the upconverter circuit (i.e., amplifier 146) of the UDC circuit 140 to the TX paths of two different beamformers 122.

[0035] The mixer 144 in the downconverter path of the UDC circuit 140 may have at least two inputs and one output. The two inputs of the mixer 144 include an input from an amplifier 142, which may be, for example, a low noise amplifier, and an input from a phase shift module 150. The amplifier 142 may be a power amplifier biased by any of the bias networks described herein. One output of the mixer 144 is an output that provides a downconverted signal 156, which may be, for example, an IF signal 156. The mixer 144 may be configured to receive an RF RX signal from an RX path of one of the beamformers 122 after being amplified by the amplifier 142, receive at its first input and receive at its second input a signal from the phase shift module 150, and mix the two signals to downconvert the RF RX signal to a lower frequency, thereby generating a downconverted RX signal 156, for example, an RX signal at an IF. Therefore, the mixer 144 in the downconverter path of the UDC circuit 140 may be referred to as a "downconversion mixer".

[0036] The mixer 148 in the upconverter path of the UDC circuit 140 may have at least two inputs and one output. The two inputs of the mixer 148 include the input from the phase shift module 150 and the lower frequency TX signal 158, for example, the TX signal at the IF. One output of the mixer 148 is the output to the amplifier 146. The amplifier 146 may be a power amplifier biased by any bias network described herein. The mixer 148 may be configured to receive the IF TX signal 158 (i.e., the lower frequency, such as IF, signal to be transmitted) at its first input and receive the signal from the phase shift module 150 at its second input, and mix the two signals to upconvert the IF TX signal to the desired RF frequency, generating an upconverted RF TX signal, which is provided to the TX path of one of the beamformers 122 after being amplified by the power amplifier 146. Therefore, the mixer 148 in the upconverter path of the UDC circuit 140 may be referred to as an "upconversion mixer".

[0037] As known in communications and electronic engineering, an IF is a frequency to which a carrier can be moved as an intermediate step in transmission or reception. An IF signal can be created by mixing a carrier signal with an LO signal in a process called heterodyning, resulting in a difference or beat frequency signal. Converting to an IF can be useful for a number of reasons. One reason is that when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and adjust. Another reason is that low frequency transistors generally have higher gain, so fewer stages may be needed. Yet another reason is to improve frequency selectivity, since it is easier to make a sharp, selective filter at a lower fixed frequency.

[0038] It should also be noted that although some of the descriptions provided herein refer to signals 156 and 158 as IF signals, these descriptions are equally applicable to embodiments in which signals 156 and 158 are baseband signals. In such embodiments, the frequency mixing of mixers 144 and 148 may be zero-IF mixing (also referred to as "zero-IF conversion"), where the center frequency of the LO signal used to perform the mixing may be within the range of the RF RX / TX frequencies.

[0039] In some embodiments, the phase shift module 150 in the LO path can be configured to provide a desired phase shift to the LO signal 160 before providing the LO signal to the mixers 144, 148. Thus, in some embodiments, instead of receiving the LO signal 160 (which may be generated by the LO) at one of their inputs, each mixer 144, 148 can receive a phase shifted version of the LO signal 160. Moving the phase shift operation out of the signal path (e.g., between the digital circuitry that processes the signal 156, 158 and the antenna element 112, and through the antenna element 112 in the wireless domain) of the LO path (e.g., between the LO signal generator and the mixers 144, 148) can advantageously reduce the negative effects of phase shift on signal quality.

[0040] Despite Figure 1 Not specifically shown, but in further embodiments, the UDC circuit 140 further includes a balancer configured to mitigate in-phase and quadrature (IQ) signal imbalances due to mismatches, such as in each of the TX and RX paths.

[0041] In addition, despite the Figure 1 Although not specifically shown in the drawings, in other embodiments, the antenna device 100 may include other examples of a combination of the antenna array 110, the beamformer array 120, and the UDC circuit 140 as described herein.

[0042] The antenna device 100 can direct the electromagnetic radiation pattern of the antenna array 110 in a particular direction, thereby enabling the antenna array 110 to generate a main beam in that direction and side lobes in other directions. The main beam of the radiation pattern can be generated based on a constructive inference of the transmitted RF signal based on the phase of the transmitted signal. The sidelobe level can be determined by the amplitude of the RF signal transmitted by the antenna element. The antenna device 100 can generate a desired antenna pattern by providing a phase shifter setting of the antenna element 112, for example, using a phase shift module 150 and / or a phase shifter of the beamformer 122.

[0043] As mentioned above, linear and efficient power amplifiers are critical to modern communication systems. Therefore, optimizing the power amplifier 146 in terms of its linearity and efficiency is important for the antenna device 100 as well as other RF devices, both wireless and cable.

[0044] Conventional bias network with adaptive bias circuit

[0045] Figure 2AA schematic diagram of an RF transmitter (i.e., RF transmission system) 200A is provided, which includes a power amplifier 210 having a bias network 220A, the bias network including a power detector 230 and a bias circuit 240, without any special coupling circuit to couple the bias circuit 240 to the power amplifier 210. Figure 2A In the following and subsequent figures, the signal RF_in indicated by the reference numeral 202 represents the signal to be amplified by the power amplifier 210, sometimes also referred to as the "input signal." For example, in some embodiments, the input signal 202 can be the RF TX signal generated by the mixer 148 of the antenna device 100, and the power amplifier 210 can be the power amplifier 146 of the antenna device 100. However, in other embodiments, the input signal 202 can be any signal within the RF frequency range, which will be amplified by the power amplifier 210 before being further transmitted by a wireless or wired connection.

[0046] The power detector 230 is configured to detect the power of the input signal 202 and provide a signal 232 indicating the detected power of the input signal 202 to the bias circuit 240. The bias circuit 240 may be an adaptive bias circuit such as Figure 2A As shown in FIG. 2 , the bias signal 242 is configured to generate an adaptation / modulation based on the input signal envelope power level. The bias signal 242 can then be combined with the input signal 202, such as Figure 2A 2, where the combiner 260 performs the combining to generate a combined signal 262A including the input signal 202 and the bias signal 242. The power amplifier 210 is then configured to amplify the combined signal 262A to generate Figure 2A and the amplified RF TX signal 212A shown in subsequent figures as signal RF_out. Figure 2A 2 shows that the combination of input signal 202 and bias signal 242 is performed outside of power amplifier 210, but in some embodiments, the combination can be performed inside power amplifier 210. In other words, in some embodiments, instead of Figure 2A The power amplifier 210 is shown receiving a single combined signal 262A. The power amplifier 210 may be configured to receive the input signal 202 and the bias signal 242 separately and combine them as part of performing amplification to generate an amplified RF TX signal 212 .

[0047] Although bias network 220A may advantageously allow adaptive biasing to be performed, bias circuit 240 may add nonlinearity to bias signal 242. As a result, the linearity of power amplifier 210 may be degraded due to the nonlinearity of bias circuit 240. A technique to address this issue is to include a fixed coupling resistor that is used to couple bias circuit 240 to power amplifier 210, such as Figure 2B shown.

[0048] Figure 2B A schematic diagram of an RF transmitter 200B is provided, which includes a power amplifier 210, whose bias network 220B includes a power detector 230 and a bias circuit 240, such as Figure 2A In addition, Figure 2B As shown, bias network 220B further includes a fixed resistor 250 located between bias circuit 240 and power amplifier 210. Figure 2A The same reference numerals as used in Figure 2B The components are used to indicate and Figure 2A Therefore, for the sake of brevity, the description thereof will not be repeated here, and only the differences between these figures will be described.

[0049] like Figure 2B As shown, instead of bias signal 242 being provided as is to power amplifier 210 (possibly as part of a signal comprising a combination of bias signal 242 and input signal 202), bias signal 242 is applied to a first terminal of fixed resistor 250, resulting in a modified bias signal 252 being output at a second terminal of fixed resistor 250. Modified bias signal 252 may then be combined with input signal 202, as shown in FIG. Figure 2B As shown, the combiner 260 performs the combining to produce a combined signal 262B including the input signal 202 and the modified bias signal 252. The power amplifier 210 is then configured to amplify the combined signal 262B to generate an amplified RF TX signal (RF_out) 212B, as shown. Figure 2B As shown. Figure 2A Similar, although Figure 2B The combination of the input signal 202 and the modified bias signal 252 is shown as being performed external to the power amplifier 210 , but in some embodiments, the combination may be performed internal to the power amplifier 210 .

[0050] In some implementations, bias network 220B may provide advantages over bias network 220A because coupling bias circuit 240 to power amplifier 210 using fixed resistor 250 may at least partially isolate nonlinearity of bias circuit 240 from power amplifier 210 and improve compensation linearity of power amplifier 210. As is known in the art, in power amplifiers, "backoff" refers to a measure of how much input power should be reduced in order to achieve a desired output linearity and power (e.g., backoff may be measured as a ratio between an input power that provides maximum power and an input power that provides desired linearity).

[0051] However, the inventors of the present disclosure have realized that the power, noise performance, and maximum efficiency of the power amplifier 210 may be reduced due to the use of the fixed resistor 250. Figure 3 To explain, according to some embodiments of the present disclosure, a schematic diagram of how the OIP3 output depends on the output power (Pout_total) of the amplified RF signal generated by the power amplifier is provided for different resistance values ​​of a resistor used to couple the bias circuit to the power amplifier. Figure 3 The different curves shown in relate to different values ​​of resistors that may couple the bias circuit to the power amplifier, e.g. Figure 2B The fixed resistor 250 shown in FIG. 1 is a fixed resistor 250, wherein the resistance value is used to mark the different curves. Figure 3 As shown, for resistance values ​​between 1 and 50 ohms (Ω), first, the OIP3 output can be advantageously increased as the resistance increases, which means that increasing the value of fixed resistor 250 can provide advantages in improving the linearity of the output power of power amplifier 210. However, at some point, further increasing the resistance value may result in a decrease in the OIP3 output, such as Figure 3 As shown, the resistance value is 60Ω, for which the OIP3 output is less than 50Ω. The threshold at which increasing the resistance further produces an adverse effect may be different in circuits having different configurations and different input signal powers. Therefore, the inventors of the present invention have recognized that for a given circuit architecture and a given input power of the signal to be amplified by the power amplifier, there may be some optimal value or a range of values ​​for the resistance (or more generally, impedance) of the coupling circuit used to couple the output of the bias circuit to the input of the power amplifier. Therefore, it may be desirable to be able to adaptively change this value in terms of achieving an improved balance between power, efficiency and linearity of the power amplifier. The implementation forms the basis of various bias networks with adaptive coupling circuits, which will be described in more detail below.

[0052] Example bias network with bias circuit and adaptive coupling circuit

[0053] Figure 4AA schematic diagram of an RF transmitter 400 including a power amplifier 210 according to some embodiments of the present disclosure is provided, and as described above, the RF transmitter 400 has a bias network 420 including a bias circuit 440 and an adaptive coupling circuit 450. In various embodiments, the RF transmitter 400 may be included in an RF device or may be an RF device. Some examples of such RF devices include, but are not limited to, a mobile device (e.g., a UE of a wireless cellular network), a base station of a wireless cellular network, or an RF transmitter of a wired communication network.

[0054] In various embodiments, the power amplifier 210 included in the RF transmitter 400 may include any suitable power amplifier, such as, but not limited to, one of a Doherty power amplifier, a Class A power amplifier, a Class B power amplifier, a Class AB power amplifier, or a Class C power amplifier. The power amplifier 210 included in the RF transmitter 400 may be configured to amplify the input signal (RF_in) 202 as described above to generate an amplified RF TX signal 412 (RF_out).

[0055] In various embodiments, the bias circuit 440 may be any suitable bias circuit configured to generate a bias signal 442 for biasing the power amplifier 210. In some embodiments, the bias circuit 440 may be an adaptive bias circuit configured to generate a bias signal that may depend on the power level at which the power amplifier 210 is operable. Various adaptive bias circuits are known in the art, and therefore, for the sake of brevity, their description is not provided here, but any of those circuits may be used as the bias circuit 440. In some embodiments, the bias network 400 may include a power detector 430 configured to receive the incoming signal 202 and provide a signal 432 to the bias circuit 440, which is configured to indicate to the bias circuit 440 the power level of the input signal 202 detected by the power detector 430. In some embodiments, the power detector 430 may be part of the bias circuit 440. In various embodiments, any power detector used in the art may be used as the power detector 430, such as a peak detector, an envelope detector, a resistor, or even just a short circuit.

[0056] The adaptive coupling circuit 450 may be a circuit for coupling the output of the bias circuit 440 and the input of the power amplifier 210 in such a manner that the bias signal 442 generated by the bias circuit 440 may be modified by the adaptive coupling circuit 450 to generate a modified bias signal 452, which may be based not only on the bias signal 442 but also on the input power of the signal 202 to be amplified by the power amplifier 210. To this end, the adaptive coupling circuit 450 may be configured such that the impedance (e.g., resistance) of the adaptive coupling circuit 450 may vary according to the power of the input signal 202. In some embodiments, the variation may be as follows: Figure 4B The curve shown schematically illustrates that in some embodiments, the impedance of the adaptive coupling circuit 450 can be maximum for a certain value or a first range of values ​​402 of the input power (i.e., the power of the input signal 202), then gradually decreases for a second range of input power values ​​404, and finally, is minimum for a certain value or a third range of values ​​406 of the input power. Figure 4B A linear decrease in impedance in the second range 404 is shown, but in various embodiments, the impedance in the second range 404 may be based on the Figure 4B Configuring the adaptive coupling circuit 450 to adaptively change its impedance based on the power of the input signal 202 may achieve an improved balance between power, efficiency, and linearity of the power amplifier 210 .

[0057] The adaptive coupling circuit 450 may be viewed as a circuit that provides a variable level of isolation (eg, adaptive isolation) between the bias circuit 440 and the power amplifier 210 , where the isolation depends on the power of the input signal 202 .

[0058] At relatively low input powers (e.g., in the first range 402), the adaptive coupling circuit 450 can provide limited optimal isolation between the bias circuit 440 and the power amplifier 210, wherein the isolation can control (e.g., reduce or limit) nonlinearities that can be added by the bias circuit 440. At such input powers, the adaptive coupling circuit 450 can be configured to function as a predistortion circuit that can be configured to reduce or eliminate nonlinearities of the power amplifier 210 at back-off power levels. To this end, at low input powers, the adaptive coupling circuit 450 can be configured to provide relatively high isolation, which means that the impedance of the adaptive coupling circuit 450 can be relatively high, such as Figure 4B For example, in some embodiments, at relatively low input power levels, the adaptive coupling circuit 450 can be configured to have a resistance between approximately 40Ω and 60Ω, including all values ​​and ranges therein.

[0059] On the other hand, at relatively high input powers (e.g., in the third range 406), the adaptive coupling circuit 450 may be configured to provide minimal or even no isolation between the bias circuit 440 and the power amplifier 210, which may advantageously allow for increased output power and efficiency of the power amplifier 210. In some embodiments, at such high input powers, for example, at power levels approaching a 1 decibel (dB) compression point (P1dB), the adaptive coupling circuit 450 may be configured to act as a short circuit (where P1dB may refer to an output power level at which the gain of the power amplifier 210 may be reduced by 1 dB from its constant value). This means that at relatively high input powers, the impedance of the adaptive coupling circuit 450 may be relatively low, such as Figure 4B For example, in some embodiments, at relatively high input power levels, the adaptive coupling circuit 450 can be configured to have a resistance between approximately 1Ω and 30Ω, including all values ​​and ranges therein.

[0060] The adaptive coupling circuit 450 may modify the bias signal 442 generated by the bias circuit 440 to generate a modified bias signal 452 that is based on the bias signal 442 and also based on the power level of the input signal 202. The modified bias signal 452 may then be combined with the input signal 202, as schematically shown in FIG. 4, wherein the combining is performed by the combiner 260 to produce a combined signal 462 that includes the input signal 202 and the modified bias signal 452. The power amplifier 210 is then configured to amplify the combined signal 462 to generate an amplified RF TX signal 412 (RF_out). Again, although in Figure 2A 4 shows that the combination of the input signal 202 and the modified bias signal 452 is performed external to the power amplifier 210, but in some embodiments, the combination can be performed internal to the power amplifier 210. In other words, in some embodiments, instead of the power amplifier 210 receiving a single combined signal 462 as shown in FIG. 4, the power amplifier 210 can be configured to receive the input signal 202 and the modified bias signal 452 separately and combine them as part of performing amplification to generate an amplified RF TX signal 412. Therefore, in general, in various embodiments, the input signal 202 and the modified bias signal 452 can be provided to the input 410 of the power amplifier 210 together as a combined signal 462 or as separate signals.

[0061] By implementing an adaptive isolator between bias circuit 440 and power amplifier 210 that can control the isolation value based on the input power range, implementing adaptive coupling circuit 450 as described herein can improve P1dB and the linearity of power amplifier 210. In some embodiments, the isolation level of adaptive coupling circuit 450 can be higher at relatively low input power levels to isolate the nonlinearity of bias circuit 440 and improve the compensated OIP3 of power amplifier 210. In some embodiments, the isolation level of adaptive coupling circuit 450 can be reduced at higher input powers to, for example, implement bias ramping and improve P1dB, high power linearity, and efficiency of power amplifier 210.

[0062] There are many different ways as to how the adaptive coupling circuit 450 can be implemented to function according to the principles described herein, all of which are within the scope of the present disclosure. For example, in some embodiments, the adaptive coupling circuit 450 can be implemented as an adaptive resistor that is configured such that the resistance value of the resistor depends on the power level of the input signal 202 as described herein. For example, in some embodiments, the resistance of such an adaptive resistor can be about 50Ω at relatively low input power levels, for example, to isolate nonlinear distortion that may be introduced by the bias circuit 440 from the input of the power amplifier 210 in order to reduce, minimize, or avoid affecting the PA compensation OIP3 of the power amplifier 210. In addition, in some embodiments, the resistance of such an adaptive resistor can be, for example, about 2Ω at relatively high input power levels to improve the P1dB, high power linearity, and efficiency of the power amplifier 210.

[0063] exist Figure 5-7 Some example embodiments of how to implement the adaptive coupling circuit 450 are shown in FIG. 4 , as described below.

[0064] Example Implementation of Adaptive Coupling Circuit

[0065] Figure 5 A schematic diagram of a first example of an RF transmitter 500 is provided, the RF transmitter 500 including the power amplifier 210 and the bias network 420 including the bias circuit 440 and the adaptive coupling circuit 450 as described above (i.e., the RF transmitter 500 is a first example implementation of the RF transmitter 400 shown in FIG. 4, wherein FIG. 4 and Figure 5 The same figure numbers in the figure refer to the same or similar elements as those described with reference to Figure 4, and therefore, for the sake of brevity, the description of these elements provided in Figure 4 will not be repeated here). Figure 5 The example of FIG. 4 shows that the adaptive coupling circuit 450 can be implemented using a PMOS transistor according to some embodiments of the present disclosure, where Figure 5 The dashed outline of illustration 550 Figure 5 Details of an example of adaptive coupling circuit 450 are shown.

[0066] like Figure 5 As shown, in some embodiments, the adaptive coupling circuit 450 may include a transistor 510 having a pair of source and drain (S / D) terminals 502-1 and 502-2 and a gate terminal 504. The transistor 510 is a FET. As is well known, for a FET, the designation of which terminal in a portion of the S / D terminals is the source terminal and which terminal is the drain terminal is interchangeable. Therefore, these terminals may be referred to as a first S / D terminal 502-1 and a second S / D terminal 502-2, wherein in some embodiments, the first S / D terminal 502-1 may be a source terminal and the second S / D terminal 502-2 may be a drain terminal, while in other embodiments, the first S / D terminal 502-1 may be a drain terminal and the second S / D terminal 502-2 may be a source terminal.

[0067] In some embodiments, the first S / D terminal 502-1 of the transistor 510 can be coupled to the input signal 202 and the input 410 of the power amplifier 210 (possibly with the combiner 260 therebetween as shown in FIG. 4 ), while the second S / D terminal 502-2 can be coupled to the output 442 of the bias circuit 440, as shown in FIG. Figure 5 As shown. Figure 5 In the example shown, transistor 510 is a PMOS transistor. Since a PMOS transistor inherently exhibits a resistance that depends on the voltage on one of its S / D terminals (in addition to being dependent on the voltage on the gate terminal, e.g., the PMOS resistance may depend on the source-gate voltage VSG), coupling one of the S / D terminals of the PMOS transistor to the input signal 202 to be amplified by the power amplifier 210 causes the voltage on that S / D terminal to depend on the input signal 202, which effectively makes the resistance of the PMOS transistor dependent on the input signal (particularly on the power of the input signal). In turn, making the resistance of the PMOS transistor dependent on the power of the input signal can modify the bias signal generated by the bias circuit to reduce or optimize at least some of the nonlinearity introduced into the bias signal by the bias circuit, and the modified bias signal can then be applied to the power amplifier. Therefore, during operation, the current flowing between the first S / D terminal 502-1 and the second S / D terminal 502-2 of the transistor 510 depends on the power of the input signal 202 because the current depends on the resistance of the PMOS transistor 510. As a result, the modified bias signal 452 may be seen as a signal at the first S / D terminal 502 - 1 of the transistor 510 .

[0068] Also like Figure 5As shown, in addition to transistor 510, adaptive coupling circuit 450 may also include resistor 512, which may be coupled between first S / D terminal 502-1 and second S / D terminal 502-2 of transistor 510. Resistor 512 may be referred to as a "shunt resistor." Including resistor 512 may advantageously allow for control of coupling between power amplifier 210 and adaptive bias circuit 440 (e.g., setting a minimum desired coupling). For example, such a resistor may set a maximum resistance of adaptive coupling circuit 450, which may be useful under low input power operation.

[0069] Likewise Figure 5 As shown, gate terminal Vg 504 of transistor 510 may be optionally coupled to bias voltage Vb 520 (e.g., from a current mirror, a bias voltage from a resistor divider, etc.) via or in association with resistor Rg 514, and may also be optionally coupled to ground potential 518 via or in association with capacitor Cg 516. Each of resistor 514 and capacitor 516 are optional; if used, in some embodiments, their values ​​may be optimized to, for example, allow some swing on the PMOS gate to control the slope of its resistance.

[0070] Figure 5 One specific example of bias circuit 440 is shown as a circuit including transistor 540 and resistor Rb 536, although in other embodiments, other implementations of bias circuit 440 are possible and within the scope of the present disclosure. Figure 5 As shown, in such an embodiment of bias circuit 440, first S / D terminal 542-1 of transistor 540 may be coupled to a first terminal of resistor 536, and a second terminal of resistor 536 may be coupled to ground potential 538. Figure 5 As shown, in such an embodiment of bias circuit 440, second S / D terminal 542-2 of transistor 540 can be coupled to VDD 546, and gate terminal 544 of transistor 540 can be coupled to Vbias_PA 548 (bias voltage applied to adaptive bias). In some embodiments, Vbias_PA 548 can be generated by a bandgap circuit or a constant gm (transconductance) bias circuit.

[0071] Figure 6 A schematic diagram of an adaptive coupling circuit 650 implemented using an NMOS transistor 610 according to some embodiments of the present disclosure is provided. The adaptive coupling circuit 650 is a second example of the adaptive coupling circuit 450 of the RF transmitter 400 described above, wherein in FIG. Figure 6In the present invention, the same reference numerals refer to the same or similar elements as those described with reference to FIG. 4 , and therefore, for the sake of brevity, the description of these elements provided in FIG. 4 will not be repeated here. .

[0072] and Figure 5 Similar to transistor 510 shown, in some embodiments, transistor 610 may include a pair of S / D terminals 602-1 and 602-2 and a gate terminal 604. Figure 5 The transistor 510 is similar to that shown in FIG. Figure 6 As shown, in some embodiments, a first S / D terminal 602-1 of transistor 610 can be coupled to input signal 202 and input 410 of power amplifier 210 (possibly with combiner 260 therebetween, as shown in FIG. 4 ), while a second S / D terminal 602-2 can be coupled to output 442 of bias circuit 440. Figure 5 On the contrary, Figure 6 In the example shown, transistor 610 is an NMOS transistor, and adaptive coupling circuit 650 may further include a power detector 630 configured to determine the power of input signal 202, such as by coupling an input of power detector 630 to input signal 202. Figure 6 As shown. In some embodiments, the power detector 630 can be coupled to the input signal 202 using a coupler 628 such as a resistor or a magnetic coupler. In some embodiments, the power detector 630 can include a peak power detector, an envelope power detector, an RMS power detector, etc. The power detector 630 is configured to generate a signal 632 indicating the power of the input signal 202. Therefore, the voltage Vg applied to the gate terminal 604 of the transistor 610 can be configured to be based on the signal 632 (e.g., by coupling the output 632 of the power detector 630 to the gate terminal 604 via the resistor Rg 614, for example, as Figure 6 202-1) and is therefore dependent on the power of the input signal 202. Having the gate voltage Vg of the NMOS transistor 610 depend on the power of the input signal 202 determined by the power detector 630 results in a resistance of the NMOS transistor 610 that depends on the power level of the input signal 202, thereby determining how much current can flow between its source and drain terminals 602. By configuring the adaptive coupling circuit 650 to have a variable resistance that depends on the power level of the input signal 202 amplified by the power amplifier 210, the adaptive coupling circuit 650 can modify the bias signal 442 at the first S / D terminal 602-1 to generate a modified bias signal 452, e.g., in which at least some of the nonlinearity introduced into the bias signal 442 by the adaptive bias circuit 440 has been reduced or compensated.

[0073] Also like Figure 6 As shown, similar to Figure 5 In addition to transistor 610, adaptive coupling circuit 650 may also include resistor 612, which may be coupled between first S / D terminal 602-1 and second S / D terminal 602-2 of transistor 610. Similar to resistor 512, including resistor 612 may advantageously allow for control of coupling (e.g., setting a minimum desired coupling) between power amplifier 210 and adaptive bias circuit 440. For example, resistor 612 may be used to set a maximum resistance of adaptive coupling circuit 650, which may be useful under low input power operation.

[0074] Figure 6 It is further shown that the gate terminal 604 of the transistor 610 can be further coupled to the ground potential 618 via a capacitor 616 between the resistor Rg 614 and the ground potential 618. Figure 6 As shown, in some embodiments, input 202 can be coupled to first S / D terminal 602-1 via capacitor 626. If used, resistor 614 and capacitor 626 can be used to filter the output signal of the detector and define the NMOS gate impedance, which may cause some swing of the NMOS gate. In some embodiments, capacitor 626 can be replaced by a short circuit.

[0075] Figure 6 Also shown are two illustrations 670 and 680 (in Figure 6 ), which can help explain some further details of implementing the adaptive coupling circuit 450 using NMOS transistors and a power detector, such as an example of the adaptive coupling circuit 650. Inset 670 shows a curve 672, providing an example of how the resistance of the NMOS transistor 610 (represented as "Rnmos" on the y-axis of the coordinate system shown in inset 670) varies depending on the power level of the input signal 202 detected by the power detector 630 (represented as "Vdet" on the x-axis of the coordinate system shown in inset 670 (e.g., the voltage output of the detector 630)). Curve 672 shows that the resistance Rnmos can decrease as the power of the input signal 202 increases, but not in a linear manner. Inset 680 shows a curve 682, providing an example of how the output 632 of the power detector 630 (represented as "Vdet" on the y-axis of the coordinate system shown in inset 680) depends on the input power level of the input signal 202 (represented as "Pin" on the x-axis of the coordinate system shown in inset 680). Curve 682 shows that the power detector output Vdet may increase as the power of the input signal 202 increases.

[0076] Figure 7A schematic diagram of an adaptive coupling circuit 750 implemented using both PMOS transistors and NMOS transistors according to some embodiments of the present disclosure is provided. The adaptive coupling circuit 750 is a third example of the adaptive coupling circuit 450 of the RF transmitter 400 described above, wherein the adaptive coupling circuit 750 is implemented using both PMOS transistors and NMOS transistors according to some embodiments of the present disclosure. Figure 7 In the embodiment, the same reference numerals refer to the same or similar elements as those described with reference to FIG. 4 , and therefore, for the sake of brevity, the description of these elements will not be repeated here. In addition, in some embodiments, the PMOS transistor of the adaptive coupling circuit 750 can be implemented as follows: Figure 5 The PMOS transistor 510 shown, and / or the NMOS transistor of the adaptive coupling circuit 750 may be implemented as follows: Figure 6 The NMOS transistor 610 shown is as described above. Therefore, Figure 5 , 6 The same reference numerals as in 7 refer to Figure 5 and 6 Those elements described are identical or similar, therefore, for the sake of brevity, relative to Figure 5 and Figure 6 The descriptions of these elements are not repeated here.

[0077] Figure 7 An embodiment is shown in which an adaptive coupling circuit 550 having a PMOS transistor 510 is combined with an adaptive coupling circuit 650 having an NMOS transistor 610, wherein the illustration is self-explanatory since the same as Figure 5 and Figure 6 Same illustrations and reference numerals as in the Figure 7 The only different aspect in FIG. 5 is that the resistors previously used as resistor 512 in adaptive coupling circuit 550 and previously used as resistor 612 in adaptive coupling circuit 650 are now replaced by a single resistor 712 shared between PMOS 510 and NMOS 610. Therefore, resistor 712 may also be coupled between first S / D terminal 502-1 and second S / D terminal 502-2 of PMOS transistor 510 and between first S / D terminal 602-1 and second S / D terminal 602-2 of NMOS transistor 610.

[0078] Including both PMOS and NMOS transistors 510, 610 in the adaptive coupling circuit 750 advantageously allows for ensuring that the resistance of the coupling circuit 750 is dependent on the power of the input signal, not only because the PMOS transistor 510 will inherently be dependent on the power when one of its S / D terminals is coupled to the input signal 202, but also because the NMOS transistor 610 together with the power detector 630 can provide additional dependence on the power when the gate voltage of the NMOS transistor 620 is based on the power measured by the power detector 630.

[0079] An amplifier biased by a bias network is operated through an adaptive coupling circuit

[0080] Figure 8 A block diagram is provided that illustrates a method for amplifying an input signal using a power amplifier that is coupled to a bias circuit using an adaptive coupling circuit according to some embodiments of the present disclosure. Although some operations of method 800 are described with reference to the system components shown in FIG4 , in general, any system configured to perform these operations in any order is within the scope of the present disclosure. In some embodiments, control logic associated with RF transmitter 400 may be configured to control the operations of method 800.

[0081] Method 800 may begin at 802 with a bias circuit generating a bias signal for a power amplifier. For example, at 802, adaptive bias circuit 440 may be configured to generate bias signal 442 for power amplifier 210, as described above.

[0082] Next, at 804, the adaptive coupling circuit may generate a modified bias signal based on the bias signal generated by the bias circuit at 802 and also based on the power of the input signal to be amplified by the power amplifier. For example, at 804, the adaptive coupling circuit 450 may be configured to generate the modified bias signal 452 based on the bias signal 442 and based on the power of the input signal 202, as described above.

[0083] At 806, the power amplifier may amplify the input signal while being biased by the modified bias signal generated at 804. For example, at 806, the power amplifier 210 may amplify the input signal 202 while being biased by (e.g., in combination with) the modified bias signal 452 generated at 804 to generate the amplified RF TX signal 412.

[0084] Although not in Figure 8 8 , but the method 800 may further include the RF transmitter 400 transmitting the amplified RF TX signal 412 generated by the power amplifier 210 at 806 .

[0085] Example Data Processing System

[0086] Fig. 9 A block diagram is provided that illustrates an example data processing system 900 that may be configured to implement or control implementation of at least a portion of a bias network that uses an adaptive coupling circuit to provide a bias to a circuit as described with reference to FIGS. 4 to 5. Figure 8 The described bias network provides a modified bias signal to a power amplifier according to some embodiments of the present disclosure. For example, in some embodiments, the data processing system 900 may implement control logic configured to control at least a portion of a bias network implemented using an adaptive coupling circuit as described herein.

[0087] like Fig. 9 As shown, the data processing system 900 may include at least one processor 902, such as a hardware processor 902 coupled to a memory element 904 via a system bus 906. In this way, the data processing system may store program codes in the memory element 904. In addition, the processor 902 may execute program codes accessed from the storage element 904 via the system bus 906. On the one hand, the data processing system may be implemented as a computer suitable for storing and / or executing program codes. However, it should be understood that the data processing system 900 may be implemented in the form of any system including a processor and a memory capable of performing the functions described in the present disclosure.

[0088] In some embodiments, the processor 902 can execute software or algorithms to perform the activities discussed in this specification, particularly activities related to implementing and / or operating a bias network that provides a modified bias signal to a power amplifier using an adaptive coupling circuit, as described herein. The processor 902 may include any combination of hardware, software, or firmware that provides programmable logic, including but not limited to a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (IC) (ASIC), or a virtual machine processor. The processor 902 can be communicatively coupled to the memory element 904, for example, in a direct memory access (DMA) configuration, so that the processor 902 can read from or write to the memory element 904.

[0089] Typically, storage element 904 may include any suitable volatile or non-volatile storage technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory area, magnetic or tape storage or any other suitable technology. Unless otherwise specified, any storage element discussed herein should be interpreted as being included in the broad term "memory". Information that is measured, processed, tracked or sent to or from any component of data processing system 900 can be provided in any database, register, control list, cache or storage structure, all of which can be referenced within any suitable time frame. Any such storage option can be included in the broad term "memory" used herein. Similarly, any potential processing element, module and machine described herein should be interpreted as being included in the broad term "processor". Each element shown in the present figures, e.g., any circuits / components shown in FIGS. 4-7 , may also include suitable interfaces for receiving, transmitting and / or otherwise communicating data or information in a network environment so that they can communicate with, for example, the data processing system 900 to which another of these elements belongs.

[0090] In certain example embodiments, mechanisms for implementing a bias network for a power amplifier using an adaptive coupling circuit to provide a modified bias signal to the power amplifier, as described herein, may be implemented by logic encoded in one or more tangible media, which may include non-transitory media, such as ASICs in DSP instructions, software (which may include object code and source code) to be executed by a processor or other similar machine, etc. In these cases, a storage element, such as Fig. 9 The storage element 904 shown can store data or information used for the operations described herein. This includes storage elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. The processor can execute any type of instructions associated with the data or information to implement the operations detailed herein. In one example, a processor, such as Fig. 9 The processor 902 shown may transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein may be implemented using fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein may be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or an ASIC including digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0091] The storage element 904 may include one or more physical storage devices, such as a local memory 908 and one or more mass storage devices 910. The local memory may refer to a RAM or other non-persistent storage device commonly used during the actual execution of the program code. The mass storage device may be implemented as a hard drive or other persistent data storage device. The processing system 900 may also include one or more cache memories (not shown) that provide temporary storage of at least some program codes to reduce the number of times that program codes must be retrieved from the mass storage device 910 during execution.

[0092] like Fig. 9 As shown, storage element 904 can store application 918. In various embodiments, application 918 can be stored in local memory 908, one or more mass storage devices 910, or separate from local memory and mass storage devices. It should be understood that data processing system 900 can further execute an operating system (OS) capable of facilitating the execution of application 918. Fig. 9 918, which may be implemented in the form of executable program code, may be executed by the data processing system 900 (eg, the processor 902). In response to executing the application, the data processing system 900 may be configured to perform one or more operations or method steps described herein.

[0093] Input / output (I / O) devices depicted as input devices 912 and output devices 914 may be optionally coupled to a data processing system. Examples of input devices may include, but are not limited to, keyboards, pointing devices such as mice, etc. Examples of output devices may include, but are not limited to, monitors or displays, speakers, etc. In some embodiments, output device 914 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some embodiments, the system may include a driver (not shown) for output device 914. Input and / or output devices 912, 914 may be coupled to a data processing system directly or through an intermediate I / O controller.

[0094] In one embodiment, the input and output devices may be implemented as a combined input / output device (in Fig. 9 912 and output device 914). An example of such a combined device is a touch-sensitive display, sometimes referred to as a "touch screen display" or simply a "touch screen." In such an embodiment, input to the device can be provided by movement of a physical object, such as a stylus or a user's finger, on or near the touch screen display.

[0095] Network adapter 916 may also be optionally coupled to the data processing system to enable it to couple to other systems, computer systems, remote network devices, and / or remote storage devices through an intervening private or public network. The network adapter may include: a data receiver for receiving data sent to the data processing system 900 by the system, device, and / or network; and a data transmitter for transmitting data from the data processing system 900 to the system, device, and / or network. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with the data processing system 900.

[0096] Select Examples

[0097] Example 1 provides a bias network for an amplifier, wherein the amplifier may be one of a power amplifier (e.g., a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, or a class C amplifier), a linear amplifier, a low noise amplifier, or a variable gain amplifier. The bias network includes: an adaptive bias circuit configured to generate a bias signal for the amplifier; and a coupling circuit configured to couple the adaptive bias circuit to the amplifier so that the bias signal can be provided to the amplifier, wherein the coupling circuit is configured such that the impedance of the coupling circuit depends on the power level of the input signal to be amplified by the amplifier (i.e., the coupling circuit is an adaptive coupling circuit).

[0098] Example 2 provides a bias network according to Example 1, wherein the coupling circuit is configured such that, when the power level of the input signal is a first power level, the impedance of the coupling circuit is a first impedance, and when the power level of the input signal is a second power level higher than the first power level, the impedance of the coupling circuit is a second impedance lower than the first impedance.

[0099] Example 3 provides a bias network according to Example 1 or 2, wherein the coupling circuit includes: an input coupled to the output of the adaptive bias circuit, wherein the bias signal generated by the adaptive bias circuit is provided at the output of the adaptive bias circuit; and an output coupled to the input of the amplifier.

[0100] Example 4 provides a bias network according to any of the above examples, wherein the coupling circuit is configured to exhibit a variable resistance or a variable impedance that depends on the power level of the input signal.

[0101] Example 5 provides a bias network according to any of the above examples, wherein the coupling circuit includes a transistor and a resistor coupled between the source terminal and the drain terminal of the transistor, and wherein a first S / D terminal in a pair of source and drain terminals is coupled to an input of the amplifier and a second S / D terminal in the pair is coupled to an output of the bias circuit.

[0102] Example 6 provides the bias network according to Example 5, wherein the first S / D terminal of the transistor is further coupled to the input signal.

[0103] Example 7 provides a bias network according to Example 5 or 6, wherein during operation, a current flowing between the first S / D terminal and the second S / D terminal of the transistor depends on a power of the input signal.

[0104] Example 8 provides a bias network for an amplifier, wherein the amplifier can be one of a power amplifier (e.g., a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, or a class C amplifier), a linear amplifier, a low noise amplifier, or a variable gain amplifier. The bias network includes: a bias circuit configured to provide a bias signal at an output of the bias circuit; and a coupling circuit coupled between the output of the bias circuit and an input of the amplifier. In such a bias network, the coupling circuit includes: a transistor, the transistor including a source terminal and a drain terminal; a first one of the source terminal or the drain terminal of the transistor is coupled to an input of the amplifier and a source of an input signal to be amplified by the amplifier; and a second one of the source terminal or the drain terminal of the transistor is coupled to the output of the bias circuit.

[0105] Example 9 provides a bias network according to Example 8, wherein the transistor is an NMOS transistor, the coupling circuit further includes a power detector configured to determine the power of the input signal to be amplified by the amplifier, and the gate voltage applied to the gate terminal of the NMOS transistor is based on the power determined by the power detector.

[0106] Example 10 provides the bias network according to Example 9, wherein an input of the power detector is coupled to the input signal, and an output of the power detector is coupled to a gate terminal of an NMOS transistor.

[0107] Example 11 provides the bias network according to Example 10, wherein the coupling circuit further includes a resistor coupled between a source terminal and a drain terminal of the NMOS transistor.

[0108] Example 12 provides a bias network according to Example 8, wherein the transistor is a PMOS transistor.

[0109] Example 13 provides the bias network according to Example 12, wherein the coupling circuit further includes a resistor coupled between a source terminal and a drain terminal of the PMOS transistor.

[0110] Example 14 provides a bias network according to Example 12, wherein the PMOS transistor is the first transistor of the coupling circuit, the coupling circuit also includes a second transistor, the second transistor is an NMOS transistor, the NMOS transistor includes a source terminal and a drain terminal, a first of the source terminals or drain terminals of the NMOS transistor is coupled to a first of the source terminals or drain terminals of the PMOS transistor (and therefore, also coupled to the input of the amplifier and the source of the input signal to be amplified by the amplifier), and a second of the source terminals or drain terminals of the NMOS transistor is coupled to a second of the source terminals or drain terminals of the PMOS transistor (and therefore also coupled to the output of the bias circuit).

[0111] Example 15 provides a bias network according to Example 14, wherein the coupling circuit further includes a power detector configured to determine the power of the input signal to be amplified by the amplifier, and the gate voltage applied to the gate terminal of the NMOS transistor is based on the power determined by the power detector.

[0112] Example 16 provides a bias network according to Example 15, wherein the coupling circuit also includes a resistor, the resistor including a first end and a second end, the first end of the resistor is coupled to a first of the source terminal or the drain terminal of the NMOS transistor and to a first of the source terminal or the drain terminal of the PMOS transistor, and the second end of the resistor is coupled to a second of the source terminal or the drain terminal of the NMOS transistor and a second of the source terminal or the drain terminal of the PMOS transistor.

[0113] Example 17 provides a bias network for an amplifier, such as a power amplifier (e.g., a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, or a class C amplifier), a linear amplifier, a low noise amplifier, or a variable gain amplifier. The bias network includes: a bias circuit configured to generate a bias signal, and a bias circuit coupled between an output of the bias circuit and an input of the amplifier to enable the bias signal to be provided from the bias circuit to the amplifier, wherein an impedance of the coupling circuit depends on a power level of an input signal to be amplified by the amplifier.

[0114] Example 18 provides a bias network according to Example 17, wherein the bias network is a bias network according to any of the preceding examples, such as a bias network according to any of Examples 1-16.

[0115] Example 19 provides a radio frequency device comprising an amplifier and a bias network for the amplifier, the bias network comprising: an adaptive bias circuit configured to generate a bias signal for the amplifier; and a coupling circuit configured to provide a modified bias signal to the amplifier, wherein the modified bias signal is based on the bias signal generated by the adaptive bias circuit and also based on a power level of an input signal to be amplified by the amplifier.

[0116] Example 20 provides an RF device according to Example 19, wherein the amplifier is one of a power amplifier (e.g., a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, or a class C amplifier), a linear amplifier, a low noise amplifier, or a variable gain amplifier.

[0117] Example 21 provides an RF device according to Example 19 or 20, wherein the RF device is a mobile device (e.g., a UE of a wireless cellular network).

[0118] Example 22 provides the RF device according to Example 19 or 20, wherein the RF device is a base station of a wireless cellular network or a transmitter of a wired communication network.

[0119] Example 23 provides an RF device according to any of Examples 19-22, wherein the bias network is a bias network according to any of the preceding examples, such as a bias network according to any of Examples 1-18.

[0120] Example 24 provides a method of operating a radio frequency device including an amplifier. The method includes: providing a bias network including a bias circuit and a coupling circuit; controlling the bias circuit to generate a bias signal for the amplifier; based on the bias signal generated by the bias circuit, controlling the coupling circuit to generate a modified bias signal, wherein the modified bias signal is further based on an impedance of the coupling circuit, and the coupling circuit is configured such that the impedance of the coupling circuit depends on a power level of an input signal to be amplified by the amplifier; and controlling the amplifier to amplify the input signal when the amplifier is biased by a signal based on the modified bias signal.

[0121] Example 25 provides a method according to Example 24, wherein the bias network is a bias network according to any of the preceding examples, such as a bias network according to any of Examples 1-18; and / or the RF device is a RF device according to any of the preceding examples, such as a RF device according to any of Examples 19-23.

[0122] Example 26 provides a non-transitory computer-readable storage medium comprising instructions for execution, which, when executed by a processor, are operable to perform operations according to the method of Example 24 or 25.

[0123] In a further example, the non-transitory computer-readable storage medium according to Example 26 may also include instructions operable to perform operations performed by any portion of the bias network and / or RF device according to any of the preceding examples.

[0124] Variants and implementations

[0125] Although the above references Figure 1-9 The exemplary embodiments shown describe embodiments of the present disclosure, but those skilled in the art will appreciate that the various teachings described above may be applied to a variety of other embodiments. For example, the description provided herein is not only applicable to a power amplifier as a specific example to illustrate an embodiment of the present disclosure, but also to any other type of amplifier, such as a low noise amplifier, a linear amplifier, or a variable gain amplifier. In another example, the description provided herein is not only applicable to a 5G system that provides an example of a wireless communication system (particularly an example of a high frequency / short wavelength spectrum, for example, a frequency in the range of about 20 to 60 GHz, corresponding to a wavelength between about 5 and 15 mm), but also to other wireless communication systems, such as but not limited to Wi-Fi technology (e.g., a 2.4 GHz band, corresponding to a wavelength of about 12 cm, or a 5.8 GHz band, corresponding to a wavelength of about 5 cm) or Bluetooth technology (e.g., a 2.4 to about 2.485 GHz band, corresponding to a wavelength of about 12 cm). In yet another example, the description provided herein is not only applicable to wireless communication systems, but also to any other system that can use an amplifier, such as a radar system, an automotive radar, and a cable communication system (e.g., a cable television system).

[0126] In some cases, the features discussed herein may be applicable to automotive systems, medical systems, scientific instrumentation, wireless and wired communications, radio, radar, and digital processing-based systems.

[0127] In the discussion of the above embodiments, components of the system, such as phase shifters, mixers, transistors, resistors, capacitors, power detectors, amplifiers and / or other components, can be easily replaced, substituted or otherwise modified to facilitate adaptation to specific circuit requirements. In addition, it should be noted that the use of complementary electronic devices, hardware, and software provide equally viable options for implementing the teachings of the present disclosure related to a bias network that provides a modified bias signal to a power amplifier using an adaptive coupling circuit, as described herein.

[0128] As proposed herein, portions of various systems for implementing a bias network that provides a modified bias signal to a power amplifier using an adaptive coupling circuit may include electronic circuits that perform the functions described herein. In some cases, one or more portions of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more dedicated components, or may include programmable logic gates configured to perform the functions described herein. The circuit may operate in an analog domain, a digital domain, or a mixed signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0129] In an example embodiment, any number of circuits in the current figure can be implemented on a board of an associated electronic device. The board can be a general circuit board that can accommodate various components of the internal electronic system of the electronic device and can also provide connectors for other peripheral devices. More specifically, the board can provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including DSP, microprocessor, supporting chipset, etc.), computer-readable non-temporary storage element, etc. can be appropriately coupled to the board according to specific configuration requirements, processing requirements, computer design, etc. Other components, such as external storage, other sensors, controllers and peripherals for audio / video display can be connected to the board as plug-in cards via cables, or they can be integrated onto the board. In various embodiments, the functions described herein can be implemented in a simulated form as software or firmware running in one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. Software or firmware providing simulation can be provided on a non-temporary computer-readable storage medium including instructions that allow the processor to perform those functions.

[0130] In another example embodiment, the circuits of the accompanying drawings of the present invention may be implemented as stand-alone modules (e.g., devices having associated components and circuits configured to perform specific applications or functions) or as plug-in modules in dedicated hardware of an electronic device. Note that specific embodiments of the present disclosure may be readily included in part or in whole in a system-on-chip (SOC) package. SOC stands for an IC that integrates the components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signal, and typically RF functions: all of which can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0131] It is also important to note that all specifications, dimensions, and relationships outlined in this article (e.g., Figure 1-9The number of components shown in the system (the number of components shown in the system) is provided for the purpose of example and instruction only. This information may be changed considerably without departing from the spirit of the present disclosure or the scope of the appended claims. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any illustrated circuits, components, modules and elements of the present invention can be combined in various possible configurations, all of which are obviously within the broad scope of this specification. In the foregoing description, example embodiments have been described with reference to specific processors and / or component arrangements. Various modifications and changes may be made to these embodiments without departing from the scope of the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

[0132] It is also important to note that the functions associated with implementing a bias network that provides a modified bias signal to a power amplifier using an adaptive coupling circuit as proposed herein are merely illustrative of some of the possible functions that may be performed by or within an RF system. Some of these operations may be deleted or removed where appropriate, or may be substantially modified or altered without departing from the scope of the present disclosure. The embodiments described herein provide great flexibility in that any suitable arrangements, timings, configurations, and timing mechanisms may be provided without departing from the teachings of the present disclosure.

Claims

1. A bias network for an amplifier, the bias network comprising: a bias circuit configured to generate a bias signal for the amplifier; and a coupling circuit configured to couple the bias circuit to the amplifier so as to provide the bias signal to the amplifier, wherein the coupling circuit comprises a transistor and a resistor, The resistor is coupled between a source terminal and a drain terminal of the transistor, A first source or drain S / D terminal of a pair of source and drain terminals of the transistor is coupled to an input of the amplifier, and a second S / D terminal of the pair is coupled to an output of a bias circuit, and The coupling circuit is configured such that an impedance of the coupling circuit depends on a power level of an input signal to be amplified by the amplifier so that during operation a current between the first and second S / D terminals of the transistor depends on the power level of the input signal.

2. The bias network of claim 1 , wherein the coupling circuit is configured such that: When the power level of the input signal to be amplified by the amplifier is a first power level, the impedance of the coupling circuit is a first impedance, When the power level of the input signal is a second power level greater than the first power level, the impedance of the coupling circuit is a second impedance lower than the first impedance.

3. The bias network of claim 1 , wherein the coupling circuit comprises: input, coupled with the output of the bias circuit, and output, coupled to the input of the amplifier.

4. The bias network of claim 1, wherein the coupling circuit is configured to exhibit a variable resistance that depends on a power level of the input signal.

5. The bias network of claim 1 , wherein the bias network is included in a radio frequency device, the radio frequency device being one of: Beamformer, Mobile device, or A base station for a wireless cellular network or a transmitter for a wired communications network.

6. The bias network of claim 1, wherein the first S / D terminal of the transistor is also coupled to the input signal to be amplified by the amplifier.

7. The bias network of claim 1, wherein the amplifier is one of the following: a Doherty amplifier, a class A amplifier, a class B amplifier, a class AB amplifier, a class C amplifier, a linear amplifier, a low noise amplifier, or a variable gain amplifier.

8. The bias network of claim 1, wherein the amplifier is a power amplifier.

9. A bias network for an amplifier, the bias network comprising: a bias circuit configured to provide a bias signal at an output of the bias circuit; and a coupling circuit including a transistor and a power detector, the coupling circuit being coupled between an output of the bias circuit and an input of the amplifier, in: A first source or drain S / D terminal of a pair of source and drain terminals of the transistor is coupled to an input of the amplifier and an input signal to be amplified by the amplifier, The second S / D terminal of the pair is coupled to the output of the bias circuit, The power detector is configured to determine the power of an input signal to be amplified by the amplifier, and A gate voltage applied to a gate terminal of the transistor is based on a power of the input signal.

10. The bias network of claim 9, wherein: The transistor is an N-type metal oxide semiconductor (NMOS) transistor.

11. The bias network of claim 9, wherein: The input of the power detector is coupled to the input signal, and An output of the power detector is coupled to a gate terminal of the transistor.

12. The bias network of claim 10, wherein the coupling circuit further comprises a resistor coupled between a source terminal and a drain terminal of the NMOS transistor.

13. The bias network of claim 9, wherein the transistor is a P-type metal oxide semiconductor (PMOS) transistor.

14. The bias network of claim 11, wherein the coupling circuit further comprises a resistor coupled between a source terminal and a drain terminal of the transistor.

15. The bias network of claim 9, wherein: The transistor is a P-type metal oxide semiconductor (PMOS) transistor, The PMOS transistor is a first transistor of the coupling circuit, The coupling circuit further includes a second transistor, which is an N-type metal oxide semiconductor (NMOS) transistor. The NMOS transistor includes a source terminal and a drain terminal, A first source or drain S / D terminal of a pair of source and drain terminals of the NMOS transistor is coupled to a first S / D terminal of the PMOS transistor, and A second S / D terminal of a pair of source and drain terminals of the NMOS transistor is coupled to a second S / D terminal of the PMOS transistor.

16. The bias network of claim 15, wherein: The coupling circuit further includes a resistor, The resistor includes a first terminal and a second terminal, A first terminal of the resistor is coupled to a first S / D terminal of the NMOS transistor and to a first S / D terminal of the PMOS transistor, and A second terminal of the resistor is coupled to a second S / D terminal of the NMOS transistor and to a second S / D terminal of the PMOS transistor.

17. Radio frequency devices, including: Amplifier; and A bias network according to any one of claims 1 to 4 and 6 to 16 for the amplifier, wherein the coupling circuit is configured to provide a modified bias signal to the amplifier, and The modified bias signal is based on the bias signal and also on a power level of an input signal to be amplified by the amplifier. The radio frequency device according to claim 17 , wherein the radio frequency device is a mobile device or a beamformer.

19. The radio frequency device according to claim 17, wherein the radio frequency device is a base station of a wireless cellular network or a transmitter of a wired communication network.

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