A Σ-Δ analog-to-digital converter circuit that corrects the mismatch error introduced by the feedback digital-to-analog converter.

Abstract

Embodiments of this disclosure relate to a Σ-Δ analog-to-digital converter (ADC) circuit that corrects for mismatch errors introduced by a feedback ADC. An Σ-Δ modulator includes: an N-bit quantization circuit for generating an N-bit codeword stream, and a feedback signal path having an N-bit DAC circuit that operates non-ideally due to mismatch errors, the N-bit DAC circuit converting the N-bit codeword stream to generate a feedback signal. A digital DAC replication circuit provides a digital copy of the N-bit DAC circuit. The digital copy takes into account the non-ideal operation of the N-bit DAC circuit 126 due to mismatch errors and converts the N-bit codeword stream to generate a P-bit codeword stream functionally equivalent to the feedback signal output from the N-bit DAC circuit, where P > N.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 859,531, filed Jun. 10, 2019, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments generally relate to analog-to-digital converter circuits, and more particularly to sigma-delta analog-to-digital converter circuits. BACKGROUND ART

[0004] Figure 1 A time-domain block diagram of a conventional sigma-delta analog-to-digital converter circuit 10 is shown. Circuit 10 includes a first-order sigma-delta modulator circuit 12 having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B, which consists of a pulse stream of a pulse-density modulated 1-bit code. A ratio formed by dividing the count of the pulses in the pulse stream of signal B by the total number of samples of the input signal A within a known time interval (set by the sampling rate fs) represents the instantaneous amplitude of the input signal A. Circuit 10 also includes a decimator circuit 14 that accumulates and averages the pulses in the pulse stream of the digital output signal B to generate a digital signal C consisting of a multi-bit (M-bit, where M>>1) digital word stream at a data rate set by the decimation rate fd, where fd<<fs (referred to in the art as oversampling).

[0005] The first-order sigma-delta modulator circuit 12 includes a differential amplifier 20 (or summing circuit) having a first (non-inverting) input receiving the analog input signal A and a second (inverting) input receiving an analog feedback signal D. The differential amplifier 20 outputs an analog difference signal vdif in response to the difference between the analog input signal A and the analog feedback signal D (i.e., vdif(t) = A(t) - D(t))). The analog difference signal vdif is integrated by an integrator circuit 22 to generate a varying signal vc, the slope and amplitude of which depend on the sign and amplitude of the analog difference signal vdif. A voltage comparator circuit 24 samples the varying signal vc at the sampling rate fs and compares each sample of the varying signal vc with a reference signal vref to generate a corresponding single-bit pulse of the digital output signal B (where if vc≥vref, the single bit has a first logic state, and if vc<vref, the single bit has a second logic state). The voltage comparator circuit 24 effectively operates as a single-bit quantization circuit. Then, a single-bit digital-to-analog converter (DAC) circuit 26 converts the logic state of the digital output signal B to a corresponding analog voltage level of the analog feedback signal D.

[0006] As Figure 2 shown, the Σ-Δ modulator circuit 12 can be implemented using multi-bit quantization (e.g., N bits, where 1 < N << M). The implementation of this circuit requires an N-bit quantization circuit 24' and an N-bit DAC circuit 26' in the feedback loop. The quantization circuit 24' samples the varying signal vc at the sampling rate fs and generates a corresponding N-bit codeword for the digital output signal B for each sample. The DAC circuit 26' converts the N-bit codeword of the digital output signal B into a corresponding analog voltage level of the analog feedback signal D. The decimator circuit 14 accumulates and averages the N-bit codewords in the stream of the digital output signal B to generate a digital signal C composed of a multi-bit (M bits, where M >> N) digital word stream at the data rate set by the decimation rate fd. In one example, N = 3 to 5 and M = 12 to 16. The use of multi-bit quantization has many advantages, including: allowing the modulator to operate to achieve a given resolution using a lower sampling rate fs; or allowing the modulator to operate to achieve a higher resolution at a given sampling rate fs.

[0007] A key feature of the Σ-Δ modulator circuit 12 is its ability to push the quantization noise resulting from the operation of the quantization circuits 24, 24' to higher frequencies away from the signal of interest. This is known as noise shaping in the art. Then, the decimator circuit 14 can be implemented using low-pass filtering characteristics to fully remove the high-frequency components of the shaped quantization noise.

[0008] However, using multi-bit quantization in a Σ-Δ modulator circuit is difficult because the inherent non-linearity present in the operation of the DAC circuit 26' in the feedback loop directly translates into non-linearity of the entire modulator 12. This non-linearity is caused, for example, by unequal analog output steps (i.e., mismatch errors) for a multi-bit DAC circuit.

[0009] The output of an ideal DAC is the sum of its outputs driving unit elements:

[0010]

[0011] where: depending on the DAC accuracy, for (i = 1, 2,... U), b (k) is called the selection signal (in this embodiment, a unary thermometer). In the case of a 4-bit DAC, there are U = (2 4 -1) = 15 unit elements, and k in b i (k) is the k-th input; and where Δ is equal to the quantization step. As an example, for Δ = 0.1V and b i (k) = <1111000>00000000>​, the ideal DAC would output an analog voltage of 0.4V (i.e., the sum of four selected unit elements each being 0.1V).

[0012] In practice, the current sources used in a DAC are not ideal in nature, leading to a deviation from their ideal values. Assume e i (i = 1, 2,..., U) is the normalized deviation value of the unit element from its average output (referred to as unit element error). Thus, the output of each unit element can be expressed as Δ(1 + e i ). Then the output of the non-ideal DAC is:

[0013]

[0014] When comparing Equation 2 with the ideal DAC output Equation 1, the second term in Equation 2 is the error introduced in the DAC and is referred to as the DAC error (or mismatch error). Using Δ = 0.1V and b i (k) = <1111000>00000000>for the same example, when summing the first four DAC elements, their errors are also summed and presented at the output to produce an analog voltage of 0.1 * ((1 + e1) + (1 + e2) + (1 + e3) + (1 + e4)).

[0015] Then, the DAC error is essentially the sum of the products of the selection signal (i.e., b i (k)) and the corresponding error (e i ) over U signals:

[0016]

[0017] Since the DAC error introduces non-linearity in the analog output of the DAC, a distorted modulator output is produced. The non-linearity also modulates the quantization noise of the modulation circuit 24' into the signal band, resulting in a reduction in the signal-to-noise ratio (SNR).

[0018] To utilize the benefits of multi-bit quantization in a Σ-Δ modulator circuit, it is necessary to estimate the inherent non-linearity present in the operation of the multi-bit DAC circuit and perform correction to nullify its effect. Summary of the Invention

[0019] In an embodiment, a Σ-Δ modulator includes: a differential circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal, and an output configured to generate a difference signal; a k-th order loop filter circuit configured to filter the difference signal and generate a variation signal; an N-bit quantization circuit configured to sample the variation signal at a sampling frequency rate, quantize the sampled variation signal, and generate an N-bit codeword stream; an N-bit bit-to-analog converter (DAC) circuit configured to convert the N-bit codeword stream to generate a feedback signal, wherein the N-bit DAC circuit has non-ideal operation due to mismatch error; and a digital DAC replication circuit providing a digital replication of the N-bit DAC circuit, the digital replication taking into account the non-ideal operation of the N-bit DAC circuit due to mismatch error, the digital DAC replication circuit being configured to convert the N-bit codeword stream to output a P-bit codeword stream functionally equivalent to the feedback signal output from the N-bit DAC circuit, where P>N.

[0020] In one embodiment, a Σ-Δ modulator includes: a differential circuit having a first input configured to receive an input signal and a second input configured to receive a feedback signal, and an output configured to generate a difference signal; a k-th order loop filter circuit configured to filter the difference signal and generate a change signal; an N-bit quantization circuit configured to sample the change signal at a sampling frequency rate, quantize the sampled change signal, and generate an N-bit codeword stream; and an N-bit bit-to-analog converter (DAC) circuit configured to convert the N-bit codeword stream to generate a feedback signal, wherein the N-bit DAC... The C circuit exhibits non-ideal operation due to mismatch errors; and a digital DAC replication circuit provides a digital replication of an N-bit DAC circuit, the digital replication taking into account the non-ideal operation of the N-bit DAC circuit due to mismatch errors, the digital DAC replication circuit being configured to convert an N-bit codeword stream to output a P-bit codeword stream, where P>N, each P-bit codeword comprising a combination of: a first digital code corresponding to the ideal output of the N-bit DAC circuit in response to the N-bit codeword; and a second digital code corresponding to the unit element error of the N-bit DAC circuit in response to the N-bit codeword. Attached Figure Description

[0021] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, in which:

[0022] Figure 1 This is a block diagram of a conventional Σ-Δ analog-to-digital converter circuit with single-bit quantization;

[0023] Figure 2 This is a block diagram of a conventional Σ-Δ analog-to-digital converter circuit with multi-bit quantization;

[0024] Figure 3It is a block diagram of a Σ-Δ analog-to-digital converter circuit with multi-bit quantization and feedback digital-to-analog converter mismatch correction; and

[0025] Figure 4 It is shown Figure 3 The circuit configuration is shown in the block diagram of the circuit system. Detailed Implementation

[0026] Now for reference Figure 3 , Figure 3 A block diagram of a Σ-Δ analog-to-digital converter circuit 110 with multi-bit quantization and feedback digital-to-analog converter (DAC) mismatch correction is shown. Circuit 110 includes an N-bit Σ-Δ modulator circuit 112 having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B comprising an N-bit codeword stream. The Σ-Δ modulator circuit 112 includes a differential amplifier 120 (i.e., a summing circuit) having a first (non-inverting) input receiving the analog input signal A and a second (inverting) input receiving an analog feedback signal D. Differential amplifier 20 outputs an analog difference signal vdif (where vdif(t) = A(t) - D(t)) in response to the difference between the analog input signal A and the analog feedback signal D. The analog difference signal vdif is integrated by a K-order loop filter 116 (using, for example, K integrator circuits 122) to generate a changing signal vc, the slope and amplitude of which depend on the sign and amplitude of the analog difference signal vdif. An N-bit quantization circuit 124 samples the changing signal vc at a sampling rate fs and generates a corresponding N-bit codeword for each sample to form a digital output signal B. An N-bit digital-to-analog converter (DAC) circuit 126 in the feedback loop converts the N-bit codeword of the digital output signal B into a corresponding voltage level for use in the analog feedback signal D.

[0027] The ∑-Δ modulator circuit 112 utilizes a K-order integrator circuit to implement the loop filter 116. Figure 1 In the illustration, K = 1 because only one integral (using integrator 122) is shown in the loop filter 116; however, it should be understood that this is merely exemplary, and K can be equal to 2, 3, or greater, depending on the desired noise shaping and the requirements of the circuit application. Those skilled in the art know how to implement a loop filter 116 with K > 1st order for use in a Σ-Δ modulator circuit 112.

[0028] It is known in the prior art to address the problem of feedback DAC mismatch error by performing correction at the DAC circuitry itself. See, for example, U.S. Patent No. 10,148,278 (incorporated by reference). It is also known in the prior art to address the problem of feedback DAC mismatch error by performing correction at the decimator circuitry. See, for example, U.S. Patent No. 9,438,266 (incorporated by reference). Figure 3 The Σ-Δ analog-to-digital converter circuit 110 uses different solutions to address the problem of compensating for feedback DAC mismatch error.

[0029] The N-bit codeword stream for the digital output signal B generated by the N-bit quantization circuit 124 is input to the N-bit DAC circuit 126 in the feedback path, and further input to the digital DAC replication circuit 118. In this case, the digital DAC replication circuit 118 is calibrated (in a manner discussed in detail herein) to digitally model the operation of the feedback N-bit DAC circuit 126. In other words, the ideal DAC operation is digitally modeled by adding the DAC error introduced by the nonlinear operation of the unit element.

[0030]

[0031] As previously described, the digital output signal B from the N-bit quantization circuit 124 undergoes quantization error along with the desired signal. Those skilled in the art will understand that any signal or noise entity injected at any point in the feedback loop of the modulator 112 will be high-passed (i.e., noise shaped) by the modulator's noise transfer function. The effect of this high-pass noise shaping on the injected signal or noise can be seen after the injection point. Therefore, the quantization error injected into the feedback loop by the N-bit quantization circuit 124 advantageously utilizes a high-pass function (1-z) proportional to the modulator's order (K). -1 ) K The modulator 112 performs noise shaping (high-pass) at the digital output signal B.

[0032] Further through the feedback loop, the digital output signal B is processed by the N-bit DAC circuit 126 of modulator 112. This N-bit DAC circuit 126 operates non-ideally, at least in part, due to mismatches between its building blocks (unit elements as described above) caused by imperfect circuit fabrication. A DAC with non-ideal operation can be modeled as an ideal DAC, followed by an error signal source that injects mismatch error (see also Equation 2). Similar to the case of the N-bit quantization circuit 124 discussed above, the N-bit DAC circuit 126 is inserted into the feedback loop of modulator 112, and the mismatch error resulting from the operation of the N-bit DAC circuit 126 is high-passed (i.e., noise-shaping) through the noise transfer function of the modulator. This high-pass noise-shaping effect on the injected mismatch error can be seen after the injection point. Therefore, the mismatch error injected into the feedback loop by the N-bit DAC circuit 126 advantageously utilizes a high-pass function (1-z) proportional to the modulator's order (K). -1 ) K The noise is shaped (high-pass) at the analog feedback signal D by modulator 112.

[0033] The digital DAC replication circuit 118 provides a digital replication of the analog N-bit DAC circuit 126, specifically taking into account the non-ideal operation of the N-bit DAC circuit 126 due to unit element mismatch. More specifically, the digital DAC replication circuit 118 is programmed using a plurality of digital codewords proportional to the value of the mismatched unit element of the analog N-bit DAC circuit 126. In other words, the digital codewords correspond to the unit element error e. i The analog value is obtained. The digital codeword can have any selected precision P, and is determined using a calibration process (discussed in detail herein). It should be understood that if the digital model provided by the digital DAC replication circuit 118 is substantially the same as the non-ideal practical operation of the analog N-bit DAC circuit 126, then the digital signal E output from the digital DAC replication circuit 118 is functionally equivalent to the analog feedback signal D output from the analog N-bit DAC circuit 126. In this document, "functionally equivalent" means that the analog conversion of the digital value of the digital signal E generated by the digital DAC replication circuit 118 in response to signal B is substantially equivalent to the corresponding analog value of the analog feedback signal D generated in response to the same signal B. The digital signal E output by the digital DAC replication circuit 118 comprises a P-bit codeword stream (where P > N, the higher resolution provided by P bits is necessary to provide fractional components to account for the effects of mismatch errors). The bit difference (PN) defines the degree of substantially equivalent that can be achieved.

[0034] The operation of the digital DAC replica circuit 118 can be better understood by using an example. Assume that the digital output signal B has four bits (i.e., N = 4), and for a particular case, has a digital value <0010> output from the N-bit quantization circuit 124, resulting in a selection signal of <1100000>00000000>. If the analog N-bit DAC circuit 126 has an ideal functional operation, the value of the analog voltage of the analog feedback signal D output from the analog N-bit DAC circuit 126 will be 2*Δ. However, due to mismatch errors, the voltage value of the generated analog feedback signal D output from the analog N-bit DAC circuit 126 is 2*Δ + e1Δ + e2Δ. The calibration process to be described herein digitally measures the analog voltage output from the analog N-bit DAC circuit 126 for each possible codeword of the digital output signal B, and determines the error for each unit element (i = 1, 2,... U) based on these measurements. Then, a digital codeword corresponding to each determined unit element error is generated and programmed into the digital DAC replica circuit 118. Thus, considering the same example where the digital value of the digital output signal B from the N-bit quantization circuit 124 is <0010>, the digital signal E output from the digital DAC replica circuit 118 will be a codeword with P-bit accuracy, which is formed by adding the N-bit digital code for 2*Δ (i.e., the ideal response) to the sum of the digital codes for Δ multiplied by the programmed digital codewords of the unit element errors e1 and e2 (i.e., Δ(e1 + e2)) (i.e., the introduced mismatch error).

[0035] It should be noted that the calibration process can be used to generate a look-up table, which is programmed into the digital DAC replica circuit 118 and used to convert the received N-bit digital value generated by the N-bit quantization circuit 124 into the corresponding P-bit digital value for the digital signal E. It should be understood that the digital look-up table replica circuit 118 can implement conversion techniques other than using a look-up table. For example, the estimated mismatch codes of the model can be selectively summed using a summing node based on the received unary input. This may be a preferred method if an input other than a thermometric code (e.g., a scrambled unary code) is used as the input to the digital DAC replica circuit 118. In rare design instances where the input to the digital DAC replica circuit 118 is binary or two's complement, a multiply-accumulate structure can be used instead.

[0036] The circuit 110 also includes a decimator circuit 114, which accumulates and averages the P-bit codewords in the stream of the digital output signal E to generate a digital signal C consisting of a multi-bit (M-bit) digital word stream at a data rate set by the decimation rate fd, where fd << fs and 1 < N < P << M. The decimator circuit 114 implements low-pass filtering to effectively remove the high-pass signal components of the quantization error and the mismatch error.

[0037] Due to the existence of unequal analog output step sizes, let em(n) be the mismatch error introduced by the operation of DAC circuit 126, where n is the sampling index. Accordingly, the analog feedback signal D in the Z-domain can be given by the following equation:

[0038] v(n)+em(n)(1-z -1 ) K

[0039] Where: v(n) is the ideal output of quantization circuit 124.

[0040] Furthermore, let eq(n) be the quantization error introduced by the operation of the n-bit quantization circuit 124. The digital output signal B can be given in the Z-domain by the following formula:

[0041] v(n)+eq(n)(1-z -1 ) K

[0042] The digital signal E can be given by the following formula:

[0043] v(n)+(eq(n)+em(n))(1-z -1 ) K

[0044] It should be noted that both quantization error and mismatch error have been shaped by Qualcomm noise.

[0045] Now for reference Figure 4 Additionally, Figure 4 A calibration circuit 200 is shown for an N-bit Σ-Δ modulator circuit 112 used to program a digital DAC replication circuit 118 using a digital model of a feedback N-bit DAC circuit 126. A first multiplexer circuit 202 has a first input coupled to receive a digital output signal B generated by an N-bit quantization circuit 124, and a second input configured to receive a digital codeword calibration signal 204. The selection operation of the first multiplexer circuit 202 is controlled by a selection control signal 206, such that when the selection control signal 206 is in a first logic state, the digital output signal B is passed from the first multiplexer circuit 202 to the feedback N-bit DAC circuit 126, and when the selection control signal 206 is in a second logic state, the digital codeword calibration signal 204 is passed from the first multiplexer circuit 202 to the feedback N-bit DAC circuit 126.

[0046] The second multiplexer circuit 212 has a first input coupled to receive a digital zero (or empty) input signal 208 and a second input configured to receive a digital output signal B generated by the N-bit quantization circuit 124. The selection operation of the second multiplexer circuit 212 is also controlled by a selection control signal 206, such that when the selection control signal 206 is in a first logic state, the digital zero (or empty) input signal 208 is passed from the second multiplexer circuit 212 to the N-bit estimation DAC circuit 216, and when the selection control signal 206 is in a second logic state, the digital output signal B is passed from the second multiplexer circuit 212 to the N-bit estimation DAC circuit 216.

[0047] By using Dynamic Element Matching (DEM) technology known to those skilled in the art, the N-bit estimation DAC circuit 216 is configured to have a linear response (i.e., no response to negligible mismatch errors). At this point, those skilled in the art will understand that DEM technology works well for low-bandwidth-limited signals, and is the signal being processed during calibration mode. DEM is less effective for high-frequency wideband signals such as input signal A, and therefore using DEM technology for the feedback N-bit DAC circuit 126 is not a particularly efficient or economical solution.

[0048] The differential (summing) circuit 220 subtracts the analog signal 222 output by the N-bit estimation DAC circuit 216 from the analog signal 224 output by the feedback N-bit DAC circuit 126 to generate the analog feedback signal D.

[0049] The control and processing circuitry 240 for calibration operations has an input coupled to receive the digital output signal B generated by the N-bit quantization circuitry 124. The control and processing circuitry 240 also generates a selection control signal 206, a digital codeword signal 204, and a digital zero (or empty) input signal 208, and can further apply a selected input signal A during calibration mode. The control and processing circuitry 240 operates in calibration mode to identify the mismatch error of the feedback N-bit DAC circuitry 126 from the received digital output signal B, and programs the digital DAC replication circuitry 118 via signal 242 to digitally model the operation of the feedback N-bit DAC circuitry 126.

[0050] When the N-bit Σ-Δ modulator circuit 112 is not calibrated, the control and processing circuit 240 asserts the selection control signal 206 as a first logic state, causing the digital output signal B to be passed from the first multiplexer circuit 202 to the feedback N-bit DAC circuit 126, and the zero (or empty) input signal 208 to be passed from the second multiplexer circuit 212. In this mode, the circuit is configured to... Figure 3The operation is performed as shown because the analog signal 222 output by the N-bit estimated DAC circuit 216 is zero.

[0051] While calibrating the N-bit Σ-Δ modulator circuit 112, the control and processing circuit 240 asserts the selection control signal 206 as a second logic state, causing the digital codeword calibration signal 204 to be passed from the first multiplexer circuit 202 to the feedback N-bit DAC circuit 126, and the digital output signal B to be passed from the second multiplexer circuit 212 to the N-bit estimation DAC circuit 216. In this calibration configuration, the control and processing circuit 240 applies a zero-voltage input as an analog input signal A. The feedback N-bit DAC circuit 126 converts the digital codeword calibration signal 204 provided by the control and processing circuit 240 to generate an analog signal 224, and the bit estimation DAC circuit 216 converts the digital output signal B to generate an analog signal 222. The analog signal 223 is added to the analog signal 224 to complete the Σ-Δ loop and generate an analog feedback signal D. Then, in response to the applied codeword calibration signal 204, in order to digitally measure the analog voltage output from the analog N-bit DAC circuit 126, the control and processing circuit 240 processes the digital output signal B using low-pass filtering and decimation (similar to what is performed by the decimator 114). In other words, the calibration mode uses the modulator 112 to measure only the operating characteristics of the N-bit DAC circuit 126.

[0052] During the calibration operation, the control and processing circuit 240 applies a value to the digital codeword calibration signal 204, which corresponds to all possible digital codewords generated by the N-bit quantization circuit 124 for the digital output signal B. In response to all possible digital codewords, by processing the analog voltage measured digitally from the analog N-bit DAC circuit 126, the control and processing circuit 240 can determine the error e for each unit element (i = 1, 2, ... U) of the analog N-bit DAC circuit 126. i Furthermore, it generates a corresponding digital codeword that provides a complete picture of the nonlinear response of the feedback N-bit DAC circuit 126. The digital codeword generated for each unit element is programmed into the digital DAC replication circuit 118 via signal 242 to digitally model the operation of the feedback N-bit DAC circuit 126.

[0053] Although the invention has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. A Σ-Δ analog-to-digital converter circuit, comprising: A differential circuit has a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a difference signal; The k-th order loop filter circuit is configured to filter the difference signal and generate a changing signal; An N-bit quantization circuit is configured to sample the changing signal at a sampling frequency rate, quantize the sampled changing signal, and generate an N-bit codeword stream. An N-bit bit-to-analog converter (DAC) circuit is configured to convert the N-bit codeword stream to generate the feedback signal, wherein the N-bit DAC circuit has non-ideal operation due to mismatch errors; and A digital DAC replication circuit provides a digital copy of the N-bit DAC circuit, the digital copy taking into account the non-ideal operation of the N-bit DAC circuit due to mismatch errors, the digital DAC replication circuit being configured to convert the N-bit codeword stream to output a P-bit codeword stream that is functionally equivalent to the feedback signal output from the N-bit DAC circuit, where P>N.

2. The circuit of claim 1, wherein the noise associated with the mismatch error is high-pass noise-shaped, and the circuit further includes a low-pass filter configured to filter out the high-frequency components of the mismatch error after high-pass noise shaping.

3. The circuit of claim 2, wherein the low-pass filter is implemented by a decimator circuit configured to decimate the P-bit codeword stream at a decimation frequency rate to generate an M-bit word stream, where M>P.

4. The circuit of claim 1 further includes a decimator circuit configured to decimate the P-bit codeword stream at a decimation frequency rate to generate an M-bit word stream, where M > P.

5. The circuit of claim 1, further comprising a calibration circuit configured to program the digital DAC replication circuit to provide the digital replication of the N-bit DAC circuit.

6. The circuit of claim 5, wherein the calibration circuit comprises: Estimate the N-bit DAC circuit; An additional differential circuit is configured to generate the feedback signal as the difference between a first signal output from the N-bit DAC circuit and a second signal output from the estimated N-bit DAC circuit. A first multiplexing circuit has a first input configured to receive the N-bit codeword stream and a second input configured to receive an N-bit calibration codeword, wherein the output of the first multiplexing circuit is applied to the input of the N-bit DAC circuit. A second multiplexing circuit has a first input configured to receive an N-bit empty codeword and a second input configured to receive the N-bit codeword stream, wherein the output of the second multiplexing circuit is applied to the input of the estimated N-bit DAC circuit. as well as A control and processing circuit has a first input configured to receive the N-bit codeword stream and an output configured to generate a programming signal for programming the digital DAC replication circuit, wherein the control and processing circuit controls a first multiplexing circuit and a second multiplexing circuit in a calibration mode to select the second input, apply a value to the N-bit calibration codeword, and process the N-bit codeword stream in response to the applied value to determine the mismatch error of the N-bit DAC circuit for the applied value, so as to program the digital DAC replication circuit to provide the digital replication.

7. The circuit of claim 6, wherein the control and processing circuit further controls the first multiplexing circuit and the second multiplexing circuit in a normal operating mode to select the first input.

8. The circuit of claim 6, wherein the control and processing circuitry further applies a series of values ​​to the N-bit calibration codeword and processes the N-bit codeword stream in response to the applied series of values ​​to determine the mismatch error of the N-bit DAC circuitry for the applied series of values, so as to program the digital DAC replication circuitry to provide the digital replication.

9. The circuit of claim 8, wherein the series of applied values ​​includes all possible values ​​for input to the N-bit DAC circuit.

10. The circuit of claim 1, wherein the digital DAC copy circuit includes a lookup table configured to convert an N-bit codeword generated by the N-bit quantization circuit into a corresponding P-bit codeword for output by the digital DAC copy circuit.

11. A Σ-Δ analog-to-digital converter circuit, comprising: A differential circuit has a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a difference signal; The k-th order loop filter circuit is configured to filter the difference signal and generate a changing signal; An N-bit quantization circuit is configured to sample the changing signal at a sampling frequency rate, quantize the sampled changing signal, and generate an N-bit codeword stream. An N-bit bit-to-analog converter (DAC) circuit is configured to convert the N-bit codeword stream to generate the feedback signal, wherein the N-bit DAC circuit has non-ideal operation due to mismatch errors; and A digital DAC replication circuit provides a digital copy of the N-bit DAC circuit, the digital copy taking into account the non-ideal operation of the N-bit DAC circuit due to mismatch errors. The digital DAC replication circuit is configured to convert the N-bit codeword stream to output a P-bit codeword stream, where P > N, and each P-bit codeword includes a combination of the following: A first digital code corresponding to the ideal output of the N-bit DAC circuit in response to the N-bit codeword; and A second digital code corresponding to the unit element error of the N-bit DAC circuit in response to the N-bit codeword.

12. The circuit of claim 11, wherein the noise associated with the mismatch error is high-pass noise-shaped, the circuit further comprising a low-pass filter configured to filter out the high-frequency components of the mismatch error after high-pass noise shaping.

13. The circuit of claim 12, wherein the low-pass filter is implemented by a decimator circuit configured to decimate the P-bit codeword stream at a decimation frequency rate to generate an M-bit word stream, where M > P.

14. The circuit of claim 11 further includes a decimator circuit configured to decimate the P-bit codeword stream at a decimation frequency rate to generate an M-bit word stream, where M > P.

15. The circuit of claim 11, further comprising a calibration circuit configured to program the digital DAC replication circuit to provide the digital replication of the N-bit DAC circuit.

16. The circuit of claim 15, wherein the calibration circuit comprises: Estimate the N-bit DAC circuit; An additional differential circuit is configured to generate the feedback signal as the difference between a first signal output from the N-bit DAC circuit and a second signal output from the estimated N-bit DAC circuit. A first multiplexing circuit has a first input configured to receive the N-bit codeword stream and a second input configured to receive an N-bit calibration codeword, wherein the output of the first multiplexing circuit is applied to the input of the N-bit DAC circuit. A second multiplexing circuit has a first input configured to receive an N-bit empty codeword and a second input configured to receive the N-bit codeword stream, wherein the output of the second multiplexing circuit is applied to the input of the estimated N-bit DAC circuit. as well as A control and processing circuit has a first input configured to receive the N-bit codeword stream and an output configured to generate a programming signal for programming the digital DAC replication circuit, wherein the control and processing circuit controls a first multiplexer circuit and a second multiplexer circuit in a calibration mode to select the second input, apply a value to the N-bit calibration codeword, and process the N-bit codeword stream in response to the applied value to determine the unit element error of the N-bit DAC circuit for the applied value.

17. The circuit of claim 16, wherein the control and processing circuit further controls the first multiplexing circuit and the second multiplexing circuit in a normal operating mode to select the first input.

18. The circuit of claim 16, wherein the control and processing circuitry further applies a series of values ​​to the N-bit calibration codeword and processes the N-bit codeword stream in response to the applied series of values ​​to determine the unit element error.

19. The circuit of claim 18, wherein the series of applied values ​​includes all possible values ​​for input to the N-bit DAC circuit.

20. A Σ-Δ analog-to-digital converter circuit, comprising: A differential circuit has a first input configured to receive an input signal, a second input configured to receive a feedback signal, and an output configured to generate a difference signal; The k-th order loop filter circuit is configured to filter the difference signal and generate a changing signal; An N-bit quantization circuit is configured to sample the changing signal at a sampling frequency rate, quantize the sampled changing signal, and generate an N-bit codeword stream. An N-bit bit-to-analog converter (DAC) circuit is configured to convert the N-bit codeword stream to generate the feedback signal, wherein the N-bit DAC circuit has non-ideal operation due to mismatch errors; and A digital DAC replication circuit provides a digital copy of the N-bit DAC circuit, the digital copy taking into account the non-ideal operation of the N-bit DAC circuit due to mismatch errors, the digital DAC replication circuit being configured to convert the N-bit codeword stream to output a P-bit codeword stream that is functionally equivalent to the feedback signal output from the N-bit DAC circuit, where P>N; A calibration circuit is configured to program the digital DAC replication circuit to provide the digital replication of the N-bit DAC circuit, wherein the calibration circuit includes: A multiplexing circuit has a first input configured to receive the N-bit codeword stream and a second input configured to receive an N-bit calibration codeword, wherein the output of the multiplexing circuit is applied to the input of the N-bit DAC circuit. as well as A control and processing circuit has a first input configured to receive the N-bit codeword stream and an output configured to generate a programming signal for programming the digital DAC replication circuit, wherein the control and processing circuit controls the multiplexing circuit in a calibration mode to select a second input, apply a value to the N-bit calibration codeword, and process the N-bit codeword stream in response to the applied value to determine the mismatch error of the N-bit DAC circuit for the applied value, so as to program the digital DAC replication circuit to provide the digital replication.

21. The circuit of claim 20, wherein the noise associated with the mismatch error is high-pass noise-shaped, the circuit further comprising a low-pass filter configured to filter out the high-frequency components of the mismatch error after high-pass noise shaping.

22. The circuit of claim 21, wherein the low-pass filter is implemented by a decimator circuit configured to decimate the P-bit codeword stream at a decimation frequency rate to generate an M-bit word stream, where M > P.

23. The circuit of claim 20 further includes a decimator circuit configured to decimate the P-bit codeword stream at a decimation frequency rate to generate an M-bit word stream, where M > P.

24. The circuit of claim 20, wherein the control and processing circuit further controls the multiplexing circuit to select the first input in a normal operating mode.

25. The circuit of claim 20, wherein the control and processing circuitry further applies a series of values ​​to the N-bit calibration codeword and processes the N-bit codeword stream in response to the applied series of values ​​to determine the mismatch error of the N-bit DAC circuitry for the applied series of values, so as to program the digital DAC replication circuitry to provide the digital replication.

26. The circuit of claim 25, wherein the series of applied values ​​includes all possible values ​​for input to the N-bit DAC circuit.

27. The circuit of claim 20, wherein the digital DAC copy circuit includes a lookup table configured to convert an N-bit codeword generated by the N-bit quantization circuit into a corresponding P-bit codeword for output by the digital DAC copy circuit.

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