Resistive element and method of manufacturing the same

Abstract

This invention provides a resistive element and a method for manufacturing the same, which can reduce chip size and the number of bonding wires. The resistive element comprises: a semiconductor substrate; a field insulating film disposed on the semiconductor substrate; a plurality of resistive layers separately disposed on the field insulating film; an interlayer insulating film covering the field insulating film and each of the plurality of resistive layers; a pad forming electrode disposed on the interlayer insulating film and electrically connected to one end of the plurality of resistive layers; a relay wiring separately disposed on the interlayer insulating film from the pad forming electrode, having a terminal electrically connected to the other end of the resistive layer and a terminal ohmically contacting the semiconductor substrate; and a back electrode disposed under the semiconductor substrate and ohmically contacting the semiconductor substrate, wherein the resistive element uses the electrical path between the pad forming electrode and the back electrode as a resistive element.

Description

Technical Field

[0001] This invention relates to a resistive element, such as a gate resistor element used as a switching element, and a method for manufacturing the same. Background Technology

[0002] As a resistive element for semiconductor devices such as semiconductor integrated circuits (ICs), a resistive element having an insulating layer on a silicon substrate and a thin film on the insulating layer is known (see Patent Document 1). In the resistive element described in Patent Document 1, two electrodes are connected to the opposing sides of the resistive layer, and aluminum wires are bonded to the two electrodes.

[0003] In the resistive element described in Patent Document 1, two electrodes connected to the opposing sides of the resistive layer are located on the upper surface of the resistive layer. Therefore, the chip size increases, and two bonding wires are required to connect to the two electrodes.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 8-306861 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] In view of the above problems, the object of the present invention is to provide a resistor element and a method thereof that can reduce chip size and reduce the number of bonding wires.

[0009] Solution for solving the problem

[0010] One aspect of the present invention relates to a resistive element comprising: (a) a semiconductor substrate; (b) a field insulating film disposed on the semiconductor substrate; (c) a plurality of resistive layers disposed separately on the field insulating film; (d) an interlayer insulating film configured to cover the field insulating film and each of the plurality of resistive layers; (e) a pad forming electrode disposed on the interlayer insulating film and electrically connected to one end of at least one selected resistive layer from the plurality of resistive layers; (f) a relay wiring disposed separately from the pad forming electrode on the interlayer insulating film, having a terminal electrically connected to the other end of the selected resistive layer and a terminal ohmically contacting the semiconductor substrate; and (g) a back electrode disposed under the semiconductor substrate and ohmically contacting the semiconductor substrate, wherein the resistive element uses the electrical path between the pad forming electrode and the back electrode as a resistive element.

[0011] The main idea of ​​another aspect of the present invention is a method for manufacturing a resistive element, characterized by comprising the following steps: (a) forming a field insulating film on a semiconductor substrate; (b) forming a plurality of resistive layers on the field insulating film; (c) forming an interlayer insulating film to cover the field insulating film and the plurality of resistive layers; (d) forming a first contact hole in the interlayer insulating film to expose one end of a selected resistive layer from the plurality of resistive layers, forming a second contact hole in the interlayer insulating film at a position separated from the first contact hole to expose the other end of the selected resistive layer, and forming a second contact hole in the interlayer insulating film at a position separated from the first contact hole to expose the other end of the selected resistive layer; and forming a second contact hole in the interlayer insulating film at a position separated from the first contact hole. (e) A third contact hole is formed at the location where the first and second contact holes are separated, exposing a portion of the upper surface of the semiconductor substrate; (f) A pad forming electrode and a relay wiring are formed, wherein the pad forming electrode is electrically connected to one end of a selected resistive layer via the first contact hole, the relay wiring is electrically connected to the other end of the selected resistive layer via the second contact hole, and makes ohmic contact with the semiconductor substrate via the third contact hole; and (f) A back electrode is formed under the semiconductor substrate, wherein a resistive element serves as a resistor for the electrical path between the pad forming electrode and the back electrode.

[0012] The effects of the invention

[0013] According to the present invention, a resistive element capable of reducing chip size and the number of bonding wires, and a method thereof are provided. Attached Figure Description

[0014] Figure 1 This is a top view of the resistive element according to an embodiment of the present invention.

[0015] Figure 2 From Figure 1 A cross-sectional view observed along the AA direction.

[0016] Figure 3 This is a circuit diagram illustrating an application example of the resistive element involved in the implementation method.

[0017] Figure 4 This is a cross-sectional view of the manufacturing method of the resistive element involved in the embodiment.

[0018] Figure 5 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 4 The process cross-sectional diagram.

[0019] Figure 6 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 5 The process cross-sectional diagram.

[0020] Figure 7 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 6 The process cross-sectional diagram.

[0021] Figure 8 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 7 The process cross-sectional diagram.

[0022] Figure 9 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 8 The process cross-sectional diagram.

[0023] Figure 10 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 9 The process cross-sectional diagram.

[0024] Figure 11 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 10 The process cross-sectional diagram.

[0025] Figure 12 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 11 The process cross-sectional diagram.

[0026] Figure 13 This is a continuation of the method for manufacturing the resistive element according to the embodiments. Figure 12 The process cross-sectional diagram.

[0027] Figure 14 This is a top view of a resistive element according to a first variation of an embodiment of the present invention.

[0028] Figure 15 From Figure 14 A cross-sectional view observed along the AA direction.

[0029] Figure 16 This is a top view of a resistive element according to a second variation of an embodiment of the present invention.

[0030] Figure 17 From Figure 16 A cross-sectional view observed along the AA direction.

[0031] Figure 18 This is a top view of a resistive element according to a third variation of an embodiment of the present invention.

[0032] Figure 19 This is a top view of the resistive element according to the fourth variation of the embodiments of the present invention.

[0033] Figure 20 This is a top view of the resistive element according to the fifth variation of the embodiments of the present invention.

[0034] Figure 21 This is a top view of the resistive element according to the sixth variation of the embodiments of the present invention.

[0035] Figure 22 From Figure 21 A cross-sectional view observed along the AA direction.

[0036] Figure 23 This is a top view of the resistive element according to the seventh variation of the embodiments of the present invention.

[0037] Figure 24 This is an equivalent circuit diagram of the resistive element involved in the seventh variation of the implementation method.

[0038] Figure 25 This is a top view of the resistive element according to the eighth variation of the embodiments of the present invention.

[0039] Figure 26 From Figure 25 A cross-sectional view observed along the AA direction.

[0040] Figure 27 This is a top view of the resistive element according to the ninth variation of the embodiments of the present invention.

[0041] Figure 28 This is a top view of the resistive element according to the tenth variation of the embodiments of the present invention.

[0042] Figure 29 This is a top view of the resistive element according to the eleventh variation of the embodiments of the present invention.

[0043] Figure 30 This is a top view of the resistive element according to the twelfth variation of the embodiments of the present invention.

[0044] Figure 31 This is a top view of the resistive element according to the thirteenth variation of the embodiments of the present invention.

[0045] Explanation of reference numerals in the attached figures

[0046] 1: Semiconductor substrate; 2: Field insulating film; 3: DOPOS layer; 4: Interlayer insulating film; 4a-4h: Contact holes; 5: Metal film; 7: Protective insulating film; 7a-7e: Openings; 9: Back electrode; 31a-31f, 34a-34h: Resistive layers; 32a-32h: Dummy layers; 33: Auxiliary film; 51, 51a, 51b: Pad forming electrodes; 51x-51z: Raised portions; 52a-52d, 54a-54h: Relay wiring 53: Protective ring layer; 55, 55a, 55b: Inter-resistor wiring; 61a~61f: Electrode contact area; 62a~62f: Wiring contact area; 63a~63f: Substrate contact area; 65a~65d: Auxiliary pads; 64a, 64b: Peripheral contact area; 100: Inverter module; 101: Pad side terminal; 102: Rear side terminal; 103: Auxiliary terminal; R1~R12: Gate resistor element; TR1~TR12: Main component. Detailed Implementation

[0047] The embodiments and variations thereof of the present invention will now be described with reference to the accompanying drawings. In the drawings, identical or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may sometimes differ from actual conditions. Furthermore, the drawings may include parts with different dimensional relationships or ratios. Additionally, the embodiments shown below are intended to illustrate apparatus and methods for embodying the technical concept of the present invention, and the technical concept of the present invention is not intended to specify the material, shape, structure, or arrangement of structural components as described below. Furthermore, the definitions of directions such as up and down in the following description are merely for ease of explanation and are not intended to limit the technical concept of the present invention. For example, if an object is rotated 90° for observation, the up and down orientation is changed to left and right; if the object is rotated 180° for observation, the up and down orientation is reversed. This is self-evident.

[0048] (Implementation Method)

[0049] <Resistive element>

[0050] like Figure 1 As shown, the resistive element according to the embodiment of the present invention has a rectangular planar pattern surrounded by the first to fourth sides. The chip size of the resistive element according to the embodiment is, for example, about 3mm × 3mm, but can be appropriately set. Figure 1 The chip shown is rectangular in shape, but the chip of the resistive element involved in the embodiment is not limited to a rectangle. Figure 1In the chip shape shown, the resistive element according to the embodiment has a first resistive layer 31a disposed on a first side, a second resistive layer 31b disposed on a second side, a third resistive layer 31c disposed on a third side, and a fourth resistive layer 31d disposed on a fourth side around the periphery of the chip. Furthermore, the names "first resistive layer 31a" to "fourth resistive layer 31d" are assigned ordinal numbers only for ease of explanation, and can be defined as "multiple resistive layers" when referring collectively to the first resistive layer 31a to the fourth resistive layer 31d.

[0051] exist Figure 2 In the cross-sectional structure shown, the resistive element according to the embodiment of the present invention includes a low-resistivity semiconductor substrate 1, a field insulating film (first insulating film) 2 disposed on the semiconductor substrate 1, and a first resistive layer 31a and a third resistive layer 31c formed of thin films disposed on the field insulating film 2. Although in Figure 2 The cross-sectional structure was omitted, but Figure 1 The second resistive layer 31b and the fourth resistive layer 31d shown in the figure are... Figure 2 The first resistive layer 31a and the third resistive layer 31c shown are similarly disposed on the field insulating film 2.

[0052] The thickness of the semiconductor substrate 1 is, for example, about 350 μm. As the semiconductor substrate 1, a low-resistivity substrate such as a silicon substrate with a high concentration of n-type impurities can be used. Preferably, the resistance component of the semiconductor substrate 1 is negligible compared to the resistance components of the first resistive layer 31a to the fourth resistive layer 31d. That is, preferably, the resistance component of the semiconductor substrate 1 is about 1 / 100 or less of the resistance components of the first resistive layer 31a to the fourth resistive layer 31d. The resistivity of the semiconductor substrate 1 can be, for example, set to about 2 mΩ·cm to 60 mΩ·cm. Furthermore, as the semiconductor substrate 1, a silicon substrate with a high concentration of p-type impurities or a semiconductor substrate other than silicon can also be used.

[0053] The thickness of the field insulating film 2 is, for example, about 800 nm. By thickening the field insulating film 2, the parasitic capacitance can be reduced. As the field insulating film 2, a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film thereof can be used. As the field insulating film 2, it can also be an insulating film (TEOS film) formed by chemical vapor deposition (CVD) or other methods using tetraethoxysilane (TEOS) gas, an organosilicon compound.

[0054] like Figure 1As shown, the first resistive layers 31a to the fourth resistive layers 31d have a rectangular planar pattern. The thickness of the first resistive layers 31a to the fourth resistive layers 31d is, for example, about 500 nm, and the sheet resistance of the first resistive layers 31a to the fourth resistive layers 31d is, for example, about 150 Ω / □. For example, an n-type doped polysilicon (DOPOS) layer can be used as the first resistive layers 31a to the fourth resistive layers 31d. The n-type DOPOS layer can be formed by implanting n-type impurities such as phosphorus (P) into polysilicon; or by adding n-type impurities such as phosphorus (P) to the polysilicon during deposition using a CVD apparatus. The resistance values ​​of the first resistive layers 31a to the fourth resistive layers 31d can be controlled by adjusting the width W1 and length L1 of the first resistive layers 31a to the fourth resistive layers 31d. In addition, when the DOPOS layer is used for the first resistance layer 31a to the fourth resistance layer 31d, the resistance values ​​of the first resistance layer 31a to the fourth resistance layer 31d can be controlled by adjusting the amount of impurity elements added to the polysilicon.

[0055] Preferably, the temperature coefficients of the first resistive layer 31a to the fourth resistive layer 31d are 0 ppm / °C or less (in other words, the temperature coefficients of the first resistive layer 31a to the fourth resistive layer 31d are 0, or the first resistive layer 31a to the fourth resistive layer 31d have negative temperature coefficients). This suppresses the increase in resistance value during high-temperature operation. For example, when the resistive element according to the embodiment is used as a gate resistive element of an insulated-gate bipolar transistor (IGBT), losses during IGBT turn-on can be suppressed. For example, the temperature coefficient of DOPOS can be controlled by adjusting the dosage during ion implantation of impurities into polysilicon. For example, if the dosage is set to 7.0 × 10⁻⁶... 15 cm -2 The temperature coefficient of DOPOS can be made to be below 0 ppm / ℃. In addition, the first resistive layer 31a to the fourth resistive layer 31d can have a positive temperature coefficient, and the temperature coefficient of the first resistive layer 31a to the fourth resistive layer 31d is not necessarily limited to below 0 ppm / ℃.

[0056] The first resistive layer 31a to the fourth resistive layer 31d can also be a p-type DOPOS layer. A p-type DOPOS layer can also be formed by ion implantation of p-type impurities such as boron (B) into polycrystalline silicon. The first resistive layer 31a to the fourth resistive layer 31d are not limited to DOPOS layers and can also be tantalum nitride (TaN). xThis refers to a laminated film of high-melting-point metal films obtained by sequentially stacking nitride films of transition metals such as chromium (Cr), nickel (Ni), and manganese (Mn). The first resistive layer 31a to the fourth resistive layer 31d can also be thin films of silver palladium (AgPd), ruthenium oxide (RuO2), etc. Furthermore, the first resistive layer 31a to the fourth resistive layer 31d can also be realized using a p-type diffusion layer or an n-type diffusion layer formed on the semiconductor surface, although this differs from... Figure 1 and Figure 2 The structure shown.

[0057] like Figure 1 As shown on the left, along the first side of the rectangle, a first dummy layer 32a and a second dummy layer 32b are disposed separately from the first resistive layer 31a, separated by a first resistive layer 31a. Furthermore, as... Figure 1 As shown on the upper side, along the second side of the rectangle, a third dummy layer 32c and a fourth dummy layer 32d are disposed separately from the second resistor layer 31b, separated by the second resistor layer 31b. Furthermore, as... Figure 1 As shown on the right, along the third side of the rectangle, a fifth dummy layer 32e and a sixth dummy layer 32f are disposed separately from the third resistor layer 31c, separated by the third resistor layer 31c. Furthermore, as... Figure 1 As shown on the lower side, along the fourth side of the rectangle, a seventh dummy layer 32g and an eighth dummy layer 32h are arranged separately from the fourth resistor layer 31d, separated by the fourth resistor layer 31d. Furthermore, the names "first dummy layer 32a" to "eighth dummy layer 32h" are merely ordinal numbers assigned for ease of explanation; when referring collectively to the first dummy layer 32a to the eighth dummy layer 32h, they can be defined as "multiple dummy layers".

[0058] The first dummy layer 32a to the eighth dummy layer 32h are formed of the same material as the first resistive layer 31a to the fourth resistive layer 31d, such as n-type DOPOS, and have the same thickness as the first resistive layer 31a to the fourth resistive layer 31d. The width and length of the first dummy layer 32a to the eighth dummy layer 32h can be the same as or different from the width W1 and length L1 of the first resistive layer 31a to the fourth resistive layer 31d. The first dummy layer 32a to the eighth dummy layer 32h may not be necessary.

[0059] exist Figure 1 The illustrations are omitted in the text, such as Figure 2As shown, an interlayer insulating film (second insulating film) 4 is disposed to cover the field insulating film 2 and the first resistive layers 31a to the fourth resistive layers 31d. The thickness of the interlayer insulating film 4 is, for example, about 1500 nm. As the interlayer insulating film 4, a single-layer film of phosphorus (P) and boron (B) free silicon oxide film (SiO2 film), a silicon oxide film with added phosphorus (PSG film), a silicon oxide film with added boron (BSG film), a silicon oxide film with added phosphorus and boron (BPSG film), or a silicon nitride film (Si3N4 film), or a composite film obtained by combining a variety of these, can be used. For example, the interlayer insulating film 4 can be composed of a composite film obtained by laminating an NSG film of about 770 nm and a PSG film of about 650 nm. The NSG film can have the function of suppressing resistance deviation. In addition, the PSG film can have the function of ensuring the strength of the lead bonding.

[0060] like Figure 2 As shown, the pad forming electrode 51 is located above the field insulating film 2. Figure 1 As shown, the pad forming electrode 51 has a rectangular planar pattern. The center O of the rectangular planar pattern of the pad forming electrode 51 is located at the center of the chip. Figure 1 and Figure 2 As shown, the left end of the pad forming electrode 51 overlaps with the right end of the first resistive layer 31a in the depth direction. The pad forming electrode 51 is connected to one end of the first resistive layer 31a via the first electrode contact area 61a.

[0061] like Figure 1 As shown, the upper end of the pad forming electrode 51 overlaps with one end of the second resistive layer 31b in the depth direction. The pad forming electrode 51 is connected to one end of the second resistive layer 31b via the second electrode contact area 61b. Figure 1 and Figure 2 As shown, the right end of the pad forming electrode 51 overlaps with one end of the left side of the third resistive layer 31c in the depth direction. The pad forming electrode 51 is connected to one end of the third resistive layer 31c via the third electrode contact area 61c. Figure 1 As shown, the lower end of the pad forming electrode 51 overlaps with one end of the fourth resistive layer 31d in the depth direction. The pad forming electrode 51 is connected to one end of the fourth resistive layer 31d via the fourth electrode contact area 61d.

[0062] like Figure 1 and Figure 2 As shown, on the interlayer insulating film 4, a first relay wiring 52a, a second relay wiring 52b, a third relay wiring 52c, and a fourth relay wiring 52d are arranged separately from the pad forming electrode 51, surrounding the central pad forming electrode (surface electrode) 51. Figure 1As shown, the first trunk cable 52a is configured along the first side of the rectangle. The second trunk cable 52b is configured along the second side of the rectangle. The third trunk cable 52c is configured along the third side of the rectangle. The fourth trunk cable 52d is configured along the fourth side of the rectangle. Furthermore, the names "first trunk cable 52a" to "fourth trunk cable 52d" are assigned ordinal numbers only for ease of explanation; when referring to the first trunk cable 52a to the fourth trunk cable 52d collectively, they can be defined as "multiple trunk cables".

[0063] The planar pattern of the pad-formed electrode 51, the first resistive layer 31a to the fourth resistive layer 31d, and the first relay wiring 52a to the fourth relay wiring 52d is rotationally symmetrical about four times with respect to the center O of the chip. Therefore, when installing the resistive element according to the embodiment, it can be rotated 90° or 180° for use, making the assembly operation easier.

[0064] like Figure 2 As shown, the right end of the first relay wiring 52a overlaps with the other end of the first resistive layer 31a in the depth direction. A resistive layer connection terminal, serving as one end (first end) of the first relay wiring 52a, contacts the other end of the first resistive layer 31a via a first wiring contact area 62a. The left end of the third relay wiring 52c overlaps with the other end of the third resistive layer 31c in the depth direction. A resistive layer connection terminal, serving as one end (first end) of the third relay wiring 52c, contacts the other end of the third resistive layer 31c via a third wiring contact area 62c.

[0065] Although the illustration is omitted, in Figure 2 Deep within the paper, the end of the second relay wiring 52b overlaps with the other end of the second resistive layer 31b in the depth direction. The resistive layer connection terminal, serving as one end (first end) of the second relay wiring 52b, contacts the other end of the second resistive layer 31b via the second wiring contact area 62b. Figure 2 On the near-front side of the paper, the end of the fourth relay wiring 52d overlaps with the other end of the fourth resistive layer 31d in the depth direction. The resistive layer connection terminal, which is one end (first end) of the fourth relay wiring 52d, contacts the other end of the fourth resistive layer 31d via the fourth wiring contact area 62d.

[0066] like Figure 1 and Figure 2As shown, the substrate connection terminal, which serves as the other end (second end) of the first relay wiring 52a to the fourth relay wiring 52d, makes ohmic contact with the semiconductor substrate 1 via the first substrate contact area 63a to the fourth substrate contact area 63d with low contact resistance. Alternatively, a contact area with a higher impurity concentration (lower resistivity) and the same conductivity type as the semiconductor substrate 1 may be provided on the upper part of the semiconductor substrate 1 at the contact area between the first substrate contact area 63a to the fourth substrate contact area 63d and the semiconductor substrate 1.

[0067] The thickness of the pad forming electrode 51 and the first relay wiring 52a to the fourth relay wiring 52d is, for example, about 3 μm. The pad forming electrode 51 and the first relay wiring 52a to the fourth relay wiring 52d can, for example, be composed of a multilayer film of titanium / titanium nitride (Ti / TiN) as a barrier metal of about 120 nm, aluminum-silicon (Al-Si) of about 3 μm, and TiN / Ti as an anti-reflective film of about 45 nm. Al or Al-Cu-Si, Al-Cu, or other Al alloys can also be used instead of Al-Si. A bonding wire (not shown) with a diameter of about 300 μm, formed of a metal such as aluminum (Al), is connected to the pad forming electrode 51.

[0068] exist Figure 1 The illustrations are omitted in the text, such as Figure 2 As shown, a guard ring 53 is disposed on the interlayer insulating film 4. The guard ring 53 is disposed in a ring shape on the outer periphery of the chip constituting the resistive element according to the embodiment. The guard ring 53 is connected to the semiconductor substrate 1 via peripheral contact areas 64a and 64b. The guard ring 53 is formed of the same material as the electrode 51 formed by the pad and the first relay wiring 52a to the fourth relay wiring 52d. The guard ring 53 can prevent moisture from entering from the side of the chip.

[0069] like Figure 2 As shown, a protective insulating film (third insulating film: passivation film) 7 is disposed on the pad forming electrode 51, the first relay wiring 52a to the fourth relay wiring 52d, and the protective ring layer 53. The protective insulating film 7 can be, for example, a composite film obtained by sequentially stacking a TEOS film, a Si3N4 film, and a polyimide film. An opening 7a is provided in the protective insulating film 7. Figure 1 The protective insulating film 7 is omitted from the illustration; only the opening 7a of the protective insulating film 7 is shown with a single dotted line. The portion of the pad forming electrode 51 exposed from the opening 7a becomes the pad area capable of connecting the bonding wire.

[0070] like Figure 2As shown, a back electrode (opposing electrode) 9 is disposed on the lower surface of the semiconductor substrate 1. The back electrode 9 can be, for example, a metal film obtained by stacking titanium (Ti), nickel (Ni), and gold (Au) in this order, or a single-layer film formed of gold (Au). The outermost layer of the back electrode 9 can be made of a solderable material. The back electrode 9 is fixed to a metal plate (not shown) by welding or the like. The resistive element according to the embodiment realizes the following vertical resistive element: four resistive layers, namely the first resistive layer 31a to the fourth resistive layer 31d, are connected in parallel between the pad forming electrode 51 and the back electrode 9, and the electrical path between the pad forming electrode 51 and the back electrode 9 is used as the resistive body.

[0071] In the resistive element according to the embodiment, four resistive layers, namely the first resistive layer 31a to the fourth resistive layer 31d, are provided. However, by changing the presence or absence of the first electrode contact area 61a to the fourth electrode contact area 61d, the first wiring contact area 62a to the fourth wiring contact area 62d, and the first substrate contact area 63a to the fourth substrate contact area 63d, the first resistive layer 31a to the fourth resistive layer 31d can be selectively used. For example, when selectively using only one of the four resistive layers, the first resistive layer 31a, the first wiring contact area 62a, and the first substrate contact area 63a to the fourth substrate contact area 63d, the first electrode contact area 61a, the first wiring contact area 62a, and the first substrate contact area 63a to the fourth substrate contact area 63d, are all provided.

[0072] When the resistance values ​​of the first resistance layer 31a to the fourth resistance layer 31d are all 120Ω, the resistance value of the resistive element according to the embodiment is 120Ω when any one of the first resistance layer 31a to the fourth resistance layer 31d is connected. When any three of the first resistance layers 31a to the fourth resistance layer 31d are connected in parallel, the resistance value of the resistive element according to the embodiment is 40Ω. When any two of the first resistance layers 31a to the fourth resistance layer 31d are connected in parallel, the resistance value of the resistive element according to the embodiment is 60Ω. Figure 1 and Figure 2 As shown, when the four resistor layers 31a to 31d are connected in parallel, the resistance value of the resistor element in this embodiment is 30Ω. In this way, the resistance value of the resistor element in this embodiment can be adjusted by increasing or decreasing the number of parallel connections of the first resistor layers 31a to 31d.

[0073] like Figure 3As shown, the resistive element involved in the embodiment can be applied, for example, to an inverter module 100 that drives a three-phase motor consisting of a u-phase, a v-phase, and a w-phase. The inverter module 100 includes a first main element TR1, a second main element TR2, a third main element TR3, and a fourth main element TR4 that drive the u-phase. The inverter module 100 also includes a fifth main element TR5, a sixth main element TR6, a seventh main element TR7, an eighth main element TR8 that drive the v-phase, and a ninth main element TR9, a tenth main element TR10, an eleventh main element TR11, and a twelfth main element TR12 that drive the w-phase. Freewheeling diodes (not shown) are connected to the first main element TR1 through the twelfth main element TR12 respectively. IGBTs can be used for the first main element TR1 through the twelfth main element TR12. First gate resistors R1 through twelfth gate resistors R12 are connected to the gate electrodes of each IGBT to suppress oscillations during switching operations.

[0074] The resistive element involved in the embodiment can be applied to each of the first gate resistive element R1 to the twelfth gate resistive element R12. For example, when the resistive element involved in the embodiment is applied to the first gate resistive element R1, the side of the first gate resistive element R1 connected to the gate electrode of the first main element TR1 corresponds to... Figure 1 and Figure 2 The pads shown form the terminals on the electrode 51 side. Additionally, the side of the first gate resistor element R1 opposite to the side connected to the gate electrode of the first main element TR1 corresponds to... Figure 2 The terminal on the back electrode 9 side is shown in the figure.

[0075] According to the embodiment, the resistor element is configured with the following vertical structure: four resistor layers, namely the first resistor layer 31a to the fourth resistor layer 31d, are connected in parallel between the pad forming electrode 51 and the back electrode 9, and the electrical path between the pad forming electrode 51 and the back electrode 9 serves as the resistive element. Therefore, the pad area formed by the pad forming electrode 51 on the upper surface connected to the first resistor layer 31a to the fourth resistor layer 31d is one. Consequently, the resistor element according to the embodiment requires only one bonding wire, which reduces the number of bonding wires compared to a lateral resistor element. Furthermore, compared to a lateral resistor element, the area occupied by the pad area on the upper surface can be reduced, thus enabling a reduction in chip size.

[0076] Furthermore, according to the resistive element of the embodiment, by changing the presence or absence of the first electrode contact areas 61a to the fourth electrode contact areas 61d, the first wiring contact areas 62a to the fourth wiring contact areas 62d, and the first substrate contact areas 63a to the fourth substrate contact areas 63d, some or all of the plurality of first resistive layers 31a to the fourth resistive layers 31d can be selectively used. Therefore, depending on the application of the resistive element according to the embodiment, the resistance value of the resistive element according to the embodiment can be adjusted by appropriately selecting the number of parallel connections of the plurality of first resistive layers 31a to the fourth resistive layers 31d.

[0077] <Manufacturing Methods of Resistor Elements>

[0078] Next, refer to Figures 4 to 13 This section describes one example of a method for manufacturing a resistive element according to an embodiment of the present invention. Furthermore, the method for manufacturing a resistive element described below is just one example; variations thereof are included as long as they fall within the scope of the claims, and it is self-evident that various other manufacturing methods can be used to achieve this.

[0079] First, prepare a semiconductor substrate 1, such as a silicon substrate with a high concentration of added n-type impurities. For example... Figure 4 As shown, a field insulating film 2, such as a TEOS film, is deposited on a semiconductor substrate 1 using a low-pressure (LP) CVD method or the like. Alternatively, the field insulating film 2 can be formed from a composite film, which is obtained by depositing an insulating film on the thermally oxidized film using a CVD method or the like after forming a thermally oxidized film via thermal oxidation, thereby stacking the thermally oxidized film and the deposited insulating film.

[0080] Next, a photoresist film is coated on the field insulating film 2, and a pattern is formed on the photoresist film using photolithography. The patterned photoresist film is then used as an etching mask, and a portion of the field insulating film 2 is selectively removed using dry etching methods such as reactive ion etching (RIE). Afterward, the photoresist film is removed. The result is as follows: Figure 5 As shown, a field insulating film 2 pattern is formed on a portion of the semiconductor substrate 1.

[0081] Next, an undoped polycrystalline silicon layer is formed on the semiconductor substrate 1 and the field insulating film 2 using methods such as CVD. Then, n-type impurities such as phosphorus (P) are ion-implanted into the polycrystalline silicon layer. For example, an accelerating voltage of 80 keV and a 6.0 × 10⁻⁶ m² / h⁻¹ are used. 15 cm -2 Phosphorus (P) ions were implanted at doses approximately as follows. Subsequently, the implanted ions were activated by heat treatment, such as... Figure 6 As shown, a DOPOS layer 3 with a high concentration of n-type impurities is formed.

[0082] Next, a photoresist film is coated on DOPOS layer 3, and a pattern is formed on the photoresist film using photolithography. The patterned photoresist film is used as an etching mask, and a portion of DOPOS layer 3 is selectively removed using methods such as RIE. Afterward, the photoresist film is removed. The result is as follows: Figure 7 As shown, a first resistive layer 31a and a third resistive layer 31c are formed on the field insulating film 2. At this time, a third resistive layer is also formed on the field insulating film 2. Figure 1 The second resistive layer 31b and the fourth resistive layer 31d are shown in the figure.

[0083] Next, as Figure 8 As shown, the interlayer insulating film 4 is deposited by covering the field insulating film 2 and the first resistive layer 31a to the fourth resistive layer 31d. For example, the NSG film and the PSG film are deposited sequentially by a CVD method, thereby forming the interlayer insulating film 4 from a composite film obtained by stacking the NSG film and the PSG film.

[0084] Next, a photoresist film is coated on the interlayer insulating film 4, and a pattern is formed on the photoresist film using photolithography. The patterned photoresist film is used as an etching mask, and a portion of the interlayer insulating film 4 is selectively removed using RIE or similar methods. Afterward, the photoresist film is removed. The result is as follows: Figure 9 As shown, a first pad contact hole 4a and a third pad contact hole 4b are formed in the interlayer insulating film 4. Although the illustration is omitted, in Figure 9 A second solder pad contact hole is also drilled deep within the paper surface. Figure 9 A fourth pad contact hole is also made on the front side of the paper. In this specification, the first to fourth pad contact holes are collectively referred to as the "first contact hole".

[0085] Furthermore, a first inner relay contact hole 4c and a third inner relay contact hole 4d are simultaneously drilled with the first contact hole. Although the illustration is omitted, in Figure 9 A second inner relay contact hole is also drilled deep within the paper surface. Figure 9 A fourth inner relay contact hole is also opened on the near-front side of the paper. In this specification, the first inner relay contact hole to the fourth inner relay contact hole are collectively referred to as the "second contact hole".

[0086] Furthermore, a first outer relay contact hole 4e and a third outer relay contact hole 4f are simultaneously drilled along with the first and second contact holes. Although the illustrations are omitted, in... Figure 9 A second outer relay contact hole is also drilled deep within the paper surface. Figure 9A fourth outer relay contact hole is also opened on the near-front side of the paper. In this specification, the first outer relay contact hole to the fourth outer relay contact hole are collectively referred to as the "third contact hole". Furthermore, protective ring contact holes 4g, 4h, etc. are also opened at the same time as the first contact hole to the third contact hole.

[0087] Next, as Figure 10 As shown, a metal film 5 is deposited on the interlayer insulating film 4 by means of vacuum evaporation or sputtering, etc., to fill the first pad contact hole 4a, the third pad contact hole 4b, the first inner relay contact hole 4c, the third inner relay contact hole 4d, the first outer relay contact hole 4e, the third outer relay contact hole 4f, the guard ring contact hole 4g, 4h, etc. For example, the metal film 5 can be formed by sequentially depositing Ti / TiN, Al-Si, TiN / Ti by CVD or other methods.

[0088] Next, a photoresist film is coated onto the metal film 5, and a pattern is formed on the photoresist film using photolithography. The patterned photoresist film is then used as an etching mask to selectively remove a portion of the metal film 5. The result is as follows: Figure 11 As shown, the pattern of pad forming electrode 51, first relay wiring 52a to fourth relay wiring 52d and protective ring layer 53 are separated on the interlayer insulating film 4.

[0089] Furthermore, a first electrode contact area 61a is formed, which is buried in the first pad contact hole 4a and connected to the first resistive layer 31a. A third electrode contact area 61c is formed, which is buried in the third pad contact hole 4b and connected to the third resistive layer 31c. As a result, the pad forming electrode 51 is connected to the first resistive layer 31a via the first electrode contact area 61a, and the pad forming electrode 51 is connected to the third resistive layer 31c via the third electrode contact area 61c. Although the illustration is omitted, in… Figure 11 A second electrode contact area is formed deep within the paper surface, connecting the pad forming electrode 51 to the second resistive layer 31b via a second pad contact hole. Additionally, in Figure 11 Near the front side of the paper, a fourth electrode contact area is also formed to connect the pad forming electrode 51 and the fourth resistive layer 31d via the fourth pad contact hole.

[0090] Furthermore, while forming the pattern of the first relay wiring 52a, a first wiring contact area 62a is formed, which is buried in the first inner relay contact hole 4c and connected to the first resistive layer 31a. Also, a first substrate contact area 63a is formed, which is buried in the first outer relay contact hole 4e and connected to the semiconductor substrate 1. Furthermore, a third wiring contact area 62c is formed, which is buried in the third inner relay contact hole 4d and connected to the third resistive layer 31c. Finally, a third substrate contact area 63c is formed, which is buried in the third outer relay contact hole 4f and connected to the semiconductor substrate 1.

[0091] Furthermore, although the illustrations are omitted, in Figure 11 Deep within the paper surface, a second wiring contact area is formed, connecting the second resistor layer 31b to the second relay wiring 52b via a second inner relay contact hole, and a second substrate contact area is formed, connecting the second relay wiring 52b to the semiconductor substrate 1 via a second outer relay contact hole. Furthermore, in Figure 11 The front side of the paper surface also forms a fourth wiring contact area that connects the fourth resistor layer 31d and the fourth relay wiring 52d via the fourth inner relay contact hole, and a fourth substrate contact area that connects the fourth relay wiring 52d and the semiconductor substrate 1 via the fourth outer relay contact hole.

[0092] Furthermore, peripheral contact areas 64a and 64b are formed respectively, which are filled into the contact holes 4g and 4h of the protective ring and connected to the semiconductor substrate 1.

[0093] Next, as Figure 12 As shown, a protective insulating film 7 is formed on the pad forming electrode 51, the first relay wiring 52a to the fourth relay wiring 52d, and the protective ring layer 53. For example, a TEOS film and a Si3N4 film are sequentially deposited by plasma CVD or the like, and a polyimide film is coated, thereby forming a protective insulating film 7 comprising a TEOS film, a Si3N4 film, and a polyimide film.

[0094] Next, a photoresist film is coated onto the protective insulating film 7, and a pattern is formed on the photoresist film using photolithography. The patterned photoresist film is then used as an etching mask to selectively remove a portion of the protective insulating film 7. The result is as follows: Figure 13 As shown, an opening 7a is formed in the protective insulating film 7, and the portion of the electrode 51 exposed in the opening 7a becomes the pad area.

[0095] Next, the lower surface of the semiconductor substrate 1 is ground using chemical mechanical polishing (CMP) or similar methods to reduce the thickness of the semiconductor substrate 1 to approximately 350 μm. Then, a deposition process is performed on the lower surface of the semiconductor substrate 1 using methods such as vacuum evaporation or sputtering. Figure 2The back electrode 9 is shown in the diagram. Furthermore, on a wafer, a large number of [devices] are formed as a matrix-like chip region. Figure 1 and Figure 2 The resistor element shown is the same element; by cutting, these chips are separated into... Figure 1 and Figure 2 The chip of the resistor element shown.

[0096] According to the method for manufacturing a resistive element as described in the embodiments, a resistive element that can reduce chip size and the number of bonding wires can be easily realized. Furthermore, in Figure 9 In the process shown, by appropriately selecting a mask, the presence or absence of the first electrode contact area 61a to the fourth electrode contact area 61d, the first wiring contact area 62a to the fourth wiring contact area 62d, and the first substrate contact area 63a to the fourth substrate contact area 63d can be changed. This allows for the selective use of some or all of the multiple first resistor layers 31a to the fourth resistor layers 31d, thereby adjusting the number of parallel connections.

[0097] <First Variation>

[0098] The resistive element involved in the first variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 14 and Figure 15 As shown, three of the four resistor layers—first resistor layer 31a, second resistor layer 31b, and fourth resistor layer 31d—are selectively used to connect them in parallel. In the resistive element involved in the first modified example, no resistor is provided. Figure 1 and Figure 2 The diagram shows a third electrode contact area 61c connecting the pad forming electrode 51 to the third resistive layer 31c, a third wiring contact area 62c connecting the third resistive layer 31c to the third relay wiring 52c, and a third substrate contact area 63c connecting the third relay wiring 52c to the semiconductor substrate 1. Other structures and figures related to the resistive element in the first modified example are also shown. Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0099] According to the resistive element involved in the first variation, and Figure 1 and Figure 2 Compared to the resistive element in the illustrated embodiment, the number of parallel connections of the first resistive layer 31a, the second resistive layer 31b, and the fourth resistive layer 31d is reduced, thereby increasing the resistance value of the resistive element in the first modified example.

[0100] Regarding the manufacturing method of the resistive element involved in the first modified example, the manufacturing method of the resistive element involved in the embodiment... Figure 9 In the process shown, a mask different from the mask used in the manufacturing method of the resistor element according to the embodiment is used, thereby avoiding the formation of the third electrode contact area 61c, the third wiring contact area 62c, and the third substrate contact area 63c. The other processes of the manufacturing method of the resistor element according to the first modification are the same as those of the manufacturing method of the resistor element according to the embodiment, so repeated descriptions are omitted.

[0101] <Second Variation>

[0102] The resistive element involved in the second variation of the embodiments of the present invention and Figure 14 and Figure 15 The resistive elements involved in the first modified example shown share commonalities in the following aspects: Figure 16 and Figure 17 As shown, three of the four resistive layers—first resistive layer 31a, second resistive layer 31b, and fourth resistive layer 31d—are selectively used to connect them in parallel. However, in the resistive element involved in the second modification example, with... Figure 14 and Figure 15 The resistive element involved in the first modified example shown differs in the following aspects: it is only not provided. Figure 1 and Figure 2 The third electrode contact region 61c shown connects the pad forming electrode 51 to the third resistive layer 31c, and includes a third wiring contact region 62c connecting the third resistive layer 31c to the third relay wiring 52c, and a third substrate contact region 63c connecting the third relay wiring 52c to the semiconductor substrate 1. Other structures of the resistive element involved in the second modification are similar to... Figure 14 and Figure 15 The first variation shown involves the same resistive element, so repeated descriptions are omitted.

[0103] According to the resistive element in the second modification, the third resistive layer 31c can be left unused even without the third electrode contact region 61c. Furthermore, even if the third electrode contact region 61c is provided, the third resistive layer 31c can be left unused without the third wiring contact region 62c or the third substrate contact region 63c. That is, the third resistive layer 31c can be left unused by omitting at least one of the third electrode contact region 61c, the third wiring contact region 62c, and the third substrate contact region 63c.

[0104] Regarding the manufacturing method of the resistive element involved in the second modification, the manufacturing method of the resistive element involved in the embodiment... Figure 9In the process shown, a mask different from the mask used in the manufacturing method of the resistive element involved in the embodiment is used so that the third electrode contact area 61c is not formed.

[0105] <Third Variation>

[0106] The resistive element involved in the third variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 18 As shown, the width W1 of the first resistive layer 31a and the third resistive layer 31c is different from the width W2 of the second resistive layer 31b and the fourth resistive layer 31d. The width W1 of the first resistive layer 31a and the third resistive layer 31c is smaller than the width W2 of the second resistive layer 31b and the fourth resistive layer 31d; therefore, the resistance value of the first resistive layer 31a and the third resistive layer 31c is larger than the resistance value of the second resistive layer 31b and the fourth resistive layer 31d. Other structures of the resistive element involved in the third modification example are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0107] According to the resistive element in the third modification, by making the width W1 of the first resistive layer 31a and the third resistive layer 31c different from the width W2 of the second resistive layer 31b and the fourth resistive layer 31d, the resistance values ​​of the first resistive layer 31a and the third resistive layer 31c can be made different from the resistance values ​​of the second resistive layer 31b and the fourth resistive layer 31d. Therefore, when selectively using the first resistive layer 31a to the fourth resistive layer 31d, the degree of freedom in determining the resistance value of the resistive element according to the third modification can be increased. Furthermore, in the resistive element according to the third modification, a case is illustrated where the resistance values ​​of the two resistive layers of the first resistive layer 31a and the third resistive layer 31c are different from the resistance values ​​of the two resistive layers of the second resistive layer 31b and the fourth resistive layer 31d, but it is not limited to this. For example, the resistance values ​​of the four resistor layers 31a to 31d can be made different by making the widths of the four resistor layers 31a to 31d different from each other.

[0108] <Fourth Variation>

[0109] The resistive element involved in the fourth variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 19As shown, two resistor layers, a first resistor layer 31a and a second resistor layer 31b, are disposed facing each other with electrodes 51 formed across pads. The planar patterns of the first resistor layer 31a and the second resistor layer 31b, the pad forming electrodes 51, the first relay wiring 52a, and the second relay wiring 52b are rotationally symmetrical about the center O of the chip. Therefore, when mounting the resistor element involved in the fourth modification, it can be rotated 180° for use, making the assembly operation easier. The other structures of the resistor element involved in the fourth modification are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0110] According to the resistive element involved in the fourth modification, when two resistive layers, namely the first resistive layer 31a and the second resistive layer 31b, are provided, one or both of the first resistive layer 31a and the second resistive layer 31b can be selectively used by changing the presence or absence of the first electrode contact area 61a and the second electrode contact area 61b, the first wiring contact area 62a and the second wiring contact area 62b, and the first substrate contact area 63a and the second substrate contact area 63b.

[0111] <Fifth Variation>

[0112] The resistive element involved in the fifth variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 20 As shown, multiple (three) resistor layers, consisting of a first resistor layer 31a to a third resistor layer 31c, are disposed on one side of the rectangular planar pattern forming the electrode 51 on the pad. Other structures of the resistor element involved in the fifth modification are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0113] According to the resistive element involved in the fifth modification, when three resistive layers, namely the first resistive layer 31a to the third resistive layer 31c, are provided on one side of the rectangular planar pattern of the pad forming electrode 51, it is also possible to selectively use part or all of the first resistive layer 31a to the third resistive layer 31c by changing the presence or absence of the first electrode contact area 61a to the third electrode contact area 61c, the first wiring contact area 62a to the third wiring contact area 62c, and the first substrate contact area 63a to the third substrate contact area 63c.

[0114] <Sixth Variation>

[0115] The resistive element involved in the sixth variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 21 and 22 As shown, a plurality of (2) pad forming electrodes, each having a first pad forming electrode 51a and a second pad forming electrode 51b, are disposed separately from each other. A first resistive layer 31a to a sixth resistive layer 31f is disposed between the first pad forming electrode 51a and the second pad forming electrode 51b.

[0116] The first pad forming electrode 51a is connected to one end of the first resistive layer 31a to the third resistive layer 31c via the first electrode contact area 61a to the third electrode contact area 61c. The other end of the first resistive layer 31a to the third resistive layer 31c is connected to the first relay wiring 52a to the third relay wiring 52c via the first wiring contact area 62a to the third wiring contact area 62c. The first relay wiring 52a to the third relay wiring 52c is connected to the semiconductor substrate 1 via the first substrate contact area 63a to the third substrate contact area 63c. On the upper part of the semiconductor substrate 1, which serves as the contact area between the first substrate contact area 63a to the third substrate contact area 63c and the semiconductor substrate 1, a first contact area 10a to the third contact area 10c and a peripheral contact area 1 are provided, which have a higher impurity concentration (lower resistivity) than the impurity concentration of the semiconductor substrate 1 and the same conductivity type as the semiconductor substrate. In other embodiments, the contact area 10 and the peripheral contact area 11 may also be provided.

[0117] The second pad forming electrode 51b is connected to one end of the fourth resistive layer 31d to the sixth resistive layer 31f via the fourth electrode contact area 61d to the sixth electrode contact area 61f. The other end of the fourth resistive layer 31d to the sixth resistive layer 31f is connected to the first relay wiring 52a to the third relay wiring 52c via the fourth wiring contact area 62d to the sixth wiring contact area 62f. The resistive element involved in the sixth modification of the embodiment of the present invention can be used, for example, as... Figure 3 A pair of first gate resistor elements R1 and second gate resistor elements R2. Other structures of the resistor elements involved in the sixth variation are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0118] According to the resistive element involved in the sixth modification, when multiple (2) pad forming electrodes are provided, including the first pad forming electrode 51a and the second pad forming electrode 51b, it is also possible to selectively use part or all of the first resistive layer 31a to the sixth resistive layer 31f by changing the presence or absence of the first electrode contact area 61a to the sixth electrode contact area 61f, the first wiring contact area 62a to the sixth wiring contact area 62f, and the first substrate contact area 63a to the sixth substrate contact area 63f.

[0119] <Seventh Variation>

[0120] The resistive element involved in the seventh variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 23 As shown, first auxiliary pads 65a to fourth auxiliary pads 65d are provided, which are electrically connected to the first trunk wiring 63a to the fourth trunk wiring 63d. Figure 23 The protective insulating film is omitted from the illustration; only the openings 7b-7e of the protective insulating film are shown with dashed lines. The first auxiliary pads 65a-65d protrude from the openings 7b-7e of the protective insulating film. The first auxiliary pads 65a-65d are formed of the same material as the first relay wiring 63a-63d, allowing the first auxiliary pads 65a-65d to be formed simultaneously with the first relay wiring 63a-63d. Other structures of the resistive element involved in the seventh modification are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0121] Figure 24 The equivalent circuit of the resistive element according to the seventh variation of the embodiments of the present invention is shown. Figure 24 In the diagram, pad forming electrode 51 corresponds to pad-side terminal 101, back electrode 9 corresponds to back-side terminal 102, and first auxiliary pads 65a to fourth auxiliary pads 65d correspond to auxiliary terminals 103a to 103d. Between pad-side terminal 101 and back-side terminal 102, a resistor R is connected in parallel corresponding to the first resistive layer 31a to the fourth resistive layer 31d. poly1 ~R poly4 Resistance R of semiconductor substrate 1 sub Series connection. Auxiliary terminals 103a to 103d are respectively connected to resistors R corresponding to the first resistance layer 31a to the fourth resistance layer 31d. poly1 ~R poly4 The resistors in the circuit and the resistance R of the semiconductor substrate 1 sub between.

[0122] According to the resistive element involved in the seventh modification, by configuring the first auxiliary pads 65a to the fourth auxiliary pads 65d, the resistance R corresponding to the removed semiconductor substrate 1 can be measured between the pad forming electrode 51 and the first auxiliary pads 65a to the fourth auxiliary pads 65d. sub The resistance R of the first resistive layer 31a to the fourth resistive layer 31d poly1 ~R poly4 Electrical characteristics.

[0123] <Eighth Variation>

[0124] The resistive element involved in the eighth variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 25 and Figure 26 As shown, an auxiliary film 33 in a floating state is disposed on the field insulating film 2, separate from the first resistive layer 31a to the fourth resistive layer 31d.

[0125] The auxiliary film 33 is disposed separately from the first resistive layers 31a to 31d below the pad forming electrode 51. The auxiliary film 33 is formed of the same material as the first resistive layers 31a to 31d, such as an n-type DOPOS, and has the same thickness as the first resistive layers 31a to 31d. The auxiliary film 33, for example, has a rectangular planar pattern. By... Figure 13 In the process shown, a portion of the DOPOS layer 3 is selectively removed to form the auxiliary film 33 simultaneously with the formation of the first resistive layers 31a to the fourth resistive layers 31d. Other structures of the resistive element involved in the eighth modification are similar to... Figure 1 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0126] According to the resistive element in the eighth modification, by distributing an auxiliary film 33 in a floating potential state on the field insulating film 2, the parasitic capacitance below the pad forming electrode 51 can be reduced, similar to the case of increasing the thickness of the field insulating film 2. This suppresses the decrease in total resistance due to impedance drop during high-frequency operation, thereby suppressing oscillation phenomena.

[0127] <Ninth Variation>

[0128] The resistive element involved in the ninth variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 27As shown, fifth resistor layers 34a to twelfth resistor layers 34h and fifth trunk wiring 54a to twelfth trunk wiring 54h are also provided. The fifth resistor layer 34a and the sixth resistor layer 34b are configured to be separated by a first resistor layer 31a. The seventh resistor layer 34c and the eighth resistor layer 34d are configured to be separated by a second resistor layer 31b. The ninth resistor layer 34e and the tenth resistor layer 34f are configured to be separated by a third resistor layer 31c. The eleventh resistor layer 34g and the twelfth resistor layer 34h are configured to be separated by a fourth resistor layer 31d.

[0129] The fifth trunk wiring 54a and the sixth trunk wiring 54b are configured to be separated from the first trunk wiring 52a. The seventh trunk wiring 54c and the eighth trunk wiring 54d are configured to be separated from the second trunk wiring 52b. The ninth trunk wiring 54e and the tenth trunk wiring 54f are configured to be separated from the third trunk wiring 52c. The eleventh trunk wiring 54g and the twelfth trunk wiring 54h are configured to be separated from the fourth trunk wiring 52d. Other structures of the resistive element involved in the ninth variation are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0130] According to the resistive element of the ninth modification, by changing the presence or absence of the fifth electrode contact area to the twelfth electrode contact area, the fifth wiring contact area to the twelfth wiring contact area, and the fifth substrate contact area to the twelfth substrate contact area used to connect the fifth resistive layers 34a to the twelfth resistive layers 34h in parallel, the number of parallel connections of the fifth resistive layers 34a to the twelfth resistive layers 34h can be increased or decreased along with the number of parallel connections of the first resistive layers 31a to the fourth resistive layers 31d, thereby allowing for more precise adjustment of the resistance value of the resistive element according to the ninth modification. As with the resistive element of the ninth modification, there are no limitations on the number and arrangement of the resistive layers, allowing for appropriate settings.

[0131] <Tenth Variation>

[0132] The resistive element involved in the tenth variation of the embodiments of the present invention and Figure 1 and Figure 2 The resistive elements involved in the illustrated embodiments differ in the following aspects: Figure 28 As shown, a first protrusion 51x to a third protrusion 51z are provided on one side of the rectangular planar pattern of the electrode 51 formed on the pad. The first protrusion 51x is connected to one end of the first resistive layer 31a via the first electrode contact area 61a. The second protrusion 51y is connected to one end of the second resistive layer 31b via the second electrode contact area 61b. The third protrusion 51z is connected to one end of the third resistive layer 31c via the third electrode contact area 61c.

[0133] The other end of the first resistive layer 31a is connected to the first relay cable 52a via the first wiring contact area 62a. The other end of the second resistive layer 31b is connected to the second relay cable 52b via the second wiring contact area 62b. The other end of the third resistive layer 31c is connected to the third relay cable 52c via the third wiring contact area 62c.

[0134] The first relay wiring 52a is connected to the semiconductor substrate 1 via the first substrate contact area 63a. The second relay wiring 52b is connected to the semiconductor substrate 1 via the second substrate contact area 63b. The third relay wiring 52c is connected to the semiconductor substrate 1 via the third substrate contact area 63c.

[0135] In the resistive element involved in the tenth modification, the three resistive layers, the first resistive layer 31a to the third resistive layer 31c, are connected in parallel. Therefore, as... Figure 28 As schematically indicated by arrows, a first current path I1 is formed, where current flows from the first protrusion 51x of the pad forming electrode 51 through the first resistive layer 31a and the first relay wiring 52a to the semiconductor substrate 1. Similarly, a second current path I2 is formed, where current flows from the second protrusion 51y of the pad forming electrode 51 through the second resistive layer 31b and the second relay wiring 52b to the semiconductor substrate 1. Furthermore, a third current path I3 is formed, where current flows from the third protrusion 51z of the pad forming electrode 51 through the third resistive layer 31c and the third relay wiring 52c to the semiconductor substrate 1. Other structures of the resistive element involved in the tenth modification are similar to... Figure 1 and Figure 2 The resistive elements involved in the embodiments shown are the same, so repeated descriptions are omitted.

[0136] According to the tenth variation of the resistive element, when three resistive layers 31a to 31c are provided, some or all of the first resistive layers 31a to 31c can be selectively used by changing the presence or absence of the first electrode contact area 61a to 61c, the first wiring contact area 62a to 62c, and the first substrate contact area 63a to 63c.

[0137] <Eleventh Variation>

[0138] The resistive element involved in the eleventh variation of the embodiments of the present invention and Figure 28 The resistive element involved in the tenth variation shown differs in the following aspects: Figure 29As shown, the first protrusion 51x and the third protrusion 51z are separated from the pad forming electrode 51. In the resistor element according to the eleventh modification, a current path I1 is formed whereby current flows from the second protrusion 51y of the pad forming electrode 51 through the second resistive layer 31b and the second relay wiring 52b to the semiconductor substrate 1. Other structures of the resistor element according to the eleventh modification are similar to those of the first protrusion 51x and the second relay wiring 52b. Figure 28 The tenth variation shown involves the same resistive element, so repeated descriptions are omitted.

[0139] According to the resistive element involved in the eleventh modification, even without changing the presence or absence of the first electrode contact area 61a to the third electrode contact area 61c, the first wiring contact area 62a to the third wiring contact area 62c, and the first substrate contact area 63a to the third substrate contact area 63c, it is possible to selectively use part or all of the first resistive layer 31a to the third resistive layer 31c by selectively separating the first protrusion 51x to the third protrusion 51z from the pad forming electrode 51.

[0140] <Twelfth Variation>

[0141] The resistive element involved in the twelfth variation of the embodiments of the present invention and Figure 28 The resistive element involved in the tenth variation shown differs in the following aspects: Figure 30 As shown, multiple (three) resistor layers, from the first resistor layer 31a to the third resistor layer 31c, are connected in series. The resistive element involved in the twelfth modification example... Figure 28 The configuration shown includes a first resistor-to-resistor wiring 54a at the locations of the second relay wiring 52b and the third relay wiring 52c. Figure 28 The positions of the first protrusion 51x and the second protrusion 51y shown in the configuration have a second resistor wiring 54b.

[0142] The first resistor wiring 54a is connected to the second resistor layer 31b and the third resistor layer 31c via the second wiring contact area 62b and the third wiring contact area 62c. The second resistor wiring 54b is connected to the first resistor layer 31a and the second resistor layer 31b via the first electrode contact area 61a and the second electrode contact area 61b.

[0143] In the resistive element involved in the twelfth variation, such as Figure 30 As schematically indicated by arrows, a first current path I1 is formed, from the third protrusion 51z of the pad forming electrode 51, through the third resistive layer 31c, the first inter-resistive wiring 54a, the second resistive layer 31b, the second inter-resistive wiring 54b, the first resistive layer 31a, and the first relay wiring 52a, to the semiconductor substrate 1. Other structures of the resistive element involved in the twelfth modification are similar to... Figure 28The tenth variation shown involves the same resistive element, so repeated descriptions are omitted.

[0144] According to the resistive element involved in the twelfth modification, by configuring the first resistor wiring 54a and the second resistor wiring 54b, multiple resistor layers from the first resistor layer 31a to the third resistor layer 31c can be connected in series, thereby increasing the resistance value.

[0145] <Thirteenth Variation>

[0146] The resistive element involved in the thirteenth variation of the embodiments of the present invention and Figure 28 The resistive element involved in the tenth variation shown differs in the following aspects: Figure 31 As shown, multiple (two) resistor layers of the first resistor layer 31a and the third resistor layer 31c are connected in series. The resistive element involved in the thirteenth modification example... Figure 28 The configuration shown includes a first protrusion 51x, a second protrusion 51y, a second relay wiring 52b, and a third relay wiring 52c, with an inter-resistor wiring 55. The inter-resistor wiring 55 is connected to the first resistive layer 31a via a first electrode contact area 61a and to the third resistive layer 31c via a third wiring contact area 62c.

[0147] In the resistive element involved in the thirteenth variation, such as Figure 31 As schematically indicated by arrows, a first current path I1 is formed, from the third protrusion 51z of the pad forming electrode 51 through the third resistive layer 31c, the inter-resistive wiring 55, the first resistive layer 31a, and the first relay wiring 52a to the semiconductor substrate 1. Other structures of the resistive element involved in the thirteenth modification are similar to... Figure 28 The tenth variation shown involves the same resistive element, so repeated descriptions are omitted.

[0148] According to the resistor element involved in the thirteenth modification, by configuring the resistor wiring 55, it is possible to increase the resistance value by connecting multiple resistor layers of the first resistor layer 31a and the third resistor layer 31c in series while avoiding substrate contact near the pad forming electrode 51.

[0149] (Other implementation methods)

[0150] As described above, the present invention has been illustrated by way of embodiments, but it should not be construed that the discussions and drawings, which form part of this disclosure, are intended to limit the invention. Based on this disclosure, those skilled in the art will be able to recognize various alternative embodiments, examples, and application techniques.

[0151] For example, examples are given as follows Figure 3The resistive element described in the embodiment is used as the first gate resistive element R1 to the twelfth gate resistive element R12 as shown, but it is not limited to being used as the first gate resistive element R1 to the twelfth gate resistive element R12. The resistive element described in the embodiment can be used as a resistive element in various ICs.

Claims

1. A resistive element, characterized in that, have: Semiconductor substrate; A field insulating film is disposed on the semiconductor substrate; Multiple resistive layers are disposed separately on the field insulating film; An interlayer insulating film is configured to cover the field insulating film and each of the plurality of resistive layers; The pad forms an electrode, which is disposed on the interlayer insulating film and electrically connected to one end of at least one of the resistive layers selected from the plurality of resistive layers; The relay wiring is disposed on the interlayer insulating film separately from the pad forming an electrode, and has a terminal on one side that is electrically connected to the other end of the selected resistive layer and a terminal on the other side that is in ohmic contact with the semiconductor substrate. as well as The back electrode is disposed under the semiconductor substrate and is in ohmic contact with the semiconductor substrate. The resistive element uses the electrical path between the pad forming electrode and the back electrode as the resistive body. The pad forming electrode is electrically connected to the selected resistive layer via an electrode contact area that penetrates the interlayer insulating film. The terminal of one of the terminals is electrically connected to the selected resistive layer via a wiring contact area that penetrates the interlayer insulating film at a location separate from the electrode contact area. The other terminal is electrically connected to the semiconductor substrate via a substrate contact area that penetrates the interlayer insulating film. At least one of the electrode contact area, the wiring contact area, and the substrate contact area corresponding to the unselected resistor layer among the plurality of resistor layers is not provided.

2. The resistive element according to claim 1, characterized in that, The relay wiring has a number equal to the number of the plurality of resistor layers. The pad forming electrode is electrically connected to one end of each of the plurality of resistive layers. The plurality of relay wirings are electrically connected to the other end of each of the plurality of resistor layers. The plurality of resistive layers are connected in parallel between the pad forming electrode and the back electrode.

3. The resistive element according to claim 1 or 2, characterized in that, The multiple resistive layers have different resistance values.

4. The resistive element according to claim 3, characterized in that, The widths of the multiple resistive layers are different from each other.

5. The resistive element according to claim 1 or 2, characterized in that, Having multiple pads to form electrodes, One end of each of the plurality of resistive layers is connected to an electrode formed by the plurality of solder pads. The relay wiring is configured to be sandwiched between the plurality of pad forming electrodes and has a plurality of terminals respectively connected to one of the other ends of the plurality of resistive layers.

6. A resistive element, characterized in that, have: Semiconductor substrate; A field insulating film is disposed on the semiconductor substrate; Multiple resistive layers are disposed separately on the field insulating film; An interlayer insulating film is configured to cover the field insulating film and each of the plurality of resistive layers; The pad forms an electrode, which is disposed on the interlayer insulating film and electrically connected to one end of at least one of the resistive layers selected from the plurality of resistive layers; The relay wiring is disposed on the interlayer insulating film separately from the pad forming an electrode, and has a terminal on one side that is electrically connected to the other end of the selected resistive layer and a terminal on the other side that is in ohmic contact with the semiconductor substrate. A back electrode is disposed under the semiconductor substrate and is in ohmic contact with the semiconductor substrate. And auxiliary pads, which are electrically connected to the relay wiring. The resistive element uses the electrical path between the pad forming electrode and the back electrode as a resistive body.

7. A resistive element, characterized in that, have: Semiconductor substrate; A field insulating film is disposed on the semiconductor substrate; Multiple resistive layers are disposed separately on the field insulating film; An interlayer insulating film is configured to cover the field insulating film and each of the plurality of resistive layers; The pad forms an electrode, which is disposed on the interlayer insulating film and electrically connected to one end of at least one of the resistive layers selected from the plurality of resistive layers; The relay wiring is disposed on the interlayer insulating film separately from the pad forming an electrode, and has a terminal on one side that is electrically connected to the other end of the selected resistive layer and a terminal on the other side that is in ohmic contact with the semiconductor substrate. as well as The back electrode is disposed under the semiconductor substrate and is in ohmic contact with the semiconductor substrate. The resistive element uses the electrical path between the pad forming electrode and the back electrode as the resistive body. The plurality of resistive layers are connected in series between the electrode formed on the pad and the back electrode.

8. A method for manufacturing a resistive element, characterized in that, The process includes the following steps: A field insulating film is formed on a semiconductor substrate; Multiple resistive layers are formed on the field insulating film; An interlayer insulating film is formed in such a manner that it covers the field insulating film and the plurality of resistive layers; A first contact hole is made in the interlayer insulating film to expose one end of a selected resistive layer from the plurality of resistive layers; a second contact hole is made in the interlayer insulating film at a position separated from the first contact hole to expose the other end of the selected resistive layer; and a third contact hole is made in the interlayer insulating film at a position separated from the first and second contact holes to expose a portion of the upper surface of the semiconductor substrate. Forming pads to form electrodes and relay wiring, wherein the pad forming electrodes are electrically connected to one end of a selected resistive layer via a first contact hole, the relay wiring is electrically connected to the other end of the selected resistive layer via a second contact hole, and makes ohmic contact with the semiconductor substrate via a third contact hole; and A back electrode is formed under the semiconductor substrate. The resistive element uses the electrical path between the pad forming electrode and the back electrode as the resistive body. Select a resistor layer from the plurality of resistor layers that forms an electrode connection with the pad and the relay wiring. The first contact hole, the second contact hole, and the third contact hole corresponding to the selected resistive layer are formed, and at least one of the first contact hole, the second contact hole, and the third contact hole corresponding to the unselected resistive layer among the plurality of resistive layers is not formed.

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